Merge branch 'master' into upstream

1 files changed, 28 insertions, 175 deletions

diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c
index 8c6c8c52b95c..48bfcaa13ecc 100644
--- a/arch/i386/kernel/smpboot.c
+++ b/arch/i386/kernel/smpboot.c
@@ -63,6 +63,7 @@
 #include <mach_apic.h>
 #include <mach_wakecpu.h>
 #include <smpboot_hooks.h>
+#include <asm/vmi.h>
 
 /* Set if we find a B stepping CPU */
 static int __devinitdata smp_b_stepping;
@@ -93,12 +94,6 @@ cpumask_t cpu_possible_map;
 EXPORT_SYMBOL(cpu_possible_map);
 static cpumask_t smp_commenced_mask;
 
-/* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
- * is no way to resync one AP against BP. TBD: for prescott and above, we
- * should use IA64's algorithm
- */
-static int __devinitdata tsc_sync_disabled;
-
 /* Per CPU bogomips and other parameters */
 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
 EXPORT_SYMBOL(cpu_data);
@@ -215,151 +210,6 @@ valid_k7:
         ;
 }
 
-/*
- * TSC synchronization.
- *
- * We first check whether all CPUs have their TSC's synchronized,
- * then we print a warning if not, and always resync.
- */
-
-static struct {
-        atomic_t start_flag;
-        atomic_t count_start;
-        atomic_t count_stop;
-        unsigned long long values[NR_CPUS];
-} tsc __cpuinitdata = {
-        .start_flag = ATOMIC_INIT(0),
-        .count_start = ATOMIC_INIT(0),
-        .count_stop = ATOMIC_INIT(0),
-};
-
-#define NR_LOOPS 5
-
-static void __init synchronize_tsc_bp(void)
-{
-        int i;
-        unsigned long long t0;
-        unsigned long long sum, avg;
-        long long delta;
-        unsigned int one_usec;
-        int buggy = 0;
-
-        printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
-
-        /* convert from kcyc/sec to cyc/usec */
-        one_usec = cpu_khz / 1000;
-
-        atomic_set(&tsc.start_flag, 1);
-        wmb();
-
-        /*
-         * We loop a few times to get a primed instruction cache,
-         * then the last pass is more or less synchronized and
-         * the BP and APs set their cycle counters to zero all at
-         * once. This reduces the chance of having random offsets
-         * between the processors, and guarantees that the maximum
-         * delay between the cycle counters is never bigger than
-         * the latency of information-passing (cachelines) between
-         * two CPUs.
-         */
-        for (i = 0; i < NR_LOOPS; i++) {
-                /*
-                 * all APs synchronize but they loop on '== num_cpus'
-                 */
-                while (atomic_read(&tsc.count_start) != num_booting_cpus()-1)
-                        cpu_relax();
-                atomic_set(&tsc.count_stop, 0);
-                wmb();
-                /*
-                 * this lets the APs save their current TSC:
-                 */
-                atomic_inc(&tsc.count_start);
-
-                rdtscll(tsc.values[smp_processor_id()]);
-                /*
-                 * We clear the TSC in the last loop:
-                 */
-                if (i == NR_LOOPS-1)
-                        write_tsc(0, 0);
-
-                /*
-                 * Wait for all APs to leave the synchronization point:
-                 */
-                while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1)
-                        cpu_relax();
-                atomic_set(&tsc.count_start, 0);
-                wmb();
-                atomic_inc(&tsc.count_stop);
-        }
-
-        sum = 0;
-        for (i = 0; i < NR_CPUS; i++) {
-                if (cpu_isset(i, cpu_callout_map)) {
-                        t0 = tsc.values[i];
-                        sum += t0;
-                }
-        }
-        avg = sum;
-        do_div(avg, num_booting_cpus());
-
-        for (i = 0; i < NR_CPUS; i++) {
-                if (!cpu_isset(i, cpu_callout_map))
-                        continue;
-                delta = tsc.values[i] - avg;
-                if (delta < 0)
-                        delta = -delta;
-                /*
-                 * We report bigger than 2 microseconds clock differences.
-                 */
-                if (delta > 2*one_usec) {
-                        long long realdelta;
-
-                        if (!buggy) {
-                                buggy = 1;
-                                printk("\n");
-                        }
-                        realdelta = delta;
-                        do_div(realdelta, one_usec);
-                        if (tsc.values[i] < avg)
-                                realdelta = -realdelta;
-
-                        if (realdelta)
-                                printk(KERN_INFO "CPU#%d had %Ld usecs TSC "
-                                        "skew, fixed it up.\n", i, realdelta);
-                }
-        }
-        if (!buggy)
-                printk("passed.\n");
-}
-
-static void __cpuinit synchronize_tsc_ap(void)
-{
-        int i;
-
-        /*
-         * Not every cpu is online at the time
-         * this gets called, so we first wait for the BP to
-         * finish SMP initialization:
-         */
-        while (!atomic_read(&tsc.start_flag))
-                cpu_relax();
-
-        for (i = 0; i < NR_LOOPS; i++) {
-                atomic_inc(&tsc.count_start);
-                while (atomic_read(&tsc.count_start) != num_booting_cpus())
-                        cpu_relax();
-
-                rdtscll(tsc.values[smp_processor_id()]);
-                if (i == NR_LOOPS-1)
-                        write_tsc(0, 0);
-
-                atomic_inc(&tsc.count_stop);
-                while (atomic_read(&tsc.count_stop) != num_booting_cpus())
-                        cpu_relax();
-        }
-}
-#undef NR_LOOPS
-
 extern void calibrate_delay(void);
 
 static atomic_t init_deasserted;
@@ -437,20 +287,12 @@ static void __cpuinit smp_callin(void)
         /*
          * Save our processor parameters
          */
-        smp_store_cpu_info(cpuid);
-
-        disable_APIC_timer();
+        smp_store_cpu_info(cpuid);
 
         /*
          * Allow the master to continue.
          */
         cpu_set(cpuid, cpu_callin_map);
-
-        /*
-         *      Synchronize the TSC with the BP
-         */
-        if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
-                synchronize_tsc_ap();
 }
 
 static int cpucount;
@@ -545,18 +387,25 @@ static void __cpuinit start_secondary(void *unused)
          * booting is too fragile that we want to limit the
          * things done here to the most necessary things.
          */
+#ifdef CONFIG_VMI
+        vmi_bringup();
+#endif
         secondary_cpu_init();
         preempt_disable();
         smp_callin();
         while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
                 rep_nop();
-        setup_secondary_APIC_clock();
+        /*
+         * Check TSC synchronization with the BP:
+         */
+        check_tsc_sync_target();
+
+        setup_secondary_clock();
         if (nmi_watchdog == NMI_IO_APIC) {
                 disable_8259A_irq(0);
                 enable_NMI_through_LVT0(NULL);
                 enable_8259A_irq(0);
         }
-        enable_APIC_timer();
         /*
          * low-memory mappings have been cleared, flush them from
          * the local TLBs too.
@@ -619,7 +468,6 @@ extern struct {
         unsigned short ss;
 } stack_start;
 extern struct i386_pda *start_pda;
-extern struct Xgt_desc_struct cpu_gdt_descr;
 
 #ifdef CONFIG_NUMA
 
@@ -749,7 +597,7 @@ wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
         /*
          * Due to the Pentium erratum 3AP.
          */
-        maxlvt = get_maxlvt();
+        maxlvt = lapic_get_maxlvt();
         if (maxlvt > 3) {
                 apic_read_around(APIC_SPIV);
                 apic_write(APIC_ESR, 0);
@@ -835,11 +683,18 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
                 num_starts = 0;
 
         /*
+         * Paravirt / VMI wants a startup IPI hook here to set up the
+         * target processor state.
+         */
+        startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
+                         (unsigned long) stack_start.esp);
+
+        /*
          * Run STARTUP IPI loop.
          */
         Dprintk("#startup loops: %d.\n", num_starts);
 
-        maxlvt = get_maxlvt();
+        maxlvt = lapic_get_maxlvt();
 
         for (j = 1; j <= num_starts; j++) {
                 Dprintk("Sending STARTUP #%d.\n",j);
@@ -1115,8 +970,6 @@ static int __cpuinit __smp_prepare_cpu(int cpu)
         info.cpu = cpu;
         INIT_WORK(&info.task, do_warm_boot_cpu);
 
-        tsc_sync_disabled = 1;
-
         /* init low mem mapping */
         clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
                         min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
@@ -1124,7 +977,6 @@ static int __cpuinit __smp_prepare_cpu(int cpu)
         schedule_work(&info.task);
         wait_for_completion(&done);
 
-        tsc_sync_disabled = 0;
         zap_low_mappings();
         ret = 0;
 exit:
@@ -1320,13 +1172,7 @@ static void __init smp_boot_cpus(unsigned int max_cpus)
 
         smpboot_setup_io_apic();
 
-        setup_boot_APIC_clock();
-
-        /*
-         * Synchronize the TSC with the AP
-         */
-        if (cpu_has_tsc && cpucount && cpu_khz)
-                synchronize_tsc_bp();
+        setup_boot_clock();
 }
 
 /* These are wrappers to interface to the new boot process.  Someone
@@ -1461,9 +1307,16 @@ int __cpuinit __cpu_up(unsigned int cpu)
         }
 
         local_irq_enable();
+
         per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
         /* Unleash the CPU! */
         cpu_set(cpu, smp_commenced_mask);
+
+        /*
+         * Check TSC synchronization with the AP:
+         */
+        check_tsc_sync_source(cpu);
+
         while (!cpu_isset(cpu, cpu_online_map))
                 cpu_relax();