aboutsummaryrefslogtreecommitdiffstats
path: root/arch/i386/kernel/process.c
diff options
context:
space:
mode:
authorVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>2006-09-25 19:28:13 -0400
committerLen Brown <len.brown@intel.com>2006-10-14 00:35:39 -0400
commit991528d7348667924176f3e29addea0675298944 (patch)
treeed8552bd4c696700a95ae37b26c4197923207ae7 /arch/i386/kernel/process.c
parentb4bd8c66435a8cdf8c90334fb3b517a23ff2ab95 (diff)
ACPI: Processor native C-states using MWAIT
Intel processors starting with the Core Duo support support processor native C-state using the MWAIT instruction. Refer: Intel Architecture Software Developer's Manual http://www.intel.com/design/Pentium4/manuals/253668.htm Platform firmware exports the support for Native C-state to OS using ACPI _PDC and _CST methods. Refer: Intel Processor Vendor-Specific ACPI: Interface Specification http://www.intel.com/technology/iapc/acpi/downloads/302223.htm With Processor Native C-state, we use 'MWAIT' instruction on the processor to enter different C-states (C1, C2, C3). We won't use the special IO ports to enter C-state and no SMM mode etc required to enter C-state. Overall this will mean better C-state support. One major advantage of using MWAIT for all C-states is, with this and "treat interrupt as break event" feature of MWAIT, we can now get accurate timing for the time spent in C1, C2, .. states. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/i386/kernel/process.c')
-rw-r--r--arch/i386/kernel/process.c22
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/i386/kernel/process.c b/arch/i386/kernel/process.c
index b0a07801d9df..57d375900afb 100644
--- a/arch/i386/kernel/process.c
+++ b/arch/i386/kernel/process.c
@@ -236,20 +236,28 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait);
236 * We execute MONITOR against need_resched and enter optimized wait state 236 * We execute MONITOR against need_resched and enter optimized wait state
237 * through MWAIT. Whenever someone changes need_resched, we would be woken 237 * through MWAIT. Whenever someone changes need_resched, we would be woken
238 * up from MWAIT (without an IPI). 238 * up from MWAIT (without an IPI).
239 *
240 * New with Core Duo processors, MWAIT can take some hints based on CPU
241 * capability.
239 */ 242 */
240static void mwait_idle(void) 243void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
241{ 244{
242 local_irq_enable(); 245 if (!need_resched()) {
243
244 while (!need_resched()) {
245 __monitor((void *)&current_thread_info()->flags, 0, 0); 246 __monitor((void *)&current_thread_info()->flags, 0, 0);
246 smp_mb(); 247 smp_mb();
247 if (need_resched()) 248 if (!need_resched())
248 break; 249 __mwait(eax, ecx);
249 __mwait(0, 0);
250 } 250 }
251} 251}
252 252
253/* Default MONITOR/MWAIT with no hints, used for default C1 state */
254static void mwait_idle(void)
255{
256 local_irq_enable();
257 while (!need_resched())
258 mwait_idle_with_hints(0, 0);
259}
260
253void __devinit select_idle_routine(const struct cpuinfo_x86 *c) 261void __devinit select_idle_routine(const struct cpuinfo_x86 *c)
254{ 262{
255 if (cpu_has(c, X86_FEATURE_MWAIT)) { 263 if (cpu_has(c, X86_FEATURE_MWAIT)) {