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authorVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>2005-09-03 18:56:31 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:10 -0400
commit911a62d42365076209e2c327e7688db296e35d62 (patch)
tree51e6d8525cd3547ea43129b5dd20339655674d57 /arch/i386/kernel/mpparse.c
parent484b90c4b965d54037ff99b198d84cdf144f8a35 (diff)
[PATCH] x86: sutomatically enable bigsmp when we have more than 8 CPUs
i386 generic subarchitecture requires explicit dmi strings or command line to enable bigsmp mode. The patch below removes that restriction, and uses bigsmp as soon as it finds more than 8 logical CPUs, Intel processors and xAPIC support. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386/kernel/mpparse.c')
-rw-r--r--arch/i386/kernel/mpparse.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index ce838abb27d8..788efffa9930 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -65,6 +65,8 @@ int nr_ioapics;
65int pic_mode; 65int pic_mode;
66unsigned long mp_lapic_addr; 66unsigned long mp_lapic_addr;
67 67
68unsigned int def_to_bigsmp = 0;
69
68/* Processor that is doing the boot up */ 70/* Processor that is doing the boot up */
69unsigned int boot_cpu_physical_apicid = -1U; 71unsigned int boot_cpu_physical_apicid = -1U;
70/* Internal processor count */ 72/* Internal processor count */
@@ -213,6 +215,13 @@ static void __init MP_processor_info (struct mpc_config_processor *m)
213 ver = 0x10; 215 ver = 0x10;
214 } 216 }
215 apic_version[m->mpc_apicid] = ver; 217 apic_version[m->mpc_apicid] = ver;
218 if ((num_processors > 8) &&
219 APIC_XAPIC(ver) &&
220 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL))
221 def_to_bigsmp = 1;
222 else
223 def_to_bigsmp = 0;
224
216 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; 225 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
217} 226}
218 227