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authorEric W. Biederman <ebiederm@xmission.com>2007-02-23 06:13:55 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-26 13:34:07 -0500
commit9f0a5ba5508143731dc63235de19659be20d26dc (patch)
treea642cd2987e119e4cda611230cf39d403e1e9706 /arch/i386/kernel/io_apic.c
parentfc5d56f987170cda1d344095c4df65a60a3e9820 (diff)
[PATCH] irq: Remove set_native_irq_info
This patch replaces all instances of "set_native_irq_info(irq, mask)" with "irq_desc[irq].affinity = mask". The latter form is clearer uses fewer abstractions, and makes access to this field uniform accross different architectures. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/i386/kernel/io_apic.c')
-rw-r--r--arch/i386/kernel/io_apic.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c
index 4ccebd454e25..6fec4dab70bb 100644
--- a/arch/i386/kernel/io_apic.c
+++ b/arch/i386/kernel/io_apic.c
@@ -343,7 +343,7 @@ static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
343 break; 343 break;
344 entry = irq_2_pin + entry->next; 344 entry = irq_2_pin + entry->next;
345 } 345 }
346 set_native_irq_info(irq, cpumask); 346 irq_desc[irq].affinity = cpumask;
347 spin_unlock_irqrestore(&ioapic_lock, flags); 347 spin_unlock_irqrestore(&ioapic_lock, flags);
348} 348}
349 349
@@ -1354,7 +1354,7 @@ static void __init setup_IO_APIC_irqs(void)
1354 } 1354 }
1355 spin_lock_irqsave(&ioapic_lock, flags); 1355 spin_lock_irqsave(&ioapic_lock, flags);
1356 __ioapic_write_entry(apic, pin, entry); 1356 __ioapic_write_entry(apic, pin, entry);
1357 set_native_irq_info(irq, TARGET_CPUS); 1357 irq_desc[irq].affinity = TARGET_CPUS;
1358 spin_unlock_irqrestore(&ioapic_lock, flags); 1358 spin_unlock_irqrestore(&ioapic_lock, flags);
1359 } 1359 }
1360 } 1360 }
@@ -2585,7 +2585,7 @@ static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2585 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 2585 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2586 2586
2587 write_msi_msg(irq, &msg); 2587 write_msi_msg(irq, &msg);
2588 set_native_irq_info(irq, mask); 2588 irq_desc[irq].affinity = mask;
2589} 2589}
2590#endif /* CONFIG_SMP */ 2590#endif /* CONFIG_SMP */
2591 2591
@@ -2669,7 +2669,7 @@ static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2669 dest = cpu_mask_to_apicid(mask); 2669 dest = cpu_mask_to_apicid(mask);
2670 2670
2671 target_ht_irq(irq, dest); 2671 target_ht_irq(irq, dest);
2672 set_native_irq_info(irq, mask); 2672 irq_desc[irq].affinity = mask;
2673} 2673}
2674#endif 2674#endif
2675 2675
@@ -2875,7 +2875,7 @@ int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int a
2875 2875
2876 spin_lock_irqsave(&ioapic_lock, flags); 2876 spin_lock_irqsave(&ioapic_lock, flags);
2877 __ioapic_write_entry(ioapic, pin, entry); 2877 __ioapic_write_entry(ioapic, pin, entry);
2878 set_native_irq_info(irq, TARGET_CPUS); 2878 irq_desc[irq].affinity = TARGET_CPUS;
2879 spin_unlock_irqrestore(&ioapic_lock, flags); 2879 spin_unlock_irqrestore(&ioapic_lock, flags);
2880 2880
2881 return 0; 2881 return 0;