diff options
author | Dave Jones <davej@redhat.com> | 2006-06-04 19:37:58 -0400 |
---|---|---|
committer | Dave Jones <davej@redhat.com> | 2006-06-04 19:37:58 -0400 |
commit | 1f729e0660f974cec1f0f7f4fba03ea4c2c4b9a9 (patch) | |
tree | 9254031f1f252e5b38c962b3e2ed93a0351ce319 /arch/i386/kernel/cpu/cpufreq/powernow-k8.h | |
parent | 911cb74bb9e77e40749abc2fca6fe74d87d940f3 (diff) |
[CPUFREQ] Prepare powernow-k8 for future CPUs.
Forthcoming AMD products will use a different algorithm for transitioning
pstates than the current generation Opteron products do. The attached
patch allows the powernow-k8 driver to work with those products.
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'arch/i386/kernel/cpu/cpufreq/powernow-k8.h')
-rw-r--r-- | arch/i386/kernel/cpu/cpufreq/powernow-k8.h | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h index 79a7c5c87edc..bf8ad9e43da3 100644 --- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h +++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. | 2 | * (c) 2003-2006 Advanced Micro Devices, Inc. |
3 | * Your use of this code is subject to the terms and conditions of the | 3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | 4 | * GNU general public license version 2. See "COPYING" or |
5 | * http://www.gnu.org/licenses/gpl.html | 5 | * http://www.gnu.org/licenses/gpl.html |
@@ -21,8 +21,8 @@ struct powernow_k8_data { | |||
21 | u32 plllock; /* pll lock time, units 1 us */ | 21 | u32 plllock; /* pll lock time, units 1 us */ |
22 | u32 exttype; /* extended interface = 1 */ | 22 | u32 exttype; /* extended interface = 1 */ |
23 | 23 | ||
24 | /* keep track of the current fid / vid */ | 24 | /* keep track of the current fid / vid or did */ |
25 | u32 currvid, currfid; | 25 | u32 currvid, currfid, currdid; |
26 | 26 | ||
27 | /* the powernow_table includes all frequency and vid/fid pairings: | 27 | /* the powernow_table includes all frequency and vid/fid pairings: |
28 | * fid are the lower 8 bits of the index, vid are the upper 8 bits. | 28 | * fid are the lower 8 bits of the index, vid are the upper 8 bits. |
@@ -34,6 +34,10 @@ struct powernow_k8_data { | |||
34 | * used to determine valid frequency/vid/fid states */ | 34 | * used to determine valid frequency/vid/fid states */ |
35 | struct acpi_processor_performance acpi_data; | 35 | struct acpi_processor_performance acpi_data; |
36 | #endif | 36 | #endif |
37 | /* we need to keep track of associated cores, but let cpufreq | ||
38 | * handle hotplug events - so just point at cpufreq pol->cpus | ||
39 | * structure */ | ||
40 | cpumask_t *available_cores; | ||
37 | }; | 41 | }; |
38 | 42 | ||
39 | 43 | ||
@@ -43,6 +47,7 @@ struct powernow_k8_data { | |||
43 | #define CPUID_XFAM_K8 0 | 47 | #define CPUID_XFAM_K8 0 |
44 | #define CPUID_XMOD 0x000f0000 /* extended model */ | 48 | #define CPUID_XMOD 0x000f0000 /* extended model */ |
45 | #define CPUID_XMOD_REV_G 0x00060000 | 49 | #define CPUID_XMOD_REV_G 0x00060000 |
50 | #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ | ||
46 | #define CPUID_USE_XFAM_XMOD 0x00000f00 | 51 | #define CPUID_USE_XFAM_XMOD 0x00000f00 |
47 | #define CPUID_GET_MAX_CAPABILITIES 0x80000000 | 52 | #define CPUID_GET_MAX_CAPABILITIES 0x80000000 |
48 | #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 | 53 | #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 |
@@ -79,6 +84,32 @@ struct powernow_k8_data { | |||
79 | #define MSR_S_HI_CURRENT_VID 0x0000003f | 84 | #define MSR_S_HI_CURRENT_VID 0x0000003f |
80 | #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 | 85 | #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 |
81 | 86 | ||
87 | |||
88 | /* Hardware Pstate _PSS and MSR definitions */ | ||
89 | #define USE_HW_PSTATE 0x00000080 | ||
90 | #define HW_PSTATE_FID_MASK 0x0000003f | ||
91 | #define HW_PSTATE_DID_MASK 0x000001c0 | ||
92 | #define HW_PSTATE_DID_SHIFT 6 | ||
93 | #define HW_PSTATE_MASK 0x00000007 | ||
94 | #define HW_PSTATE_VALID_MASK 0x80000000 | ||
95 | #define HW_FID_INDEX_SHIFT 8 | ||
96 | #define HW_FID_INDEX_MASK 0x0000ff00 | ||
97 | #define HW_DID_INDEX_SHIFT 16 | ||
98 | #define HW_DID_INDEX_MASK 0x00ff0000 | ||
99 | #define HW_WATTS_MASK 0xff | ||
100 | #define HW_PWR_DVR_MASK 0x300 | ||
101 | #define HW_PWR_DVR_SHIFT 8 | ||
102 | #define HW_PWR_MAX_MULT 3 | ||
103 | #define MAX_HW_PSTATE 8 /* hw pstate supports up to 8 */ | ||
104 | #define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ | ||
105 | #define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ | ||
106 | #define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ | ||
107 | |||
108 | /* define the two driver architectures */ | ||
109 | #define CPU_OPTERON 0 | ||
110 | #define CPU_HW_PSTATE 1 | ||
111 | |||
112 | |||
82 | /* | 113 | /* |
83 | * There are restrictions frequencies have to follow: | 114 | * There are restrictions frequencies have to follow: |
84 | * - only 1 entry in the low fid table ( <=1.4GHz ) | 115 | * - only 1 entry in the low fid table ( <=1.4GHz ) |
@@ -182,6 +213,9 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); | |||
182 | 213 | ||
183 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); | 214 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); |
184 | 215 | ||
216 | static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); | ||
217 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); | ||
218 | |||
185 | #ifdef CONFIG_SMP | 219 | #ifdef CONFIG_SMP |
186 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) | 220 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) |
187 | { | 221 | { |