[PATCH] kexec: x86: resture apic virtual wire mode on shutdown

When coming out of apic mode attempt to set the appropriate
apic back into virtual wire mode.  This improves on previous versions
of this patch by by never setting bot the local apic and the ioapic
into veritual wire mode.

This code looks at data from the mptable to see if an ioapic has
an ExtInt input to make this decision.  A future improvement
is to figure out which apic or ioapic was in virtual wire mode
at boot time and to remember it.  That is potentially a more accurate
method, of selecting which apic to place in virutal wire mode.

Signed-off-by: Eric Biederman <ebiederm@xmission.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 37 insertions, 1 deletions

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index cf45bed96d08..93df90bbb87e 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -211,7 +211,7 @@ void __init connect_bsp_APIC(void)
         enable_apic_mode();
 }
 
-void disconnect_bsp_APIC(void)
+void disconnect_bsp_APIC(int virt_wire_setup)
 {
         if (pic_mode) {
                 /*
@@ -225,6 +225,42 @@ void disconnect_bsp_APIC(void)
                 outb(0x70, 0x22);
                 outb(0x00, 0x23);
         }
+        else {
+                /* Go back to Virtual Wire compatibility mode */
+                unsigned long value;
+
+                /* For the spurious interrupt use vector F, and enable it */
+                value = apic_read(APIC_SPIV);
+                value &= ~APIC_VECTOR_MASK;
+                value |= APIC_SPIV_APIC_ENABLED;
+                value |= 0xf;
+                apic_write_around(APIC_SPIV, value);
+
+                if (!virt_wire_setup) {
+                        /* For LVT0 make it edge triggered, active high, external and enabled */
+                        value = apic_read(APIC_LVT0);
+                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
+                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+                        apic_write_around(APIC_LVT0, value);
+                }
+                else {
+                        /* Disable LVT0 */
+                        apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
+                }
+
+                /* For LVT1 make it edge triggered, active high, nmi and enabled */
+                value = apic_read(APIC_LVT1);
+                value &= ~(
+                        APIC_MODE_MASK | APIC_SEND_PENDING |
+                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+                value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+                apic_write_around(APIC_LVT1, value);
+        }
 }
 
 void disable_local_APIC(void)