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authorRichard Kuo <rkuo@codeaurora.org>2011-10-31 19:36:04 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 10:34:18 -0400
commit99a70aa051d2aef6a91761c2230264cfcf20ae74 (patch)
tree3944c62bdd83d6360f8e5198296a68489526e7f4 /arch/hexagon
parentb9398a84590be3a828c168ed25bf1fd3d637988a (diff)
Hexagon: Add processor and system headers
Signed-off-by: Richard Kuo <rkuo@codeaurora.org> Signed-off-by: Linas Vepstas <linas@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/hexagon')
-rw-r--r--arch/hexagon/include/asm/asm-offsets.h1
-rw-r--r--arch/hexagon/include/asm/irqflags.h62
-rw-r--r--arch/hexagon/include/asm/processor.h123
-rw-r--r--arch/hexagon/include/asm/registers.h236
-rw-r--r--arch/hexagon/include/asm/system.h126
5 files changed, 548 insertions, 0 deletions
diff --git a/arch/hexagon/include/asm/asm-offsets.h b/arch/hexagon/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/hexagon/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/hexagon/include/asm/irqflags.h b/arch/hexagon/include/asm/irqflags.h
new file mode 100644
index 000000000000..ec1523655416
--- /dev/null
+++ b/arch/hexagon/include/asm/irqflags.h
@@ -0,0 +1,62 @@
1/*
2 * IRQ support for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_IRQFLAGS_H
22#define _ASM_IRQFLAGS_H
23
24#include <asm/hexagon_vm.h>
25#include <linux/types.h>
26
27static inline unsigned long arch_local_save_flags(void)
28{
29 return __vmgetie();
30}
31
32static inline unsigned long arch_local_irq_save(void)
33{
34 return __vmsetie(VM_INT_DISABLE);
35}
36
37static inline bool arch_irqs_disabled_flags(unsigned long flags)
38{
39 return !flags;
40}
41
42static inline bool arch_irqs_disabled(void)
43{
44 return !__vmgetie();
45}
46
47static inline void arch_local_irq_enable(void)
48{
49 __vmsetie(VM_INT_ENABLE);
50}
51
52static inline void arch_local_irq_disable(void)
53{
54 __vmsetie(VM_INT_DISABLE);
55}
56
57static inline void arch_local_irq_restore(unsigned long flags)
58{
59 __vmsetie(flags);
60}
61
62#endif
diff --git a/arch/hexagon/include/asm/processor.h b/arch/hexagon/include/asm/processor.h
new file mode 100644
index 000000000000..20c5ddabbd8b
--- /dev/null
+++ b/arch/hexagon/include/asm/processor.h
@@ -0,0 +1,123 @@
1/*
2 * Process/processor support for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_PROCESSOR_H
22#define _ASM_PROCESSOR_H
23
24#ifndef __ASSEMBLY__
25
26#include <asm/mem-layout.h>
27#include <asm/registers.h>
28#include <asm/hexagon_vm.h>
29
30/* must be a macro */
31#define current_text_addr() ({ __label__ _l; _l: &&_l; })
32
33/* task_struct, defined elsewhere, is the "process descriptor" */
34struct task_struct;
35
36/* this is defined in arch/process.c */
37extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
38extern unsigned long thread_saved_pc(struct task_struct *tsk);
39
40extern void start_thread(struct pt_regs *, unsigned long, unsigned long);
41
42/*
43 * thread_struct is supposed to be for context switch data.
44 * Specifically, to hold the state necessary to perform switch_to...
45 */
46struct thread_struct {
47 void *switch_sp;
48};
49
50/*
51 * initializes thread_struct
52 * The only thing we have in there is switch_sp
53 * which doesn't really need to be initialized.
54 */
55
56#define INIT_THREAD { \
57}
58
59#define cpu_relax() __vmyield()
60
61/*
62 * "Unlazying all lazy status" occurs here.
63 */
64static inline void prepare_to_copy(struct task_struct *tsk)
65{
66}
67
68/*
69 * Decides where the kernel will search for a free chunk of vm space during
70 * mmaps.
71 * See also arch_get_unmapped_area.
72 * Doesn't affect if you have MAX_FIXED in the page flags set though...
73 *
74 * Apparently the convention is that ld.so will ask for "unmapped" private
75 * memory to be allocated SOMEWHERE, but it also asks for memory explicitly
76 * via MAP_FIXED at the lower * addresses starting at VA=0x0.
77 *
78 * If the two requests collide, you get authentic segfaulting action, so
79 * you have to kick the "unmapped" base requests higher up.
80 */
81#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE/3))
82
83
84#define task_pt_regs(task) \
85 ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE) - 1)
86
87#define KSTK_EIP(tsk) (pt_elr(task_pt_regs(tsk)))
88#define KSTK_ESP(tsk) (pt_psp(task_pt_regs(tsk)))
89
90/* Free all resources held by a thread; defined in process.c */
91extern void release_thread(struct task_struct *dead_task);
92
93/* Get wait channel for task P. */
94extern unsigned long get_wchan(struct task_struct *p);
95
96/* The following stuff is pretty HEXAGON specific. */
97
98/* This is really just here for __switch_to.
99 Offsets are pulled via asm-offsets.c */
100
101/*
102 * No real reason why VM and native switch stacks should be different.
103 * Ultimately this should merge. Note that Rev C. ABI called out only
104 * R24-27 as callee saved GPRs needing explicit attention (R29-31 being
105 * dealt with automagically by allocframe), but the current ABI has
106 * more, R16-R27. By saving more, the worst case is that we waste some
107 * cycles if building with the old compilers.
108 */
109
110struct hexagon_switch_stack {
111 unsigned long long r1716;
112 unsigned long long r1918;
113 unsigned long long r2120;
114 unsigned long long r2322;
115 unsigned long long r2524;
116 unsigned long long r2726;
117 unsigned long fp;
118 unsigned long lr;
119};
120
121#endif /* !__ASSEMBLY__ */
122
123#endif
diff --git a/arch/hexagon/include/asm/registers.h b/arch/hexagon/include/asm/registers.h
new file mode 100644
index 000000000000..4dd741be855d
--- /dev/null
+++ b/arch/hexagon/include/asm/registers.h
@@ -0,0 +1,236 @@
1/*
2 * Register definitions for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_REGISTERS_H
22#define _ASM_REGISTERS_H
23
24#define SP r29
25
26#ifndef __ASSEMBLY__
27
28/* See kernel/entry.S for further documentation. */
29
30/*
31 * Entry code copies the event record out of guest registers into
32 * this structure (which is on the stack).
33 */
34
35struct hvm_event_record {
36 unsigned long vmel; /* Event Linkage (return address) */
37 unsigned long vmest; /* Event context - pre-event SSR values */
38 unsigned long vmpsp; /* Previous stack pointer */
39 unsigned long vmbadva; /* Bad virtual address for addressing events */
40};
41
42struct pt_regs {
43 long restart_r0; /* R0 checkpoint for syscall restart */
44 long syscall_nr; /* Only used in system calls */
45 union {
46 struct {
47 unsigned long usr;
48 unsigned long preds;
49 };
50 long long int predsusr;
51 };
52 union {
53 struct {
54 unsigned long m0;
55 unsigned long m1;
56 };
57 long long int m1m0;
58 };
59 union {
60 struct {
61 unsigned long sa1;
62 unsigned long lc1;
63 };
64 long long int lc1sa1;
65 };
66 union {
67 struct {
68 unsigned long sa0;
69 unsigned long lc0;
70 };
71 long long int lc0sa0;
72 };
73 union {
74 struct {
75 unsigned long gp;
76 unsigned long ugp;
77 };
78 long long int ugpgp;
79 };
80 /*
81 * Be extremely careful with rearranging these, if at all. Some code
82 * assumes the 32 registers exist exactly like this in memory;
83 * e.g. kernel/ptrace.c
84 * e.g. kernel/signal.c (restore_sigcontext)
85 */
86 union {
87 struct {
88 unsigned long r00;
89 unsigned long r01;
90 };
91 long long int r0100;
92 };
93 union {
94 struct {
95 unsigned long r02;
96 unsigned long r03;
97 };
98 long long int r0302;
99 };
100 union {
101 struct {
102 unsigned long r04;
103 unsigned long r05;
104 };
105 long long int r0504;
106 };
107 union {
108 struct {
109 unsigned long r06;
110 unsigned long r07;
111 };
112 long long int r0706;
113 };
114 union {
115 struct {
116 unsigned long r08;
117 unsigned long r09;
118 };
119 long long int r0908;
120 };
121 union {
122 struct {
123 unsigned long r10;
124 unsigned long r11;
125 };
126 long long int r1110;
127 };
128 union {
129 struct {
130 unsigned long r12;
131 unsigned long r13;
132 };
133 long long int r1312;
134 };
135 union {
136 struct {
137 unsigned long r14;
138 unsigned long r15;
139 };
140 long long int r1514;
141 };
142 union {
143 struct {
144 unsigned long r16;
145 unsigned long r17;
146 };
147 long long int r1716;
148 };
149 union {
150 struct {
151 unsigned long r18;
152 unsigned long r19;
153 };
154 long long int r1918;
155 };
156 union {
157 struct {
158 unsigned long r20;
159 unsigned long r21;
160 };
161 long long int r2120;
162 };
163 union {
164 struct {
165 unsigned long r22;
166 unsigned long r23;
167 };
168 long long int r2322;
169 };
170 union {
171 struct {
172 unsigned long r24;
173 unsigned long r25;
174 };
175 long long int r2524;
176 };
177 union {
178 struct {
179 unsigned long r26;
180 unsigned long r27;
181 };
182 long long int r2726;
183 };
184 union {
185 struct {
186 unsigned long r28;
187 unsigned long r29;
188 };
189 long long int r2928;
190 };
191 union {
192 struct {
193 unsigned long r30;
194 unsigned long r31;
195 };
196 long long int r3130;
197 };
198 /* VM dispatch pushes event record onto stack - we can build on it */
199 struct hvm_event_record hvmer;
200};
201
202/* Defines to conveniently access the values */
203
204/*
205 * As of the VM spec 0.5, these registers are now set/retrieved via a
206 * VM call. On the in-bound side, we just fetch the values
207 * at the entry points and stuff them into the old record in pt_regs.
208 * However, on the outbound side, probably at VM rte, we set the
209 * registers back.
210 */
211
212#define pt_elr(regs) ((regs)->hvmer.vmel)
213#define pt_set_elr(regs, val) ((regs)->hvmer.vmel = (val))
214#define pt_cause(regs) ((regs)->hvmer.vmest & (HVM_VMEST_CAUSE_MSK))
215#define user_mode(regs) \
216 (((regs)->hvmer.vmest & (HVM_VMEST_UM_MSK << HVM_VMEST_UM_SFT)) != 0)
217#define ints_enabled(regs) \
218 (((regs)->hvmer.vmest & (HVM_VMEST_IE_MSK << HVM_VMEST_IE_SFT)) != 0)
219#define pt_psp(regs) ((regs)->hvmer.vmpsp)
220#define pt_badva(regs) ((regs)->hvmer.vmbadva)
221
222#define pt_set_rte_sp(regs, sp) do {\
223 pt_psp(regs) = (sp);\
224 (regs)->SP = (unsigned long) &((regs)->hvmer);\
225 } while (0)
226
227#define pt_set_kmode(regs) \
228 (regs)->hvmer.vmest = (HVM_VMEST_IE_MSK << HVM_VMEST_IE_SFT)
229
230#define pt_set_usermode(regs) \
231 (regs)->hvmer.vmest = (HVM_VMEST_UM_MSK << HVM_VMEST_UM_SFT) \
232 | (HVM_VMEST_IE_MSK << HVM_VMEST_IE_SFT)
233
234#endif /* ifndef __ASSEMBLY */
235
236#endif
diff --git a/arch/hexagon/include/asm/system.h b/arch/hexagon/include/asm/system.h
new file mode 100644
index 000000000000..323ed1dd65e2
--- /dev/null
+++ b/arch/hexagon/include/asm/system.h
@@ -0,0 +1,126 @@
1/*
2 * System level definitions for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_SYSTEM_H
22#define _ASM_SYSTEM_H
23
24#include <linux/linkage.h>
25#include <linux/irqflags.h>
26#include <asm/atomic.h>
27#include <asm/hexagon_vm.h>
28
29struct thread_struct;
30
31extern struct task_struct *__switch_to(struct task_struct *,
32 struct task_struct *,
33 struct task_struct *);
34
35#define switch_to(p, n, r) do {\
36 r = __switch_to((p), (n), (r));\
37} while (0)
38
39
40#define rmb() barrier()
41#define read_barrier_depends() barrier()
42#define wmb() barrier()
43#define mb() barrier()
44#define smp_rmb() barrier()
45#define smp_read_barrier_depends() barrier()
46#define smp_wmb() barrier()
47#define smp_mb() barrier()
48#define smp_mb__before_atomic_dec() barrier()
49#define smp_mb__after_atomic_dec() barrier()
50#define smp_mb__before_atomic_inc() barrier()
51#define smp_mb__after_atomic_inc() barrier()
52
53/*
54 * __xchg - atomically exchange a register and a memory location
55 * @x: value to swap
56 * @ptr: pointer to memory
57 * @size: size of the value
58 *
59 * Only 4 bytes supported currently.
60 *
61 * Note: there was an errata for V2 about .new's and memw_locked.
62 *
63 */
64static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
65 int size)
66{
67 unsigned long retval;
68
69 /* Can't seem to use printk or panic here, so just stop */
70 if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
71
72 __asm__ __volatile__ (
73 "1: %0 = memw_locked(%1);\n" /* load into retval */
74 " memw_locked(%1,P0) = %2;\n" /* store into memory */
75 " if !P0 jump 1b;\n"
76 : "=&r" (retval)
77 : "r" (ptr), "r" (x)
78 : "memory", "p0"
79 );
80 return retval;
81}
82
83/*
84 * Atomically swap the contents of a register with memory. Should be atomic
85 * between multiple CPU's and within interrupts on the same CPU.
86 */
87#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
88 sizeof(*(ptr))))
89
90/* Set a value and use a memory barrier. Used by the scheduler somewhere. */
91#define set_mb(var, value) \
92 do { var = value; mb(); } while (0)
93
94/*
95 * see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
96 * looks just like atomic_cmpxchg on our arch currently with a bunch of
97 * variable casting.
98 */
99#define __HAVE_ARCH_CMPXCHG 1
100
101#define cmpxchg(ptr, old, new) \
102({ \
103 __typeof__(ptr) __ptr = (ptr); \
104 __typeof__(*(ptr)) __old = (old); \
105 __typeof__(*(ptr)) __new = (new); \
106 __typeof__(*(ptr)) __oldval = 0; \
107 \
108 asm volatile( \
109 "1: %0 = memw_locked(%1);\n" \
110 " { P0 = cmp.eq(%0,%2);\n" \
111 " if (!P0.new) jump:nt 2f; }\n" \
112 " memw_locked(%1,p0) = %3;\n" \
113 " if (!P0) jump 1b;\n" \
114 "2:\n" \
115 : "=&r" (__oldval) \
116 : "r" (__ptr), "r" (__old), "r" (__new) \
117 : "memory", "p0" \
118 ); \
119 __oldval; \
120})
121
122/* Should probably shoot for an 8-byte aligned stack pointer */
123#define STACK_MASK (~7)
124#define arch_align_stack(x) (x & STACK_MASK)
125
126#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 01:31:57 -0500