aboutsummaryrefslogtreecommitdiffstats
path: root/arch/hexagon/include
diff options
context:
space:
mode:
authorDavid Howells <dhowells@redhat.com>2012-03-28 13:30:02 -0400
committerDavid Howells <dhowells@redhat.com>2012-03-28 13:30:02 -0400
commit8335896bed16d8b86a28ec5b1e0f723d1cf75aa8 (patch)
treece95f070b734d4ad67ee4b2c3a7b04f433012c5d /arch/hexagon/include
parenta5401ee3da720d29bcce90ed352738c85a71f6cf (diff)
Disintegrate asm/system.h for Hexagon
Disintegrate asm/system.h for Hexagon. Not compiled. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Richard Kuo <rkuo@codeaurora.org> cc: linux-hexagon@vger.kernel.org
Diffstat (limited to 'arch/hexagon/include')
-rw-r--r--arch/hexagon/include/asm/atomic.h1
-rw-r--r--arch/hexagon/include/asm/barrier.h41
-rw-r--r--arch/hexagon/include/asm/bitops.h1
-rw-r--r--arch/hexagon/include/asm/cmpxchg.h90
-rw-r--r--arch/hexagon/include/asm/exec.h28
-rw-r--r--arch/hexagon/include/asm/switch_to.h34
-rw-r--r--arch/hexagon/include/asm/system.h131
7 files changed, 199 insertions, 127 deletions
diff --git a/arch/hexagon/include/asm/atomic.h b/arch/hexagon/include/asm/atomic.h
index e220f9053035..3e258043337b 100644
--- a/arch/hexagon/include/asm/atomic.h
+++ b/arch/hexagon/include/asm/atomic.h
@@ -23,6 +23,7 @@
23#define _ASM_ATOMIC_H 23#define _ASM_ATOMIC_H
24 24
25#include <linux/types.h> 25#include <linux/types.h>
26#include <asm/cmpxchg.h>
26 27
27#define ATOMIC_INIT(i) { (i) } 28#define ATOMIC_INIT(i) { (i) }
28#define atomic_set(v, i) ((v)->counter = (i)) 29#define atomic_set(v, i) ((v)->counter = (i))
diff --git a/arch/hexagon/include/asm/barrier.h b/arch/hexagon/include/asm/barrier.h
new file mode 100644
index 000000000000..a4ed6e26cb1d
--- /dev/null
+++ b/arch/hexagon/include/asm/barrier.h
@@ -0,0 +1,41 @@
1/*
2 * Memory barrier definitions for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_BARRIER_H
22#define _ASM_BARRIER_H
23
24#define rmb() barrier()
25#define read_barrier_depends() barrier()
26#define wmb() barrier()
27#define mb() barrier()
28#define smp_rmb() barrier()
29#define smp_read_barrier_depends() barrier()
30#define smp_wmb() barrier()
31#define smp_mb() barrier()
32#define smp_mb__before_atomic_dec() barrier()
33#define smp_mb__after_atomic_dec() barrier()
34#define smp_mb__before_atomic_inc() barrier()
35#define smp_mb__after_atomic_inc() barrier()
36
37/* Set a value and use a memory barrier. Used by the scheduler somewhere. */
38#define set_mb(var, value) \
39 do { var = value; mb(); } while (0)
40
41#endif /* _ASM_BARRIER_H */
diff --git a/arch/hexagon/include/asm/bitops.h b/arch/hexagon/include/asm/bitops.h
index d23461e080ff..4caa649ad78b 100644
--- a/arch/hexagon/include/asm/bitops.h
+++ b/arch/hexagon/include/asm/bitops.h
@@ -24,7 +24,6 @@
24 24
25#include <linux/compiler.h> 25#include <linux/compiler.h>
26#include <asm/byteorder.h> 26#include <asm/byteorder.h>
27#include <asm/system.h>
28#include <asm/atomic.h> 27#include <asm/atomic.h>
29 28
30#ifdef __KERNEL__ 29#ifdef __KERNEL__
diff --git a/arch/hexagon/include/asm/cmpxchg.h b/arch/hexagon/include/asm/cmpxchg.h
new file mode 100644
index 000000000000..c5f9527e1df6
--- /dev/null
+++ b/arch/hexagon/include/asm/cmpxchg.h
@@ -0,0 +1,90 @@
1/*
2 * xchg/cmpxchg operations for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301, USA.
20 */
21
22#ifndef _ASM_CMPXCHG_H
23#define _ASM_CMPXCHG_H
24
25/*
26 * __xchg - atomically exchange a register and a memory location
27 * @x: value to swap
28 * @ptr: pointer to memory
29 * @size: size of the value
30 *
31 * Only 4 bytes supported currently.
32 *
33 * Note: there was an errata for V2 about .new's and memw_locked.
34 *
35 */
36static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
37 int size)
38{
39 unsigned long retval;
40
41 /* Can't seem to use printk or panic here, so just stop */
42 if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
43
44 __asm__ __volatile__ (
45 "1: %0 = memw_locked(%1);\n" /* load into retval */
46 " memw_locked(%1,P0) = %2;\n" /* store into memory */
47 " if !P0 jump 1b;\n"
48 : "=&r" (retval)
49 : "r" (ptr), "r" (x)
50 : "memory", "p0"
51 );
52 return retval;
53}
54
55/*
56 * Atomically swap the contents of a register with memory. Should be atomic
57 * between multiple CPU's and within interrupts on the same CPU.
58 */
59#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
60 sizeof(*(ptr))))
61
62/*
63 * see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
64 * looks just like atomic_cmpxchg on our arch currently with a bunch of
65 * variable casting.
66 */
67#define __HAVE_ARCH_CMPXCHG 1
68
69#define cmpxchg(ptr, old, new) \
70({ \
71 __typeof__(ptr) __ptr = (ptr); \
72 __typeof__(*(ptr)) __old = (old); \
73 __typeof__(*(ptr)) __new = (new); \
74 __typeof__(*(ptr)) __oldval = 0; \
75 \
76 asm volatile( \
77 "1: %0 = memw_locked(%1);\n" \
78 " { P0 = cmp.eq(%0,%2);\n" \
79 " if (!P0.new) jump:nt 2f; }\n" \
80 " memw_locked(%1,p0) = %3;\n" \
81 " if (!P0) jump 1b;\n" \
82 "2:\n" \
83 : "=&r" (__oldval) \
84 : "r" (__ptr), "r" (__old), "r" (__new) \
85 : "memory", "p0" \
86 ); \
87 __oldval; \
88})
89
90#endif /* _ASM_CMPXCHG_H */
diff --git a/arch/hexagon/include/asm/exec.h b/arch/hexagon/include/asm/exec.h
new file mode 100644
index 000000000000..350e6d497d44
--- /dev/null
+++ b/arch/hexagon/include/asm/exec.h
@@ -0,0 +1,28 @@
1/*
2 * Process execution related definitions for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_EXEC_H
22#define _ASM_EXEC_H
23
24/* Should probably shoot for an 8-byte aligned stack pointer */
25#define STACK_MASK (~7)
26#define arch_align_stack(x) (x & STACK_MASK)
27
28#endif /* _ASM_EXEC_H */
diff --git a/arch/hexagon/include/asm/switch_to.h b/arch/hexagon/include/asm/switch_to.h
new file mode 100644
index 000000000000..28ca0dfb6064
--- /dev/null
+++ b/arch/hexagon/include/asm/switch_to.h
@@ -0,0 +1,34 @@
1/*
2 * Task switching definitions for the Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_SWITCH_TO_H
22#define _ASM_SWITCH_TO_H
23
24struct thread_struct;
25
26extern struct task_struct *__switch_to(struct task_struct *,
27 struct task_struct *,
28 struct task_struct *);
29
30#define switch_to(p, n, r) do {\
31 r = __switch_to((p), (n), (r));\
32} while (0)
33
34#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/hexagon/include/asm/system.h b/arch/hexagon/include/asm/system.h
index 323ed1dd65e2..a7f40578587c 100644
--- a/arch/hexagon/include/asm/system.h
+++ b/arch/hexagon/include/asm/system.h
@@ -1,126 +1,5 @@
1/* 1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2 * System level definitions for the Hexagon architecture 2#include <asm/barrier.h>
3 * 3#include <asm/cmpxchg.h>
4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 4#include <asm/exec.h>
5 * 5#include <asm/switch_to.h>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21#ifndef _ASM_SYSTEM_H
22#define _ASM_SYSTEM_H
23
24#include <linux/linkage.h>
25#include <linux/irqflags.h>
26#include <asm/atomic.h>
27#include <asm/hexagon_vm.h>
28
29struct thread_struct;
30
31extern struct task_struct *__switch_to(struct task_struct *,
32 struct task_struct *,
33 struct task_struct *);
34
35#define switch_to(p, n, r) do {\
36 r = __switch_to((p), (n), (r));\
37} while (0)
38
39
40#define rmb() barrier()
41#define read_barrier_depends() barrier()
42#define wmb() barrier()
43#define mb() barrier()
44#define smp_rmb() barrier()
45#define smp_read_barrier_depends() barrier()
46#define smp_wmb() barrier()
47#define smp_mb() barrier()
48#define smp_mb__before_atomic_dec() barrier()
49#define smp_mb__after_atomic_dec() barrier()
50#define smp_mb__before_atomic_inc() barrier()
51#define smp_mb__after_atomic_inc() barrier()
52
53/*
54 * __xchg - atomically exchange a register and a memory location
55 * @x: value to swap
56 * @ptr: pointer to memory
57 * @size: size of the value
58 *
59 * Only 4 bytes supported currently.
60 *
61 * Note: there was an errata for V2 about .new's and memw_locked.
62 *
63 */
64static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
65 int size)
66{
67 unsigned long retval;
68
69 /* Can't seem to use printk or panic here, so just stop */
70 if (size != 4) do { asm volatile("brkpt;\n"); } while (1);
71
72 __asm__ __volatile__ (
73 "1: %0 = memw_locked(%1);\n" /* load into retval */
74 " memw_locked(%1,P0) = %2;\n" /* store into memory */
75 " if !P0 jump 1b;\n"
76 : "=&r" (retval)
77 : "r" (ptr), "r" (x)
78 : "memory", "p0"
79 );
80 return retval;
81}
82
83/*
84 * Atomically swap the contents of a register with memory. Should be atomic
85 * between multiple CPU's and within interrupts on the same CPU.
86 */
87#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
88 sizeof(*(ptr))))
89
90/* Set a value and use a memory barrier. Used by the scheduler somewhere. */
91#define set_mb(var, value) \
92 do { var = value; mb(); } while (0)
93
94/*
95 * see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
96 * looks just like atomic_cmpxchg on our arch currently with a bunch of
97 * variable casting.
98 */
99#define __HAVE_ARCH_CMPXCHG 1
100
101#define cmpxchg(ptr, old, new) \
102({ \
103 __typeof__(ptr) __ptr = (ptr); \
104 __typeof__(*(ptr)) __old = (old); \
105 __typeof__(*(ptr)) __new = (new); \
106 __typeof__(*(ptr)) __oldval = 0; \
107 \
108 asm volatile( \
109 "1: %0 = memw_locked(%1);\n" \
110 " { P0 = cmp.eq(%0,%2);\n" \
111 " if (!P0.new) jump:nt 2f; }\n" \
112 " memw_locked(%1,p0) = %3;\n" \
113 " if (!P0) jump 1b;\n" \
114 "2:\n" \
115 : "=&r" (__oldval) \
116 : "r" (__ptr), "r" (__old), "r" (__new) \
117 : "memory", "p0" \
118 ); \
119 __oldval; \
120})
121
122/* Should probably shoot for an 8-byte aligned stack pointer */
123#define STACK_MASK (~7)
124#define arch_align_stack(x) (x & STACK_MASK)
125
126#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 04:44:09 -0500