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authorThomas Gleixner <tglx@linutronix.de>2011-03-29 09:05:13 -0400
committerDavid Howells <dhowells@redhat.com>2011-03-29 09:05:13 -0400
commit60af3ab1e6b0b7a1bdbb7392134c27e6be9630df (patch)
tree21a55b8c9bc64fc099ab2136df9db70d044f5ca8 /arch/frv/kernel
parenta9554c3a5d02d50aeff08203ca8dd1e2dffdaa0d (diff)
FRV: Convert genirq namespace
Convert to new function names. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/frv/kernel')
-rw-r--r--arch/frv/kernel/irq-mb93091.c4
-rw-r--r--arch/frv/kernel/irq-mb93093.c2
-rw-r--r--arch/frv/kernel/irq-mb93493.c3
-rw-r--r--arch/frv/kernel/irq.c4
4 files changed, 7 insertions, 6 deletions
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
index f007aaf1426b..9afc2ea400dc 100644
--- a/arch/frv/kernel/irq-mb93091.c
+++ b/arch/frv/kernel/irq-mb93091.c
@@ -146,9 +146,9 @@ void __init fpga_init(void)
146 __clr_IFR(0x0000); 146 __clr_IFR(0x0000);
147 147
148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) 148 for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
149 set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); 149 irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
150 150
151 set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); 151 irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
152 152
153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ 153 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */
154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); 154 setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
index c7027fba6c04..4d4ad09d3c91 100644
--- a/arch/frv/kernel/irq-mb93093.c
+++ b/arch/frv/kernel/irq-mb93093.c
@@ -124,7 +124,7 @@ void __init fpga_init(void)
124 __clr_IFR(0x0000); 124 __clr_IFR(0x0000);
125 125
126 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++) 126 for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
127 set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); 127 irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
128 128
129 /* the FPGA drives external IRQ input #2 on the CPU PIC */ 129 /* the FPGA drives external IRQ input #2 on the CPU PIC */
130 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]); 130 setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
index 4800f2402ecb..4d034c7840c9 100644
--- a/arch/frv/kernel/irq-mb93493.c
+++ b/arch/frv/kernel/irq-mb93493.c
@@ -139,7 +139,8 @@ void __init mb93493_init(void)
139 int irq; 139 int irq;
140 140
141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++) 141 for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
142 set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq); 142 irq_set_chip_and_handler(irq, &frv_mb93493_pic,
143 handle_edge_irq);
143 144
144 /* the MB93493 drives external IRQ inputs on the CPU PIC */ 145 /* the MB93493 drives external IRQ inputs on the CPU PIC */
145 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]); 146 setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
index d2365a7d7c57..a5631e940a00 100644
--- a/arch/frv/kernel/irq.c
+++ b/arch/frv/kernel/irq.c
@@ -156,10 +156,10 @@ void __init init_IRQ(void)
156 int level; 156 int level;
157 157
158 for (level = 1; level <= 14; level++) 158 for (level = 1; level <= 14; level++)
159 set_irq_chip_and_handler(level, &frv_cpu_pic, 159 irq_set_chip_and_handler(level, &frv_cpu_pic,
160 handle_level_irq); 160 handle_level_irq);
161 161
162 set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq); 162 irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
163 163
164 /* set the trigger levels for internal interrupt sources 164 /* set the trigger levels for internal interrupt sources
165 * - timers all falling-edge 165 * - timers all falling-edge