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authorDavid Howells <dhowells@redhat.com>2007-11-28 19:22:05 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-29 12:24:54 -0500
commit3c835670ab5f72a4ea2d0db232b1acc07924f186 (patch)
tree32d632e21f6788427d6d7a0a3ae538e124c82c1d /arch/frv/kernel/vmlinux.lds.S
parent9e6c1e633355b69803094ecbac4cecc96e00965c (diff)
FRV: arrange things such that BRA can reach from the trap table
Arrange the sections in the FRV arch so that a BRA instruction with a 16-bit displacement can always reach from the trap table to entry.S, tlb-miss.S and break.S. The problem otherwise is that the linker can insert sufficient code between the slots in the trap table and the targets of the branch instructions in those slots that the displacement field in the instruction isn't sufficiently large. This is because the branch targets were in the .text section along with most of the other code in the kernel. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/frv/kernel/vmlinux.lds.S')
-rw-r--r--arch/frv/kernel/vmlinux.lds.S27
1 files changed, 15 insertions, 12 deletions
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
index 3b71e0c86399..a17a81d58bf6 100644
--- a/arch/frv/kernel/vmlinux.lds.S
+++ b/arch/frv/kernel/vmlinux.lds.S
@@ -76,6 +76,12 @@ SECTIONS
76 *(.data.init_task) 76 *(.data.init_task)
77 } 77 }
78 78
79 . = ALIGN(4096);
80 .data.page_aligned : { *(.data.idt) }
81
82 . = ALIGN(L1_CACHE_BYTES);
83 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
84
79 .trap : { 85 .trap : {
80 /* trap table management - read entry-table.S before modifying */ 86 /* trap table management - read entry-table.S before modifying */
81 . = ALIGN(8192); 87 . = ALIGN(8192);
@@ -86,28 +92,25 @@ SECTIONS
86 *(.trap.break) 92 *(.trap.break)
87 } 93 }
88 94
89 . = ALIGN(4096);
90 .data.page_aligned : { *(.data.idt) }
91
92 . = ALIGN(L1_CACHE_BYTES);
93 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
94
95 /* Text and read-only data */ 95 /* Text and read-only data */
96 . = ALIGN(4); 96 . = ALIGN(4);
97 _text = .; 97 _text = .;
98 _stext = .; 98 _stext = .;
99 .text : { 99 .text : {
100 *( 100 *(.text.start)
101 .text.start .text.* 101 *(.text.entry)
102 *(.text.break)
103 *(.text.tlbmiss)
104 TEXT_TEXT
105 SCHED_TEXT
106 LOCK_TEXT
102#ifdef CONFIG_DEBUG_INFO 107#ifdef CONFIG_DEBUG_INFO
108 *(
103 .init.text 109 .init.text
104 .exit.text 110 .exit.text
105 .exitcall.exit 111 .exitcall.exit
106#endif
107 ) 112 )
108 TEXT_TEXT 113#endif
109 SCHED_TEXT
110 LOCK_TEXT
111 *(.fixup) 114 *(.fixup)
112 *(.gnu.warning) 115 *(.gnu.warning)
113 *(.exitcall.exit) 116 *(.exitcall.exit)