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authorFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>2010-08-10 21:03:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-11 11:59:21 -0400
commita6eb9fe105d5de0053b261148cee56c94b4720ca (patch)
tree36e3f324a6a768397ef398674176c0f5f5365bff /arch/frv/include
parentcd1542c8197fc3c2eb3a8301505d5d9738fab1e4 (diff)
dma-mapping: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN
Now each architecture has the own dma_get_cache_alignment implementation. dma_get_cache_alignment returns the minimum DMA alignment. Architectures define it as ARCH_KMALLOC_MINALIGN (it's used to make sure that malloc'ed buffer is DMA-safe; the buffer doesn't share a cache with the others). So we can unify dma_get_cache_alignment implementations. This patch: dma_get_cache_alignment() needs to know if an architecture defines ARCH_KMALLOC_MINALIGN or not (needs to know if architecture has DMA alignment restriction). However, slab.h define ARCH_KMALLOC_MINALIGN if architectures doesn't define it. Let's rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN. ARCH_KMALLOC_MINALIGN is used only in the internals of slab/slob/slub (except for crypto). Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/frv/include')
-rw-r--r--arch/frv/include/asm/mem-layout.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h
index ccae981876fa..e9a0ec85a402 100644
--- a/arch/frv/include/asm/mem-layout.h
+++ b/arch/frv/include/asm/mem-layout.h
@@ -35,7 +35,7 @@
35 * the slab must be aligned such that load- and store-double instructions don't 35 * the slab must be aligned such that load- and store-double instructions don't
36 * fault if used 36 * fault if used
37 */ 37 */
38#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES 38#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
39#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES 39#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
40 40
41/*****************************************************************************/ 41/*****************************************************************************/