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authorThomas Gleixner <tglx@linutronix.de>2011-01-19 08:05:30 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-01-21 05:55:25 -0500
commit9af7503dbd9c4c5e11fcf253ac93fefc9793dff8 (patch)
tree065ab177741131b0449621d7edab7459887e95d4 /arch/cris
parentf7a004baa202f919d060c2da250535b085813a4b (diff)
cris: Convert V32 interrupt handling
Convert the irq chip functions and install handle_simple_irq for each interrupt to get rid of __do_IRQ() Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Mikael Starvik <starvik@axis.com>
Diffstat (limited to 'arch/cris')
-rw-r--r--arch/cris/arch-v32/kernel/irq.c50
1 files changed, 15 insertions, 35 deletions
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 2ed48ae3d313..0ad9db5126c7 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq)
291} 291}
292 292
293 293
294static unsigned int startup_crisv32_irq(unsigned int irq) 294static void enable_crisv32_irq(struct irq_data *data)
295{ 295{
296 crisv32_unmask_irq(irq); 296 crisv32_unmask_irq(data->irq);
297 return 0;
298}
299
300static void shutdown_crisv32_irq(unsigned int irq)
301{
302 crisv32_mask_irq(irq);
303} 297}
304 298
305static void enable_crisv32_irq(unsigned int irq) 299static void disable_crisv32_irq(struct irq_data *data)
306{ 300{
307 crisv32_unmask_irq(irq); 301 crisv32_mask_irq(data->irq);
308} 302}
309 303
310static void disable_crisv32_irq(unsigned int irq) 304static int set_affinity_crisv32_irq(struct irq_data *data,
311{ 305 const struct cpumask *dest, bool force)
312 crisv32_mask_irq(irq);
313}
314
315static void ack_crisv32_irq(unsigned int irq)
316{
317}
318
319static void end_crisv32_irq(unsigned int irq)
320{
321}
322
323int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
324{ 306{
325 unsigned long flags; 307 unsigned long flags;
308
326 spin_lock_irqsave(&irq_lock, flags); 309 spin_lock_irqsave(&irq_lock, flags);
327 irq_allocations[irq - FIRST_IRQ].mask = *dest; 310 irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
328 spin_unlock_irqrestore(&irq_lock, flags); 311 spin_unlock_irqrestore(&irq_lock, flags);
329
330 return 0; 312 return 0;
331} 313}
332 314
333static struct irq_chip crisv32_irq_type = { 315static struct irq_chip crisv32_irq_type = {
334 .name = "CRISv32", 316 .name = "CRISv32",
335 .startup = startup_crisv32_irq, 317 .irq_shutdown = disable_crisv32_irq,
336 .shutdown = shutdown_crisv32_irq, 318 .irq_enable = enable_crisv32_irq,
337 .enable = enable_crisv32_irq, 319 .irq_disable = disable_crisv32_irq,
338 .disable = disable_crisv32_irq, 320 .irq_set_affinity = set_affinity_crisv32_irq,
339 .ack = ack_crisv32_irq,
340 .end = end_crisv32_irq,
341 .set_affinity = set_affinity_crisv32_irq
342}; 321};
343 322
344void 323void
@@ -472,7 +451,8 @@ init_IRQ(void)
472 451
473 /* Point all IRQ's to bad handlers. */ 452 /* Point all IRQ's to bad handlers. */
474 for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { 453 for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
475 irq_desc[j].chip = &crisv32_irq_type; 454 set_irq_chip_and_handler(j, &crisv32_irq_type,
455 handle_simple_irq);
476 set_exception_vector(i, interrupt[j]); 456 set_exception_vector(i, interrupt[j]);
477 } 457 }
478 458