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authorJesper Nilsson <jesper.nilsson@axis.com>2010-08-04 04:49:17 -0400
committerJesper Nilsson <jesper.nilsson@axis.com>2010-08-04 07:02:36 -0400
commit6f09963caf5ff7cb4b8de600caee3ff016e97139 (patch)
tree828df837a9f1cc945195f82f4227d51fa646c572 /arch/cris
parentda2af0a771caa8f8cff9c7bfc979f0510eb0faea (diff)
CRIS: New DMA defines for ARTPEC-3
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch/cris')
-rw-r--r--arch/cris/include/arch-v32/mach-a3/mach/dma.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
index 9e8eb13b601d..f01dca1ad108 100644
--- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h
+++ b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
@@ -5,6 +5,33 @@
5 5
6#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ 6#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
7 7
8#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */
9#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */
10
11#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */
12#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */
13
14#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */
15#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */
16
17#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */
18#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */
19
20#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
21#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
22
23#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */
24#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */
25
26#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */
27#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */
28
29#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */
30#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */
31
32#define dma_eth0 dma_eth
33#define dma_eth1 dma_eth
34
8enum dma_owner { 35enum dma_owner {
9 dma_eth, 36 dma_eth,
10 dma_ser0, 37 dma_ser0,