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authorJesper Nilsson <jesper.nilsson@axis.com>2008-10-21 11:45:58 -0400
committerJesper Nilsson <jesper.nilsson@axis.com>2008-10-29 12:29:44 -0400
commit556dcee7b829e5c350c3ffdbdb87a8b15aa3c5d3 (patch)
tree26485b0d92eedcba6c0c96d4069469041aaf7106 /arch/cris/include/arch-v10
parent242bfafc8e42da4697c1e2dea108049d14dbac4b (diff)
[CRIS] Move header files from include to arch/cris/include.
Change all users of header files to correct path. Remove some unneeded headers for arch-v32. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch/cris/include/arch-v10')
-rw-r--r--arch/cris/include/arch-v10/arch/Kbuild4
-rw-r--r--arch/cris/include/arch-v10/arch/atomic.h7
-rw-r--r--arch/cris/include/arch-v10/arch/bitops.h73
-rw-r--r--arch/cris/include/arch-v10/arch/bug.h66
-rw-r--r--arch/cris/include/arch-v10/arch/byteorder.h26
-rw-r--r--arch/cris/include/arch-v10/arch/cache.h8
-rw-r--r--arch/cris/include/arch-v10/arch/checksum.h29
-rw-r--r--arch/cris/include/arch-v10/arch/delay.h20
-rw-r--r--arch/cris/include/arch-v10/arch/dma.h74
-rw-r--r--arch/cris/include/arch-v10/arch/elf.h81
-rw-r--r--arch/cris/include/arch-v10/arch/io.h199
-rw-r--r--arch/cris/include/arch-v10/arch/io_interface_mux.h75
-rw-r--r--arch/cris/include/arch-v10/arch/irq.h160
-rw-r--r--arch/cris/include/arch-v10/arch/memmap.h22
-rw-r--r--arch/cris/include/arch-v10/arch/mmu.h109
-rw-r--r--arch/cris/include/arch-v10/arch/offset.h33
-rw-r--r--arch/cris/include/arch-v10/arch/page.h30
-rw-r--r--arch/cris/include/arch-v10/arch/pgtable.h17
-rw-r--r--arch/cris/include/arch-v10/arch/processor.h70
-rw-r--r--arch/cris/include/arch-v10/arch/ptrace.h119
-rw-r--r--arch/cris/include/arch-v10/arch/sv_addr.agh7306
-rw-r--r--arch/cris/include/arch-v10/arch/sv_addr_ag.h139
-rw-r--r--arch/cris/include/arch-v10/arch/svinto.h64
-rw-r--r--arch/cris/include/arch-v10/arch/system.h63
-rw-r--r--arch/cris/include/arch-v10/arch/thread_info.h12
-rw-r--r--arch/cris/include/arch-v10/arch/timex.h30
-rw-r--r--arch/cris/include/arch-v10/arch/tlb.h13
-rw-r--r--arch/cris/include/arch-v10/arch/uaccess.h660
-rw-r--r--arch/cris/include/arch-v10/arch/unistd.h148
-rw-r--r--arch/cris/include/arch-v10/arch/user.h46
30 files changed, 9703 insertions, 0 deletions
diff --git a/arch/cris/include/arch-v10/arch/Kbuild b/arch/cris/include/arch-v10/arch/Kbuild
new file mode 100644
index 000000000000..7a192e1290b1
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/Kbuild
@@ -0,0 +1,4 @@
1header-y += user.h
2header-y += svinto.h
3header-y += sv_addr_ag.h
4header-y += sv_addr.agh
diff --git a/arch/cris/include/arch-v10/arch/atomic.h b/arch/cris/include/arch-v10/arch/atomic.h
new file mode 100644
index 000000000000..6ef5e7d09024
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/atomic.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_CRIS_ARCH_ATOMIC__
2#define __ASM_CRIS_ARCH_ATOMIC__
3
4#define cris_atomic_save(addr, flags) local_irq_save(flags);
5#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
6
7#endif
diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h
new file mode 100644
index 000000000000..be85f6de25d3
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/bitops.h
@@ -0,0 +1,73 @@
1/* asm/arch/bitops.h for Linux/CRISv10 */
2
3#ifndef _CRIS_ARCH_BITOPS_H
4#define _CRIS_ARCH_BITOPS_H
5
6/*
7 * Helper functions for the core of the ff[sz] functions, wrapping the
8 * syntactically awkward asms. The asms compute the number of leading
9 * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped
10 * number. They differ in that the first function also inverts all bits
11 * in the input.
12 */
13static inline unsigned long cris_swapnwbrlz(unsigned long w)
14{
15 /* Let's just say we return the result in the same register as the
16 input. Saying we clobber the input but can return the result
17 in another register:
18 ! __asm__ ("swapnwbr %2\n\tlz %2,%0"
19 ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
20 confuses gcc (sched.c, gcc from cris-dist-1.14). */
21
22 unsigned long res;
23 __asm__ ("swapnwbr %0 \n\t"
24 "lz %0,%0"
25 : "=r" (res) : "0" (w));
26 return res;
27}
28
29static inline unsigned long cris_swapwbrlz(unsigned long w)
30{
31 unsigned res;
32 __asm__ ("swapwbr %0 \n\t"
33 "lz %0,%0"
34 : "=r" (res)
35 : "0" (w));
36 return res;
37}
38
39/*
40 * ffz = Find First Zero in word. Undefined if no zero exists,
41 * so code should check against ~0UL first..
42 */
43static inline unsigned long ffz(unsigned long w)
44{
45 return cris_swapnwbrlz(w);
46}
47
48/**
49 * __ffs - find first bit in word.
50 * @word: The word to search
51 *
52 * Undefined if no bit exists, so code should check against 0 first.
53 */
54static inline unsigned long __ffs(unsigned long word)
55{
56 return cris_swapnwbrlz(~word);
57}
58
59/**
60 * ffs - find first bit set
61 * @x: the word to search
62 *
63 * This is defined the same way as
64 * the libc and compiler builtin ffs routines, therefore
65 * differs in spirit from the above ffz (man ffs).
66 */
67
68static inline unsigned long kernel_ffs(unsigned long w)
69{
70 return w ? cris_swapwbrlz (w) + 1 : 0;
71}
72
73#endif
diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h
new file mode 100644
index 000000000000..3485d6b34bb0
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/bug.h
@@ -0,0 +1,66 @@
1#ifndef __ASM_CRISv10_ARCH_BUG_H
2#define __ASM_CRISv10_ARCH_BUG_H
3
4#include <linux/stringify.h>
5
6#ifdef CONFIG_BUG
7#ifdef CONFIG_DEBUG_BUGVERBOSE
8/* The BUG() macro is used for marking obviously incorrect code paths.
9 * It will cause a message with the file name and line number to be printed,
10 * and then cause an oops. The message is actually printed by handle_BUG()
11 * in arch/cris/kernel/traps.c, and the reason we use this method of storing
12 * the file name and line number is that we do not want to affect the registers
13 * by calling printk() before causing the oops.
14 */
15
16#define BUG_PREFIX 0x0D7F
17#define BUG_MAGIC 0x00001234
18
19struct bug_frame {
20 unsigned short prefix;
21 unsigned int magic;
22 unsigned short clear;
23 unsigned short movu;
24 unsigned short line;
25 unsigned short jump;
26 unsigned char *filename;
27};
28
29#if 0
30/* Unfortunately this version of the macro does not work due to a problem
31 * with the compiler (aka a bug) when compiling with -O2, which sometimes
32 * erroneously causes the second input to be stored in a register...
33 */
34#define BUG() \
35 __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
36 "movu.w %0,$r0\n\t" \
37 "jump %1\n\t" \
38 : : "i" (__LINE__), "i" (__FILE__))
39#else
40/* This version will have to do for now, until the compiler is fixed.
41 * The drawbacks of this version are that the file name will appear multiple
42 * times in the .rodata section, and that __LINE__ and __FILE__ can probably
43 * not be used like this with newer versions of gcc.
44 */
45#define BUG() \
46 __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
47 "movu.w " __stringify(__LINE__) ",$r0\n\t"\
48 "jump 0f\n\t" \
49 ".section .rodata\n" \
50 "0:\t.string \"" __FILE__ "\"\n\t" \
51 ".previous")
52#endif
53
54#else
55
56/* This just causes an oops. */
57#define BUG() (*(int *)0 = 0)
58
59#endif
60
61#define HAVE_ARCH_BUG
62#endif
63
64#include <asm-generic/bug.h>
65
66#endif
diff --git a/arch/cris/include/arch-v10/arch/byteorder.h b/arch/cris/include/arch-v10/arch/byteorder.h
new file mode 100644
index 000000000000..255b646b7fa8
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/byteorder.h
@@ -0,0 +1,26 @@
1#ifndef _CRIS_ARCH_BYTEORDER_H
2#define _CRIS_ARCH_BYTEORDER_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7/* we just define these two (as we can do the swap in a single
8 * asm instruction in CRIS) and the arch-independent files will put
9 * them together into ntohl etc.
10 */
11
12static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
13{
14 __asm__ ("swapwb %0" : "=r" (x) : "0" (x));
15
16 return(x);
17}
18
19static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
20{
21 __asm__ ("swapb %0" : "=r" (x) : "0" (x));
22
23 return(x);
24}
25
26#endif
diff --git a/arch/cris/include/arch-v10/arch/cache.h b/arch/cris/include/arch-v10/arch/cache.h
new file mode 100644
index 000000000000..aea27184d2d2
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/cache.h
@@ -0,0 +1,8 @@
1#ifndef _ASM_ARCH_CACHE_H
2#define _ASM_ARCH_CACHE_H
3
4/* Etrax 100LX have 32-byte cache-lines. */
5#define L1_CACHE_BYTES 32
6#define L1_CACHE_SHIFT 5
7
8#endif /* _ASM_ARCH_CACHE_H */
diff --git a/arch/cris/include/arch-v10/arch/checksum.h b/arch/cris/include/arch-v10/arch/checksum.h
new file mode 100644
index 000000000000..b8000c5d7fe1
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/checksum.h
@@ -0,0 +1,29 @@
1#ifndef _CRIS_ARCH_CHECKSUM_H
2#define _CRIS_ARCH_CHECKSUM_H
3
4/* Checksum some values used in TCP/UDP headers.
5 *
6 * The gain by doing this in asm is that C will not generate carry-additions
7 * for the 32-bit components of the checksum, so otherwise we would have had
8 * to split all of those into 16-bit components, then add.
9 */
10
11static inline __wsum
12csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
13 unsigned short proto, __wsum sum)
14{
15 __wsum res;
16 __asm__ ("add.d %2, %0\n\t"
17 "ax\n\t"
18 "add.d %3, %0\n\t"
19 "ax\n\t"
20 "add.d %4, %0\n\t"
21 "ax\n\t"
22 "addq 0, %0\n"
23 : "=r" (res)
24 : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8));
25
26 return res;
27}
28
29#endif
diff --git a/arch/cris/include/arch-v10/arch/delay.h b/arch/cris/include/arch-v10/arch/delay.h
new file mode 100644
index 000000000000..39481f6e0c30
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/delay.h
@@ -0,0 +1,20 @@
1#ifndef _CRIS_ARCH_DELAY_H
2#define _CRIS_ARCH_DELAY_H
3
4static inline void __delay(int loops)
5{
6 __asm__ __volatile__ (
7 "move.d %0,$r9\n\t"
8 "beq 2f\n\t"
9 "subq 1,$r9\n\t"
10 "1:\n\t"
11 "bne 1b\n\t"
12 "subq 1,$r9\n"
13 "2:"
14 : : "g" (loops) : "r9");
15}
16
17#endif /* defined(_CRIS_ARCH_DELAY_H) */
18
19
20
diff --git a/arch/cris/include/arch-v10/arch/dma.h b/arch/cris/include/arch-v10/arch/dma.h
new file mode 100644
index 000000000000..ecb9dba6fa4f
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/dma.h
@@ -0,0 +1,74 @@
1/* Defines for using and allocating dma channels. */
2
3#ifndef _ASM_ARCH_DMA_H
4#define _ASM_ARCH_DMA_H
5
6#define MAX_DMA_CHANNELS 10
7
8/* dma0 and dma1 used for network (ethernet) */
9#define NETWORK_TX_DMA_NBR 0
10#define NETWORK_RX_DMA_NBR 1
11
12/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
13#define PAR0_TX_DMA_NBR 2
14#define PAR0_RX_DMA_NBR 3
15#define SCSI0_TX_DMA_NBR 2
16#define SCSI0_RX_DMA_NBR 3
17#define SER2_TX_DMA_NBR 2
18#define SER2_RX_DMA_NBR 3
19#define ATA_TX_DMA_NBR 2
20#define ATA_RX_DMA_NBR 3
21
22/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
23#define PAR1_TX_DMA_NBR 4
24#define PAR1_RX_DMA_NBR 5
25#define SCSI1_TX_DMA_NBR 4
26#define SCSI1_RX_DMA_NBR 5
27#define SER3_TX_DMA_NBR 4
28#define SER3_RX_DMA_NBR 5
29#define EXTDMA0_TX_DMA_NBR 4
30#define EXTDMA0_RX_DMA_NBR 5
31
32/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
33#define SER0_TX_DMA_NBR 6
34#define SER0_RX_DMA_NBR 7
35#define EXTDMA1_TX_DMA_NBR 6
36#define EXTDMA1_RX_DMA_NBR 7
37#define MEM2MEM_TX_DMA_NBR 6
38#define MEM2MEM_RX_DMA_NBR 7
39
40/* dma8 and dma9 shared by ser1 and usb */
41#define SER1_TX_DMA_NBR 8
42#define SER1_RX_DMA_NBR 9
43#define USB_TX_DMA_NBR 8
44#define USB_RX_DMA_NBR 9
45
46#endif
47
48enum dma_owner
49{
50 dma_eth,
51 dma_ser0,
52 dma_ser1, /* Async and sync */
53 dma_ser2,
54 dma_ser3, /* Async and sync */
55 dma_ata,
56 dma_par0,
57 dma_par1,
58 dma_ext0,
59 dma_ext1,
60 dma_int6,
61 dma_int7,
62 dma_usb,
63 dma_scsi0,
64 dma_scsi1
65};
66
67/* Masks used by cris_request_dma options: */
68#define DMA_VERBOSE_ON_ERROR (1<<0)
69#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
70
71int cris_request_dma(unsigned int dmanr, const char * device_id,
72 unsigned options, enum dma_owner owner);
73
74void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/arch/cris/include/arch-v10/arch/elf.h b/arch/cris/include/arch-v10/arch/elf.h
new file mode 100644
index 000000000000..1c38ee728b17
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/elf.h
@@ -0,0 +1,81 @@
1#ifndef __ASMCRIS_ARCH_ELF_H
2#define __ASMCRIS_ARCH_ELF_H
3
4#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
5
6/*
7 * This is used to ensure we don't load something for the wrong architecture.
8 */
9#define elf_check_arch(x) \
10 ((x)->e_machine == EM_CRIS \
11 && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \
12 || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
13
14/*
15 * ELF register definitions..
16 */
17
18#include <asm/ptrace.h>
19
20/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
21 starts (a register; assume first param register for CRIS)
22 contains a pointer to a function which might be
23 registered using `atexit'. This provides a mean for the
24 dynamic linker to call DT_FINI functions for shared libraries
25 that have been loaded before the code runs.
26
27 A value of 0 tells we have no such handler. */
28
29/* Explicitly set registers to 0 to increase determinism. */
30#define ELF_PLAT_INIT(_r, load_addr) do { \
31 (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
32 (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
33 (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
34 (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
35} while (0)
36
37/* The additional layer below is because the stack pointer is missing in
38 the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t,
39 and should be filled in according to the layout of the user_regs_struct
40 struct; regs is a pt_regs struct. We dump all registers, though several are
41 obviously unnecessary. That way there's less need for intelligence at
42 the receiving end (i.e. gdb). */
43#define ELF_CORE_COPY_REGS(pr_reg, regs) \
44 pr_reg[0] = regs->r0; \
45 pr_reg[1] = regs->r1; \
46 pr_reg[2] = regs->r2; \
47 pr_reg[3] = regs->r3; \
48 pr_reg[4] = regs->r4; \
49 pr_reg[5] = regs->r5; \
50 pr_reg[6] = regs->r6; \
51 pr_reg[7] = regs->r7; \
52 pr_reg[8] = regs->r8; \
53 pr_reg[9] = regs->r9; \
54 pr_reg[10] = regs->r10; \
55 pr_reg[11] = regs->r11; \
56 pr_reg[12] = regs->r12; \
57 pr_reg[13] = regs->r13; \
58 pr_reg[14] = rdusp(); /* sp */ \
59 pr_reg[15] = regs->irp; /* pc */ \
60 pr_reg[16] = 0; /* p0 */ \
61 pr_reg[17] = rdvr(); /* vr */ \
62 pr_reg[18] = 0; /* p2 */ \
63 pr_reg[19] = 0; /* p3 */ \
64 pr_reg[20] = 0; /* p4 */ \
65 pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \
66 pr_reg[22] = 0; /* p6 */ \
67 pr_reg[23] = regs->mof; /* mof */ \
68 pr_reg[24] = 0; /* p8 */ \
69 pr_reg[25] = 0; /* ibr */ \
70 pr_reg[26] = 0; /* irp */ \
71 pr_reg[27] = regs->srp; /* srp */ \
72 pr_reg[28] = 0; /* bar */ \
73 pr_reg[29] = regs->dccr; /* dccr */ \
74 pr_reg[30] = 0; /* brp */ \
75 pr_reg[31] = rdusp(); /* usp */ \
76 pr_reg[32] = 0; /* csrinstr */ \
77 pr_reg[33] = 0; /* csraddr */ \
78 pr_reg[34] = 0; /* csrdata */
79
80
81#endif
diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h
new file mode 100644
index 000000000000..f627ad0b8a3d
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/io.h
@@ -0,0 +1,199 @@
1#ifndef _ASM_ARCH_CRIS_IO_H
2#define _ASM_ARCH_CRIS_IO_H
3
4#include <arch/svinto.h>
5
6/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
7
8extern unsigned long gen_config_ii_shadow;
9extern unsigned long port_g_data_shadow;
10extern unsigned char port_pa_dir_shadow;
11extern unsigned char port_pa_data_shadow;
12extern unsigned char port_pb_i2c_shadow;
13extern unsigned char port_pb_config_shadow;
14extern unsigned char port_pb_dir_shadow;
15extern unsigned char port_pb_data_shadow;
16extern unsigned long r_timer_ctrl_shadow;
17
18extern unsigned long port_cse1_shadow;
19extern unsigned long port_csp0_shadow;
20extern unsigned long port_csp4_shadow;
21
22extern volatile unsigned long *port_cse1_addr;
23extern volatile unsigned long *port_csp0_addr;
24extern volatile unsigned long *port_csp4_addr;
25
26/* macro for setting regs through a shadow -
27 * r = register name (like R_PORT_PA_DATA)
28 * s = shadow name (like port_pa_data_shadow)
29 * b = bit number
30 * v = value (0 or 1)
31 */
32
33#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b))
34
35/* The LED's on various Etrax-based products are set differently. */
36
37#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM)
38#undef CONFIG_ETRAX_PA_LEDS
39#undef CONFIG_ETRAX_PB_LEDS
40#undef CONFIG_ETRAX_CSP0_LEDS
41#define CRIS_LED_NETWORK_SET_G(x)
42#define CRIS_LED_NETWORK_SET_R(x)
43#define CRIS_LED_ACTIVE_SET_G(x)
44#define CRIS_LED_ACTIVE_SET_R(x)
45#define CRIS_LED_DISK_WRITE(x)
46#define CRIS_LED_DISK_READ(x)
47#endif
48
49#if !defined(CONFIG_ETRAX_CSP0_LEDS)
50#define CRIS_LED_BIT_SET(x)
51#define CRIS_LED_BIT_CLR(x)
52#endif
53
54#define CRIS_LED_OFF 0x00
55#define CRIS_LED_GREEN 0x01
56#define CRIS_LED_RED 0x02
57#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
58
59#if defined(CONFIG_ETRAX_NO_LEDS)
60#define CRIS_LED_NETWORK_SET(x)
61#else
62#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
63#define CRIS_LED_NETWORK_SET(x) \
64 do { \
65 CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
66 } while (0)
67#else
68#define CRIS_LED_NETWORK_SET(x) \
69 do { \
70 CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
71 CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \
72 } while (0)
73#endif
74#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
75#define CRIS_LED_ACTIVE_SET(x) \
76 do { \
77 CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
78 } while (0)
79#else
80#define CRIS_LED_ACTIVE_SET(x) \
81 do { \
82 CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
83 CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
84 } while (0)
85#endif
86#endif
87
88#ifdef CONFIG_ETRAX_PA_LEDS
89#define CRIS_LED_NETWORK_SET_G(x) \
90 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
91#define CRIS_LED_NETWORK_SET_R(x) \
92 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
93#define CRIS_LED_ACTIVE_SET_G(x) \
94 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
95#define CRIS_LED_ACTIVE_SET_R(x) \
96 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
97#define CRIS_LED_DISK_WRITE(x) \
98 do{\
99 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
100 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
101 }while(0)
102#define CRIS_LED_DISK_READ(x) \
103 REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
104 CONFIG_ETRAX_LED3G, !(x))
105#endif
106
107#ifdef CONFIG_ETRAX_PB_LEDS
108#define CRIS_LED_NETWORK_SET_G(x) \
109 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
110#define CRIS_LED_NETWORK_SET_R(x) \
111 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
112#define CRIS_LED_ACTIVE_SET_G(x) \
113 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
114#define CRIS_LED_ACTIVE_SET_R(x) \
115 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
116#define CRIS_LED_DISK_WRITE(x) \
117 do{\
118 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
119 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
120 }while(0)
121#define CRIS_LED_DISK_READ(x) \
122 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
123 CONFIG_ETRAX_LED3G, !(x))
124#endif
125
126#ifdef CONFIG_ETRAX_CSP0_LEDS
127#define CONFIGURABLE_LEDS\
128 ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\
129 (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\
130 (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\
131 (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\
132 (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\
133 (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\
134 (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\
135 (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\
136 (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
137 (1 << CONFIG_ETRAX_LED12R ))
138
139#define CRIS_LED_NETWORK_SET_G(x) \
140 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
141#define CRIS_LED_NETWORK_SET_R(x) \
142 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
143#define CRIS_LED_ACTIVE_SET_G(x) \
144 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
145#define CRIS_LED_ACTIVE_SET_R(x) \
146 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
147#define CRIS_LED_DISK_WRITE(x) \
148 do{\
149 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
150 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
151 }while(0)
152#define CRIS_LED_DISK_READ(x) \
153 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
154#define CRIS_LED_BIT_SET(x)\
155 do{\
156 if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
157 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
158 }while(0)
159#define CRIS_LED_BIT_CLR(x)\
160 do{\
161 if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
162 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
163 }while(0)
164#endif
165
166#
167#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN
168#define SOFT_SHUTDOWN() \
169 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1)
170#else
171#define SOFT_SHUTDOWN()
172#endif
173
174/* Console I/O for simulated etrax100. Use #ifdef so erroneous
175 use will be evident. */
176#ifdef CONFIG_SVINTO_SIM
177 /* Let's use the ucsim interface since it lets us do write(2, ...) */
178#define SIMCOUT(s,len) \
179 asm ("moveq 4,$r9 \n\t" \
180 "moveq 2,$r10 \n\t" \
181 "move.d %0,$r11 \n\t" \
182 "move.d %1,$r12 \n\t" \
183 "push $irp \n\t" \
184 "move 0f,$irp \n\t" \
185 "jump -6809 \n" \
186 "0: \n\t" \
187 "pop $irp" \
188 : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory")
189#define TRACE_ON() __extension__ \
190 ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \
191 (255)); _Foofoo; })
192
193#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0)
194#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0)
195#define CRIS_CYCLES() __extension__ \
196 ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;})
197#endif /* ! defined CONFIG_SVINTO_SIM */
198
199#endif
diff --git a/arch/cris/include/arch-v10/arch/io_interface_mux.h b/arch/cris/include/arch-v10/arch/io_interface_mux.h
new file mode 100644
index 000000000000..d92500080883
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/io_interface_mux.h
@@ -0,0 +1,75 @@
1/* IO interface mux allocator for ETRAX100LX.
2 * Copyright 2004, Axis Communications AB
3 * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
4 */
5
6
7#ifndef _IO_INTERFACE_MUX_H
8#define _IO_INTERFACE_MUX_H
9
10
11/* C.f. ETRAX100LX Designer's Reference 20.9 */
12
13/* The order in enum must match the order of interfaces[] in
14 * io_interface_mux.c */
15enum cris_io_interface {
16 /* Begin Non-multiplexed interfaces */
17 if_eth = 0,
18 if_serial_0,
19 /* End Non-multiplexed interfaces */
20 if_serial_1,
21 if_serial_2,
22 if_serial_3,
23 if_sync_serial_1,
24 if_sync_serial_3,
25 if_shared_ram,
26 if_shared_ram_w,
27 if_par_0,
28 if_par_1,
29 if_par_w,
30 if_scsi8_0,
31 if_scsi8_1,
32 if_scsi_w,
33 if_ata,
34 if_csp,
35 if_i2c,
36 if_usb_1,
37 if_usb_2,
38 /* GPIO pins */
39 if_gpio_grp_a,
40 if_gpio_grp_b,
41 if_gpio_grp_c,
42 if_gpio_grp_d,
43 if_gpio_grp_e,
44 if_gpio_grp_f,
45 if_max_interfaces,
46 if_unclaimed
47};
48
49int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
50
51void cris_free_io_interface(enum cris_io_interface ioif);
52
53/* port can be 'a', 'b' or 'g' */
54int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
55 const char port,
56 const unsigned start_bit,
57 const unsigned stop_bit);
58
59/* port can be 'a', 'b' or 'g' */
60int cris_io_interface_free_pins(const enum cris_io_interface ioif,
61 const char port,
62 const unsigned start_bit,
63 const unsigned stop_bit);
64
65int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
66 const unsigned int gpio_out_available,
67 const unsigned char pa_available,
68 const unsigned char pb_available));
69
70void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
71 const unsigned int gpio_out_available,
72 const unsigned char pa_available,
73 const unsigned char pb_available));
74
75#endif /* _IO_INTERFACE_MUX_H */
diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h
new file mode 100644
index 000000000000..6248004eca1c
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/irq.h
@@ -0,0 +1,160 @@
1/*
2 * Interrupt handling assembler and defines for Linux/CRISv10
3 */
4
5#ifndef _ASM_ARCH_IRQ_H
6#define _ASM_ARCH_IRQ_H
7
8#include <arch/sv_addr_ag.h>
9
10#define NR_IRQS 32
11
12/* The first vector number used for IRQs in v10 is really 0x20 */
13/* but all the code and constants are offseted to make 0 the first */
14#define FIRST_IRQ 0
15
16#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */
17#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */
18#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
19#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
20/* mio, ata, par0, scsi0 on 4 */
21/* par1, scsi1 on 5 */
22#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
23
24#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
25#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
26/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
27#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
28#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
29
30/* dma0-9 is irq 16..25 */
31/* 16,17: network */
32#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
33#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
34#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
35#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
36
37/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
38#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
39#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
40#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
41#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
42
43/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
44#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
45#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
46#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
47#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
48
49/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
50#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
51#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
52#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
53#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
54#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
55#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
56
57/* 24,25: dma8 and dma9 shared by ser1 and usb */
58#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
59#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
60#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
61#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
62#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
63#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
64
65/* usb: controller at irq 31 + uses DMA8 and DMA9 */
66#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
67
68/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
69
70typedef void (*irqvectptr)(void);
71
72struct etrax_interrupt_vector {
73 irqvectptr v[256];
74};
75
76extern struct etrax_interrupt_vector *etrax_irv;
77void set_int_vector(int n, irqvectptr addr);
78void set_break_vector(int n, irqvectptr addr);
79
80#define __STR(x) #x
81#define STR(x) __STR(x)
82
83/* SAVE_ALL saves registers so they match pt_regs */
84
85#define SAVE_ALL \
86 "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
87 "push $srp\n\t" /* push subroutine return pointer */ \
88 "push $dccr\n\t" /* push condition codes */ \
89 "push $mof\n\t" /* push multiply overflow reg */ \
90 "di\n\t" /* need to disable irq's at this point */\
91 "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \
92 "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
93 "push $r10\n\t" /* push orig_r10 */ \
94 "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
95
96 /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */
97
98#define BLOCK_IRQ(mask,nr) \
99 "move.d " #mask ",$r0\n\t" \
100 "move.d $r0,[0xb00000d8]\n\t"
101
102#define UNBLOCK_IRQ(mask) \
103 "move.d " #mask ",$r0\n\t" \
104 "move.d $r0,[0xb00000dc]\n\t"
105
106#define IRQ_NAME2(nr) nr##_interrupt(void)
107#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
108#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
109#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
110
111 /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
112 * do_IRQ (with irq disabled still). after that it unblocks and jumps to
113 * ret_from_intr (entry.S)
114 *
115 * The reason the IRQ is blocked is to allow an sti() before the handler which
116 * will acknowledge the interrupt is run.
117 */
118
119#define BUILD_IRQ(nr,mask) \
120void IRQ_NAME(nr); \
121__asm__ ( \
122 ".text\n\t" \
123 "IRQ" #nr "_interrupt:\n\t" \
124 SAVE_ALL \
125 BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
126 "moveq "#nr",$r10\n\t" \
127 "move.d $sp,$r11\n\t" \
128 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
129 UNBLOCK_IRQ(mask) \
130 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
131 "jump ret_from_intr\n\t");
132
133/* This is subtle. The timer interrupt is crucial and it should not be disabled for
134 * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
135 * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
136 * If the softirq's take too much time to run, the timer irq won't run and the
137 * watchdog will kill us.
138 *
139 * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
140 * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
141 * it here, we would not get the multiple_irq at all.
142 *
143 * The non-blocking here is based on the knowledge that the timer interrupt is
144 * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
145 * be an sti() before the timer irq handler is run to acknowledge the interrupt.
146 */
147
148#define BUILD_TIMER_IRQ(nr,mask) \
149void IRQ_NAME(nr); \
150__asm__ ( \
151 ".text\n\t" \
152 "IRQ" #nr "_interrupt:\n\t" \
153 SAVE_ALL \
154 "moveq "#nr",$r10\n\t" \
155 "move.d $sp,$r11\n\t" \
156 "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
157 "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
158 "jump ret_from_intr\n\t");
159
160#endif
diff --git a/arch/cris/include/arch-v10/arch/memmap.h b/arch/cris/include/arch-v10/arch/memmap.h
new file mode 100644
index 000000000000..13f3b971407f
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/memmap.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_ARCH_MEMMAP_H
2#define _ASM_ARCH_MEMMAP_H
3
4#define MEM_CSE0_START (0x00000000)
5#define MEM_CSE0_SIZE (0x04000000)
6#define MEM_CSE1_START (0x04000000)
7#define MEM_CSE1_SIZE (0x04000000)
8#define MEM_CSR0_START (0x08000000)
9#define MEM_CSR1_START (0x0c000000)
10#define MEM_CSP0_START (0x10000000)
11#define MEM_CSP1_START (0x14000000)
12#define MEM_CSP2_START (0x18000000)
13#define MEM_CSP3_START (0x1c000000)
14#define MEM_CSP4_START (0x20000000)
15#define MEM_CSP5_START (0x24000000)
16#define MEM_CSP6_START (0x28000000)
17#define MEM_CSP7_START (0x2c000000)
18#define MEM_DRAM_START (0x40000000)
19
20#define MEM_NON_CACHEABLE (0x80000000)
21
22#endif
diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h
new file mode 100644
index 000000000000..df84f1716e6b
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/mmu.h
@@ -0,0 +1,109 @@
1/*
2 * CRIS MMU constants and PTE layout
3 */
4
5#ifndef _CRIS_ARCH_MMU_H
6#define _CRIS_ARCH_MMU_H
7
8/* type used in struct mm to couple an MMU context to an active mm */
9
10typedef struct
11{
12 unsigned int page_id;
13} mm_context_t;
14
15/* kernel memory segments */
16
17#define KSEG_F 0xf0000000UL
18#define KSEG_E 0xe0000000UL
19#define KSEG_D 0xd0000000UL
20#define KSEG_C 0xc0000000UL
21#define KSEG_B 0xb0000000UL
22#define KSEG_A 0xa0000000UL
23#define KSEG_9 0x90000000UL
24#define KSEG_8 0x80000000UL
25#define KSEG_7 0x70000000UL
26#define KSEG_6 0x60000000UL
27#define KSEG_5 0x50000000UL
28#define KSEG_4 0x40000000UL
29#define KSEG_3 0x30000000UL
30#define KSEG_2 0x20000000UL
31#define KSEG_1 0x10000000UL
32#define KSEG_0 0x00000000UL
33
34/* CRIS PTE bits (see R_TLB_LO in the register description)
35 *
36 * Bit: 31-13 12-------4 3 2 1 0
37 * ________________________________________________
38 * | pfn | reserved | global | valid | kernel | we |
39 * |_____|__________|________|_______|________|_____|
40 *
41 * (pfn = physical frame number)
42 */
43
44/* Real HW-based PTE bits. We use some synonym names so that
45 * things become less confusing in combination with the SW-based
46 * bits further below.
47 *
48 */
49
50#define _PAGE_WE (1<<0) /* page is write-enabled */
51#define _PAGE_SILENT_WRITE (1<<0) /* synonym */
52#define _PAGE_KERNEL (1<<1) /* page is kernel only */
53#define _PAGE_VALID (1<<2) /* page is valid */
54#define _PAGE_SILENT_READ (1<<2) /* synonym */
55#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
56
57/* Bits the HW doesn't care about but the kernel uses them in SW */
58
59#define _PAGE_PRESENT (1<<4) /* page present in memory */
60#define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */
61#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */
62#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */
63#define _PAGE_READ (1<<7) /* read-enabled */
64#define _PAGE_WRITE (1<<8) /* write-enabled */
65
66/* Define some higher level generic page attributes. */
67
68#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
69#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
70
71#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
72#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
73
74#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
75#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
76 _PAGE_ACCESSED)
77#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
78#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
79#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
80 _PAGE_PRESENT | __READABLE | __WRITEABLE)
81#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
82
83/*
84 * CRIS can't do page protection for execute, and considers read the same.
85 * Also, write permissions imply read permissions. This is the closest we can
86 * get..
87 */
88
89#define __P000 PAGE_NONE
90#define __P001 PAGE_READONLY
91#define __P010 PAGE_COPY
92#define __P011 PAGE_COPY
93#define __P100 PAGE_READONLY
94#define __P101 PAGE_READONLY
95#define __P110 PAGE_COPY
96#define __P111 PAGE_COPY
97
98#define __S000 PAGE_NONE
99#define __S001 PAGE_READONLY
100#define __S010 PAGE_SHARED
101#define __S011 PAGE_SHARED
102#define __S100 PAGE_READONLY
103#define __S101 PAGE_READONLY
104#define __S110 PAGE_SHARED
105#define __S111 PAGE_SHARED
106
107#define PTE_FILE_MAX_BITS 26
108
109#endif
diff --git a/arch/cris/include/arch-v10/arch/offset.h b/arch/cris/include/arch-v10/arch/offset.h
new file mode 100644
index 000000000000..675b51d85639
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/offset.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_OFFSETS_H__
2#define __ASM_OFFSETS_H__
3/*
4 * DO NOT MODIFY.
5 *
6 * This file was generated by arch/cris/Makefile
7 *
8 */
9
10#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */
11#define PT_r13 8 /* offsetof(struct pt_regs, r13) */
12#define PT_r12 12 /* offsetof(struct pt_regs, r12) */
13#define PT_r11 16 /* offsetof(struct pt_regs, r11) */
14#define PT_r10 20 /* offsetof(struct pt_regs, r10) */
15#define PT_r9 24 /* offsetof(struct pt_regs, r9) */
16#define PT_mof 64 /* offsetof(struct pt_regs, mof) */
17#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */
18#define PT_srp 72 /* offsetof(struct pt_regs, srp) */
19
20#define TI_task 0 /* offsetof(struct thread_info, task) */
21#define TI_flags 8 /* offsetof(struct thread_info, flags) */
22#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
23
24#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
25#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
26#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
27
28#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
29
30#define LCLONE_VM 256 /* CLONE_VM */
31#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
32
33#endif
diff --git a/arch/cris/include/arch-v10/arch/page.h b/arch/cris/include/arch-v10/arch/page.h
new file mode 100644
index 000000000000..ffafc99c3472
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/page.h
@@ -0,0 +1,30 @@
1#ifndef _CRIS_ARCH_PAGE_H
2#define _CRIS_ARCH_PAGE_H
3
4
5#ifdef __KERNEL__
6
7/* This handles the memory map.. */
8#ifdef CONFIG_CRIS_LOW_MAP
9#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */
10#else
11#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */
12#endif
13
14/* macros to convert between really physical and virtual addresses
15 * by stripping a selected bit, we can convert between KSEG_x and
16 * 0x40000000 where the DRAM really resides
17 */
18
19#ifdef CONFIG_CRIS_LOW_MAP
20/* we have DRAM virtually at 0x6 */
21#define __pa(x) ((unsigned long)(x) & 0xdfffffff)
22#define __va(x) ((void *)((unsigned long)(x) | 0x20000000))
23#else
24/* we have DRAM virtually at 0xc */
25#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
26#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
27#endif
28
29#endif
30#endif
diff --git a/arch/cris/include/arch-v10/arch/pgtable.h b/arch/cris/include/arch-v10/arch/pgtable.h
new file mode 100644
index 000000000000..2a2576d1fc97
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/pgtable.h
@@ -0,0 +1,17 @@
1#ifndef _CRIS_ARCH_PGTABLE_H
2#define _CRIS_ARCH_PGTABLE_H
3
4/*
5 * Kernels own virtual memory area.
6 */
7
8#ifdef CONFIG_CRIS_LOW_MAP
9#define VMALLOC_START KSEG_7
10#define VMALLOC_END KSEG_8
11#else
12#define VMALLOC_START KSEG_D
13#define VMALLOC_END KSEG_E
14#endif
15
16#endif
17
diff --git a/arch/cris/include/arch-v10/arch/processor.h b/arch/cris/include/arch-v10/arch/processor.h
new file mode 100644
index 000000000000..cc692c7a0660
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/processor.h
@@ -0,0 +1,70 @@
1#ifndef __ASM_CRIS_ARCH_PROCESSOR_H
2#define __ASM_CRIS_ARCH_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; })
9
10/* CRIS has no problems with write protection */
11#define wp_works_ok 1
12
13/* CRIS thread_struct. this really has nothing to do with the processor itself, since
14 * CRIS does not do any hardware task-switching, but it's here for legacy reasons.
15 * The thread_struct here is used when task-switching using _resume defined in entry.S.
16 * The offsets here are hardcoded into _resume - if you change this struct, you need to
17 * change them as well!!!
18*/
19
20struct thread_struct {
21 unsigned long ksp; /* kernel stack pointer */
22 unsigned long usp; /* user stack pointer */
23 unsigned long dccr; /* saved flag register */
24};
25
26/*
27 * User space process size. This is hardcoded into a few places,
28 * so don't change it unless you know what you are doing.
29 */
30
31#ifdef CONFIG_CRIS_LOW_MAP
32#define TASK_SIZE (0x50000000UL) /* 1.25 GB */
33#else
34#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */
35#endif
36
37#define INIT_THREAD { \
38 0, 0, 0x20 } /* ccr = int enable, nothing else */
39
40#define KSTK_EIP(tsk) \
41({ \
42 unsigned long eip = 0; \
43 unsigned long regs = (unsigned long)task_pt_regs(tsk); \
44 if (regs > PAGE_SIZE && \
45 virt_addr_valid(regs)) \
46 eip = ((struct pt_regs *)regs)->irp; \
47 eip; \
48})
49
50/* give the thread a program location
51 * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8)
52 * switch user-stackpointer
53 */
54
55#define start_thread(regs, ip, usp) do { \
56 set_fs(USER_DS); \
57 regs->irp = ip; \
58 regs->dccr |= 1 << U_DCCR_BITNR; \
59 wrusp(usp); \
60} while(0)
61
62/* Called when handling a kernel bus fault fixup.
63 *
64 * After a fixup we do not want to return by restoring the CPU-state
65 * anymore, so switch frame-types (see ptrace.h)
66 */
67#define arch_fixup(regs) \
68 regs->frametype = CRIS_FRAME_NORMAL;
69
70#endif
diff --git a/arch/cris/include/arch-v10/arch/ptrace.h b/arch/cris/include/arch-v10/arch/ptrace.h
new file mode 100644
index 000000000000..2f464eab3a51
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/ptrace.h
@@ -0,0 +1,119 @@
1#ifndef _CRIS_ARCH_PTRACE_H
2#define _CRIS_ARCH_PTRACE_H
3
4/* Frame types */
5
6#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */
7#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return
8 path */
9
10/* Register numbers in the ptrace system call interface */
11
12#define PT_FRAMETYPE 0
13#define PT_ORIG_R10 1
14#define PT_R13 2
15#define PT_R12 3
16#define PT_R11 4
17#define PT_R10 5
18#define PT_R9 6
19#define PT_R8 7
20#define PT_R7 8
21#define PT_R6 9
22#define PT_R5 10
23#define PT_R4 11
24#define PT_R3 12
25#define PT_R2 13
26#define PT_R1 14
27#define PT_R0 15
28#define PT_MOF 16
29#define PT_DCCR 17
30#define PT_SRP 18
31#define PT_IRP 19 /* This is actually the debugged process' PC */
32#define PT_CSRINSTR 20 /* CPU Status record remnants -
33 valid if frametype == busfault */
34#define PT_CSRADDR 21
35#define PT_CSRDATA 22
36#define PT_USP 23 /* special case - USP is not in the pt_regs */
37#define PT_MAX 23
38
39/* Condition code bit numbers. The same numbers apply to CCR of course,
40 but we use DCCR everywhere else, so let's try and be consistent. */
41#define C_DCCR_BITNR 0
42#define V_DCCR_BITNR 1
43#define Z_DCCR_BITNR 2
44#define N_DCCR_BITNR 3
45#define X_DCCR_BITNR 4
46#define I_DCCR_BITNR 5
47#define B_DCCR_BITNR 6
48#define M_DCCR_BITNR 7
49#define U_DCCR_BITNR 8
50#define P_DCCR_BITNR 9
51#define F_DCCR_BITNR 10
52
53/* pt_regs not only specifices the format in the user-struct during
54 * ptrace but is also the frame format used in the kernel prologue/epilogues
55 * themselves
56 */
57
58struct pt_regs {
59 unsigned long frametype; /* type of stackframe */
60 unsigned long orig_r10;
61 /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */
62 unsigned long r13;
63 unsigned long r12;
64 unsigned long r11;
65 unsigned long r10;
66 unsigned long r9;
67 unsigned long r8;
68 unsigned long r7;
69 unsigned long r6;
70 unsigned long r5;
71 unsigned long r4;
72 unsigned long r3;
73 unsigned long r2;
74 unsigned long r1;
75 unsigned long r0;
76 unsigned long mof;
77 unsigned long dccr;
78 unsigned long srp;
79 unsigned long irp; /* This is actually the debugged process' PC */
80 unsigned long csrinstr;
81 unsigned long csraddr;
82 unsigned long csrdata;
83};
84
85/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
86 * when doing a context-switch. it is used (apart from in resume) when a new
87 * thread is made and we need to make _resume (which is starting it for the
88 * first time) realise what is going on.
89 *
90 * Actually, the use is very close to the thread struct (TSS) in that both the
91 * switch_stack and the TSS are used to keep thread stuff when switching in
92 * _resume.
93 */
94
95struct switch_stack {
96 unsigned long r9;
97 unsigned long r8;
98 unsigned long r7;
99 unsigned long r6;
100 unsigned long r5;
101 unsigned long r4;
102 unsigned long r3;
103 unsigned long r2;
104 unsigned long r1;
105 unsigned long r0;
106 unsigned long return_ip; /* ip that _resume will return to */
107};
108
109#ifdef __KERNEL__
110
111/* bit 8 is user-mode flag */
112#define user_mode(regs) (((regs)->dccr & 0x100) != 0)
113#define instruction_pointer(regs) ((regs)->irp)
114#define profile_pc(regs) instruction_pointer(regs)
115extern void show_regs(struct pt_regs *);
116
117#endif /* __KERNEL__ */
118
119#endif
diff --git a/arch/cris/include/arch-v10/arch/sv_addr.agh b/arch/cris/include/arch-v10/arch/sv_addr.agh
new file mode 100644
index 000000000000..6ac3a7bc9760
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/sv_addr.agh
@@ -0,0 +1,7306 @@
1/*
2!* This file was automatically generated by /n/asic/bin/reg_macro_gen
3!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
4!* Editing within this file is thus not recommended,
5!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
6!*/
7
8
9/*
10!* Bus interface configuration registers
11!*/
12
13#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
14#define R_WAITSTATES__pcs4_7_zw__BITNR 30
15#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
16#define R_WAITSTATES__pcs4_7_ew__BITNR 28
17#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
18#define R_WAITSTATES__pcs4_7_lw__BITNR 24
19#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
20#define R_WAITSTATES__pcs0_3_zw__BITNR 22
21#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
22#define R_WAITSTATES__pcs0_3_ew__BITNR 20
23#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
24#define R_WAITSTATES__pcs0_3_lw__BITNR 16
25#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
26#define R_WAITSTATES__sram_zw__BITNR 14
27#define R_WAITSTATES__sram_zw__WIDTH 2
28#define R_WAITSTATES__sram_ew__BITNR 12
29#define R_WAITSTATES__sram_ew__WIDTH 2
30#define R_WAITSTATES__sram_lw__BITNR 8
31#define R_WAITSTATES__sram_lw__WIDTH 4
32#define R_WAITSTATES__flash_zw__BITNR 6
33#define R_WAITSTATES__flash_zw__WIDTH 2
34#define R_WAITSTATES__flash_ew__BITNR 4
35#define R_WAITSTATES__flash_ew__WIDTH 2
36#define R_WAITSTATES__flash_lw__BITNR 0
37#define R_WAITSTATES__flash_lw__WIDTH 4
38
39#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
40#define R_BUS_CONFIG__sram_type__BITNR 9
41#define R_BUS_CONFIG__sram_type__WIDTH 1
42#define R_BUS_CONFIG__sram_type__cwe 1
43#define R_BUS_CONFIG__sram_type__bwe 0
44#define R_BUS_CONFIG__dma_burst__BITNR 8
45#define R_BUS_CONFIG__dma_burst__WIDTH 1
46#define R_BUS_CONFIG__dma_burst__burst16 1
47#define R_BUS_CONFIG__dma_burst__burst32 0
48#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
49#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
50#define R_BUS_CONFIG__pcs4_7_wr__ext 1
51#define R_BUS_CONFIG__pcs4_7_wr__norm 0
52#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
53#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
54#define R_BUS_CONFIG__pcs0_3_wr__ext 1
55#define R_BUS_CONFIG__pcs0_3_wr__norm 0
56#define R_BUS_CONFIG__sram_wr__BITNR 5
57#define R_BUS_CONFIG__sram_wr__WIDTH 1
58#define R_BUS_CONFIG__sram_wr__ext 1
59#define R_BUS_CONFIG__sram_wr__norm 0
60#define R_BUS_CONFIG__flash_wr__BITNR 4
61#define R_BUS_CONFIG__flash_wr__WIDTH 1
62#define R_BUS_CONFIG__flash_wr__ext 1
63#define R_BUS_CONFIG__flash_wr__norm 0
64#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
65#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
66#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
67#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
68#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
69#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
70#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
71#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
72#define R_BUS_CONFIG__sram_bw__BITNR 1
73#define R_BUS_CONFIG__sram_bw__WIDTH 1
74#define R_BUS_CONFIG__sram_bw__bw32 1
75#define R_BUS_CONFIG__sram_bw__bw16 0
76#define R_BUS_CONFIG__flash_bw__BITNR 0
77#define R_BUS_CONFIG__flash_bw__WIDTH 1
78#define R_BUS_CONFIG__flash_bw__bw32 1
79#define R_BUS_CONFIG__flash_bw__bw16 0
80
81#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
82#define R_BUS_STATUS__pll_lock_tm__BITNR 5
83#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
84#define R_BUS_STATUS__pll_lock_tm__expired 0
85#define R_BUS_STATUS__pll_lock_tm__counting 1
86#define R_BUS_STATUS__both_faults__BITNR 4
87#define R_BUS_STATUS__both_faults__WIDTH 1
88#define R_BUS_STATUS__both_faults__no 0
89#define R_BUS_STATUS__both_faults__yes 1
90#define R_BUS_STATUS__bsen___BITNR 3
91#define R_BUS_STATUS__bsen___WIDTH 1
92#define R_BUS_STATUS__bsen___enable 0
93#define R_BUS_STATUS__bsen___disable 1
94#define R_BUS_STATUS__boot__BITNR 1
95#define R_BUS_STATUS__boot__WIDTH 2
96#define R_BUS_STATUS__boot__uncached 0
97#define R_BUS_STATUS__boot__serial 1
98#define R_BUS_STATUS__boot__network 2
99#define R_BUS_STATUS__boot__parallel 3
100#define R_BUS_STATUS__flashw__BITNR 0
101#define R_BUS_STATUS__flashw__WIDTH 1
102#define R_BUS_STATUS__flashw__bw32 1
103#define R_BUS_STATUS__flashw__bw16 0
104
105#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
106#define R_DRAM_TIMING__sdram__BITNR 31
107#define R_DRAM_TIMING__sdram__WIDTH 1
108#define R_DRAM_TIMING__sdram__enable 1
109#define R_DRAM_TIMING__sdram__disable 0
110#define R_DRAM_TIMING__ref__BITNR 14
111#define R_DRAM_TIMING__ref__WIDTH 2
112#define R_DRAM_TIMING__ref__e52us 0
113#define R_DRAM_TIMING__ref__e13us 1
114#define R_DRAM_TIMING__ref__e8700ns 2
115#define R_DRAM_TIMING__ref__disable 3
116#define R_DRAM_TIMING__rp__BITNR 12
117#define R_DRAM_TIMING__rp__WIDTH 2
118#define R_DRAM_TIMING__rs__BITNR 10
119#define R_DRAM_TIMING__rs__WIDTH 2
120#define R_DRAM_TIMING__rh__BITNR 8
121#define R_DRAM_TIMING__rh__WIDTH 2
122#define R_DRAM_TIMING__w__BITNR 7
123#define R_DRAM_TIMING__w__WIDTH 1
124#define R_DRAM_TIMING__w__norm 0
125#define R_DRAM_TIMING__w__ext 1
126#define R_DRAM_TIMING__c__BITNR 6
127#define R_DRAM_TIMING__c__WIDTH 1
128#define R_DRAM_TIMING__c__norm 0
129#define R_DRAM_TIMING__c__ext 1
130#define R_DRAM_TIMING__cz__BITNR 4
131#define R_DRAM_TIMING__cz__WIDTH 2
132#define R_DRAM_TIMING__cp__BITNR 2
133#define R_DRAM_TIMING__cp__WIDTH 2
134#define R_DRAM_TIMING__cw__BITNR 0
135#define R_DRAM_TIMING__cw__WIDTH 2
136
137#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
138#define R_SDRAM_TIMING__sdram__BITNR 31
139#define R_SDRAM_TIMING__sdram__WIDTH 1
140#define R_SDRAM_TIMING__sdram__enable 1
141#define R_SDRAM_TIMING__sdram__disable 0
142#define R_SDRAM_TIMING__mrs_data__BITNR 16
143#define R_SDRAM_TIMING__mrs_data__WIDTH 15
144#define R_SDRAM_TIMING__ref__BITNR 14
145#define R_SDRAM_TIMING__ref__WIDTH 2
146#define R_SDRAM_TIMING__ref__e52us 0
147#define R_SDRAM_TIMING__ref__e13us 1
148#define R_SDRAM_TIMING__ref__e6500ns 2
149#define R_SDRAM_TIMING__ref__disable 3
150#define R_SDRAM_TIMING__ddr__BITNR 13
151#define R_SDRAM_TIMING__ddr__WIDTH 1
152#define R_SDRAM_TIMING__ddr__on 1
153#define R_SDRAM_TIMING__ddr__off 0
154#define R_SDRAM_TIMING__clk100__BITNR 12
155#define R_SDRAM_TIMING__clk100__WIDTH 1
156#define R_SDRAM_TIMING__clk100__on 1
157#define R_SDRAM_TIMING__clk100__off 0
158#define R_SDRAM_TIMING__ps__BITNR 11
159#define R_SDRAM_TIMING__ps__WIDTH 1
160#define R_SDRAM_TIMING__ps__on 1
161#define R_SDRAM_TIMING__ps__off 0
162#define R_SDRAM_TIMING__cmd__BITNR 9
163#define R_SDRAM_TIMING__cmd__WIDTH 2
164#define R_SDRAM_TIMING__cmd__pre 3
165#define R_SDRAM_TIMING__cmd__ref 2
166#define R_SDRAM_TIMING__cmd__mrs 1
167#define R_SDRAM_TIMING__cmd__nop 0
168#define R_SDRAM_TIMING__pde__BITNR 8
169#define R_SDRAM_TIMING__pde__WIDTH 1
170#define R_SDRAM_TIMING__rc__BITNR 6
171#define R_SDRAM_TIMING__rc__WIDTH 2
172#define R_SDRAM_TIMING__rp__BITNR 4
173#define R_SDRAM_TIMING__rp__WIDTH 2
174#define R_SDRAM_TIMING__rcd__BITNR 2
175#define R_SDRAM_TIMING__rcd__WIDTH 2
176#define R_SDRAM_TIMING__cl__BITNR 0
177#define R_SDRAM_TIMING__cl__WIDTH 2
178
179#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
180#define R_DRAM_CONFIG__wmm1__BITNR 31
181#define R_DRAM_CONFIG__wmm1__WIDTH 1
182#define R_DRAM_CONFIG__wmm1__wmm 1
183#define R_DRAM_CONFIG__wmm1__norm 0
184#define R_DRAM_CONFIG__wmm0__BITNR 30
185#define R_DRAM_CONFIG__wmm0__WIDTH 1
186#define R_DRAM_CONFIG__wmm0__wmm 1
187#define R_DRAM_CONFIG__wmm0__norm 0
188#define R_DRAM_CONFIG__sh1__BITNR 27
189#define R_DRAM_CONFIG__sh1__WIDTH 3
190#define R_DRAM_CONFIG__sh0__BITNR 24
191#define R_DRAM_CONFIG__sh0__WIDTH 3
192#define R_DRAM_CONFIG__w__BITNR 23
193#define R_DRAM_CONFIG__w__WIDTH 1
194#define R_DRAM_CONFIG__w__bw16 0
195#define R_DRAM_CONFIG__w__bw32 1
196#define R_DRAM_CONFIG__c__BITNR 22
197#define R_DRAM_CONFIG__c__WIDTH 1
198#define R_DRAM_CONFIG__c__byte 0
199#define R_DRAM_CONFIG__c__bank 1
200#define R_DRAM_CONFIG__e__BITNR 21
201#define R_DRAM_CONFIG__e__WIDTH 1
202#define R_DRAM_CONFIG__e__fast 0
203#define R_DRAM_CONFIG__e__edo 1
204#define R_DRAM_CONFIG__group_sel__BITNR 16
205#define R_DRAM_CONFIG__group_sel__WIDTH 5
206#define R_DRAM_CONFIG__group_sel__grp0 0
207#define R_DRAM_CONFIG__group_sel__grp1 1
208#define R_DRAM_CONFIG__group_sel__bit9 9
209#define R_DRAM_CONFIG__group_sel__bit10 10
210#define R_DRAM_CONFIG__group_sel__bit11 11
211#define R_DRAM_CONFIG__group_sel__bit12 12
212#define R_DRAM_CONFIG__group_sel__bit13 13
213#define R_DRAM_CONFIG__group_sel__bit14 14
214#define R_DRAM_CONFIG__group_sel__bit15 15
215#define R_DRAM_CONFIG__group_sel__bit16 16
216#define R_DRAM_CONFIG__group_sel__bit17 17
217#define R_DRAM_CONFIG__group_sel__bit18 18
218#define R_DRAM_CONFIG__group_sel__bit19 19
219#define R_DRAM_CONFIG__group_sel__bit20 20
220#define R_DRAM_CONFIG__group_sel__bit21 21
221#define R_DRAM_CONFIG__group_sel__bit22 22
222#define R_DRAM_CONFIG__group_sel__bit23 23
223#define R_DRAM_CONFIG__group_sel__bit24 24
224#define R_DRAM_CONFIG__group_sel__bit25 25
225#define R_DRAM_CONFIG__group_sel__bit26 26
226#define R_DRAM_CONFIG__group_sel__bit27 27
227#define R_DRAM_CONFIG__group_sel__bit28 28
228#define R_DRAM_CONFIG__group_sel__bit29 29
229#define R_DRAM_CONFIG__ca1__BITNR 13
230#define R_DRAM_CONFIG__ca1__WIDTH 3
231#define R_DRAM_CONFIG__bank23sel__BITNR 8
232#define R_DRAM_CONFIG__bank23sel__WIDTH 5
233#define R_DRAM_CONFIG__bank23sel__bank0 0
234#define R_DRAM_CONFIG__bank23sel__bank1 1
235#define R_DRAM_CONFIG__bank23sel__bit9 9
236#define R_DRAM_CONFIG__bank23sel__bit10 10
237#define R_DRAM_CONFIG__bank23sel__bit11 11
238#define R_DRAM_CONFIG__bank23sel__bit12 12
239#define R_DRAM_CONFIG__bank23sel__bit13 13
240#define R_DRAM_CONFIG__bank23sel__bit14 14
241#define R_DRAM_CONFIG__bank23sel__bit15 15
242#define R_DRAM_CONFIG__bank23sel__bit16 16
243#define R_DRAM_CONFIG__bank23sel__bit17 17
244#define R_DRAM_CONFIG__bank23sel__bit18 18
245#define R_DRAM_CONFIG__bank23sel__bit19 19
246#define R_DRAM_CONFIG__bank23sel__bit20 20
247#define R_DRAM_CONFIG__bank23sel__bit21 21
248#define R_DRAM_CONFIG__bank23sel__bit22 22
249#define R_DRAM_CONFIG__bank23sel__bit23 23
250#define R_DRAM_CONFIG__bank23sel__bit24 24
251#define R_DRAM_CONFIG__bank23sel__bit25 25
252#define R_DRAM_CONFIG__bank23sel__bit26 26
253#define R_DRAM_CONFIG__bank23sel__bit27 27
254#define R_DRAM_CONFIG__bank23sel__bit28 28
255#define R_DRAM_CONFIG__bank23sel__bit29 29
256#define R_DRAM_CONFIG__ca0__BITNR 5
257#define R_DRAM_CONFIG__ca0__WIDTH 3
258#define R_DRAM_CONFIG__bank01sel__BITNR 0
259#define R_DRAM_CONFIG__bank01sel__WIDTH 5
260#define R_DRAM_CONFIG__bank01sel__bank0 0
261#define R_DRAM_CONFIG__bank01sel__bank1 1
262#define R_DRAM_CONFIG__bank01sel__bit9 9
263#define R_DRAM_CONFIG__bank01sel__bit10 10
264#define R_DRAM_CONFIG__bank01sel__bit11 11
265#define R_DRAM_CONFIG__bank01sel__bit12 12
266#define R_DRAM_CONFIG__bank01sel__bit13 13
267#define R_DRAM_CONFIG__bank01sel__bit14 14
268#define R_DRAM_CONFIG__bank01sel__bit15 15
269#define R_DRAM_CONFIG__bank01sel__bit16 16
270#define R_DRAM_CONFIG__bank01sel__bit17 17
271#define R_DRAM_CONFIG__bank01sel__bit18 18
272#define R_DRAM_CONFIG__bank01sel__bit19 19
273#define R_DRAM_CONFIG__bank01sel__bit20 20
274#define R_DRAM_CONFIG__bank01sel__bit21 21
275#define R_DRAM_CONFIG__bank01sel__bit22 22
276#define R_DRAM_CONFIG__bank01sel__bit23 23
277#define R_DRAM_CONFIG__bank01sel__bit24 24
278#define R_DRAM_CONFIG__bank01sel__bit25 25
279#define R_DRAM_CONFIG__bank01sel__bit26 26
280#define R_DRAM_CONFIG__bank01sel__bit27 27
281#define R_DRAM_CONFIG__bank01sel__bit28 28
282#define R_DRAM_CONFIG__bank01sel__bit29 29
283
284#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
285#define R_SDRAM_CONFIG__wmm1__BITNR 31
286#define R_SDRAM_CONFIG__wmm1__WIDTH 1
287#define R_SDRAM_CONFIG__wmm1__wmm 1
288#define R_SDRAM_CONFIG__wmm1__norm 0
289#define R_SDRAM_CONFIG__wmm0__BITNR 30
290#define R_SDRAM_CONFIG__wmm0__WIDTH 1
291#define R_SDRAM_CONFIG__wmm0__wmm 1
292#define R_SDRAM_CONFIG__wmm0__norm 0
293#define R_SDRAM_CONFIG__sh1__BITNR 27
294#define R_SDRAM_CONFIG__sh1__WIDTH 3
295#define R_SDRAM_CONFIG__sh0__BITNR 24
296#define R_SDRAM_CONFIG__sh0__WIDTH 3
297#define R_SDRAM_CONFIG__w__BITNR 23
298#define R_SDRAM_CONFIG__w__WIDTH 1
299#define R_SDRAM_CONFIG__w__bw16 0
300#define R_SDRAM_CONFIG__w__bw32 1
301#define R_SDRAM_CONFIG__type1__BITNR 22
302#define R_SDRAM_CONFIG__type1__WIDTH 1
303#define R_SDRAM_CONFIG__type1__bank2 0
304#define R_SDRAM_CONFIG__type1__bank4 1
305#define R_SDRAM_CONFIG__type0__BITNR 21
306#define R_SDRAM_CONFIG__type0__WIDTH 1
307#define R_SDRAM_CONFIG__type0__bank2 0
308#define R_SDRAM_CONFIG__type0__bank4 1
309#define R_SDRAM_CONFIG__group_sel__BITNR 16
310#define R_SDRAM_CONFIG__group_sel__WIDTH 5
311#define R_SDRAM_CONFIG__group_sel__grp0 0
312#define R_SDRAM_CONFIG__group_sel__grp1 1
313#define R_SDRAM_CONFIG__group_sel__bit9 9
314#define R_SDRAM_CONFIG__group_sel__bit10 10
315#define R_SDRAM_CONFIG__group_sel__bit11 11
316#define R_SDRAM_CONFIG__group_sel__bit12 12
317#define R_SDRAM_CONFIG__group_sel__bit13 13
318#define R_SDRAM_CONFIG__group_sel__bit14 14
319#define R_SDRAM_CONFIG__group_sel__bit15 15
320#define R_SDRAM_CONFIG__group_sel__bit16 16
321#define R_SDRAM_CONFIG__group_sel__bit17 17
322#define R_SDRAM_CONFIG__group_sel__bit18 18
323#define R_SDRAM_CONFIG__group_sel__bit19 19
324#define R_SDRAM_CONFIG__group_sel__bit20 20
325#define R_SDRAM_CONFIG__group_sel__bit21 21
326#define R_SDRAM_CONFIG__group_sel__bit22 22
327#define R_SDRAM_CONFIG__group_sel__bit23 23
328#define R_SDRAM_CONFIG__group_sel__bit24 24
329#define R_SDRAM_CONFIG__group_sel__bit25 25
330#define R_SDRAM_CONFIG__group_sel__bit26 26
331#define R_SDRAM_CONFIG__group_sel__bit27 27
332#define R_SDRAM_CONFIG__group_sel__bit28 28
333#define R_SDRAM_CONFIG__group_sel__bit29 29
334#define R_SDRAM_CONFIG__ca1__BITNR 13
335#define R_SDRAM_CONFIG__ca1__WIDTH 3
336#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
337#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
338#define R_SDRAM_CONFIG__bank_sel1__bit9 9
339#define R_SDRAM_CONFIG__bank_sel1__bit10 10
340#define R_SDRAM_CONFIG__bank_sel1__bit11 11
341#define R_SDRAM_CONFIG__bank_sel1__bit12 12
342#define R_SDRAM_CONFIG__bank_sel1__bit13 13
343#define R_SDRAM_CONFIG__bank_sel1__bit14 14
344#define R_SDRAM_CONFIG__bank_sel1__bit15 15
345#define R_SDRAM_CONFIG__bank_sel1__bit16 16
346#define R_SDRAM_CONFIG__bank_sel1__bit17 17
347#define R_SDRAM_CONFIG__bank_sel1__bit18 18
348#define R_SDRAM_CONFIG__bank_sel1__bit19 19
349#define R_SDRAM_CONFIG__bank_sel1__bit20 20
350#define R_SDRAM_CONFIG__bank_sel1__bit21 21
351#define R_SDRAM_CONFIG__bank_sel1__bit22 22
352#define R_SDRAM_CONFIG__bank_sel1__bit23 23
353#define R_SDRAM_CONFIG__bank_sel1__bit24 24
354#define R_SDRAM_CONFIG__bank_sel1__bit25 25
355#define R_SDRAM_CONFIG__bank_sel1__bit26 26
356#define R_SDRAM_CONFIG__bank_sel1__bit27 27
357#define R_SDRAM_CONFIG__bank_sel1__bit28 28
358#define R_SDRAM_CONFIG__bank_sel1__bit29 29
359#define R_SDRAM_CONFIG__ca0__BITNR 5
360#define R_SDRAM_CONFIG__ca0__WIDTH 3
361#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
362#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
363#define R_SDRAM_CONFIG__bank_sel0__bit9 9
364#define R_SDRAM_CONFIG__bank_sel0__bit10 10
365#define R_SDRAM_CONFIG__bank_sel0__bit11 11
366#define R_SDRAM_CONFIG__bank_sel0__bit12 12
367#define R_SDRAM_CONFIG__bank_sel0__bit13 13
368#define R_SDRAM_CONFIG__bank_sel0__bit14 14
369#define R_SDRAM_CONFIG__bank_sel0__bit15 15
370#define R_SDRAM_CONFIG__bank_sel0__bit16 16
371#define R_SDRAM_CONFIG__bank_sel0__bit17 17
372#define R_SDRAM_CONFIG__bank_sel0__bit18 18
373#define R_SDRAM_CONFIG__bank_sel0__bit19 19
374#define R_SDRAM_CONFIG__bank_sel0__bit20 20
375#define R_SDRAM_CONFIG__bank_sel0__bit21 21
376#define R_SDRAM_CONFIG__bank_sel0__bit22 22
377#define R_SDRAM_CONFIG__bank_sel0__bit23 23
378#define R_SDRAM_CONFIG__bank_sel0__bit24 24
379#define R_SDRAM_CONFIG__bank_sel0__bit25 25
380#define R_SDRAM_CONFIG__bank_sel0__bit26 26
381#define R_SDRAM_CONFIG__bank_sel0__bit27 27
382#define R_SDRAM_CONFIG__bank_sel0__bit28 28
383#define R_SDRAM_CONFIG__bank_sel0__bit29 29
384
385/*
386!* External DMA registers
387!*/
388
389#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
390#define R_EXT_DMA_0_CMD__cnt__BITNR 23
391#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
392#define R_EXT_DMA_0_CMD__cnt__enable 1
393#define R_EXT_DMA_0_CMD__cnt__disable 0
394#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
395#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
396#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
397#define R_EXT_DMA_0_CMD__rqpol__alow 1
398#define R_EXT_DMA_0_CMD__apol__BITNR 21
399#define R_EXT_DMA_0_CMD__apol__WIDTH 1
400#define R_EXT_DMA_0_CMD__apol__ahigh 0
401#define R_EXT_DMA_0_CMD__apol__alow 1
402#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
403#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
404#define R_EXT_DMA_0_CMD__rq_ack__burst 0
405#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
406#define R_EXT_DMA_0_CMD__wid__BITNR 18
407#define R_EXT_DMA_0_CMD__wid__WIDTH 2
408#define R_EXT_DMA_0_CMD__wid__byte 0
409#define R_EXT_DMA_0_CMD__wid__word 1
410#define R_EXT_DMA_0_CMD__wid__dword 2
411#define R_EXT_DMA_0_CMD__dir__BITNR 17
412#define R_EXT_DMA_0_CMD__dir__WIDTH 1
413#define R_EXT_DMA_0_CMD__dir__input 0
414#define R_EXT_DMA_0_CMD__dir__output 1
415#define R_EXT_DMA_0_CMD__run__BITNR 16
416#define R_EXT_DMA_0_CMD__run__WIDTH 1
417#define R_EXT_DMA_0_CMD__run__start 1
418#define R_EXT_DMA_0_CMD__run__stop 0
419#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
420#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16
421
422#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
423#define R_EXT_DMA_0_STAT__run__BITNR 16
424#define R_EXT_DMA_0_STAT__run__WIDTH 1
425#define R_EXT_DMA_0_STAT__run__start 1
426#define R_EXT_DMA_0_STAT__run__stop 0
427#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
428#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16
429
430#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
431#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
432#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28
433
434#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
435#define R_EXT_DMA_1_CMD__cnt__BITNR 23
436#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
437#define R_EXT_DMA_1_CMD__cnt__enable 1
438#define R_EXT_DMA_1_CMD__cnt__disable 0
439#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
440#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
441#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
442#define R_EXT_DMA_1_CMD__rqpol__alow 1
443#define R_EXT_DMA_1_CMD__apol__BITNR 21
444#define R_EXT_DMA_1_CMD__apol__WIDTH 1
445#define R_EXT_DMA_1_CMD__apol__ahigh 0
446#define R_EXT_DMA_1_CMD__apol__alow 1
447#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
448#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
449#define R_EXT_DMA_1_CMD__rq_ack__burst 0
450#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
451#define R_EXT_DMA_1_CMD__wid__BITNR 18
452#define R_EXT_DMA_1_CMD__wid__WIDTH 2
453#define R_EXT_DMA_1_CMD__wid__byte 0
454#define R_EXT_DMA_1_CMD__wid__word 1
455#define R_EXT_DMA_1_CMD__wid__dword 2
456#define R_EXT_DMA_1_CMD__dir__BITNR 17
457#define R_EXT_DMA_1_CMD__dir__WIDTH 1
458#define R_EXT_DMA_1_CMD__dir__input 0
459#define R_EXT_DMA_1_CMD__dir__output 1
460#define R_EXT_DMA_1_CMD__run__BITNR 16
461#define R_EXT_DMA_1_CMD__run__WIDTH 1
462#define R_EXT_DMA_1_CMD__run__start 1
463#define R_EXT_DMA_1_CMD__run__stop 0
464#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
465#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16
466
467#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
468#define R_EXT_DMA_1_STAT__run__BITNR 16
469#define R_EXT_DMA_1_STAT__run__WIDTH 1
470#define R_EXT_DMA_1_STAT__run__start 1
471#define R_EXT_DMA_1_STAT__run__stop 0
472#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
473#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16
474
475#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
476#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
477#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28
478
479/*
480!* Timer registers
481!*/
482
483#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
484#define R_TIMER_CTRL__timerdiv1__BITNR 24
485#define R_TIMER_CTRL__timerdiv1__WIDTH 8
486#define R_TIMER_CTRL__timerdiv0__BITNR 16
487#define R_TIMER_CTRL__timerdiv0__WIDTH 8
488#define R_TIMER_CTRL__presc_timer1__BITNR 15
489#define R_TIMER_CTRL__presc_timer1__WIDTH 1
490#define R_TIMER_CTRL__presc_timer1__normal 0
491#define R_TIMER_CTRL__presc_timer1__prescale 1
492#define R_TIMER_CTRL__i1__BITNR 14
493#define R_TIMER_CTRL__i1__WIDTH 1
494#define R_TIMER_CTRL__i1__clr 1
495#define R_TIMER_CTRL__i1__nop 0
496#define R_TIMER_CTRL__tm1__BITNR 12
497#define R_TIMER_CTRL__tm1__WIDTH 2
498#define R_TIMER_CTRL__tm1__stop_ld 0
499#define R_TIMER_CTRL__tm1__freeze 1
500#define R_TIMER_CTRL__tm1__run 2
501#define R_TIMER_CTRL__tm1__reserved 3
502#define R_TIMER_CTRL__clksel1__BITNR 8
503#define R_TIMER_CTRL__clksel1__WIDTH 4
504#define R_TIMER_CTRL__clksel1__c300Hz 0
505#define R_TIMER_CTRL__clksel1__c600Hz 1
506#define R_TIMER_CTRL__clksel1__c1200Hz 2
507#define R_TIMER_CTRL__clksel1__c2400Hz 3
508#define R_TIMER_CTRL__clksel1__c4800Hz 4
509#define R_TIMER_CTRL__clksel1__c9600Hz 5
510#define R_TIMER_CTRL__clksel1__c19k2Hz 6
511#define R_TIMER_CTRL__clksel1__c38k4Hz 7
512#define R_TIMER_CTRL__clksel1__c57k6Hz 8
513#define R_TIMER_CTRL__clksel1__c115k2Hz 9
514#define R_TIMER_CTRL__clksel1__c230k4Hz 10
515#define R_TIMER_CTRL__clksel1__c460k8Hz 11
516#define R_TIMER_CTRL__clksel1__c921k6Hz 12
517#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
518#define R_TIMER_CTRL__clksel1__c6250kHz 14
519#define R_TIMER_CTRL__clksel1__cascade0 15
520#define R_TIMER_CTRL__presc_ext__BITNR 7
521#define R_TIMER_CTRL__presc_ext__WIDTH 1
522#define R_TIMER_CTRL__presc_ext__prescale 0
523#define R_TIMER_CTRL__presc_ext__external 1
524#define R_TIMER_CTRL__i0__BITNR 6
525#define R_TIMER_CTRL__i0__WIDTH 1
526#define R_TIMER_CTRL__i0__clr 1
527#define R_TIMER_CTRL__i0__nop 0
528#define R_TIMER_CTRL__tm0__BITNR 4
529#define R_TIMER_CTRL__tm0__WIDTH 2
530#define R_TIMER_CTRL__tm0__stop_ld 0
531#define R_TIMER_CTRL__tm0__freeze 1
532#define R_TIMER_CTRL__tm0__run 2
533#define R_TIMER_CTRL__tm0__reserved 3
534#define R_TIMER_CTRL__clksel0__BITNR 0
535#define R_TIMER_CTRL__clksel0__WIDTH 4
536#define R_TIMER_CTRL__clksel0__c300Hz 0
537#define R_TIMER_CTRL__clksel0__c600Hz 1
538#define R_TIMER_CTRL__clksel0__c1200Hz 2
539#define R_TIMER_CTRL__clksel0__c2400Hz 3
540#define R_TIMER_CTRL__clksel0__c4800Hz 4
541#define R_TIMER_CTRL__clksel0__c9600Hz 5
542#define R_TIMER_CTRL__clksel0__c19k2Hz 6
543#define R_TIMER_CTRL__clksel0__c38k4Hz 7
544#define R_TIMER_CTRL__clksel0__c57k6Hz 8
545#define R_TIMER_CTRL__clksel0__c115k2Hz 9
546#define R_TIMER_CTRL__clksel0__c230k4Hz 10
547#define R_TIMER_CTRL__clksel0__c460k8Hz 11
548#define R_TIMER_CTRL__clksel0__c921k6Hz 12
549#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
550#define R_TIMER_CTRL__clksel0__c6250kHz 14
551#define R_TIMER_CTRL__clksel0__flexible 15
552
553#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
554#define R_TIMER_DATA__timer1__BITNR 24
555#define R_TIMER_DATA__timer1__WIDTH 8
556#define R_TIMER_DATA__timer0__BITNR 16
557#define R_TIMER_DATA__timer0__WIDTH 8
558#define R_TIMER_DATA__clkdiv_high__BITNR 8
559#define R_TIMER_DATA__clkdiv_high__WIDTH 8
560#define R_TIMER_DATA__clkdiv_low__BITNR 0
561#define R_TIMER_DATA__clkdiv_low__WIDTH 8
562
563#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
564#define R_TIMER01_DATA__count__BITNR 0
565#define R_TIMER01_DATA__count__WIDTH 16
566
567#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
568#define R_TIMER0_DATA__count__BITNR 0
569#define R_TIMER0_DATA__count__WIDTH 8
570
571#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
572#define R_TIMER1_DATA__count__BITNR 0
573#define R_TIMER1_DATA__count__WIDTH 8
574
575#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
576#define R_WATCHDOG__key__BITNR 1
577#define R_WATCHDOG__key__WIDTH 3
578#define R_WATCHDOG__enable__BITNR 0
579#define R_WATCHDOG__enable__WIDTH 1
580#define R_WATCHDOG__enable__stop 0
581#define R_WATCHDOG__enable__start 1
582
583#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
584#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
585#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
586#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
587#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16
588
589#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
590#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
591#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16
592
593#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
594#define R_TIMER_PRESCALE__tim_presc__BITNR 0
595#define R_TIMER_PRESCALE__tim_presc__WIDTH 16
596
597#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
598#define R_PRESCALE_STATUS__ser_status__BITNR 16
599#define R_PRESCALE_STATUS__ser_status__WIDTH 16
600#define R_PRESCALE_STATUS__tim_status__BITNR 0
601#define R_PRESCALE_STATUS__tim_status__WIDTH 16
602
603#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
604#define R_SER_PRESC_STATUS__ser_status__BITNR 0
605#define R_SER_PRESC_STATUS__ser_status__WIDTH 16
606
607#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
608#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
609#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16
610
611#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
612#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
613#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
614#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
615#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
616#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
617#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
618#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
619#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
620#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
621#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
622#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
623#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
624#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
625#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
626#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
627#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
628#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
629#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
630#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
631#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
632#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
633#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
634#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
635#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
636#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
637#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
638#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
639#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
640#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
641#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
642#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
643#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
644#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
645#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10
646
647/*
648!* Shared RAM interface registers
649!*/
650
651#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
652#define R_SHARED_RAM_CONFIG__width__BITNR 3
653#define R_SHARED_RAM_CONFIG__width__WIDTH 1
654#define R_SHARED_RAM_CONFIG__width__byte 0
655#define R_SHARED_RAM_CONFIG__width__word 1
656#define R_SHARED_RAM_CONFIG__enable__BITNR 2
657#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
658#define R_SHARED_RAM_CONFIG__enable__yes 1
659#define R_SHARED_RAM_CONFIG__enable__no 0
660#define R_SHARED_RAM_CONFIG__pint__BITNR 1
661#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
662#define R_SHARED_RAM_CONFIG__pint__int 1
663#define R_SHARED_RAM_CONFIG__pint__nop 0
664#define R_SHARED_RAM_CONFIG__clri__BITNR 0
665#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
666#define R_SHARED_RAM_CONFIG__clri__clr 1
667#define R_SHARED_RAM_CONFIG__clri__nop 0
668
669#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
670#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
671#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22
672
673/*
674!* General config registers
675!*/
676
677#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
678#define R_GEN_CONFIG__par_w__BITNR 31
679#define R_GEN_CONFIG__par_w__WIDTH 1
680#define R_GEN_CONFIG__par_w__select 1
681#define R_GEN_CONFIG__par_w__disable 0
682#define R_GEN_CONFIG__usb2__BITNR 30
683#define R_GEN_CONFIG__usb2__WIDTH 1
684#define R_GEN_CONFIG__usb2__select 1
685#define R_GEN_CONFIG__usb2__disable 0
686#define R_GEN_CONFIG__usb1__BITNR 29
687#define R_GEN_CONFIG__usb1__WIDTH 1
688#define R_GEN_CONFIG__usb1__select 1
689#define R_GEN_CONFIG__usb1__disable 0
690#define R_GEN_CONFIG__g24dir__BITNR 27
691#define R_GEN_CONFIG__g24dir__WIDTH 1
692#define R_GEN_CONFIG__g24dir__in 0
693#define R_GEN_CONFIG__g24dir__out 1
694#define R_GEN_CONFIG__g16_23dir__BITNR 26
695#define R_GEN_CONFIG__g16_23dir__WIDTH 1
696#define R_GEN_CONFIG__g16_23dir__in 0
697#define R_GEN_CONFIG__g16_23dir__out 1
698#define R_GEN_CONFIG__g8_15dir__BITNR 25
699#define R_GEN_CONFIG__g8_15dir__WIDTH 1
700#define R_GEN_CONFIG__g8_15dir__in 0
701#define R_GEN_CONFIG__g8_15dir__out 1
702#define R_GEN_CONFIG__g0dir__BITNR 24
703#define R_GEN_CONFIG__g0dir__WIDTH 1
704#define R_GEN_CONFIG__g0dir__in 0
705#define R_GEN_CONFIG__g0dir__out 1
706#define R_GEN_CONFIG__dma9__BITNR 23
707#define R_GEN_CONFIG__dma9__WIDTH 1
708#define R_GEN_CONFIG__dma9__usb 0
709#define R_GEN_CONFIG__dma9__serial1 1
710#define R_GEN_CONFIG__dma8__BITNR 22
711#define R_GEN_CONFIG__dma8__WIDTH 1
712#define R_GEN_CONFIG__dma8__usb 0
713#define R_GEN_CONFIG__dma8__serial1 1
714#define R_GEN_CONFIG__dma7__BITNR 20
715#define R_GEN_CONFIG__dma7__WIDTH 2
716#define R_GEN_CONFIG__dma7__unused 0
717#define R_GEN_CONFIG__dma7__serial0 1
718#define R_GEN_CONFIG__dma7__extdma1 2
719#define R_GEN_CONFIG__dma7__intdma6 3
720#define R_GEN_CONFIG__dma6__BITNR 18
721#define R_GEN_CONFIG__dma6__WIDTH 2
722#define R_GEN_CONFIG__dma6__unused 0
723#define R_GEN_CONFIG__dma6__serial0 1
724#define R_GEN_CONFIG__dma6__extdma1 2
725#define R_GEN_CONFIG__dma6__intdma7 3
726#define R_GEN_CONFIG__dma5__BITNR 16
727#define R_GEN_CONFIG__dma5__WIDTH 2
728#define R_GEN_CONFIG__dma5__par1 0
729#define R_GEN_CONFIG__dma5__scsi1 1
730#define R_GEN_CONFIG__dma5__serial3 2
731#define R_GEN_CONFIG__dma5__extdma0 3
732#define R_GEN_CONFIG__dma4__BITNR 14
733#define R_GEN_CONFIG__dma4__WIDTH 2
734#define R_GEN_CONFIG__dma4__par1 0
735#define R_GEN_CONFIG__dma4__scsi1 1
736#define R_GEN_CONFIG__dma4__serial3 2
737#define R_GEN_CONFIG__dma4__extdma0 3
738#define R_GEN_CONFIG__dma3__BITNR 12
739#define R_GEN_CONFIG__dma3__WIDTH 2
740#define R_GEN_CONFIG__dma3__par0 0
741#define R_GEN_CONFIG__dma3__scsi0 1
742#define R_GEN_CONFIG__dma3__serial2 2
743#define R_GEN_CONFIG__dma3__ata 3
744#define R_GEN_CONFIG__dma2__BITNR 10
745#define R_GEN_CONFIG__dma2__WIDTH 2
746#define R_GEN_CONFIG__dma2__par0 0
747#define R_GEN_CONFIG__dma2__scsi0 1
748#define R_GEN_CONFIG__dma2__serial2 2
749#define R_GEN_CONFIG__dma2__ata 3
750#define R_GEN_CONFIG__mio_w__BITNR 9
751#define R_GEN_CONFIG__mio_w__WIDTH 1
752#define R_GEN_CONFIG__mio_w__select 1
753#define R_GEN_CONFIG__mio_w__disable 0
754#define R_GEN_CONFIG__ser3__BITNR 8
755#define R_GEN_CONFIG__ser3__WIDTH 1
756#define R_GEN_CONFIG__ser3__select 1
757#define R_GEN_CONFIG__ser3__disable 0
758#define R_GEN_CONFIG__par1__BITNR 7
759#define R_GEN_CONFIG__par1__WIDTH 1
760#define R_GEN_CONFIG__par1__select 1
761#define R_GEN_CONFIG__par1__disable 0
762#define R_GEN_CONFIG__scsi0w__BITNR 6
763#define R_GEN_CONFIG__scsi0w__WIDTH 1
764#define R_GEN_CONFIG__scsi0w__select 1
765#define R_GEN_CONFIG__scsi0w__disable 0
766#define R_GEN_CONFIG__scsi1__BITNR 5
767#define R_GEN_CONFIG__scsi1__WIDTH 1
768#define R_GEN_CONFIG__scsi1__select 1
769#define R_GEN_CONFIG__scsi1__disable 0
770#define R_GEN_CONFIG__mio__BITNR 4
771#define R_GEN_CONFIG__mio__WIDTH 1
772#define R_GEN_CONFIG__mio__select 1
773#define R_GEN_CONFIG__mio__disable 0
774#define R_GEN_CONFIG__ser2__BITNR 3
775#define R_GEN_CONFIG__ser2__WIDTH 1
776#define R_GEN_CONFIG__ser2__select 1
777#define R_GEN_CONFIG__ser2__disable 0
778#define R_GEN_CONFIG__par0__BITNR 2
779#define R_GEN_CONFIG__par0__WIDTH 1
780#define R_GEN_CONFIG__par0__select 1
781#define R_GEN_CONFIG__par0__disable 0
782#define R_GEN_CONFIG__ata__BITNR 1
783#define R_GEN_CONFIG__ata__WIDTH 1
784#define R_GEN_CONFIG__ata__select 1
785#define R_GEN_CONFIG__ata__disable 0
786#define R_GEN_CONFIG__scsi0__BITNR 0
787#define R_GEN_CONFIG__scsi0__WIDTH 1
788#define R_GEN_CONFIG__scsi0__select 1
789#define R_GEN_CONFIG__scsi0__disable 0
790
791#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
792#define R_GEN_CONFIG_II__sermode3__BITNR 6
793#define R_GEN_CONFIG_II__sermode3__WIDTH 1
794#define R_GEN_CONFIG_II__sermode3__async 0
795#define R_GEN_CONFIG_II__sermode3__sync 1
796#define R_GEN_CONFIG_II__sermode1__BITNR 4
797#define R_GEN_CONFIG_II__sermode1__WIDTH 1
798#define R_GEN_CONFIG_II__sermode1__async 0
799#define R_GEN_CONFIG_II__sermode1__sync 1
800#define R_GEN_CONFIG_II__ext_clk__BITNR 2
801#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
802#define R_GEN_CONFIG_II__ext_clk__select 1
803#define R_GEN_CONFIG_II__ext_clk__disable 0
804#define R_GEN_CONFIG_II__ser2__BITNR 1
805#define R_GEN_CONFIG_II__ser2__WIDTH 1
806#define R_GEN_CONFIG_II__ser2__select 1
807#define R_GEN_CONFIG_II__ser2__disable 0
808#define R_GEN_CONFIG_II__ser3__BITNR 0
809#define R_GEN_CONFIG_II__ser3__WIDTH 1
810#define R_GEN_CONFIG_II__ser3__select 1
811#define R_GEN_CONFIG_II__ser3__disable 0
812
813#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
814#define R_PORT_G_DATA__data__BITNR 0
815#define R_PORT_G_DATA__data__WIDTH 32
816
817/*
818!* General port configuration registers
819!*/
820
821#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
822#define R_PORT_PA_SET__dir7__BITNR 15
823#define R_PORT_PA_SET__dir7__WIDTH 1
824#define R_PORT_PA_SET__dir7__input 0
825#define R_PORT_PA_SET__dir7__output 1
826#define R_PORT_PA_SET__dir6__BITNR 14
827#define R_PORT_PA_SET__dir6__WIDTH 1
828#define R_PORT_PA_SET__dir6__input 0
829#define R_PORT_PA_SET__dir6__output 1
830#define R_PORT_PA_SET__dir5__BITNR 13
831#define R_PORT_PA_SET__dir5__WIDTH 1
832#define R_PORT_PA_SET__dir5__input 0
833#define R_PORT_PA_SET__dir5__output 1
834#define R_PORT_PA_SET__dir4__BITNR 12
835#define R_PORT_PA_SET__dir4__WIDTH 1
836#define R_PORT_PA_SET__dir4__input 0
837#define R_PORT_PA_SET__dir4__output 1
838#define R_PORT_PA_SET__dir3__BITNR 11
839#define R_PORT_PA_SET__dir3__WIDTH 1
840#define R_PORT_PA_SET__dir3__input 0
841#define R_PORT_PA_SET__dir3__output 1
842#define R_PORT_PA_SET__dir2__BITNR 10
843#define R_PORT_PA_SET__dir2__WIDTH 1
844#define R_PORT_PA_SET__dir2__input 0
845#define R_PORT_PA_SET__dir2__output 1
846#define R_PORT_PA_SET__dir1__BITNR 9
847#define R_PORT_PA_SET__dir1__WIDTH 1
848#define R_PORT_PA_SET__dir1__input 0
849#define R_PORT_PA_SET__dir1__output 1
850#define R_PORT_PA_SET__dir0__BITNR 8
851#define R_PORT_PA_SET__dir0__WIDTH 1
852#define R_PORT_PA_SET__dir0__input 0
853#define R_PORT_PA_SET__dir0__output 1
854#define R_PORT_PA_SET__data_out__BITNR 0
855#define R_PORT_PA_SET__data_out__WIDTH 8
856
857#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
858#define R_PORT_PA_DATA__data_out__BITNR 0
859#define R_PORT_PA_DATA__data_out__WIDTH 8
860
861#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
862#define R_PORT_PA_DIR__dir7__BITNR 7
863#define R_PORT_PA_DIR__dir7__WIDTH 1
864#define R_PORT_PA_DIR__dir7__input 0
865#define R_PORT_PA_DIR__dir7__output 1
866#define R_PORT_PA_DIR__dir6__BITNR 6
867#define R_PORT_PA_DIR__dir6__WIDTH 1
868#define R_PORT_PA_DIR__dir6__input 0
869#define R_PORT_PA_DIR__dir6__output 1
870#define R_PORT_PA_DIR__dir5__BITNR 5
871#define R_PORT_PA_DIR__dir5__WIDTH 1
872#define R_PORT_PA_DIR__dir5__input 0
873#define R_PORT_PA_DIR__dir5__output 1
874#define R_PORT_PA_DIR__dir4__BITNR 4
875#define R_PORT_PA_DIR__dir4__WIDTH 1
876#define R_PORT_PA_DIR__dir4__input 0
877#define R_PORT_PA_DIR__dir4__output 1
878#define R_PORT_PA_DIR__dir3__BITNR 3
879#define R_PORT_PA_DIR__dir3__WIDTH 1
880#define R_PORT_PA_DIR__dir3__input 0
881#define R_PORT_PA_DIR__dir3__output 1
882#define R_PORT_PA_DIR__dir2__BITNR 2
883#define R_PORT_PA_DIR__dir2__WIDTH 1
884#define R_PORT_PA_DIR__dir2__input 0
885#define R_PORT_PA_DIR__dir2__output 1
886#define R_PORT_PA_DIR__dir1__BITNR 1
887#define R_PORT_PA_DIR__dir1__WIDTH 1
888#define R_PORT_PA_DIR__dir1__input 0
889#define R_PORT_PA_DIR__dir1__output 1
890#define R_PORT_PA_DIR__dir0__BITNR 0
891#define R_PORT_PA_DIR__dir0__WIDTH 1
892#define R_PORT_PA_DIR__dir0__input 0
893#define R_PORT_PA_DIR__dir0__output 1
894
895#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
896#define R_PORT_PA_READ__data_in__BITNR 0
897#define R_PORT_PA_READ__data_in__WIDTH 8
898
899#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
900#define R_PORT_PB_SET__syncser3__BITNR 29
901#define R_PORT_PB_SET__syncser3__WIDTH 1
902#define R_PORT_PB_SET__syncser3__port_cs 0
903#define R_PORT_PB_SET__syncser3__ss3extra 1
904#define R_PORT_PB_SET__syncser1__BITNR 28
905#define R_PORT_PB_SET__syncser1__WIDTH 1
906#define R_PORT_PB_SET__syncser1__port_cs 0
907#define R_PORT_PB_SET__syncser1__ss1extra 1
908#define R_PORT_PB_SET__i2c_en__BITNR 27
909#define R_PORT_PB_SET__i2c_en__WIDTH 1
910#define R_PORT_PB_SET__i2c_en__off 0
911#define R_PORT_PB_SET__i2c_en__on 1
912#define R_PORT_PB_SET__i2c_d__BITNR 26
913#define R_PORT_PB_SET__i2c_d__WIDTH 1
914#define R_PORT_PB_SET__i2c_clk__BITNR 25
915#define R_PORT_PB_SET__i2c_clk__WIDTH 1
916#define R_PORT_PB_SET__i2c_oe___BITNR 24
917#define R_PORT_PB_SET__i2c_oe___WIDTH 1
918#define R_PORT_PB_SET__i2c_oe___enable 0
919#define R_PORT_PB_SET__i2c_oe___disable 1
920#define R_PORT_PB_SET__cs7__BITNR 23
921#define R_PORT_PB_SET__cs7__WIDTH 1
922#define R_PORT_PB_SET__cs7__port 0
923#define R_PORT_PB_SET__cs7__cs 1
924#define R_PORT_PB_SET__cs6__BITNR 22
925#define R_PORT_PB_SET__cs6__WIDTH 1
926#define R_PORT_PB_SET__cs6__port 0
927#define R_PORT_PB_SET__cs6__cs 1
928#define R_PORT_PB_SET__cs5__BITNR 21
929#define R_PORT_PB_SET__cs5__WIDTH 1
930#define R_PORT_PB_SET__cs5__port 0
931#define R_PORT_PB_SET__cs5__cs 1
932#define R_PORT_PB_SET__cs4__BITNR 20
933#define R_PORT_PB_SET__cs4__WIDTH 1
934#define R_PORT_PB_SET__cs4__port 0
935#define R_PORT_PB_SET__cs4__cs 1
936#define R_PORT_PB_SET__cs3__BITNR 19
937#define R_PORT_PB_SET__cs3__WIDTH 1
938#define R_PORT_PB_SET__cs3__port 0
939#define R_PORT_PB_SET__cs3__cs 1
940#define R_PORT_PB_SET__cs2__BITNR 18
941#define R_PORT_PB_SET__cs2__WIDTH 1
942#define R_PORT_PB_SET__cs2__port 0
943#define R_PORT_PB_SET__cs2__cs 1
944#define R_PORT_PB_SET__scsi1__BITNR 17
945#define R_PORT_PB_SET__scsi1__WIDTH 1
946#define R_PORT_PB_SET__scsi1__port_cs 0
947#define R_PORT_PB_SET__scsi1__enph 1
948#define R_PORT_PB_SET__scsi0__BITNR 16
949#define R_PORT_PB_SET__scsi0__WIDTH 1
950#define R_PORT_PB_SET__scsi0__port_cs 0
951#define R_PORT_PB_SET__scsi0__enph 1
952#define R_PORT_PB_SET__dir7__BITNR 15
953#define R_PORT_PB_SET__dir7__WIDTH 1
954#define R_PORT_PB_SET__dir7__input 0
955#define R_PORT_PB_SET__dir7__output 1
956#define R_PORT_PB_SET__dir6__BITNR 14
957#define R_PORT_PB_SET__dir6__WIDTH 1
958#define R_PORT_PB_SET__dir6__input 0
959#define R_PORT_PB_SET__dir6__output 1
960#define R_PORT_PB_SET__dir5__BITNR 13
961#define R_PORT_PB_SET__dir5__WIDTH 1
962#define R_PORT_PB_SET__dir5__input 0
963#define R_PORT_PB_SET__dir5__output 1
964#define R_PORT_PB_SET__dir4__BITNR 12
965#define R_PORT_PB_SET__dir4__WIDTH 1
966#define R_PORT_PB_SET__dir4__input 0
967#define R_PORT_PB_SET__dir4__output 1
968#define R_PORT_PB_SET__dir3__BITNR 11
969#define R_PORT_PB_SET__dir3__WIDTH 1
970#define R_PORT_PB_SET__dir3__input 0
971#define R_PORT_PB_SET__dir3__output 1
972#define R_PORT_PB_SET__dir2__BITNR 10
973#define R_PORT_PB_SET__dir2__WIDTH 1
974#define R_PORT_PB_SET__dir2__input 0
975#define R_PORT_PB_SET__dir2__output 1
976#define R_PORT_PB_SET__dir1__BITNR 9
977#define R_PORT_PB_SET__dir1__WIDTH 1
978#define R_PORT_PB_SET__dir1__input 0
979#define R_PORT_PB_SET__dir1__output 1
980#define R_PORT_PB_SET__dir0__BITNR 8
981#define R_PORT_PB_SET__dir0__WIDTH 1
982#define R_PORT_PB_SET__dir0__input 0
983#define R_PORT_PB_SET__dir0__output 1
984#define R_PORT_PB_SET__data_out__BITNR 0
985#define R_PORT_PB_SET__data_out__WIDTH 8
986
987#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)
988#define R_PORT_PB_DATA__data_out__BITNR 0
989#define R_PORT_PB_DATA__data_out__WIDTH 8
990
991#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
992#define R_PORT_PB_DIR__dir7__BITNR 7
993#define R_PORT_PB_DIR__dir7__WIDTH 1
994#define R_PORT_PB_DIR__dir7__input 0
995#define R_PORT_PB_DIR__dir7__output 1
996#define R_PORT_PB_DIR__dir6__BITNR 6
997#define R_PORT_PB_DIR__dir6__WIDTH 1
998#define R_PORT_PB_DIR__dir6__input 0
999#define R_PORT_PB_DIR__dir6__output 1
1000#define R_PORT_PB_DIR__dir5__BITNR 5
1001#define R_PORT_PB_DIR__dir5__WIDTH 1
1002#define R_PORT_PB_DIR__dir5__input 0
1003#define R_PORT_PB_DIR__dir5__output 1
1004#define R_PORT_PB_DIR__dir4__BITNR 4
1005#define R_PORT_PB_DIR__dir4__WIDTH 1
1006#define R_PORT_PB_DIR__dir4__input 0
1007#define R_PORT_PB_DIR__dir4__output 1
1008#define R_PORT_PB_DIR__dir3__BITNR 3
1009#define R_PORT_PB_DIR__dir3__WIDTH 1
1010#define R_PORT_PB_DIR__dir3__input 0
1011#define R_PORT_PB_DIR__dir3__output 1
1012#define R_PORT_PB_DIR__dir2__BITNR 2
1013#define R_PORT_PB_DIR__dir2__WIDTH 1
1014#define R_PORT_PB_DIR__dir2__input 0
1015#define R_PORT_PB_DIR__dir2__output 1
1016#define R_PORT_PB_DIR__dir1__BITNR 1
1017#define R_PORT_PB_DIR__dir1__WIDTH 1
1018#define R_PORT_PB_DIR__dir1__input 0
1019#define R_PORT_PB_DIR__dir1__output 1
1020#define R_PORT_PB_DIR__dir0__BITNR 0
1021#define R_PORT_PB_DIR__dir0__WIDTH 1
1022#define R_PORT_PB_DIR__dir0__input 0
1023#define R_PORT_PB_DIR__dir0__output 1
1024
1025#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
1026#define R_PORT_PB_CONFIG__cs7__BITNR 7
1027#define R_PORT_PB_CONFIG__cs7__WIDTH 1
1028#define R_PORT_PB_CONFIG__cs7__port 0
1029#define R_PORT_PB_CONFIG__cs7__cs 1
1030#define R_PORT_PB_CONFIG__cs6__BITNR 6
1031#define R_PORT_PB_CONFIG__cs6__WIDTH 1
1032#define R_PORT_PB_CONFIG__cs6__port 0
1033#define R_PORT_PB_CONFIG__cs6__cs 1
1034#define R_PORT_PB_CONFIG__cs5__BITNR 5
1035#define R_PORT_PB_CONFIG__cs5__WIDTH 1
1036#define R_PORT_PB_CONFIG__cs5__port 0
1037#define R_PORT_PB_CONFIG__cs5__cs 1
1038#define R_PORT_PB_CONFIG__cs4__BITNR 4
1039#define R_PORT_PB_CONFIG__cs4__WIDTH 1
1040#define R_PORT_PB_CONFIG__cs4__port 0
1041#define R_PORT_PB_CONFIG__cs4__cs 1
1042#define R_PORT_PB_CONFIG__cs3__BITNR 3
1043#define R_PORT_PB_CONFIG__cs3__WIDTH 1
1044#define R_PORT_PB_CONFIG__cs3__port 0
1045#define R_PORT_PB_CONFIG__cs3__cs 1
1046#define R_PORT_PB_CONFIG__cs2__BITNR 2
1047#define R_PORT_PB_CONFIG__cs2__WIDTH 1
1048#define R_PORT_PB_CONFIG__cs2__port 0
1049#define R_PORT_PB_CONFIG__cs2__cs 1
1050#define R_PORT_PB_CONFIG__scsi1__BITNR 1
1051#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
1052#define R_PORT_PB_CONFIG__scsi1__port_cs 0
1053#define R_PORT_PB_CONFIG__scsi1__enph 1
1054#define R_PORT_PB_CONFIG__scsi0__BITNR 0
1055#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
1056#define R_PORT_PB_CONFIG__scsi0__port_cs 0
1057#define R_PORT_PB_CONFIG__scsi0__enph 1
1058
1059#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
1060#define R_PORT_PB_I2C__syncser3__BITNR 5
1061#define R_PORT_PB_I2C__syncser3__WIDTH 1
1062#define R_PORT_PB_I2C__syncser3__port_cs 0
1063#define R_PORT_PB_I2C__syncser3__ss3extra 1
1064#define R_PORT_PB_I2C__syncser1__BITNR 4
1065#define R_PORT_PB_I2C__syncser1__WIDTH 1
1066#define R_PORT_PB_I2C__syncser1__port_cs 0
1067#define R_PORT_PB_I2C__syncser1__ss1extra 1
1068#define R_PORT_PB_I2C__i2c_en__BITNR 3
1069#define R_PORT_PB_I2C__i2c_en__WIDTH 1
1070#define R_PORT_PB_I2C__i2c_en__off 0
1071#define R_PORT_PB_I2C__i2c_en__on 1
1072#define R_PORT_PB_I2C__i2c_d__BITNR 2
1073#define R_PORT_PB_I2C__i2c_d__WIDTH 1
1074#define R_PORT_PB_I2C__i2c_clk__BITNR 1
1075#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
1076#define R_PORT_PB_I2C__i2c_oe___BITNR 0
1077#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
1078#define R_PORT_PB_I2C__i2c_oe___enable 0
1079#define R_PORT_PB_I2C__i2c_oe___disable 1
1080
1081#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
1082#define R_PORT_PB_READ__data_in__BITNR 0
1083#define R_PORT_PB_READ__data_in__WIDTH 8
1084
1085/*
1086!* Serial port registers
1087!*/
1088
1089#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
1090#define R_SERIAL0_CTRL__tr_baud__BITNR 28
1091#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
1092#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
1093#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
1094#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
1095#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
1096#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
1097#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
1098#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
1099#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
1100#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
1101#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
1102#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
1103#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
1104#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
1105#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
1106#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
1107#define R_SERIAL0_CTRL__tr_baud__reserved 15
1108#define R_SERIAL0_CTRL__rec_baud__BITNR 24
1109#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
1110#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
1111#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
1112#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
1113#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
1114#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
1115#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
1116#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
1117#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
1118#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
1119#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
1120#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
1121#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
1122#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
1123#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
1124#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
1125#define R_SERIAL0_CTRL__rec_baud__reserved 15
1126#define R_SERIAL0_CTRL__dma_err__BITNR 23
1127#define R_SERIAL0_CTRL__dma_err__WIDTH 1
1128#define R_SERIAL0_CTRL__dma_err__stop 0
1129#define R_SERIAL0_CTRL__dma_err__ignore 1
1130#define R_SERIAL0_CTRL__rec_enable__BITNR 22
1131#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
1132#define R_SERIAL0_CTRL__rec_enable__disable 0
1133#define R_SERIAL0_CTRL__rec_enable__enable 1
1134#define R_SERIAL0_CTRL__rts___BITNR 21
1135#define R_SERIAL0_CTRL__rts___WIDTH 1
1136#define R_SERIAL0_CTRL__rts___active 0
1137#define R_SERIAL0_CTRL__rts___inactive 1
1138#define R_SERIAL0_CTRL__sampling__BITNR 20
1139#define R_SERIAL0_CTRL__sampling__WIDTH 1
1140#define R_SERIAL0_CTRL__sampling__middle 0
1141#define R_SERIAL0_CTRL__sampling__majority 1
1142#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
1143#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
1144#define R_SERIAL0_CTRL__rec_stick_par__normal 0
1145#define R_SERIAL0_CTRL__rec_stick_par__stick 1
1146#define R_SERIAL0_CTRL__rec_par__BITNR 18
1147#define R_SERIAL0_CTRL__rec_par__WIDTH 1
1148#define R_SERIAL0_CTRL__rec_par__even 0
1149#define R_SERIAL0_CTRL__rec_par__odd 1
1150#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
1151#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
1152#define R_SERIAL0_CTRL__rec_par_en__disable 0
1153#define R_SERIAL0_CTRL__rec_par_en__enable 1
1154#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
1155#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
1156#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
1157#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
1158#define R_SERIAL0_CTRL__txd__BITNR 15
1159#define R_SERIAL0_CTRL__txd__WIDTH 1
1160#define R_SERIAL0_CTRL__tr_enable__BITNR 14
1161#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
1162#define R_SERIAL0_CTRL__tr_enable__disable 0
1163#define R_SERIAL0_CTRL__tr_enable__enable 1
1164#define R_SERIAL0_CTRL__auto_cts__BITNR 13
1165#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
1166#define R_SERIAL0_CTRL__auto_cts__disabled 0
1167#define R_SERIAL0_CTRL__auto_cts__active 1
1168#define R_SERIAL0_CTRL__stop_bits__BITNR 12
1169#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
1170#define R_SERIAL0_CTRL__stop_bits__one_bit 0
1171#define R_SERIAL0_CTRL__stop_bits__two_bits 1
1172#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
1173#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
1174#define R_SERIAL0_CTRL__tr_stick_par__normal 0
1175#define R_SERIAL0_CTRL__tr_stick_par__stick 1
1176#define R_SERIAL0_CTRL__tr_par__BITNR 10
1177#define R_SERIAL0_CTRL__tr_par__WIDTH 1
1178#define R_SERIAL0_CTRL__tr_par__even 0
1179#define R_SERIAL0_CTRL__tr_par__odd 1
1180#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
1181#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
1182#define R_SERIAL0_CTRL__tr_par_en__disable 0
1183#define R_SERIAL0_CTRL__tr_par_en__enable 1
1184#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
1185#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
1186#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
1187#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
1188#define R_SERIAL0_CTRL__data_out__BITNR 0
1189#define R_SERIAL0_CTRL__data_out__WIDTH 8
1190
1191#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
1192#define R_SERIAL0_BAUD__tr_baud__BITNR 4
1193#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
1194#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
1195#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
1196#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
1197#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
1198#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
1199#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
1200#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
1201#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
1202#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
1203#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
1204#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
1205#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
1206#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
1207#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
1208#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
1209#define R_SERIAL0_BAUD__tr_baud__reserved 15
1210#define R_SERIAL0_BAUD__rec_baud__BITNR 0
1211#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
1212#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
1213#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
1214#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
1215#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
1216#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
1217#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
1218#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
1219#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
1220#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
1221#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
1222#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
1223#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
1224#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
1225#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
1226#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
1227#define R_SERIAL0_BAUD__rec_baud__reserved 15
1228
1229#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
1230#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
1231#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
1232#define R_SERIAL0_REC_CTRL__dma_err__stop 0
1233#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
1234#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
1235#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
1236#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
1237#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
1238#define R_SERIAL0_REC_CTRL__rts___BITNR 5
1239#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
1240#define R_SERIAL0_REC_CTRL__rts___active 0
1241#define R_SERIAL0_REC_CTRL__rts___inactive 1
1242#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
1243#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
1244#define R_SERIAL0_REC_CTRL__sampling__middle 0
1245#define R_SERIAL0_REC_CTRL__sampling__majority 1
1246#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
1247#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
1248#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
1249#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
1250#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
1251#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
1252#define R_SERIAL0_REC_CTRL__rec_par__even 0
1253#define R_SERIAL0_REC_CTRL__rec_par__odd 1
1254#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
1255#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
1256#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
1257#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
1258#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
1259#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
1260#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
1261#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1
1262
1263#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
1264#define R_SERIAL0_TR_CTRL__txd__BITNR 7
1265#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
1266#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
1267#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
1268#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
1269#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
1270#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
1271#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
1272#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
1273#define R_SERIAL0_TR_CTRL__auto_cts__active 1
1274#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
1275#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
1276#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
1277#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
1278#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
1279#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
1280#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
1281#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
1282#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
1283#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
1284#define R_SERIAL0_TR_CTRL__tr_par__even 0
1285#define R_SERIAL0_TR_CTRL__tr_par__odd 1
1286#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
1287#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
1288#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
1289#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
1290#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
1291#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
1292#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
1293#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1
1294
1295#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
1296#define R_SERIAL0_TR_DATA__data_out__BITNR 0
1297#define R_SERIAL0_TR_DATA__data_out__WIDTH 8
1298
1299#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
1300#define R_SERIAL0_READ__xoff_detect__BITNR 15
1301#define R_SERIAL0_READ__xoff_detect__WIDTH 1
1302#define R_SERIAL0_READ__xoff_detect__no_xoff 0
1303#define R_SERIAL0_READ__xoff_detect__xoff 1
1304#define R_SERIAL0_READ__cts___BITNR 14
1305#define R_SERIAL0_READ__cts___WIDTH 1
1306#define R_SERIAL0_READ__cts___active 0
1307#define R_SERIAL0_READ__cts___inactive 1
1308#define R_SERIAL0_READ__tr_ready__BITNR 13
1309#define R_SERIAL0_READ__tr_ready__WIDTH 1
1310#define R_SERIAL0_READ__tr_ready__full 0
1311#define R_SERIAL0_READ__tr_ready__ready 1
1312#define R_SERIAL0_READ__rxd__BITNR 12
1313#define R_SERIAL0_READ__rxd__WIDTH 1
1314#define R_SERIAL0_READ__overrun__BITNR 11
1315#define R_SERIAL0_READ__overrun__WIDTH 1
1316#define R_SERIAL0_READ__overrun__no 0
1317#define R_SERIAL0_READ__overrun__yes 1
1318#define R_SERIAL0_READ__par_err__BITNR 10
1319#define R_SERIAL0_READ__par_err__WIDTH 1
1320#define R_SERIAL0_READ__par_err__no 0
1321#define R_SERIAL0_READ__par_err__yes 1
1322#define R_SERIAL0_READ__framing_err__BITNR 9
1323#define R_SERIAL0_READ__framing_err__WIDTH 1
1324#define R_SERIAL0_READ__framing_err__no 0
1325#define R_SERIAL0_READ__framing_err__yes 1
1326#define R_SERIAL0_READ__data_avail__BITNR 8
1327#define R_SERIAL0_READ__data_avail__WIDTH 1
1328#define R_SERIAL0_READ__data_avail__no 0
1329#define R_SERIAL0_READ__data_avail__yes 1
1330#define R_SERIAL0_READ__data_in__BITNR 0
1331#define R_SERIAL0_READ__data_in__WIDTH 8
1332
1333#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
1334#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
1335#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
1336#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
1337#define R_SERIAL0_STATUS__xoff_detect__xoff 1
1338#define R_SERIAL0_STATUS__cts___BITNR 6
1339#define R_SERIAL0_STATUS__cts___WIDTH 1
1340#define R_SERIAL0_STATUS__cts___active 0
1341#define R_SERIAL0_STATUS__cts___inactive 1
1342#define R_SERIAL0_STATUS__tr_ready__BITNR 5
1343#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
1344#define R_SERIAL0_STATUS__tr_ready__full 0
1345#define R_SERIAL0_STATUS__tr_ready__ready 1
1346#define R_SERIAL0_STATUS__rxd__BITNR 4
1347#define R_SERIAL0_STATUS__rxd__WIDTH 1
1348#define R_SERIAL0_STATUS__overrun__BITNR 3
1349#define R_SERIAL0_STATUS__overrun__WIDTH 1
1350#define R_SERIAL0_STATUS__overrun__no 0
1351#define R_SERIAL0_STATUS__overrun__yes 1
1352#define R_SERIAL0_STATUS__par_err__BITNR 2
1353#define R_SERIAL0_STATUS__par_err__WIDTH 1
1354#define R_SERIAL0_STATUS__par_err__no 0
1355#define R_SERIAL0_STATUS__par_err__yes 1
1356#define R_SERIAL0_STATUS__framing_err__BITNR 1
1357#define R_SERIAL0_STATUS__framing_err__WIDTH 1
1358#define R_SERIAL0_STATUS__framing_err__no 0
1359#define R_SERIAL0_STATUS__framing_err__yes 1
1360#define R_SERIAL0_STATUS__data_avail__BITNR 0
1361#define R_SERIAL0_STATUS__data_avail__WIDTH 1
1362#define R_SERIAL0_STATUS__data_avail__no 0
1363#define R_SERIAL0_STATUS__data_avail__yes 1
1364
1365#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
1366#define R_SERIAL0_REC_DATA__data_in__BITNR 0
1367#define R_SERIAL0_REC_DATA__data_in__WIDTH 8
1368
1369#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
1370#define R_SERIAL0_XOFF__tx_stop__BITNR 9
1371#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
1372#define R_SERIAL0_XOFF__tx_stop__enable 0
1373#define R_SERIAL0_XOFF__tx_stop__stop 1
1374#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
1375#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
1376#define R_SERIAL0_XOFF__auto_xoff__disable 0
1377#define R_SERIAL0_XOFF__auto_xoff__enable 1
1378#define R_SERIAL0_XOFF__xoff_char__BITNR 0
1379#define R_SERIAL0_XOFF__xoff_char__WIDTH 8
1380
1381#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
1382#define R_SERIAL1_CTRL__tr_baud__BITNR 28
1383#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
1384#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
1385#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
1386#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
1387#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
1388#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
1389#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
1390#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
1391#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
1392#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
1393#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
1394#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
1395#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
1396#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
1397#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
1398#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
1399#define R_SERIAL1_CTRL__tr_baud__reserved 15
1400#define R_SERIAL1_CTRL__rec_baud__BITNR 24
1401#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
1402#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
1403#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
1404#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
1405#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
1406#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
1407#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
1408#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
1409#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
1410#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
1411#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
1412#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
1413#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
1414#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
1415#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
1416#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
1417#define R_SERIAL1_CTRL__rec_baud__reserved 15
1418#define R_SERIAL1_CTRL__dma_err__BITNR 23
1419#define R_SERIAL1_CTRL__dma_err__WIDTH 1
1420#define R_SERIAL1_CTRL__dma_err__stop 0
1421#define R_SERIAL1_CTRL__dma_err__ignore 1
1422#define R_SERIAL1_CTRL__rec_enable__BITNR 22
1423#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
1424#define R_SERIAL1_CTRL__rec_enable__disable 0
1425#define R_SERIAL1_CTRL__rec_enable__enable 1
1426#define R_SERIAL1_CTRL__rts___BITNR 21
1427#define R_SERIAL1_CTRL__rts___WIDTH 1
1428#define R_SERIAL1_CTRL__rts___active 0
1429#define R_SERIAL1_CTRL__rts___inactive 1
1430#define R_SERIAL1_CTRL__sampling__BITNR 20
1431#define R_SERIAL1_CTRL__sampling__WIDTH 1
1432#define R_SERIAL1_CTRL__sampling__middle 0
1433#define R_SERIAL1_CTRL__sampling__majority 1
1434#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
1435#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
1436#define R_SERIAL1_CTRL__rec_stick_par__normal 0
1437#define R_SERIAL1_CTRL__rec_stick_par__stick 1
1438#define R_SERIAL1_CTRL__rec_par__BITNR 18
1439#define R_SERIAL1_CTRL__rec_par__WIDTH 1
1440#define R_SERIAL1_CTRL__rec_par__even 0
1441#define R_SERIAL1_CTRL__rec_par__odd 1
1442#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
1443#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
1444#define R_SERIAL1_CTRL__rec_par_en__disable 0
1445#define R_SERIAL1_CTRL__rec_par_en__enable 1
1446#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
1447#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
1448#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
1449#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
1450#define R_SERIAL1_CTRL__txd__BITNR 15
1451#define R_SERIAL1_CTRL__txd__WIDTH 1
1452#define R_SERIAL1_CTRL__tr_enable__BITNR 14
1453#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
1454#define R_SERIAL1_CTRL__tr_enable__disable 0
1455#define R_SERIAL1_CTRL__tr_enable__enable 1
1456#define R_SERIAL1_CTRL__auto_cts__BITNR 13
1457#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
1458#define R_SERIAL1_CTRL__auto_cts__disabled 0
1459#define R_SERIAL1_CTRL__auto_cts__active 1
1460#define R_SERIAL1_CTRL__stop_bits__BITNR 12
1461#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
1462#define R_SERIAL1_CTRL__stop_bits__one_bit 0
1463#define R_SERIAL1_CTRL__stop_bits__two_bits 1
1464#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
1465#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
1466#define R_SERIAL1_CTRL__tr_stick_par__normal 0
1467#define R_SERIAL1_CTRL__tr_stick_par__stick 1
1468#define R_SERIAL1_CTRL__tr_par__BITNR 10
1469#define R_SERIAL1_CTRL__tr_par__WIDTH 1
1470#define R_SERIAL1_CTRL__tr_par__even 0
1471#define R_SERIAL1_CTRL__tr_par__odd 1
1472#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
1473#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
1474#define R_SERIAL1_CTRL__tr_par_en__disable 0
1475#define R_SERIAL1_CTRL__tr_par_en__enable 1
1476#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
1477#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
1478#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
1479#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
1480#define R_SERIAL1_CTRL__data_out__BITNR 0
1481#define R_SERIAL1_CTRL__data_out__WIDTH 8
1482
1483#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
1484#define R_SERIAL1_BAUD__tr_baud__BITNR 4
1485#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
1486#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
1487#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
1488#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
1489#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
1490#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
1491#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
1492#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
1493#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
1494#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
1495#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
1496#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
1497#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
1498#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
1499#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
1500#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
1501#define R_SERIAL1_BAUD__tr_baud__reserved 15
1502#define R_SERIAL1_BAUD__rec_baud__BITNR 0
1503#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
1504#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
1505#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
1506#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
1507#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
1508#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
1509#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
1510#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
1511#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
1512#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
1513#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
1514#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
1515#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
1516#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
1517#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
1518#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
1519#define R_SERIAL1_BAUD__rec_baud__reserved 15
1520
1521#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
1522#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
1523#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
1524#define R_SERIAL1_REC_CTRL__dma_err__stop 0
1525#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
1526#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
1527#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
1528#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
1529#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
1530#define R_SERIAL1_REC_CTRL__rts___BITNR 5
1531#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
1532#define R_SERIAL1_REC_CTRL__rts___active 0
1533#define R_SERIAL1_REC_CTRL__rts___inactive 1
1534#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
1535#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
1536#define R_SERIAL1_REC_CTRL__sampling__middle 0
1537#define R_SERIAL1_REC_CTRL__sampling__majority 1
1538#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
1539#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
1540#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
1541#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
1542#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
1543#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
1544#define R_SERIAL1_REC_CTRL__rec_par__even 0
1545#define R_SERIAL1_REC_CTRL__rec_par__odd 1
1546#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
1547#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
1548#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
1549#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
1550#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
1551#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
1552#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
1553#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1
1554
1555#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
1556#define R_SERIAL1_TR_CTRL__txd__BITNR 7
1557#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
1558#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
1559#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
1560#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
1561#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
1562#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
1563#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
1564#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
1565#define R_SERIAL1_TR_CTRL__auto_cts__active 1
1566#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
1567#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
1568#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
1569#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
1570#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
1571#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
1572#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
1573#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
1574#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
1575#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
1576#define R_SERIAL1_TR_CTRL__tr_par__even 0
1577#define R_SERIAL1_TR_CTRL__tr_par__odd 1
1578#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
1579#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
1580#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
1581#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
1582#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
1583#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
1584#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
1585#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1
1586
1587#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
1588#define R_SERIAL1_TR_DATA__data_out__BITNR 0
1589#define R_SERIAL1_TR_DATA__data_out__WIDTH 8
1590
1591#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
1592#define R_SERIAL1_READ__xoff_detect__BITNR 15
1593#define R_SERIAL1_READ__xoff_detect__WIDTH 1
1594#define R_SERIAL1_READ__xoff_detect__no_xoff 0
1595#define R_SERIAL1_READ__xoff_detect__xoff 1
1596#define R_SERIAL1_READ__cts___BITNR 14
1597#define R_SERIAL1_READ__cts___WIDTH 1
1598#define R_SERIAL1_READ__cts___active 0
1599#define R_SERIAL1_READ__cts___inactive 1
1600#define R_SERIAL1_READ__tr_ready__BITNR 13
1601#define R_SERIAL1_READ__tr_ready__WIDTH 1
1602#define R_SERIAL1_READ__tr_ready__full 0
1603#define R_SERIAL1_READ__tr_ready__ready 1
1604#define R_SERIAL1_READ__rxd__BITNR 12
1605#define R_SERIAL1_READ__rxd__WIDTH 1
1606#define R_SERIAL1_READ__overrun__BITNR 11
1607#define R_SERIAL1_READ__overrun__WIDTH 1
1608#define R_SERIAL1_READ__overrun__no 0
1609#define R_SERIAL1_READ__overrun__yes 1
1610#define R_SERIAL1_READ__par_err__BITNR 10
1611#define R_SERIAL1_READ__par_err__WIDTH 1
1612#define R_SERIAL1_READ__par_err__no 0
1613#define R_SERIAL1_READ__par_err__yes 1
1614#define R_SERIAL1_READ__framing_err__BITNR 9
1615#define R_SERIAL1_READ__framing_err__WIDTH 1
1616#define R_SERIAL1_READ__framing_err__no 0
1617#define R_SERIAL1_READ__framing_err__yes 1
1618#define R_SERIAL1_READ__data_avail__BITNR 8
1619#define R_SERIAL1_READ__data_avail__WIDTH 1
1620#define R_SERIAL1_READ__data_avail__no 0
1621#define R_SERIAL1_READ__data_avail__yes 1
1622#define R_SERIAL1_READ__data_in__BITNR 0
1623#define R_SERIAL1_READ__data_in__WIDTH 8
1624
1625#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
1626#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
1627#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
1628#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
1629#define R_SERIAL1_STATUS__xoff_detect__xoff 1
1630#define R_SERIAL1_STATUS__cts___BITNR 6
1631#define R_SERIAL1_STATUS__cts___WIDTH 1
1632#define R_SERIAL1_STATUS__cts___active 0
1633#define R_SERIAL1_STATUS__cts___inactive 1
1634#define R_SERIAL1_STATUS__tr_ready__BITNR 5
1635#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
1636#define R_SERIAL1_STATUS__tr_ready__full 0
1637#define R_SERIAL1_STATUS__tr_ready__ready 1
1638#define R_SERIAL1_STATUS__rxd__BITNR 4
1639#define R_SERIAL1_STATUS__rxd__WIDTH 1
1640#define R_SERIAL1_STATUS__overrun__BITNR 3
1641#define R_SERIAL1_STATUS__overrun__WIDTH 1
1642#define R_SERIAL1_STATUS__overrun__no 0
1643#define R_SERIAL1_STATUS__overrun__yes 1
1644#define R_SERIAL1_STATUS__par_err__BITNR 2
1645#define R_SERIAL1_STATUS__par_err__WIDTH 1
1646#define R_SERIAL1_STATUS__par_err__no 0
1647#define R_SERIAL1_STATUS__par_err__yes 1
1648#define R_SERIAL1_STATUS__framing_err__BITNR 1
1649#define R_SERIAL1_STATUS__framing_err__WIDTH 1
1650#define R_SERIAL1_STATUS__framing_err__no 0
1651#define R_SERIAL1_STATUS__framing_err__yes 1
1652#define R_SERIAL1_STATUS__data_avail__BITNR 0
1653#define R_SERIAL1_STATUS__data_avail__WIDTH 1
1654#define R_SERIAL1_STATUS__data_avail__no 0
1655#define R_SERIAL1_STATUS__data_avail__yes 1
1656
1657#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068)
1658#define R_SERIAL1_REC_DATA__data_in__BITNR 0
1659#define R_SERIAL1_REC_DATA__data_in__WIDTH 8
1660
1661#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c)
1662#define R_SERIAL1_XOFF__tx_stop__BITNR 9
1663#define R_SERIAL1_XOFF__tx_stop__WIDTH 1
1664#define R_SERIAL1_XOFF__tx_stop__enable 0
1665#define R_SERIAL1_XOFF__tx_stop__stop 1
1666#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
1667#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1
1668#define R_SERIAL1_XOFF__auto_xoff__disable 0
1669#define R_SERIAL1_XOFF__auto_xoff__enable 1
1670#define R_SERIAL1_XOFF__xoff_char__BITNR 0
1671#define R_SERIAL1_XOFF__xoff_char__WIDTH 8
1672
1673#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070)
1674#define R_SERIAL2_CTRL__tr_baud__BITNR 28
1675#define R_SERIAL2_CTRL__tr_baud__WIDTH 4
1676#define R_SERIAL2_CTRL__tr_baud__c300Hz 0
1677#define R_SERIAL2_CTRL__tr_baud__c600Hz 1
1678#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2
1679#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3
1680#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4
1681#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5
1682#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6
1683#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7
1684#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8
1685#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9
1686#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10
1687#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11
1688#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12
1689#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13
1690#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14
1691#define R_SERIAL2_CTRL__tr_baud__reserved 15
1692#define R_SERIAL2_CTRL__rec_baud__BITNR 24
1693#define R_SERIAL2_CTRL__rec_baud__WIDTH 4
1694#define R_SERIAL2_CTRL__rec_baud__c300Hz 0
1695#define R_SERIAL2_CTRL__rec_baud__c600Hz 1
1696#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2
1697#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3
1698#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4
1699#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5
1700#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6
1701#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7
1702#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8
1703#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9
1704#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10
1705#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11
1706#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12
1707#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13
1708#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14
1709#define R_SERIAL2_CTRL__rec_baud__reserved 15
1710#define R_SERIAL2_CTRL__dma_err__BITNR 23
1711#define R_SERIAL2_CTRL__dma_err__WIDTH 1
1712#define R_SERIAL2_CTRL__dma_err__stop 0
1713#define R_SERIAL2_CTRL__dma_err__ignore 1
1714#define R_SERIAL2_CTRL__rec_enable__BITNR 22
1715#define R_SERIAL2_CTRL__rec_enable__WIDTH 1
1716#define R_SERIAL2_CTRL__rec_enable__disable 0
1717#define R_SERIAL2_CTRL__rec_enable__enable 1
1718#define R_SERIAL2_CTRL__rts___BITNR 21
1719#define R_SERIAL2_CTRL__rts___WIDTH 1
1720#define R_SERIAL2_CTRL__rts___active 0
1721#define R_SERIAL2_CTRL__rts___inactive 1
1722#define R_SERIAL2_CTRL__sampling__BITNR 20
1723#define R_SERIAL2_CTRL__sampling__WIDTH 1
1724#define R_SERIAL2_CTRL__sampling__middle 0
1725#define R_SERIAL2_CTRL__sampling__majority 1
1726#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
1727#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1
1728#define R_SERIAL2_CTRL__rec_stick_par__normal 0
1729#define R_SERIAL2_CTRL__rec_stick_par__stick 1
1730#define R_SERIAL2_CTRL__rec_par__BITNR 18
1731#define R_SERIAL2_CTRL__rec_par__WIDTH 1
1732#define R_SERIAL2_CTRL__rec_par__even 0
1733#define R_SERIAL2_CTRL__rec_par__odd 1
1734#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
1735#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1
1736#define R_SERIAL2_CTRL__rec_par_en__disable 0
1737#define R_SERIAL2_CTRL__rec_par_en__enable 1
1738#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
1739#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1
1740#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0
1741#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1
1742#define R_SERIAL2_CTRL__txd__BITNR 15
1743#define R_SERIAL2_CTRL__txd__WIDTH 1
1744#define R_SERIAL2_CTRL__tr_enable__BITNR 14
1745#define R_SERIAL2_CTRL__tr_enable__WIDTH 1
1746#define R_SERIAL2_CTRL__tr_enable__disable 0
1747#define R_SERIAL2_CTRL__tr_enable__enable 1
1748#define R_SERIAL2_CTRL__auto_cts__BITNR 13
1749#define R_SERIAL2_CTRL__auto_cts__WIDTH 1
1750#define R_SERIAL2_CTRL__auto_cts__disabled 0
1751#define R_SERIAL2_CTRL__auto_cts__active 1
1752#define R_SERIAL2_CTRL__stop_bits__BITNR 12
1753#define R_SERIAL2_CTRL__stop_bits__WIDTH 1
1754#define R_SERIAL2_CTRL__stop_bits__one_bit 0
1755#define R_SERIAL2_CTRL__stop_bits__two_bits 1
1756#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
1757#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1
1758#define R_SERIAL2_CTRL__tr_stick_par__normal 0
1759#define R_SERIAL2_CTRL__tr_stick_par__stick 1
1760#define R_SERIAL2_CTRL__tr_par__BITNR 10
1761#define R_SERIAL2_CTRL__tr_par__WIDTH 1
1762#define R_SERIAL2_CTRL__tr_par__even 0
1763#define R_SERIAL2_CTRL__tr_par__odd 1
1764#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
1765#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1
1766#define R_SERIAL2_CTRL__tr_par_en__disable 0
1767#define R_SERIAL2_CTRL__tr_par_en__enable 1
1768#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
1769#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1
1770#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0
1771#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1
1772#define R_SERIAL2_CTRL__data_out__BITNR 0
1773#define R_SERIAL2_CTRL__data_out__WIDTH 8
1774
1775#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073)
1776#define R_SERIAL2_BAUD__tr_baud__BITNR 4
1777#define R_SERIAL2_BAUD__tr_baud__WIDTH 4
1778#define R_SERIAL2_BAUD__tr_baud__c300Hz 0
1779#define R_SERIAL2_BAUD__tr_baud__c600Hz 1
1780#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2
1781#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3
1782#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4
1783#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5
1784#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6
1785#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7
1786#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8
1787#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9
1788#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10
1789#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11
1790#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12
1791#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13
1792#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14
1793#define R_SERIAL2_BAUD__tr_baud__reserved 15
1794#define R_SERIAL2_BAUD__rec_baud__BITNR 0
1795#define R_SERIAL2_BAUD__rec_baud__WIDTH 4
1796#define R_SERIAL2_BAUD__rec_baud__c300Hz 0
1797#define R_SERIAL2_BAUD__rec_baud__c600Hz 1
1798#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2
1799#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3
1800#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4
1801#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5
1802#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6
1803#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7
1804#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8
1805#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9
1806#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10
1807#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11
1808#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12
1809#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13
1810#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14
1811#define R_SERIAL2_BAUD__rec_baud__reserved 15
1812
1813#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072)
1814#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
1815#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1
1816#define R_SERIAL2_REC_CTRL__dma_err__stop 0
1817#define R_SERIAL2_REC_CTRL__dma_err__ignore 1
1818#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
1819#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1
1820#define R_SERIAL2_REC_CTRL__rec_enable__disable 0
1821#define R_SERIAL2_REC_CTRL__rec_enable__enable 1
1822#define R_SERIAL2_REC_CTRL__rts___BITNR 5
1823#define R_SERIAL2_REC_CTRL__rts___WIDTH 1
1824#define R_SERIAL2_REC_CTRL__rts___active 0
1825#define R_SERIAL2_REC_CTRL__rts___inactive 1
1826#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
1827#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1
1828#define R_SERIAL2_REC_CTRL__sampling__middle 0
1829#define R_SERIAL2_REC_CTRL__sampling__majority 1
1830#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
1831#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1
1832#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0
1833#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1
1834#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
1835#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1
1836#define R_SERIAL2_REC_CTRL__rec_par__even 0
1837#define R_SERIAL2_REC_CTRL__rec_par__odd 1
1838#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
1839#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1
1840#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0
1841#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1
1842#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
1843#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1
1844#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0
1845#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1
1846
1847#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071)
1848#define R_SERIAL2_TR_CTRL__txd__BITNR 7
1849#define R_SERIAL2_TR_CTRL__txd__WIDTH 1
1850#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
1851#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1
1852#define R_SERIAL2_TR_CTRL__tr_enable__disable 0
1853#define R_SERIAL2_TR_CTRL__tr_enable__enable 1
1854#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
1855#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1
1856#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0
1857#define R_SERIAL2_TR_CTRL__auto_cts__active 1
1858#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
1859#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1
1860#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0
1861#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1
1862#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
1863#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1
1864#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0
1865#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1
1866#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
1867#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1
1868#define R_SERIAL2_TR_CTRL__tr_par__even 0
1869#define R_SERIAL2_TR_CTRL__tr_par__odd 1
1870#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
1871#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1
1872#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0
1873#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1
1874#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
1875#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1
1876#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0
1877#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1
1878
1879#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070)
1880#define R_SERIAL2_TR_DATA__data_out__BITNR 0
1881#define R_SERIAL2_TR_DATA__data_out__WIDTH 8
1882
1883#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070)
1884#define R_SERIAL2_READ__xoff_detect__BITNR 15
1885#define R_SERIAL2_READ__xoff_detect__WIDTH 1
1886#define R_SERIAL2_READ__xoff_detect__no_xoff 0
1887#define R_SERIAL2_READ__xoff_detect__xoff 1
1888#define R_SERIAL2_READ__cts___BITNR 14
1889#define R_SERIAL2_READ__cts___WIDTH 1
1890#define R_SERIAL2_READ__cts___active 0
1891#define R_SERIAL2_READ__cts___inactive 1
1892#define R_SERIAL2_READ__tr_ready__BITNR 13
1893#define R_SERIAL2_READ__tr_ready__WIDTH 1
1894#define R_SERIAL2_READ__tr_ready__full 0
1895#define R_SERIAL2_READ__tr_ready__ready 1
1896#define R_SERIAL2_READ__rxd__BITNR 12
1897#define R_SERIAL2_READ__rxd__WIDTH 1
1898#define R_SERIAL2_READ__overrun__BITNR 11
1899#define R_SERIAL2_READ__overrun__WIDTH 1
1900#define R_SERIAL2_READ__overrun__no 0
1901#define R_SERIAL2_READ__overrun__yes 1
1902#define R_SERIAL2_READ__par_err__BITNR 10
1903#define R_SERIAL2_READ__par_err__WIDTH 1
1904#define R_SERIAL2_READ__par_err__no 0
1905#define R_SERIAL2_READ__par_err__yes 1
1906#define R_SERIAL2_READ__framing_err__BITNR 9
1907#define R_SERIAL2_READ__framing_err__WIDTH 1
1908#define R_SERIAL2_READ__framing_err__no 0
1909#define R_SERIAL2_READ__framing_err__yes 1
1910#define R_SERIAL2_READ__data_avail__BITNR 8
1911#define R_SERIAL2_READ__data_avail__WIDTH 1
1912#define R_SERIAL2_READ__data_avail__no 0
1913#define R_SERIAL2_READ__data_avail__yes 1
1914#define R_SERIAL2_READ__data_in__BITNR 0
1915#define R_SERIAL2_READ__data_in__WIDTH 8
1916
1917#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071)
1918#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
1919#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1
1920#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0
1921#define R_SERIAL2_STATUS__xoff_detect__xoff 1
1922#define R_SERIAL2_STATUS__cts___BITNR 6
1923#define R_SERIAL2_STATUS__cts___WIDTH 1
1924#define R_SERIAL2_STATUS__cts___active 0
1925#define R_SERIAL2_STATUS__cts___inactive 1
1926#define R_SERIAL2_STATUS__tr_ready__BITNR 5
1927#define R_SERIAL2_STATUS__tr_ready__WIDTH 1
1928#define R_SERIAL2_STATUS__tr_ready__full 0
1929#define R_SERIAL2_STATUS__tr_ready__ready 1
1930#define R_SERIAL2_STATUS__rxd__BITNR 4
1931#define R_SERIAL2_STATUS__rxd__WIDTH 1
1932#define R_SERIAL2_STATUS__overrun__BITNR 3
1933#define R_SERIAL2_STATUS__overrun__WIDTH 1
1934#define R_SERIAL2_STATUS__overrun__no 0
1935#define R_SERIAL2_STATUS__overrun__yes 1
1936#define R_SERIAL2_STATUS__par_err__BITNR 2
1937#define R_SERIAL2_STATUS__par_err__WIDTH 1
1938#define R_SERIAL2_STATUS__par_err__no 0
1939#define R_SERIAL2_STATUS__par_err__yes 1
1940#define R_SERIAL2_STATUS__framing_err__BITNR 1
1941#define R_SERIAL2_STATUS__framing_err__WIDTH 1
1942#define R_SERIAL2_STATUS__framing_err__no 0
1943#define R_SERIAL2_STATUS__framing_err__yes 1
1944#define R_SERIAL2_STATUS__data_avail__BITNR 0
1945#define R_SERIAL2_STATUS__data_avail__WIDTH 1
1946#define R_SERIAL2_STATUS__data_avail__no 0
1947#define R_SERIAL2_STATUS__data_avail__yes 1
1948
1949#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070)
1950#define R_SERIAL2_REC_DATA__data_in__BITNR 0
1951#define R_SERIAL2_REC_DATA__data_in__WIDTH 8
1952
1953#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074)
1954#define R_SERIAL2_XOFF__tx_stop__BITNR 9
1955#define R_SERIAL2_XOFF__tx_stop__WIDTH 1
1956#define R_SERIAL2_XOFF__tx_stop__enable 0
1957#define R_SERIAL2_XOFF__tx_stop__stop 1
1958#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
1959#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1
1960#define R_SERIAL2_XOFF__auto_xoff__disable 0
1961#define R_SERIAL2_XOFF__auto_xoff__enable 1
1962#define R_SERIAL2_XOFF__xoff_char__BITNR 0
1963#define R_SERIAL2_XOFF__xoff_char__WIDTH 8
1964
1965#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
1966#define R_SERIAL3_CTRL__tr_baud__BITNR 28
1967#define R_SERIAL3_CTRL__tr_baud__WIDTH 4
1968#define R_SERIAL3_CTRL__tr_baud__c300Hz 0
1969#define R_SERIAL3_CTRL__tr_baud__c600Hz 1
1970#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2
1971#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3
1972#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4
1973#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5
1974#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6
1975#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7
1976#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8
1977#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9
1978#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10
1979#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11
1980#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12
1981#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13
1982#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14
1983#define R_SERIAL3_CTRL__tr_baud__reserved 15
1984#define R_SERIAL3_CTRL__rec_baud__BITNR 24
1985#define R_SERIAL3_CTRL__rec_baud__WIDTH 4
1986#define R_SERIAL3_CTRL__rec_baud__c300Hz 0
1987#define R_SERIAL3_CTRL__rec_baud__c600Hz 1
1988#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2
1989#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3
1990#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4
1991#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5
1992#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6
1993#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7
1994#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8
1995#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9
1996#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10
1997#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11
1998#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12
1999#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13
2000#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14
2001#define R_SERIAL3_CTRL__rec_baud__reserved 15
2002#define R_SERIAL3_CTRL__dma_err__BITNR 23
2003#define R_SERIAL3_CTRL__dma_err__WIDTH 1
2004#define R_SERIAL3_CTRL__dma_err__stop 0
2005#define R_SERIAL3_CTRL__dma_err__ignore 1
2006#define R_SERIAL3_CTRL__rec_enable__BITNR 22
2007#define R_SERIAL3_CTRL__rec_enable__WIDTH 1
2008#define R_SERIAL3_CTRL__rec_enable__disable 0
2009#define R_SERIAL3_CTRL__rec_enable__enable 1
2010#define R_SERIAL3_CTRL__rts___BITNR 21
2011#define R_SERIAL3_CTRL__rts___WIDTH 1
2012#define R_SERIAL3_CTRL__rts___active 0
2013#define R_SERIAL3_CTRL__rts___inactive 1
2014#define R_SERIAL3_CTRL__sampling__BITNR 20
2015#define R_SERIAL3_CTRL__sampling__WIDTH 1
2016#define R_SERIAL3_CTRL__sampling__middle 0
2017#define R_SERIAL3_CTRL__sampling__majority 1
2018#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
2019#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1
2020#define R_SERIAL3_CTRL__rec_stick_par__normal 0
2021#define R_SERIAL3_CTRL__rec_stick_par__stick 1
2022#define R_SERIAL3_CTRL__rec_par__BITNR 18
2023#define R_SERIAL3_CTRL__rec_par__WIDTH 1
2024#define R_SERIAL3_CTRL__rec_par__even 0
2025#define R_SERIAL3_CTRL__rec_par__odd 1
2026#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
2027#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1
2028#define R_SERIAL3_CTRL__rec_par_en__disable 0
2029#define R_SERIAL3_CTRL__rec_par_en__enable 1
2030#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
2031#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1
2032#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0
2033#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1
2034#define R_SERIAL3_CTRL__txd__BITNR 15
2035#define R_SERIAL3_CTRL__txd__WIDTH 1
2036#define R_SERIAL3_CTRL__tr_enable__BITNR 14
2037#define R_SERIAL3_CTRL__tr_enable__WIDTH 1
2038#define R_SERIAL3_CTRL__tr_enable__disable 0
2039#define R_SERIAL3_CTRL__tr_enable__enable 1
2040#define R_SERIAL3_CTRL__auto_cts__BITNR 13
2041#define R_SERIAL3_CTRL__auto_cts__WIDTH 1
2042#define R_SERIAL3_CTRL__auto_cts__disabled 0
2043#define R_SERIAL3_CTRL__auto_cts__active 1
2044#define R_SERIAL3_CTRL__stop_bits__BITNR 12
2045#define R_SERIAL3_CTRL__stop_bits__WIDTH 1
2046#define R_SERIAL3_CTRL__stop_bits__one_bit 0
2047#define R_SERIAL3_CTRL__stop_bits__two_bits 1
2048#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
2049#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1
2050#define R_SERIAL3_CTRL__tr_stick_par__normal 0
2051#define R_SERIAL3_CTRL__tr_stick_par__stick 1
2052#define R_SERIAL3_CTRL__tr_par__BITNR 10
2053#define R_SERIAL3_CTRL__tr_par__WIDTH 1
2054#define R_SERIAL3_CTRL__tr_par__even 0
2055#define R_SERIAL3_CTRL__tr_par__odd 1
2056#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
2057#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1
2058#define R_SERIAL3_CTRL__tr_par_en__disable 0
2059#define R_SERIAL3_CTRL__tr_par_en__enable 1
2060#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
2061#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1
2062#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0
2063#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1
2064#define R_SERIAL3_CTRL__data_out__BITNR 0
2065#define R_SERIAL3_CTRL__data_out__WIDTH 8
2066
2067#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b)
2068#define R_SERIAL3_BAUD__tr_baud__BITNR 4
2069#define R_SERIAL3_BAUD__tr_baud__WIDTH 4
2070#define R_SERIAL3_BAUD__tr_baud__c300Hz 0
2071#define R_SERIAL3_BAUD__tr_baud__c600Hz 1
2072#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2
2073#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3
2074#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4
2075#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5
2076#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6
2077#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7
2078#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8
2079#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9
2080#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10
2081#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11
2082#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12
2083#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13
2084#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14
2085#define R_SERIAL3_BAUD__tr_baud__reserved 15
2086#define R_SERIAL3_BAUD__rec_baud__BITNR 0
2087#define R_SERIAL3_BAUD__rec_baud__WIDTH 4
2088#define R_SERIAL3_BAUD__rec_baud__c300Hz 0
2089#define R_SERIAL3_BAUD__rec_baud__c600Hz 1
2090#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2
2091#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3
2092#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4
2093#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5
2094#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6
2095#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7
2096#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8
2097#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9
2098#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10
2099#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11
2100#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12
2101#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13
2102#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14
2103#define R_SERIAL3_BAUD__rec_baud__reserved 15
2104
2105#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a)
2106#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
2107#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1
2108#define R_SERIAL3_REC_CTRL__dma_err__stop 0
2109#define R_SERIAL3_REC_CTRL__dma_err__ignore 1
2110#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
2111#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1
2112#define R_SERIAL3_REC_CTRL__rec_enable__disable 0
2113#define R_SERIAL3_REC_CTRL__rec_enable__enable 1
2114#define R_SERIAL3_REC_CTRL__rts___BITNR 5
2115#define R_SERIAL3_REC_CTRL__rts___WIDTH 1
2116#define R_SERIAL3_REC_CTRL__rts___active 0
2117#define R_SERIAL3_REC_CTRL__rts___inactive 1
2118#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
2119#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1
2120#define R_SERIAL3_REC_CTRL__sampling__middle 0
2121#define R_SERIAL3_REC_CTRL__sampling__majority 1
2122#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
2123#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1
2124#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0
2125#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1
2126#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
2127#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1
2128#define R_SERIAL3_REC_CTRL__rec_par__even 0
2129#define R_SERIAL3_REC_CTRL__rec_par__odd 1
2130#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
2131#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1
2132#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0
2133#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1
2134#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
2135#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1
2136#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0
2137#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1
2138
2139#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079)
2140#define R_SERIAL3_TR_CTRL__txd__BITNR 7
2141#define R_SERIAL3_TR_CTRL__txd__WIDTH 1
2142#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
2143#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1
2144#define R_SERIAL3_TR_CTRL__tr_enable__disable 0
2145#define R_SERIAL3_TR_CTRL__tr_enable__enable 1
2146#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
2147#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1
2148#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0
2149#define R_SERIAL3_TR_CTRL__auto_cts__active 1
2150#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
2151#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1
2152#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0
2153#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1
2154#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
2155#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1
2156#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0
2157#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1
2158#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
2159#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1
2160#define R_SERIAL3_TR_CTRL__tr_par__even 0
2161#define R_SERIAL3_TR_CTRL__tr_par__odd 1
2162#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
2163#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1
2164#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0
2165#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1
2166#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
2167#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1
2168#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0
2169#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1
2170
2171#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078)
2172#define R_SERIAL3_TR_DATA__data_out__BITNR 0
2173#define R_SERIAL3_TR_DATA__data_out__WIDTH 8
2174
2175#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078)
2176#define R_SERIAL3_READ__xoff_detect__BITNR 15
2177#define R_SERIAL3_READ__xoff_detect__WIDTH 1
2178#define R_SERIAL3_READ__xoff_detect__no_xoff 0
2179#define R_SERIAL3_READ__xoff_detect__xoff 1
2180#define R_SERIAL3_READ__cts___BITNR 14
2181#define R_SERIAL3_READ__cts___WIDTH 1
2182#define R_SERIAL3_READ__cts___active 0
2183#define R_SERIAL3_READ__cts___inactive 1
2184#define R_SERIAL3_READ__tr_ready__BITNR 13
2185#define R_SERIAL3_READ__tr_ready__WIDTH 1
2186#define R_SERIAL3_READ__tr_ready__full 0
2187#define R_SERIAL3_READ__tr_ready__ready 1
2188#define R_SERIAL3_READ__rxd__BITNR 12
2189#define R_SERIAL3_READ__rxd__WIDTH 1
2190#define R_SERIAL3_READ__overrun__BITNR 11
2191#define R_SERIAL3_READ__overrun__WIDTH 1
2192#define R_SERIAL3_READ__overrun__no 0
2193#define R_SERIAL3_READ__overrun__yes 1
2194#define R_SERIAL3_READ__par_err__BITNR 10
2195#define R_SERIAL3_READ__par_err__WIDTH 1
2196#define R_SERIAL3_READ__par_err__no 0
2197#define R_SERIAL3_READ__par_err__yes 1
2198#define R_SERIAL3_READ__framing_err__BITNR 9
2199#define R_SERIAL3_READ__framing_err__WIDTH 1
2200#define R_SERIAL3_READ__framing_err__no 0
2201#define R_SERIAL3_READ__framing_err__yes 1
2202#define R_SERIAL3_READ__data_avail__BITNR 8
2203#define R_SERIAL3_READ__data_avail__WIDTH 1
2204#define R_SERIAL3_READ__data_avail__no 0
2205#define R_SERIAL3_READ__data_avail__yes 1
2206#define R_SERIAL3_READ__data_in__BITNR 0
2207#define R_SERIAL3_READ__data_in__WIDTH 8
2208
2209#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079)
2210#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
2211#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1
2212#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0
2213#define R_SERIAL3_STATUS__xoff_detect__xoff 1
2214#define R_SERIAL3_STATUS__cts___BITNR 6
2215#define R_SERIAL3_STATUS__cts___WIDTH 1
2216#define R_SERIAL3_STATUS__cts___active 0
2217#define R_SERIAL3_STATUS__cts___inactive 1
2218#define R_SERIAL3_STATUS__tr_ready__BITNR 5
2219#define R_SERIAL3_STATUS__tr_ready__WIDTH 1
2220#define R_SERIAL3_STATUS__tr_ready__full 0
2221#define R_SERIAL3_STATUS__tr_ready__ready 1
2222#define R_SERIAL3_STATUS__rxd__BITNR 4
2223#define R_SERIAL3_STATUS__rxd__WIDTH 1
2224#define R_SERIAL3_STATUS__overrun__BITNR 3
2225#define R_SERIAL3_STATUS__overrun__WIDTH 1
2226#define R_SERIAL3_STATUS__overrun__no 0
2227#define R_SERIAL3_STATUS__overrun__yes 1
2228#define R_SERIAL3_STATUS__par_err__BITNR 2
2229#define R_SERIAL3_STATUS__par_err__WIDTH 1
2230#define R_SERIAL3_STATUS__par_err__no 0
2231#define R_SERIAL3_STATUS__par_err__yes 1
2232#define R_SERIAL3_STATUS__framing_err__BITNR 1
2233#define R_SERIAL3_STATUS__framing_err__WIDTH 1
2234#define R_SERIAL3_STATUS__framing_err__no 0
2235#define R_SERIAL3_STATUS__framing_err__yes 1
2236#define R_SERIAL3_STATUS__data_avail__BITNR 0
2237#define R_SERIAL3_STATUS__data_avail__WIDTH 1
2238#define R_SERIAL3_STATUS__data_avail__no 0
2239#define R_SERIAL3_STATUS__data_avail__yes 1
2240
2241#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078)
2242#define R_SERIAL3_REC_DATA__data_in__BITNR 0
2243#define R_SERIAL3_REC_DATA__data_in__WIDTH 8
2244
2245#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c)
2246#define R_SERIAL3_XOFF__tx_stop__BITNR 9
2247#define R_SERIAL3_XOFF__tx_stop__WIDTH 1
2248#define R_SERIAL3_XOFF__tx_stop__enable 0
2249#define R_SERIAL3_XOFF__tx_stop__stop 1
2250#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
2251#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1
2252#define R_SERIAL3_XOFF__auto_xoff__disable 0
2253#define R_SERIAL3_XOFF__auto_xoff__enable 1
2254#define R_SERIAL3_XOFF__xoff_char__BITNR 0
2255#define R_SERIAL3_XOFF__xoff_char__WIDTH 8
2256
2257#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c)
2258#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
2259#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2
2260#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0
2261#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1
2262#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2
2263#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3
2264#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
2265#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2
2266#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0
2267#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1
2268#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2
2269#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3
2270#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
2271#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2
2272#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0
2273#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1
2274#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2
2275#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3
2276#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
2277#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2
2278#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0
2279#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1
2280#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2
2281#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3
2282#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
2283#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2
2284#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0
2285#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1
2286#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2
2287#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3
2288#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
2289#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2
2290#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0
2291#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1
2292#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2
2293#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3
2294#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
2295#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2
2296#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0
2297#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1
2298#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2
2299#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3
2300#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
2301#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2
2302#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0
2303#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1
2304#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2
2305#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3
2306
2307/*
2308!* Network interface registers
2309!*/
2310
2311#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080)
2312#define R_NETWORK_SA_0__ma0_low__BITNR 0
2313#define R_NETWORK_SA_0__ma0_low__WIDTH 32
2314
2315#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084)
2316#define R_NETWORK_SA_1__ma1_low__BITNR 16
2317#define R_NETWORK_SA_1__ma1_low__WIDTH 16
2318#define R_NETWORK_SA_1__ma0_high__BITNR 0
2319#define R_NETWORK_SA_1__ma0_high__WIDTH 16
2320
2321#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088)
2322#define R_NETWORK_SA_2__ma1_high__BITNR 0
2323#define R_NETWORK_SA_2__ma1_high__WIDTH 32
2324
2325#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c)
2326#define R_NETWORK_GA_0__ga_low__BITNR 0
2327#define R_NETWORK_GA_0__ga_low__WIDTH 32
2328
2329#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090)
2330#define R_NETWORK_GA_1__ga_high__BITNR 0
2331#define R_NETWORK_GA_1__ga_high__WIDTH 32
2332
2333#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
2334#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
2335#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
2336#define R_NETWORK_REC_CONFIG__max_size__size1518 0
2337#define R_NETWORK_REC_CONFIG__max_size__size1522 1
2338#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
2339#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
2340#define R_NETWORK_REC_CONFIG__duplex__full 1
2341#define R_NETWORK_REC_CONFIG__duplex__half 0
2342#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
2343#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1
2344#define R_NETWORK_REC_CONFIG__bad_crc__receive 1
2345#define R_NETWORK_REC_CONFIG__bad_crc__discard 0
2346#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
2347#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1
2348#define R_NETWORK_REC_CONFIG__oversize__receive 1
2349#define R_NETWORK_REC_CONFIG__oversize__discard 0
2350#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
2351#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1
2352#define R_NETWORK_REC_CONFIG__undersize__receive 1
2353#define R_NETWORK_REC_CONFIG__undersize__discard 0
2354#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
2355#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1
2356#define R_NETWORK_REC_CONFIG__all_roots__receive 1
2357#define R_NETWORK_REC_CONFIG__all_roots__discard 0
2358#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
2359#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1
2360#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1
2361#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0
2362#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
2363#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1
2364#define R_NETWORK_REC_CONFIG__broadcast__receive 1
2365#define R_NETWORK_REC_CONFIG__broadcast__discard 0
2366#define R_NETWORK_REC_CONFIG__individual__BITNR 2
2367#define R_NETWORK_REC_CONFIG__individual__WIDTH 1
2368#define R_NETWORK_REC_CONFIG__individual__receive 1
2369#define R_NETWORK_REC_CONFIG__individual__discard 0
2370#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
2371#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1
2372#define R_NETWORK_REC_CONFIG__ma1__enable 1
2373#define R_NETWORK_REC_CONFIG__ma1__disable 0
2374#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
2375#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1
2376#define R_NETWORK_REC_CONFIG__ma0__enable 1
2377#define R_NETWORK_REC_CONFIG__ma0__disable 0
2378
2379#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098)
2380#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
2381#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1
2382#define R_NETWORK_GEN_CONFIG__loopback__on 1
2383#define R_NETWORK_GEN_CONFIG__loopback__off 0
2384#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
2385#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1
2386#define R_NETWORK_GEN_CONFIG__frame__tokenr 1
2387#define R_NETWORK_GEN_CONFIG__frame__ether 0
2388#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
2389#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1
2390#define R_NETWORK_GEN_CONFIG__vg__on 1
2391#define R_NETWORK_GEN_CONFIG__vg__off 0
2392#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
2393#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2
2394#define R_NETWORK_GEN_CONFIG__phy__sni 0
2395#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1
2396#define R_NETWORK_GEN_CONFIG__phy__mii_err 2
2397#define R_NETWORK_GEN_CONFIG__phy__mii_req 3
2398#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
2399#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1
2400#define R_NETWORK_GEN_CONFIG__enable__on 1
2401#define R_NETWORK_GEN_CONFIG__enable__off 0
2402
2403#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c)
2404#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
2405#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1
2406#define R_NETWORK_TR_CTRL__clr_error__clr 1
2407#define R_NETWORK_TR_CTRL__clr_error__nop 0
2408#define R_NETWORK_TR_CTRL__delay__BITNR 5
2409#define R_NETWORK_TR_CTRL__delay__WIDTH 1
2410#define R_NETWORK_TR_CTRL__delay__d2us 1
2411#define R_NETWORK_TR_CTRL__delay__none 0
2412#define R_NETWORK_TR_CTRL__cancel__BITNR 4
2413#define R_NETWORK_TR_CTRL__cancel__WIDTH 1
2414#define R_NETWORK_TR_CTRL__cancel__do 1
2415#define R_NETWORK_TR_CTRL__cancel__dont 0
2416#define R_NETWORK_TR_CTRL__cd__BITNR 3
2417#define R_NETWORK_TR_CTRL__cd__WIDTH 1
2418#define R_NETWORK_TR_CTRL__cd__enable 0
2419#define R_NETWORK_TR_CTRL__cd__disable 1
2420#define R_NETWORK_TR_CTRL__cd__ack_col 0
2421#define R_NETWORK_TR_CTRL__cd__ack_crs 1
2422#define R_NETWORK_TR_CTRL__retry__BITNR 2
2423#define R_NETWORK_TR_CTRL__retry__WIDTH 1
2424#define R_NETWORK_TR_CTRL__retry__enable 0
2425#define R_NETWORK_TR_CTRL__retry__disable 1
2426#define R_NETWORK_TR_CTRL__pad__BITNR 1
2427#define R_NETWORK_TR_CTRL__pad__WIDTH 1
2428#define R_NETWORK_TR_CTRL__pad__enable 1
2429#define R_NETWORK_TR_CTRL__pad__disable 0
2430#define R_NETWORK_TR_CTRL__crc__BITNR 0
2431#define R_NETWORK_TR_CTRL__crc__WIDTH 1
2432#define R_NETWORK_TR_CTRL__crc__enable 0
2433#define R_NETWORK_TR_CTRL__crc__disable 1
2434
2435#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0)
2436#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
2437#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4
2438#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
2439#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1
2440#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
2441#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1
2442#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
2443#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1
2444#define R_NETWORK_MGM_CTRL__mdoe__enable 1
2445#define R_NETWORK_MGM_CTRL__mdoe__disable 0
2446#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
2447#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1
2448
2449#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0)
2450#define R_NETWORK_STAT__rxd_pins__BITNR 4
2451#define R_NETWORK_STAT__rxd_pins__WIDTH 4
2452#define R_NETWORK_STAT__rxer__BITNR 3
2453#define R_NETWORK_STAT__rxer__WIDTH 1
2454#define R_NETWORK_STAT__underrun__BITNR 2
2455#define R_NETWORK_STAT__underrun__WIDTH 1
2456#define R_NETWORK_STAT__underrun__yes 1
2457#define R_NETWORK_STAT__underrun__no 0
2458#define R_NETWORK_STAT__exc_col__BITNR 1
2459#define R_NETWORK_STAT__exc_col__WIDTH 1
2460#define R_NETWORK_STAT__exc_col__yes 1
2461#define R_NETWORK_STAT__exc_col__no 0
2462#define R_NETWORK_STAT__mdio__BITNR 0
2463#define R_NETWORK_STAT__mdio__WIDTH 1
2464
2465#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4)
2466#define R_REC_COUNTERS__congestion__BITNR 24
2467#define R_REC_COUNTERS__congestion__WIDTH 8
2468#define R_REC_COUNTERS__oversize__BITNR 16
2469#define R_REC_COUNTERS__oversize__WIDTH 8
2470#define R_REC_COUNTERS__alignment_error__BITNR 8
2471#define R_REC_COUNTERS__alignment_error__WIDTH 8
2472#define R_REC_COUNTERS__crc_error__BITNR 0
2473#define R_REC_COUNTERS__crc_error__WIDTH 8
2474
2475#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8)
2476#define R_TR_COUNTERS__deferred__BITNR 24
2477#define R_TR_COUNTERS__deferred__WIDTH 8
2478#define R_TR_COUNTERS__late_col__BITNR 16
2479#define R_TR_COUNTERS__late_col__WIDTH 8
2480#define R_TR_COUNTERS__multiple_col__BITNR 8
2481#define R_TR_COUNTERS__multiple_col__WIDTH 8
2482#define R_TR_COUNTERS__single_col__BITNR 0
2483#define R_TR_COUNTERS__single_col__WIDTH 8
2484
2485#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac)
2486#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
2487#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8
2488#define R_PHY_COUNTERS__carrier_loss__BITNR 0
2489#define R_PHY_COUNTERS__carrier_loss__WIDTH 8
2490
2491/*
2492!* Parallel printer port registers
2493!*/
2494
2495#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
2496#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
2497#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1
2498#define R_PAR0_CTRL_DATA__peri_int__ack 1
2499#define R_PAR0_CTRL_DATA__peri_int__nop 0
2500#define R_PAR0_CTRL_DATA__oe__BITNR 20
2501#define R_PAR0_CTRL_DATA__oe__WIDTH 1
2502#define R_PAR0_CTRL_DATA__oe__enable 1
2503#define R_PAR0_CTRL_DATA__oe__disable 0
2504#define R_PAR0_CTRL_DATA__seli__BITNR 19
2505#define R_PAR0_CTRL_DATA__seli__WIDTH 1
2506#define R_PAR0_CTRL_DATA__seli__active 1
2507#define R_PAR0_CTRL_DATA__seli__inactive 0
2508#define R_PAR0_CTRL_DATA__autofd__BITNR 18
2509#define R_PAR0_CTRL_DATA__autofd__WIDTH 1
2510#define R_PAR0_CTRL_DATA__autofd__active 1
2511#define R_PAR0_CTRL_DATA__autofd__inactive 0
2512#define R_PAR0_CTRL_DATA__strb__BITNR 17
2513#define R_PAR0_CTRL_DATA__strb__WIDTH 1
2514#define R_PAR0_CTRL_DATA__strb__active 1
2515#define R_PAR0_CTRL_DATA__strb__inactive 0
2516#define R_PAR0_CTRL_DATA__init__BITNR 16
2517#define R_PAR0_CTRL_DATA__init__WIDTH 1
2518#define R_PAR0_CTRL_DATA__init__active 1
2519#define R_PAR0_CTRL_DATA__init__inactive 0
2520#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
2521#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1
2522#define R_PAR0_CTRL_DATA__ecp_cmd__command 1
2523#define R_PAR0_CTRL_DATA__ecp_cmd__data 0
2524#define R_PAR0_CTRL_DATA__data__BITNR 0
2525#define R_PAR0_CTRL_DATA__data__WIDTH 8
2526
2527#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042)
2528#define R_PAR0_CTRL__ctrl__BITNR 0
2529#define R_PAR0_CTRL__ctrl__WIDTH 5
2530
2531#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
2532#define R_PAR0_STATUS_DATA__mode__BITNR 29
2533#define R_PAR0_STATUS_DATA__mode__WIDTH 3
2534#define R_PAR0_STATUS_DATA__mode__manual 0
2535#define R_PAR0_STATUS_DATA__mode__centronics 1
2536#define R_PAR0_STATUS_DATA__mode__fastbyte 2
2537#define R_PAR0_STATUS_DATA__mode__nibble 3
2538#define R_PAR0_STATUS_DATA__mode__byte 4
2539#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
2540#define R_PAR0_STATUS_DATA__mode__ecp_rev 6
2541#define R_PAR0_STATUS_DATA__mode__off 7
2542#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
2543#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
2544#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
2545#define R_PAR0_STATUS_DATA__mode__epp_rd 0
2546#define R_PAR0_STATUS_DATA__perr__BITNR 28
2547#define R_PAR0_STATUS_DATA__perr__WIDTH 1
2548#define R_PAR0_STATUS_DATA__perr__active 1
2549#define R_PAR0_STATUS_DATA__perr__inactive 0
2550#define R_PAR0_STATUS_DATA__ack__BITNR 27
2551#define R_PAR0_STATUS_DATA__ack__WIDTH 1
2552#define R_PAR0_STATUS_DATA__ack__active 0
2553#define R_PAR0_STATUS_DATA__ack__inactive 1
2554#define R_PAR0_STATUS_DATA__busy__BITNR 26
2555#define R_PAR0_STATUS_DATA__busy__WIDTH 1
2556#define R_PAR0_STATUS_DATA__busy__active 1
2557#define R_PAR0_STATUS_DATA__busy__inactive 0
2558#define R_PAR0_STATUS_DATA__fault__BITNR 25
2559#define R_PAR0_STATUS_DATA__fault__WIDTH 1
2560#define R_PAR0_STATUS_DATA__fault__active 0
2561#define R_PAR0_STATUS_DATA__fault__inactive 1
2562#define R_PAR0_STATUS_DATA__sel__BITNR 24
2563#define R_PAR0_STATUS_DATA__sel__WIDTH 1
2564#define R_PAR0_STATUS_DATA__sel__active 1
2565#define R_PAR0_STATUS_DATA__sel__inactive 0
2566#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
2567#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
2568#define R_PAR0_STATUS_DATA__ext_mode__enable 1
2569#define R_PAR0_STATUS_DATA__ext_mode__disable 0
2570#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
2571#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
2572#define R_PAR0_STATUS_DATA__ecp_16__active 1
2573#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
2574#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
2575#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
2576#define R_PAR0_STATUS_DATA__tr_rdy__ready 1
2577#define R_PAR0_STATUS_DATA__tr_rdy__busy 0
2578#define R_PAR0_STATUS_DATA__dav__BITNR 16
2579#define R_PAR0_STATUS_DATA__dav__WIDTH 1
2580#define R_PAR0_STATUS_DATA__dav__data 1
2581#define R_PAR0_STATUS_DATA__dav__nodata 0
2582#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
2583#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1
2584#define R_PAR0_STATUS_DATA__ecp_cmd__command 1
2585#define R_PAR0_STATUS_DATA__ecp_cmd__data 0
2586#define R_PAR0_STATUS_DATA__data__BITNR 0
2587#define R_PAR0_STATUS_DATA__data__WIDTH 8
2588
2589#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
2590#define R_PAR0_STATUS__mode__BITNR 13
2591#define R_PAR0_STATUS__mode__WIDTH 3
2592#define R_PAR0_STATUS__mode__manual 0
2593#define R_PAR0_STATUS__mode__centronics 1
2594#define R_PAR0_STATUS__mode__fastbyte 2
2595#define R_PAR0_STATUS__mode__nibble 3
2596#define R_PAR0_STATUS__mode__byte 4
2597#define R_PAR0_STATUS__mode__ecp_fwd 5
2598#define R_PAR0_STATUS__mode__ecp_rev 6
2599#define R_PAR0_STATUS__mode__off 7
2600#define R_PAR0_STATUS__mode__epp_wr1 5
2601#define R_PAR0_STATUS__mode__epp_wr2 6
2602#define R_PAR0_STATUS__mode__epp_wr3 7
2603#define R_PAR0_STATUS__mode__epp_rd 0
2604#define R_PAR0_STATUS__perr__BITNR 12
2605#define R_PAR0_STATUS__perr__WIDTH 1
2606#define R_PAR0_STATUS__perr__active 1
2607#define R_PAR0_STATUS__perr__inactive 0
2608#define R_PAR0_STATUS__ack__BITNR 11
2609#define R_PAR0_STATUS__ack__WIDTH 1
2610#define R_PAR0_STATUS__ack__active 0
2611#define R_PAR0_STATUS__ack__inactive 1
2612#define R_PAR0_STATUS__busy__BITNR 10
2613#define R_PAR0_STATUS__busy__WIDTH 1
2614#define R_PAR0_STATUS__busy__active 1
2615#define R_PAR0_STATUS__busy__inactive 0
2616#define R_PAR0_STATUS__fault__BITNR 9
2617#define R_PAR0_STATUS__fault__WIDTH 1
2618#define R_PAR0_STATUS__fault__active 0
2619#define R_PAR0_STATUS__fault__inactive 1
2620#define R_PAR0_STATUS__sel__BITNR 8
2621#define R_PAR0_STATUS__sel__WIDTH 1
2622#define R_PAR0_STATUS__sel__active 1
2623#define R_PAR0_STATUS__sel__inactive 0
2624#define R_PAR0_STATUS__ext_mode__BITNR 7
2625#define R_PAR0_STATUS__ext_mode__WIDTH 1
2626#define R_PAR0_STATUS__ext_mode__enable 1
2627#define R_PAR0_STATUS__ext_mode__disable 0
2628#define R_PAR0_STATUS__ecp_16__BITNR 6
2629#define R_PAR0_STATUS__ecp_16__WIDTH 1
2630#define R_PAR0_STATUS__ecp_16__active 1
2631#define R_PAR0_STATUS__ecp_16__inactive 0
2632#define R_PAR0_STATUS__tr_rdy__BITNR 1
2633#define R_PAR0_STATUS__tr_rdy__WIDTH 1
2634#define R_PAR0_STATUS__tr_rdy__ready 1
2635#define R_PAR0_STATUS__tr_rdy__busy 0
2636#define R_PAR0_STATUS__dav__BITNR 0
2637#define R_PAR0_STATUS__dav__WIDTH 1
2638#define R_PAR0_STATUS__dav__data 1
2639#define R_PAR0_STATUS__dav__nodata 0
2640
2641#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
2642#define R_PAR_ECP16_DATA__data__BITNR 0
2643#define R_PAR_ECP16_DATA__data__WIDTH 16
2644
2645#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
2646#define R_PAR0_CONFIG__ioe__BITNR 25
2647#define R_PAR0_CONFIG__ioe__WIDTH 1
2648#define R_PAR0_CONFIG__ioe__inv 1
2649#define R_PAR0_CONFIG__ioe__noninv 0
2650#define R_PAR0_CONFIG__iseli__BITNR 24
2651#define R_PAR0_CONFIG__iseli__WIDTH 1
2652#define R_PAR0_CONFIG__iseli__inv 1
2653#define R_PAR0_CONFIG__iseli__noninv 0
2654#define R_PAR0_CONFIG__iautofd__BITNR 23
2655#define R_PAR0_CONFIG__iautofd__WIDTH 1
2656#define R_PAR0_CONFIG__iautofd__inv 1
2657#define R_PAR0_CONFIG__iautofd__noninv 0
2658#define R_PAR0_CONFIG__istrb__BITNR 22
2659#define R_PAR0_CONFIG__istrb__WIDTH 1
2660#define R_PAR0_CONFIG__istrb__inv 1
2661#define R_PAR0_CONFIG__istrb__noninv 0
2662#define R_PAR0_CONFIG__iinit__BITNR 21
2663#define R_PAR0_CONFIG__iinit__WIDTH 1
2664#define R_PAR0_CONFIG__iinit__inv 1
2665#define R_PAR0_CONFIG__iinit__noninv 0
2666#define R_PAR0_CONFIG__iperr__BITNR 20
2667#define R_PAR0_CONFIG__iperr__WIDTH 1
2668#define R_PAR0_CONFIG__iperr__inv 1
2669#define R_PAR0_CONFIG__iperr__noninv 0
2670#define R_PAR0_CONFIG__iack__BITNR 19
2671#define R_PAR0_CONFIG__iack__WIDTH 1
2672#define R_PAR0_CONFIG__iack__inv 1
2673#define R_PAR0_CONFIG__iack__noninv 0
2674#define R_PAR0_CONFIG__ibusy__BITNR 18
2675#define R_PAR0_CONFIG__ibusy__WIDTH 1
2676#define R_PAR0_CONFIG__ibusy__inv 1
2677#define R_PAR0_CONFIG__ibusy__noninv 0
2678#define R_PAR0_CONFIG__ifault__BITNR 17
2679#define R_PAR0_CONFIG__ifault__WIDTH 1
2680#define R_PAR0_CONFIG__ifault__inv 1
2681#define R_PAR0_CONFIG__ifault__noninv 0
2682#define R_PAR0_CONFIG__isel__BITNR 16
2683#define R_PAR0_CONFIG__isel__WIDTH 1
2684#define R_PAR0_CONFIG__isel__inv 1
2685#define R_PAR0_CONFIG__isel__noninv 0
2686#define R_PAR0_CONFIG__ext_mode__BITNR 11
2687#define R_PAR0_CONFIG__ext_mode__WIDTH 1
2688#define R_PAR0_CONFIG__ext_mode__enable 1
2689#define R_PAR0_CONFIG__ext_mode__disable 0
2690#define R_PAR0_CONFIG__wide__BITNR 10
2691#define R_PAR0_CONFIG__wide__WIDTH 1
2692#define R_PAR0_CONFIG__wide__enable 1
2693#define R_PAR0_CONFIG__wide__disable 0
2694#define R_PAR0_CONFIG__dma__BITNR 9
2695#define R_PAR0_CONFIG__dma__WIDTH 1
2696#define R_PAR0_CONFIG__dma__enable 1
2697#define R_PAR0_CONFIG__dma__disable 0
2698#define R_PAR0_CONFIG__rle_in__BITNR 8
2699#define R_PAR0_CONFIG__rle_in__WIDTH 1
2700#define R_PAR0_CONFIG__rle_in__enable 1
2701#define R_PAR0_CONFIG__rle_in__disable 0
2702#define R_PAR0_CONFIG__rle_out__BITNR 7
2703#define R_PAR0_CONFIG__rle_out__WIDTH 1
2704#define R_PAR0_CONFIG__rle_out__enable 1
2705#define R_PAR0_CONFIG__rle_out__disable 0
2706#define R_PAR0_CONFIG__enable__BITNR 6
2707#define R_PAR0_CONFIG__enable__WIDTH 1
2708#define R_PAR0_CONFIG__enable__on 1
2709#define R_PAR0_CONFIG__enable__reset 0
2710#define R_PAR0_CONFIG__force__BITNR 5
2711#define R_PAR0_CONFIG__force__WIDTH 1
2712#define R_PAR0_CONFIG__force__on 1
2713#define R_PAR0_CONFIG__force__off 0
2714#define R_PAR0_CONFIG__ign_ack__BITNR 4
2715#define R_PAR0_CONFIG__ign_ack__WIDTH 1
2716#define R_PAR0_CONFIG__ign_ack__ignore 1
2717#define R_PAR0_CONFIG__ign_ack__wait 0
2718#define R_PAR0_CONFIG__oe_ack__BITNR 3
2719#define R_PAR0_CONFIG__oe_ack__WIDTH 1
2720#define R_PAR0_CONFIG__oe_ack__wait_oe 1
2721#define R_PAR0_CONFIG__oe_ack__dont_wait 0
2722#define R_PAR0_CONFIG__oe_ack__epp_addr 1
2723#define R_PAR0_CONFIG__oe_ack__epp_data 0
2724#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
2725#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1
2726#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1
2727#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0
2728#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1
2729#define R_PAR0_CONFIG__epp_addr_data__epp_data 0
2730#define R_PAR0_CONFIG__mode__BITNR 0
2731#define R_PAR0_CONFIG__mode__WIDTH 3
2732#define R_PAR0_CONFIG__mode__manual 0
2733#define R_PAR0_CONFIG__mode__centronics 1
2734#define R_PAR0_CONFIG__mode__fastbyte 2
2735#define R_PAR0_CONFIG__mode__nibble 3
2736#define R_PAR0_CONFIG__mode__byte 4
2737#define R_PAR0_CONFIG__mode__ecp_fwd 5
2738#define R_PAR0_CONFIG__mode__ecp_rev 6
2739#define R_PAR0_CONFIG__mode__off 7
2740#define R_PAR0_CONFIG__mode__epp_wr1 5
2741#define R_PAR0_CONFIG__mode__epp_wr2 6
2742#define R_PAR0_CONFIG__mode__epp_wr3 7
2743#define R_PAR0_CONFIG__mode__epp_rd 0
2744
2745#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
2746#define R_PAR0_DELAY__fine_hold__BITNR 21
2747#define R_PAR0_DELAY__fine_hold__WIDTH 3
2748#define R_PAR0_DELAY__hold__BITNR 16
2749#define R_PAR0_DELAY__hold__WIDTH 5
2750#define R_PAR0_DELAY__fine_strb__BITNR 13
2751#define R_PAR0_DELAY__fine_strb__WIDTH 3
2752#define R_PAR0_DELAY__strobe__BITNR 8
2753#define R_PAR0_DELAY__strobe__WIDTH 5
2754#define R_PAR0_DELAY__fine_setup__BITNR 5
2755#define R_PAR0_DELAY__fine_setup__WIDTH 3
2756#define R_PAR0_DELAY__setup__BITNR 0
2757#define R_PAR0_DELAY__setup__WIDTH 5
2758
2759#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050)
2760#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
2761#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1
2762#define R_PAR1_CTRL_DATA__peri_int__ack 1
2763#define R_PAR1_CTRL_DATA__peri_int__nop 0
2764#define R_PAR1_CTRL_DATA__oe__BITNR 20
2765#define R_PAR1_CTRL_DATA__oe__WIDTH 1
2766#define R_PAR1_CTRL_DATA__oe__enable 1
2767#define R_PAR1_CTRL_DATA__oe__disable 0
2768#define R_PAR1_CTRL_DATA__seli__BITNR 19
2769#define R_PAR1_CTRL_DATA__seli__WIDTH 1
2770#define R_PAR1_CTRL_DATA__seli__active 1
2771#define R_PAR1_CTRL_DATA__seli__inactive 0
2772#define R_PAR1_CTRL_DATA__autofd__BITNR 18
2773#define R_PAR1_CTRL_DATA__autofd__WIDTH 1
2774#define R_PAR1_CTRL_DATA__autofd__active 1
2775#define R_PAR1_CTRL_DATA__autofd__inactive 0
2776#define R_PAR1_CTRL_DATA__strb__BITNR 17
2777#define R_PAR1_CTRL_DATA__strb__WIDTH 1
2778#define R_PAR1_CTRL_DATA__strb__active 1
2779#define R_PAR1_CTRL_DATA__strb__inactive 0
2780#define R_PAR1_CTRL_DATA__init__BITNR 16
2781#define R_PAR1_CTRL_DATA__init__WIDTH 1
2782#define R_PAR1_CTRL_DATA__init__active 1
2783#define R_PAR1_CTRL_DATA__init__inactive 0
2784#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
2785#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1
2786#define R_PAR1_CTRL_DATA__ecp_cmd__command 1
2787#define R_PAR1_CTRL_DATA__ecp_cmd__data 0
2788#define R_PAR1_CTRL_DATA__data__BITNR 0
2789#define R_PAR1_CTRL_DATA__data__WIDTH 8
2790
2791#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052)
2792#define R_PAR1_CTRL__ctrl__BITNR 0
2793#define R_PAR1_CTRL__ctrl__WIDTH 5
2794
2795#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050)
2796#define R_PAR1_STATUS_DATA__mode__BITNR 29
2797#define R_PAR1_STATUS_DATA__mode__WIDTH 3
2798#define R_PAR1_STATUS_DATA__mode__manual 0
2799#define R_PAR1_STATUS_DATA__mode__centronics 1
2800#define R_PAR1_STATUS_DATA__mode__fastbyte 2
2801#define R_PAR1_STATUS_DATA__mode__nibble 3
2802#define R_PAR1_STATUS_DATA__mode__byte 4
2803#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
2804#define R_PAR1_STATUS_DATA__mode__ecp_rev 6
2805#define R_PAR1_STATUS_DATA__mode__off 7
2806#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
2807#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
2808#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
2809#define R_PAR1_STATUS_DATA__mode__epp_rd 0
2810#define R_PAR1_STATUS_DATA__perr__BITNR 28
2811#define R_PAR1_STATUS_DATA__perr__WIDTH 1
2812#define R_PAR1_STATUS_DATA__perr__active 1
2813#define R_PAR1_STATUS_DATA__perr__inactive 0
2814#define R_PAR1_STATUS_DATA__ack__BITNR 27
2815#define R_PAR1_STATUS_DATA__ack__WIDTH 1
2816#define R_PAR1_STATUS_DATA__ack__active 0
2817#define R_PAR1_STATUS_DATA__ack__inactive 1
2818#define R_PAR1_STATUS_DATA__busy__BITNR 26
2819#define R_PAR1_STATUS_DATA__busy__WIDTH 1
2820#define R_PAR1_STATUS_DATA__busy__active 1
2821#define R_PAR1_STATUS_DATA__busy__inactive 0
2822#define R_PAR1_STATUS_DATA__fault__BITNR 25
2823#define R_PAR1_STATUS_DATA__fault__WIDTH 1
2824#define R_PAR1_STATUS_DATA__fault__active 0
2825#define R_PAR1_STATUS_DATA__fault__inactive 1
2826#define R_PAR1_STATUS_DATA__sel__BITNR 24
2827#define R_PAR1_STATUS_DATA__sel__WIDTH 1
2828#define R_PAR1_STATUS_DATA__sel__active 1
2829#define R_PAR1_STATUS_DATA__sel__inactive 0
2830#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
2831#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
2832#define R_PAR1_STATUS_DATA__ext_mode__enable 1
2833#define R_PAR1_STATUS_DATA__ext_mode__disable 0
2834#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
2835#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
2836#define R_PAR1_STATUS_DATA__tr_rdy__ready 1
2837#define R_PAR1_STATUS_DATA__tr_rdy__busy 0
2838#define R_PAR1_STATUS_DATA__dav__BITNR 16
2839#define R_PAR1_STATUS_DATA__dav__WIDTH 1
2840#define R_PAR1_STATUS_DATA__dav__data 1
2841#define R_PAR1_STATUS_DATA__dav__nodata 0
2842#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
2843#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1
2844#define R_PAR1_STATUS_DATA__ecp_cmd__command 1
2845#define R_PAR1_STATUS_DATA__ecp_cmd__data 0
2846#define R_PAR1_STATUS_DATA__data__BITNR 0
2847#define R_PAR1_STATUS_DATA__data__WIDTH 8
2848
2849#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
2850#define R_PAR1_STATUS__mode__BITNR 13
2851#define R_PAR1_STATUS__mode__WIDTH 3
2852#define R_PAR1_STATUS__mode__manual 0
2853#define R_PAR1_STATUS__mode__centronics 1
2854#define R_PAR1_STATUS__mode__fastbyte 2
2855#define R_PAR1_STATUS__mode__nibble 3
2856#define R_PAR1_STATUS__mode__byte 4
2857#define R_PAR1_STATUS__mode__ecp_fwd 5
2858#define R_PAR1_STATUS__mode__ecp_rev 6
2859#define R_PAR1_STATUS__mode__off 7
2860#define R_PAR1_STATUS__mode__epp_wr1 5
2861#define R_PAR1_STATUS__mode__epp_wr2 6
2862#define R_PAR1_STATUS__mode__epp_wr3 7
2863#define R_PAR1_STATUS__mode__epp_rd 0
2864#define R_PAR1_STATUS__perr__BITNR 12
2865#define R_PAR1_STATUS__perr__WIDTH 1
2866#define R_PAR1_STATUS__perr__active 1
2867#define R_PAR1_STATUS__perr__inactive 0
2868#define R_PAR1_STATUS__ack__BITNR 11
2869#define R_PAR1_STATUS__ack__WIDTH 1
2870#define R_PAR1_STATUS__ack__active 0
2871#define R_PAR1_STATUS__ack__inactive 1
2872#define R_PAR1_STATUS__busy__BITNR 10
2873#define R_PAR1_STATUS__busy__WIDTH 1
2874#define R_PAR1_STATUS__busy__active 1
2875#define R_PAR1_STATUS__busy__inactive 0
2876#define R_PAR1_STATUS__fault__BITNR 9
2877#define R_PAR1_STATUS__fault__WIDTH 1
2878#define R_PAR1_STATUS__fault__active 0
2879#define R_PAR1_STATUS__fault__inactive 1
2880#define R_PAR1_STATUS__sel__BITNR 8
2881#define R_PAR1_STATUS__sel__WIDTH 1
2882#define R_PAR1_STATUS__sel__active 1
2883#define R_PAR1_STATUS__sel__inactive 0
2884#define R_PAR1_STATUS__ext_mode__BITNR 7
2885#define R_PAR1_STATUS__ext_mode__WIDTH 1
2886#define R_PAR1_STATUS__ext_mode__enable 1
2887#define R_PAR1_STATUS__ext_mode__disable 0
2888#define R_PAR1_STATUS__tr_rdy__BITNR 1
2889#define R_PAR1_STATUS__tr_rdy__WIDTH 1
2890#define R_PAR1_STATUS__tr_rdy__ready 1
2891#define R_PAR1_STATUS__tr_rdy__busy 0
2892#define R_PAR1_STATUS__dav__BITNR 0
2893#define R_PAR1_STATUS__dav__WIDTH 1
2894#define R_PAR1_STATUS__dav__data 1
2895#define R_PAR1_STATUS__dav__nodata 0
2896
2897#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
2898#define R_PAR1_CONFIG__ioe__BITNR 25
2899#define R_PAR1_CONFIG__ioe__WIDTH 1
2900#define R_PAR1_CONFIG__ioe__inv 1
2901#define R_PAR1_CONFIG__ioe__noninv 0
2902#define R_PAR1_CONFIG__iseli__BITNR 24
2903#define R_PAR1_CONFIG__iseli__WIDTH 1
2904#define R_PAR1_CONFIG__iseli__inv 1
2905#define R_PAR1_CONFIG__iseli__noninv 0
2906#define R_PAR1_CONFIG__iautofd__BITNR 23
2907#define R_PAR1_CONFIG__iautofd__WIDTH 1
2908#define R_PAR1_CONFIG__iautofd__inv 1
2909#define R_PAR1_CONFIG__iautofd__noninv 0
2910#define R_PAR1_CONFIG__istrb__BITNR 22
2911#define R_PAR1_CONFIG__istrb__WIDTH 1
2912#define R_PAR1_CONFIG__istrb__inv 1
2913#define R_PAR1_CONFIG__istrb__noninv 0
2914#define R_PAR1_CONFIG__iinit__BITNR 21
2915#define R_PAR1_CONFIG__iinit__WIDTH 1
2916#define R_PAR1_CONFIG__iinit__inv 1
2917#define R_PAR1_CONFIG__iinit__noninv 0
2918#define R_PAR1_CONFIG__iperr__BITNR 20
2919#define R_PAR1_CONFIG__iperr__WIDTH 1
2920#define R_PAR1_CONFIG__iperr__inv 1
2921#define R_PAR1_CONFIG__iperr__noninv 0
2922#define R_PAR1_CONFIG__iack__BITNR 19
2923#define R_PAR1_CONFIG__iack__WIDTH 1
2924#define R_PAR1_CONFIG__iack__inv 1
2925#define R_PAR1_CONFIG__iack__noninv 0
2926#define R_PAR1_CONFIG__ibusy__BITNR 18
2927#define R_PAR1_CONFIG__ibusy__WIDTH 1
2928#define R_PAR1_CONFIG__ibusy__inv 1
2929#define R_PAR1_CONFIG__ibusy__noninv 0
2930#define R_PAR1_CONFIG__ifault__BITNR 17
2931#define R_PAR1_CONFIG__ifault__WIDTH 1
2932#define R_PAR1_CONFIG__ifault__inv 1
2933#define R_PAR1_CONFIG__ifault__noninv 0
2934#define R_PAR1_CONFIG__isel__BITNR 16
2935#define R_PAR1_CONFIG__isel__WIDTH 1
2936#define R_PAR1_CONFIG__isel__inv 1
2937#define R_PAR1_CONFIG__isel__noninv 0
2938#define R_PAR1_CONFIG__ext_mode__BITNR 11
2939#define R_PAR1_CONFIG__ext_mode__WIDTH 1
2940#define R_PAR1_CONFIG__ext_mode__enable 1
2941#define R_PAR1_CONFIG__ext_mode__disable 0
2942#define R_PAR1_CONFIG__dma__BITNR 9
2943#define R_PAR1_CONFIG__dma__WIDTH 1
2944#define R_PAR1_CONFIG__dma__enable 1
2945#define R_PAR1_CONFIG__dma__disable 0
2946#define R_PAR1_CONFIG__rle_in__BITNR 8
2947#define R_PAR1_CONFIG__rle_in__WIDTH 1
2948#define R_PAR1_CONFIG__rle_in__enable 1
2949#define R_PAR1_CONFIG__rle_in__disable 0
2950#define R_PAR1_CONFIG__rle_out__BITNR 7
2951#define R_PAR1_CONFIG__rle_out__WIDTH 1
2952#define R_PAR1_CONFIG__rle_out__enable 1
2953#define R_PAR1_CONFIG__rle_out__disable 0
2954#define R_PAR1_CONFIG__enable__BITNR 6
2955#define R_PAR1_CONFIG__enable__WIDTH 1
2956#define R_PAR1_CONFIG__enable__on 1
2957#define R_PAR1_CONFIG__enable__reset 0
2958#define R_PAR1_CONFIG__force__BITNR 5
2959#define R_PAR1_CONFIG__force__WIDTH 1
2960#define R_PAR1_CONFIG__force__on 1
2961#define R_PAR1_CONFIG__force__off 0
2962#define R_PAR1_CONFIG__ign_ack__BITNR 4
2963#define R_PAR1_CONFIG__ign_ack__WIDTH 1
2964#define R_PAR1_CONFIG__ign_ack__ignore 1
2965#define R_PAR1_CONFIG__ign_ack__wait 0
2966#define R_PAR1_CONFIG__oe_ack__BITNR 3
2967#define R_PAR1_CONFIG__oe_ack__WIDTH 1
2968#define R_PAR1_CONFIG__oe_ack__wait_oe 1
2969#define R_PAR1_CONFIG__oe_ack__dont_wait 0
2970#define R_PAR1_CONFIG__oe_ack__epp_addr 1
2971#define R_PAR1_CONFIG__oe_ack__epp_data 0
2972#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
2973#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1
2974#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1
2975#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0
2976#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1
2977#define R_PAR1_CONFIG__epp_addr_data__epp_data 0
2978#define R_PAR1_CONFIG__mode__BITNR 0
2979#define R_PAR1_CONFIG__mode__WIDTH 3
2980#define R_PAR1_CONFIG__mode__manual 0
2981#define R_PAR1_CONFIG__mode__centronics 1
2982#define R_PAR1_CONFIG__mode__fastbyte 2
2983#define R_PAR1_CONFIG__mode__nibble 3
2984#define R_PAR1_CONFIG__mode__byte 4
2985#define R_PAR1_CONFIG__mode__ecp_fwd 5
2986#define R_PAR1_CONFIG__mode__ecp_rev 6
2987#define R_PAR1_CONFIG__mode__off 7
2988#define R_PAR1_CONFIG__mode__epp_wr1 5
2989#define R_PAR1_CONFIG__mode__epp_wr2 6
2990#define R_PAR1_CONFIG__mode__epp_wr3 7
2991#define R_PAR1_CONFIG__mode__epp_rd 0
2992
2993#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
2994#define R_PAR1_DELAY__fine_hold__BITNR 21
2995#define R_PAR1_DELAY__fine_hold__WIDTH 3
2996#define R_PAR1_DELAY__hold__BITNR 16
2997#define R_PAR1_DELAY__hold__WIDTH 5
2998#define R_PAR1_DELAY__fine_strb__BITNR 13
2999#define R_PAR1_DELAY__fine_strb__WIDTH 3
3000#define R_PAR1_DELAY__strobe__BITNR 8
3001#define R_PAR1_DELAY__strobe__WIDTH 5
3002#define R_PAR1_DELAY__fine_setup__BITNR 5
3003#define R_PAR1_DELAY__fine_setup__WIDTH 3
3004#define R_PAR1_DELAY__setup__BITNR 0
3005#define R_PAR1_DELAY__setup__WIDTH 5
3006
3007/*
3008!* ATA interface registers
3009!*/
3010
3011#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
3012#define R_ATA_CTRL_DATA__sel__BITNR 30
3013#define R_ATA_CTRL_DATA__sel__WIDTH 2
3014#define R_ATA_CTRL_DATA__cs1__BITNR 29
3015#define R_ATA_CTRL_DATA__cs1__WIDTH 1
3016#define R_ATA_CTRL_DATA__cs1__active 1
3017#define R_ATA_CTRL_DATA__cs1__inactive 0
3018#define R_ATA_CTRL_DATA__cs0__BITNR 28
3019#define R_ATA_CTRL_DATA__cs0__WIDTH 1
3020#define R_ATA_CTRL_DATA__cs0__active 1
3021#define R_ATA_CTRL_DATA__cs0__inactive 0
3022#define R_ATA_CTRL_DATA__addr__BITNR 25
3023#define R_ATA_CTRL_DATA__addr__WIDTH 3
3024#define R_ATA_CTRL_DATA__rw__BITNR 24
3025#define R_ATA_CTRL_DATA__rw__WIDTH 1
3026#define R_ATA_CTRL_DATA__rw__read 1
3027#define R_ATA_CTRL_DATA__rw__write 0
3028#define R_ATA_CTRL_DATA__src_dst__BITNR 23
3029#define R_ATA_CTRL_DATA__src_dst__WIDTH 1
3030#define R_ATA_CTRL_DATA__src_dst__dma 1
3031#define R_ATA_CTRL_DATA__src_dst__register 0
3032#define R_ATA_CTRL_DATA__handsh__BITNR 22
3033#define R_ATA_CTRL_DATA__handsh__WIDTH 1
3034#define R_ATA_CTRL_DATA__handsh__dma 1
3035#define R_ATA_CTRL_DATA__handsh__pio 0
3036#define R_ATA_CTRL_DATA__multi__BITNR 21
3037#define R_ATA_CTRL_DATA__multi__WIDTH 1
3038#define R_ATA_CTRL_DATA__multi__on 1
3039#define R_ATA_CTRL_DATA__multi__off 0
3040#define R_ATA_CTRL_DATA__dma_size__BITNR 20
3041#define R_ATA_CTRL_DATA__dma_size__WIDTH 1
3042#define R_ATA_CTRL_DATA__dma_size__byte 1
3043#define R_ATA_CTRL_DATA__dma_size__word 0
3044#define R_ATA_CTRL_DATA__data__BITNR 0
3045#define R_ATA_CTRL_DATA__data__WIDTH 16
3046
3047#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
3048#define R_ATA_STATUS_DATA__busy__BITNR 18
3049#define R_ATA_STATUS_DATA__busy__WIDTH 1
3050#define R_ATA_STATUS_DATA__busy__yes 1
3051#define R_ATA_STATUS_DATA__busy__no 0
3052#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
3053#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1
3054#define R_ATA_STATUS_DATA__tr_rdy__ready 1
3055#define R_ATA_STATUS_DATA__tr_rdy__busy 0
3056#define R_ATA_STATUS_DATA__dav__BITNR 16
3057#define R_ATA_STATUS_DATA__dav__WIDTH 1
3058#define R_ATA_STATUS_DATA__dav__data 1
3059#define R_ATA_STATUS_DATA__dav__nodata 0
3060#define R_ATA_STATUS_DATA__data__BITNR 0
3061#define R_ATA_STATUS_DATA__data__WIDTH 16
3062
3063#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
3064#define R_ATA_CONFIG__enable__BITNR 25
3065#define R_ATA_CONFIG__enable__WIDTH 1
3066#define R_ATA_CONFIG__enable__on 1
3067#define R_ATA_CONFIG__enable__off 0
3068#define R_ATA_CONFIG__dma_strobe__BITNR 20
3069#define R_ATA_CONFIG__dma_strobe__WIDTH 5
3070#define R_ATA_CONFIG__dma_hold__BITNR 15
3071#define R_ATA_CONFIG__dma_hold__WIDTH 5
3072#define R_ATA_CONFIG__pio_setup__BITNR 10
3073#define R_ATA_CONFIG__pio_setup__WIDTH 5
3074#define R_ATA_CONFIG__pio_strobe__BITNR 5
3075#define R_ATA_CONFIG__pio_strobe__WIDTH 5
3076#define R_ATA_CONFIG__pio_hold__BITNR 0
3077#define R_ATA_CONFIG__pio_hold__WIDTH 5
3078
3079#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048)
3080#define R_ATA_TRANSFER_CNT__count__BITNR 0
3081#define R_ATA_TRANSFER_CNT__count__WIDTH 17
3082
3083/*
3084!* SCSI registers
3085!*/
3086
3087#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044)
3088#define R_SCSI0_CTRL__id_type__BITNR 31
3089#define R_SCSI0_CTRL__id_type__WIDTH 1
3090#define R_SCSI0_CTRL__id_type__software 1
3091#define R_SCSI0_CTRL__id_type__hardware 0
3092#define R_SCSI0_CTRL__sel_timeout__BITNR 24
3093#define R_SCSI0_CTRL__sel_timeout__WIDTH 7
3094#define R_SCSI0_CTRL__synch_per__BITNR 16
3095#define R_SCSI0_CTRL__synch_per__WIDTH 8
3096#define R_SCSI0_CTRL__rst__BITNR 15
3097#define R_SCSI0_CTRL__rst__WIDTH 1
3098#define R_SCSI0_CTRL__rst__yes 1
3099#define R_SCSI0_CTRL__rst__no 0
3100#define R_SCSI0_CTRL__atn__BITNR 14
3101#define R_SCSI0_CTRL__atn__WIDTH 1
3102#define R_SCSI0_CTRL__atn__yes 1
3103#define R_SCSI0_CTRL__atn__no 0
3104#define R_SCSI0_CTRL__my_id__BITNR 9
3105#define R_SCSI0_CTRL__my_id__WIDTH 4
3106#define R_SCSI0_CTRL__target_id__BITNR 4
3107#define R_SCSI0_CTRL__target_id__WIDTH 4
3108#define R_SCSI0_CTRL__fast_20__BITNR 3
3109#define R_SCSI0_CTRL__fast_20__WIDTH 1
3110#define R_SCSI0_CTRL__fast_20__yes 1
3111#define R_SCSI0_CTRL__fast_20__no 0
3112#define R_SCSI0_CTRL__bus_width__BITNR 2
3113#define R_SCSI0_CTRL__bus_width__WIDTH 1
3114#define R_SCSI0_CTRL__bus_width__wide 1
3115#define R_SCSI0_CTRL__bus_width__narrow 0
3116#define R_SCSI0_CTRL__synch__BITNR 1
3117#define R_SCSI0_CTRL__synch__WIDTH 1
3118#define R_SCSI0_CTRL__synch__synch 1
3119#define R_SCSI0_CTRL__synch__asynch 0
3120#define R_SCSI0_CTRL__enable__BITNR 0
3121#define R_SCSI0_CTRL__enable__WIDTH 1
3122#define R_SCSI0_CTRL__enable__on 1
3123#define R_SCSI0_CTRL__enable__off 0
3124
3125#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040)
3126#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
3127#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1
3128#define R_SCSI0_CMD_DATA__parity_in__on 0
3129#define R_SCSI0_CMD_DATA__parity_in__off 1
3130#define R_SCSI0_CMD_DATA__skip__BITNR 25
3131#define R_SCSI0_CMD_DATA__skip__WIDTH 1
3132#define R_SCSI0_CMD_DATA__skip__on 1
3133#define R_SCSI0_CMD_DATA__skip__off 0
3134#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
3135#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1
3136#define R_SCSI0_CMD_DATA__clr_status__yes 1
3137#define R_SCSI0_CMD_DATA__clr_status__nop 0
3138#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
3139#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4
3140#define R_SCSI0_CMD_DATA__command__BITNR 16
3141#define R_SCSI0_CMD_DATA__command__WIDTH 4
3142#define R_SCSI0_CMD_DATA__command__full_din_1 0
3143#define R_SCSI0_CMD_DATA__command__full_dout_1 1
3144#define R_SCSI0_CMD_DATA__command__full_stat_1 2
3145#define R_SCSI0_CMD_DATA__command__resel_din 3
3146#define R_SCSI0_CMD_DATA__command__resel_dout 4
3147#define R_SCSI0_CMD_DATA__command__resel_stat 5
3148#define R_SCSI0_CMD_DATA__command__arb_only 6
3149#define R_SCSI0_CMD_DATA__command__full_din_3 8
3150#define R_SCSI0_CMD_DATA__command__full_dout_3 9
3151#define R_SCSI0_CMD_DATA__command__full_stat_3 10
3152#define R_SCSI0_CMD_DATA__command__man_data_in 11
3153#define R_SCSI0_CMD_DATA__command__man_data_out 12
3154#define R_SCSI0_CMD_DATA__command__man_rat 13
3155#define R_SCSI0_CMD_DATA__data_out__BITNR 0
3156#define R_SCSI0_CMD_DATA__data_out__WIDTH 16
3157
3158#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040)
3159#define R_SCSI0_DATA__data_out__BITNR 0
3160#define R_SCSI0_DATA__data_out__WIDTH 16
3161
3162#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042)
3163#define R_SCSI0_CMD__asynch_setup__BITNR 4
3164#define R_SCSI0_CMD__asynch_setup__WIDTH 4
3165#define R_SCSI0_CMD__command__BITNR 0
3166#define R_SCSI0_CMD__command__WIDTH 4
3167#define R_SCSI0_CMD__command__full_din_1 0
3168#define R_SCSI0_CMD__command__full_dout_1 1
3169#define R_SCSI0_CMD__command__full_stat_1 2
3170#define R_SCSI0_CMD__command__resel_din 3
3171#define R_SCSI0_CMD__command__resel_dout 4
3172#define R_SCSI0_CMD__command__resel_stat 5
3173#define R_SCSI0_CMD__command__arb_only 6
3174#define R_SCSI0_CMD__command__full_din_3 8
3175#define R_SCSI0_CMD__command__full_dout_3 9
3176#define R_SCSI0_CMD__command__full_stat_3 10
3177#define R_SCSI0_CMD__command__man_data_in 11
3178#define R_SCSI0_CMD__command__man_data_out 12
3179#define R_SCSI0_CMD__command__man_rat 13
3180
3181#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043)
3182#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
3183#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1
3184#define R_SCSI0_STATUS_CTRL__parity_in__on 0
3185#define R_SCSI0_STATUS_CTRL__parity_in__off 1
3186#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
3187#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1
3188#define R_SCSI0_STATUS_CTRL__skip__on 1
3189#define R_SCSI0_STATUS_CTRL__skip__off 0
3190#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
3191#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1
3192#define R_SCSI0_STATUS_CTRL__clr_status__yes 1
3193#define R_SCSI0_STATUS_CTRL__clr_status__nop 0
3194
3195#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048)
3196#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
3197#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1
3198#define R_SCSI0_STATUS__tst_resel__BITNR 22
3199#define R_SCSI0_STATUS__tst_resel__WIDTH 1
3200#define R_SCSI0_STATUS__parity_error__BITNR 21
3201#define R_SCSI0_STATUS__parity_error__WIDTH 1
3202#define R_SCSI0_STATUS__bus_reset__BITNR 20
3203#define R_SCSI0_STATUS__bus_reset__WIDTH 1
3204#define R_SCSI0_STATUS__bus_reset__yes 1
3205#define R_SCSI0_STATUS__bus_reset__no 0
3206#define R_SCSI0_STATUS__resel_target__BITNR 15
3207#define R_SCSI0_STATUS__resel_target__WIDTH 4
3208#define R_SCSI0_STATUS__resel__BITNR 14
3209#define R_SCSI0_STATUS__resel__WIDTH 1
3210#define R_SCSI0_STATUS__resel__yes 1
3211#define R_SCSI0_STATUS__resel__no 0
3212#define R_SCSI0_STATUS__curr_phase__BITNR 11
3213#define R_SCSI0_STATUS__curr_phase__WIDTH 3
3214#define R_SCSI0_STATUS__curr_phase__ph_undef 0
3215#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7
3216#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6
3217#define R_SCSI0_STATUS__curr_phase__ph_status 3
3218#define R_SCSI0_STATUS__curr_phase__ph_command 2
3219#define R_SCSI0_STATUS__curr_phase__ph_data_in 5
3220#define R_SCSI0_STATUS__curr_phase__ph_data_out 4
3221#define R_SCSI0_STATUS__curr_phase__ph_resel 1
3222#define R_SCSI0_STATUS__last_seq_step__BITNR 6
3223#define R_SCSI0_STATUS__last_seq_step__WIDTH 5
3224#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24
3225#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8
3226#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29
3227#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2
3228#define R_SCSI0_STATUS__last_seq_step__st_manual 28
3229#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30
3230#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6
3231#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22
3232#define R_SCSI0_STATUS__last_seq_step__st_answer 3
3233#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1
3234#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15
3235#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0
3236#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25
3237#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13
3238#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9
3239#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4
3240#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12
3241#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5
3242#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11
3243#define R_SCSI0_STATUS__last_seq_step__st_iwr 27
3244#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21
3245#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7
3246#define R_SCSI0_STATUS__last_seq_step__st_cc 31
3247#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14
3248#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23
3249#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17
3250#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20
3251#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16
3252#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10
3253#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18
3254#define R_SCSI0_STATUS__valid_status__BITNR 5
3255#define R_SCSI0_STATUS__valid_status__WIDTH 1
3256#define R_SCSI0_STATUS__valid_status__yes 1
3257#define R_SCSI0_STATUS__valid_status__no 0
3258#define R_SCSI0_STATUS__seq_status__BITNR 0
3259#define R_SCSI0_STATUS__seq_status__WIDTH 5
3260#define R_SCSI0_STATUS__seq_status__info_seq_complete 0
3261#define R_SCSI0_STATUS__seq_status__info_parity_error 1
3262#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2
3263#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3
3264#define R_SCSI0_STATUS__seq_status__info_arb_lost 4
3265#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5
3266#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6
3267#define R_SCSI0_STATUS__seq_status__info_illegal_op 7
3268#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8
3269#define R_SCSI0_STATUS__seq_status__info_reselected 9
3270#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10
3271#define R_SCSI0_STATUS__seq_status__info_bus_reset 11
3272#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12
3273#define R_SCSI0_STATUS__seq_status__info_bus_free 13
3274
3275#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040)
3276#define R_SCSI0_DATA_IN__data_in__BITNR 0
3277#define R_SCSI0_DATA_IN__data_in__WIDTH 16
3278
3279#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054)
3280#define R_SCSI1_CTRL__id_type__BITNR 31
3281#define R_SCSI1_CTRL__id_type__WIDTH 1
3282#define R_SCSI1_CTRL__id_type__software 1
3283#define R_SCSI1_CTRL__id_type__hardware 0
3284#define R_SCSI1_CTRL__sel_timeout__BITNR 24
3285#define R_SCSI1_CTRL__sel_timeout__WIDTH 7
3286#define R_SCSI1_CTRL__synch_per__BITNR 16
3287#define R_SCSI1_CTRL__synch_per__WIDTH 8
3288#define R_SCSI1_CTRL__rst__BITNR 15
3289#define R_SCSI1_CTRL__rst__WIDTH 1
3290#define R_SCSI1_CTRL__rst__yes 1
3291#define R_SCSI1_CTRL__rst__no 0
3292#define R_SCSI1_CTRL__atn__BITNR 14
3293#define R_SCSI1_CTRL__atn__WIDTH 1
3294#define R_SCSI1_CTRL__atn__yes 1
3295#define R_SCSI1_CTRL__atn__no 0
3296#define R_SCSI1_CTRL__my_id__BITNR 9
3297#define R_SCSI1_CTRL__my_id__WIDTH 4
3298#define R_SCSI1_CTRL__target_id__BITNR 4
3299#define R_SCSI1_CTRL__target_id__WIDTH 4
3300#define R_SCSI1_CTRL__fast_20__BITNR 3
3301#define R_SCSI1_CTRL__fast_20__WIDTH 1
3302#define R_SCSI1_CTRL__fast_20__yes 1
3303#define R_SCSI1_CTRL__fast_20__no 0
3304#define R_SCSI1_CTRL__bus_width__BITNR 2
3305#define R_SCSI1_CTRL__bus_width__WIDTH 1
3306#define R_SCSI1_CTRL__bus_width__wide 1
3307#define R_SCSI1_CTRL__bus_width__narrow 0
3308#define R_SCSI1_CTRL__synch__BITNR 1
3309#define R_SCSI1_CTRL__synch__WIDTH 1
3310#define R_SCSI1_CTRL__synch__synch 1
3311#define R_SCSI1_CTRL__synch__asynch 0
3312#define R_SCSI1_CTRL__enable__BITNR 0
3313#define R_SCSI1_CTRL__enable__WIDTH 1
3314#define R_SCSI1_CTRL__enable__on 1
3315#define R_SCSI1_CTRL__enable__off 0
3316
3317#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050)
3318#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
3319#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1
3320#define R_SCSI1_CMD_DATA__parity_in__on 0
3321#define R_SCSI1_CMD_DATA__parity_in__off 1
3322#define R_SCSI1_CMD_DATA__skip__BITNR 25
3323#define R_SCSI1_CMD_DATA__skip__WIDTH 1
3324#define R_SCSI1_CMD_DATA__skip__on 1
3325#define R_SCSI1_CMD_DATA__skip__off 0
3326#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
3327#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1
3328#define R_SCSI1_CMD_DATA__clr_status__yes 1
3329#define R_SCSI1_CMD_DATA__clr_status__nop 0
3330#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
3331#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4
3332#define R_SCSI1_CMD_DATA__command__BITNR 16
3333#define R_SCSI1_CMD_DATA__command__WIDTH 4
3334#define R_SCSI1_CMD_DATA__command__full_din_1 0
3335#define R_SCSI1_CMD_DATA__command__full_dout_1 1
3336#define R_SCSI1_CMD_DATA__command__full_stat_1 2
3337#define R_SCSI1_CMD_DATA__command__resel_din 3
3338#define R_SCSI1_CMD_DATA__command__resel_dout 4
3339#define R_SCSI1_CMD_DATA__command__resel_stat 5
3340#define R_SCSI1_CMD_DATA__command__arb_only 6
3341#define R_SCSI1_CMD_DATA__command__full_din_3 8
3342#define R_SCSI1_CMD_DATA__command__full_dout_3 9
3343#define R_SCSI1_CMD_DATA__command__full_stat_3 10
3344#define R_SCSI1_CMD_DATA__command__man_data_in 11
3345#define R_SCSI1_CMD_DATA__command__man_data_out 12
3346#define R_SCSI1_CMD_DATA__command__man_rat 13
3347#define R_SCSI1_CMD_DATA__data_out__BITNR 0
3348#define R_SCSI1_CMD_DATA__data_out__WIDTH 16
3349
3350#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050)
3351#define R_SCSI1_DATA__data_out__BITNR 0
3352#define R_SCSI1_DATA__data_out__WIDTH 16
3353
3354#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052)
3355#define R_SCSI1_CMD__asynch_setup__BITNR 4
3356#define R_SCSI1_CMD__asynch_setup__WIDTH 4
3357#define R_SCSI1_CMD__command__BITNR 0
3358#define R_SCSI1_CMD__command__WIDTH 4
3359#define R_SCSI1_CMD__command__full_din_1 0
3360#define R_SCSI1_CMD__command__full_dout_1 1
3361#define R_SCSI1_CMD__command__full_stat_1 2
3362#define R_SCSI1_CMD__command__resel_din 3
3363#define R_SCSI1_CMD__command__resel_dout 4
3364#define R_SCSI1_CMD__command__resel_stat 5
3365#define R_SCSI1_CMD__command__arb_only 6
3366#define R_SCSI1_CMD__command__full_din_3 8
3367#define R_SCSI1_CMD__command__full_dout_3 9
3368#define R_SCSI1_CMD__command__full_stat_3 10
3369#define R_SCSI1_CMD__command__man_data_in 11
3370#define R_SCSI1_CMD__command__man_data_out 12
3371#define R_SCSI1_CMD__command__man_rat 13
3372
3373#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053)
3374#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
3375#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1
3376#define R_SCSI1_STATUS_CTRL__parity_in__on 0
3377#define R_SCSI1_STATUS_CTRL__parity_in__off 1
3378#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
3379#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1
3380#define R_SCSI1_STATUS_CTRL__skip__on 1
3381#define R_SCSI1_STATUS_CTRL__skip__off 0
3382#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
3383#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1
3384#define R_SCSI1_STATUS_CTRL__clr_status__yes 1
3385#define R_SCSI1_STATUS_CTRL__clr_status__nop 0
3386
3387#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058)
3388#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
3389#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1
3390#define R_SCSI1_STATUS__tst_resel__BITNR 22
3391#define R_SCSI1_STATUS__tst_resel__WIDTH 1
3392#define R_SCSI1_STATUS__parity_error__BITNR 21
3393#define R_SCSI1_STATUS__parity_error__WIDTH 1
3394#define R_SCSI1_STATUS__bus_reset__BITNR 20
3395#define R_SCSI1_STATUS__bus_reset__WIDTH 1
3396#define R_SCSI1_STATUS__bus_reset__yes 1
3397#define R_SCSI1_STATUS__bus_reset__no 0
3398#define R_SCSI1_STATUS__resel_target__BITNR 15
3399#define R_SCSI1_STATUS__resel_target__WIDTH 4
3400#define R_SCSI1_STATUS__resel__BITNR 14
3401#define R_SCSI1_STATUS__resel__WIDTH 1
3402#define R_SCSI1_STATUS__resel__yes 1
3403#define R_SCSI1_STATUS__resel__no 0
3404#define R_SCSI1_STATUS__curr_phase__BITNR 11
3405#define R_SCSI1_STATUS__curr_phase__WIDTH 3
3406#define R_SCSI1_STATUS__curr_phase__ph_undef 0
3407#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7
3408#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6
3409#define R_SCSI1_STATUS__curr_phase__ph_status 3
3410#define R_SCSI1_STATUS__curr_phase__ph_command 2
3411#define R_SCSI1_STATUS__curr_phase__ph_data_in 5
3412#define R_SCSI1_STATUS__curr_phase__ph_data_out 4
3413#define R_SCSI1_STATUS__curr_phase__ph_resel 1
3414#define R_SCSI1_STATUS__last_seq_step__BITNR 6
3415#define R_SCSI1_STATUS__last_seq_step__WIDTH 5
3416#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24
3417#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8
3418#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29
3419#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2
3420#define R_SCSI1_STATUS__last_seq_step__st_manual 28
3421#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30
3422#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6
3423#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22
3424#define R_SCSI1_STATUS__last_seq_step__st_answer 3
3425#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1
3426#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15
3427#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0
3428#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25
3429#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13
3430#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9
3431#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4
3432#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12
3433#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5
3434#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11
3435#define R_SCSI1_STATUS__last_seq_step__st_iwr 27
3436#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21
3437#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7
3438#define R_SCSI1_STATUS__last_seq_step__st_cc 31
3439#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14
3440#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23
3441#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17
3442#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20
3443#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16
3444#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10
3445#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18
3446#define R_SCSI1_STATUS__valid_status__BITNR 5
3447#define R_SCSI1_STATUS__valid_status__WIDTH 1
3448#define R_SCSI1_STATUS__valid_status__yes 1
3449#define R_SCSI1_STATUS__valid_status__no 0
3450#define R_SCSI1_STATUS__seq_status__BITNR 0
3451#define R_SCSI1_STATUS__seq_status__WIDTH 5
3452#define R_SCSI1_STATUS__seq_status__info_seq_complete 0
3453#define R_SCSI1_STATUS__seq_status__info_parity_error 1
3454#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2
3455#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3
3456#define R_SCSI1_STATUS__seq_status__info_arb_lost 4
3457#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5
3458#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6
3459#define R_SCSI1_STATUS__seq_status__info_illegal_op 7
3460#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8
3461#define R_SCSI1_STATUS__seq_status__info_reselected 9
3462#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10
3463#define R_SCSI1_STATUS__seq_status__info_bus_reset 11
3464#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12
3465#define R_SCSI1_STATUS__seq_status__info_bus_free 13
3466
3467#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050)
3468#define R_SCSI1_DATA_IN__data_in__BITNR 0
3469#define R_SCSI1_DATA_IN__data_in__WIDTH 16
3470
3471/*
3472!* Interrupt mask and status registers
3473!*/
3474
3475#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0)
3476#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
3477#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1
3478#define R_IRQ_MASK0_RD__nmi_pin__active 1
3479#define R_IRQ_MASK0_RD__nmi_pin__inactive 0
3480#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
3481#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1
3482#define R_IRQ_MASK0_RD__watchdog_nmi__active 1
3483#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0
3484#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
3485#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1
3486#define R_IRQ_MASK0_RD__sqe_test_error__active 1
3487#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0
3488#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
3489#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1
3490#define R_IRQ_MASK0_RD__carrier_loss__active 1
3491#define R_IRQ_MASK0_RD__carrier_loss__inactive 0
3492#define R_IRQ_MASK0_RD__deferred__BITNR 27
3493#define R_IRQ_MASK0_RD__deferred__WIDTH 1
3494#define R_IRQ_MASK0_RD__deferred__active 1
3495#define R_IRQ_MASK0_RD__deferred__inactive 0
3496#define R_IRQ_MASK0_RD__late_col__BITNR 26
3497#define R_IRQ_MASK0_RD__late_col__WIDTH 1
3498#define R_IRQ_MASK0_RD__late_col__active 1
3499#define R_IRQ_MASK0_RD__late_col__inactive 0
3500#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
3501#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1
3502#define R_IRQ_MASK0_RD__multiple_col__active 1
3503#define R_IRQ_MASK0_RD__multiple_col__inactive 0
3504#define R_IRQ_MASK0_RD__single_col__BITNR 24
3505#define R_IRQ_MASK0_RD__single_col__WIDTH 1
3506#define R_IRQ_MASK0_RD__single_col__active 1
3507#define R_IRQ_MASK0_RD__single_col__inactive 0
3508#define R_IRQ_MASK0_RD__congestion__BITNR 23
3509#define R_IRQ_MASK0_RD__congestion__WIDTH 1
3510#define R_IRQ_MASK0_RD__congestion__active 1
3511#define R_IRQ_MASK0_RD__congestion__inactive 0
3512#define R_IRQ_MASK0_RD__oversize__BITNR 22
3513#define R_IRQ_MASK0_RD__oversize__WIDTH 1
3514#define R_IRQ_MASK0_RD__oversize__active 1
3515#define R_IRQ_MASK0_RD__oversize__inactive 0
3516#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
3517#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1
3518#define R_IRQ_MASK0_RD__alignment_error__active 1
3519#define R_IRQ_MASK0_RD__alignment_error__inactive 0
3520#define R_IRQ_MASK0_RD__crc_error__BITNR 20
3521#define R_IRQ_MASK0_RD__crc_error__WIDTH 1
3522#define R_IRQ_MASK0_RD__crc_error__active 1
3523#define R_IRQ_MASK0_RD__crc_error__inactive 0
3524#define R_IRQ_MASK0_RD__overrun__BITNR 19
3525#define R_IRQ_MASK0_RD__overrun__WIDTH 1
3526#define R_IRQ_MASK0_RD__overrun__active 1
3527#define R_IRQ_MASK0_RD__overrun__inactive 0
3528#define R_IRQ_MASK0_RD__underrun__BITNR 18
3529#define R_IRQ_MASK0_RD__underrun__WIDTH 1
3530#define R_IRQ_MASK0_RD__underrun__active 1
3531#define R_IRQ_MASK0_RD__underrun__inactive 0
3532#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
3533#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1
3534#define R_IRQ_MASK0_RD__excessive_col__active 1
3535#define R_IRQ_MASK0_RD__excessive_col__inactive 0
3536#define R_IRQ_MASK0_RD__mdio__BITNR 16
3537#define R_IRQ_MASK0_RD__mdio__WIDTH 1
3538#define R_IRQ_MASK0_RD__mdio__active 1
3539#define R_IRQ_MASK0_RD__mdio__inactive 0
3540#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
3541#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1
3542#define R_IRQ_MASK0_RD__ata_drq3__active 1
3543#define R_IRQ_MASK0_RD__ata_drq3__inactive 0
3544#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
3545#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1
3546#define R_IRQ_MASK0_RD__ata_drq2__active 1
3547#define R_IRQ_MASK0_RD__ata_drq2__inactive 0
3548#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
3549#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1
3550#define R_IRQ_MASK0_RD__ata_drq1__active 1
3551#define R_IRQ_MASK0_RD__ata_drq1__inactive 0
3552#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
3553#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1
3554#define R_IRQ_MASK0_RD__ata_drq0__active 1
3555#define R_IRQ_MASK0_RD__ata_drq0__inactive 0
3556#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
3557#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1
3558#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1
3559#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0
3560#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
3561#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1
3562#define R_IRQ_MASK0_RD__ata_irq3__active 1
3563#define R_IRQ_MASK0_RD__ata_irq3__inactive 0
3564#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
3565#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1
3566#define R_IRQ_MASK0_RD__par0_peri__active 1
3567#define R_IRQ_MASK0_RD__par0_peri__inactive 0
3568#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
3569#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
3570#define R_IRQ_MASK0_RD__ata_irq2__active 1
3571#define R_IRQ_MASK0_RD__ata_irq2__inactive 0
3572#define R_IRQ_MASK0_RD__par0_data__BITNR 9
3573#define R_IRQ_MASK0_RD__par0_data__WIDTH 1
3574#define R_IRQ_MASK0_RD__par0_data__active 1
3575#define R_IRQ_MASK0_RD__par0_data__inactive 0
3576#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
3577#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
3578#define R_IRQ_MASK0_RD__ata_irq1__active 1
3579#define R_IRQ_MASK0_RD__ata_irq1__inactive 0
3580#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
3581#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
3582#define R_IRQ_MASK0_RD__par0_ready__active 1
3583#define R_IRQ_MASK0_RD__par0_ready__inactive 0
3584#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
3585#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1
3586#define R_IRQ_MASK0_RD__ata_irq0__active 1
3587#define R_IRQ_MASK0_RD__ata_irq0__inactive 0
3588#define R_IRQ_MASK0_RD__mio__BITNR 8
3589#define R_IRQ_MASK0_RD__mio__WIDTH 1
3590#define R_IRQ_MASK0_RD__mio__active 1
3591#define R_IRQ_MASK0_RD__mio__inactive 0
3592#define R_IRQ_MASK0_RD__scsi0__BITNR 8
3593#define R_IRQ_MASK0_RD__scsi0__WIDTH 1
3594#define R_IRQ_MASK0_RD__scsi0__active 1
3595#define R_IRQ_MASK0_RD__scsi0__inactive 0
3596#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
3597#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
3598#define R_IRQ_MASK0_RD__ata_dmaend__active 1
3599#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0
3600#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
3601#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1
3602#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1
3603#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0
3604#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
3605#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1
3606#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1
3607#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0
3608#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
3609#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1
3610#define R_IRQ_MASK0_RD__ext_dma1__active 1
3611#define R_IRQ_MASK0_RD__ext_dma1__inactive 0
3612#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
3613#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1
3614#define R_IRQ_MASK0_RD__ext_dma0__active 1
3615#define R_IRQ_MASK0_RD__ext_dma0__inactive 0
3616#define R_IRQ_MASK0_RD__timer1__BITNR 1
3617#define R_IRQ_MASK0_RD__timer1__WIDTH 1
3618#define R_IRQ_MASK0_RD__timer1__active 1
3619#define R_IRQ_MASK0_RD__timer1__inactive 0
3620#define R_IRQ_MASK0_RD__timer0__BITNR 0
3621#define R_IRQ_MASK0_RD__timer0__WIDTH 1
3622#define R_IRQ_MASK0_RD__timer0__active 1
3623#define R_IRQ_MASK0_RD__timer0__inactive 0
3624
3625#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0)
3626#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
3627#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1
3628#define R_IRQ_MASK0_CLR__nmi_pin__clr 1
3629#define R_IRQ_MASK0_CLR__nmi_pin__nop 0
3630#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
3631#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1
3632#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1
3633#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0
3634#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
3635#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1
3636#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1
3637#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0
3638#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
3639#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1
3640#define R_IRQ_MASK0_CLR__carrier_loss__clr 1
3641#define R_IRQ_MASK0_CLR__carrier_loss__nop 0
3642#define R_IRQ_MASK0_CLR__deferred__BITNR 27
3643#define R_IRQ_MASK0_CLR__deferred__WIDTH 1
3644#define R_IRQ_MASK0_CLR__deferred__clr 1
3645#define R_IRQ_MASK0_CLR__deferred__nop 0
3646#define R_IRQ_MASK0_CLR__late_col__BITNR 26
3647#define R_IRQ_MASK0_CLR__late_col__WIDTH 1
3648#define R_IRQ_MASK0_CLR__late_col__clr 1
3649#define R_IRQ_MASK0_CLR__late_col__nop 0
3650#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
3651#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1
3652#define R_IRQ_MASK0_CLR__multiple_col__clr 1
3653#define R_IRQ_MASK0_CLR__multiple_col__nop 0
3654#define R_IRQ_MASK0_CLR__single_col__BITNR 24
3655#define R_IRQ_MASK0_CLR__single_col__WIDTH 1
3656#define R_IRQ_MASK0_CLR__single_col__clr 1
3657#define R_IRQ_MASK0_CLR__single_col__nop 0
3658#define R_IRQ_MASK0_CLR__congestion__BITNR 23
3659#define R_IRQ_MASK0_CLR__congestion__WIDTH 1
3660#define R_IRQ_MASK0_CLR__congestion__clr 1
3661#define R_IRQ_MASK0_CLR__congestion__nop 0
3662#define R_IRQ_MASK0_CLR__oversize__BITNR 22
3663#define R_IRQ_MASK0_CLR__oversize__WIDTH 1
3664#define R_IRQ_MASK0_CLR__oversize__clr 1
3665#define R_IRQ_MASK0_CLR__oversize__nop 0
3666#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
3667#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1
3668#define R_IRQ_MASK0_CLR__alignment_error__clr 1
3669#define R_IRQ_MASK0_CLR__alignment_error__nop 0
3670#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
3671#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1
3672#define R_IRQ_MASK0_CLR__crc_error__clr 1
3673#define R_IRQ_MASK0_CLR__crc_error__nop 0
3674#define R_IRQ_MASK0_CLR__overrun__BITNR 19
3675#define R_IRQ_MASK0_CLR__overrun__WIDTH 1
3676#define R_IRQ_MASK0_CLR__overrun__clr 1
3677#define R_IRQ_MASK0_CLR__overrun__nop 0
3678#define R_IRQ_MASK0_CLR__underrun__BITNR 18
3679#define R_IRQ_MASK0_CLR__underrun__WIDTH 1
3680#define R_IRQ_MASK0_CLR__underrun__clr 1
3681#define R_IRQ_MASK0_CLR__underrun__nop 0
3682#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
3683#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1
3684#define R_IRQ_MASK0_CLR__excessive_col__clr 1
3685#define R_IRQ_MASK0_CLR__excessive_col__nop 0
3686#define R_IRQ_MASK0_CLR__mdio__BITNR 16
3687#define R_IRQ_MASK0_CLR__mdio__WIDTH 1
3688#define R_IRQ_MASK0_CLR__mdio__clr 1
3689#define R_IRQ_MASK0_CLR__mdio__nop 0
3690#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
3691#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1
3692#define R_IRQ_MASK0_CLR__ata_drq3__clr 1
3693#define R_IRQ_MASK0_CLR__ata_drq3__nop 0
3694#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
3695#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1
3696#define R_IRQ_MASK0_CLR__ata_drq2__clr 1
3697#define R_IRQ_MASK0_CLR__ata_drq2__nop 0
3698#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
3699#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1
3700#define R_IRQ_MASK0_CLR__ata_drq1__clr 1
3701#define R_IRQ_MASK0_CLR__ata_drq1__nop 0
3702#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
3703#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1
3704#define R_IRQ_MASK0_CLR__ata_drq0__clr 1
3705#define R_IRQ_MASK0_CLR__ata_drq0__nop 0
3706#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
3707#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1
3708#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1
3709#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0
3710#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
3711#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1
3712#define R_IRQ_MASK0_CLR__ata_irq3__clr 1
3713#define R_IRQ_MASK0_CLR__ata_irq3__nop 0
3714#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
3715#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1
3716#define R_IRQ_MASK0_CLR__par0_peri__clr 1
3717#define R_IRQ_MASK0_CLR__par0_peri__nop 0
3718#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
3719#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
3720#define R_IRQ_MASK0_CLR__ata_irq2__clr 1
3721#define R_IRQ_MASK0_CLR__ata_irq2__nop 0
3722#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
3723#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
3724#define R_IRQ_MASK0_CLR__par0_data__clr 1
3725#define R_IRQ_MASK0_CLR__par0_data__nop 0
3726#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
3727#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
3728#define R_IRQ_MASK0_CLR__ata_irq1__clr 1
3729#define R_IRQ_MASK0_CLR__ata_irq1__nop 0
3730#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
3731#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
3732#define R_IRQ_MASK0_CLR__par0_ready__clr 1
3733#define R_IRQ_MASK0_CLR__par0_ready__nop 0
3734#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
3735#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1
3736#define R_IRQ_MASK0_CLR__ata_irq0__clr 1
3737#define R_IRQ_MASK0_CLR__ata_irq0__nop 0
3738#define R_IRQ_MASK0_CLR__mio__BITNR 8
3739#define R_IRQ_MASK0_CLR__mio__WIDTH 1
3740#define R_IRQ_MASK0_CLR__mio__clr 1
3741#define R_IRQ_MASK0_CLR__mio__nop 0
3742#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
3743#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
3744#define R_IRQ_MASK0_CLR__scsi0__clr 1
3745#define R_IRQ_MASK0_CLR__scsi0__nop 0
3746#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
3747#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
3748#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
3749#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0
3750#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
3751#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1
3752#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1
3753#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0
3754#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
3755#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1
3756#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1
3757#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0
3758#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
3759#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1
3760#define R_IRQ_MASK0_CLR__ext_dma1__clr 1
3761#define R_IRQ_MASK0_CLR__ext_dma1__nop 0
3762#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
3763#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1
3764#define R_IRQ_MASK0_CLR__ext_dma0__clr 1
3765#define R_IRQ_MASK0_CLR__ext_dma0__nop 0
3766#define R_IRQ_MASK0_CLR__timer1__BITNR 1
3767#define R_IRQ_MASK0_CLR__timer1__WIDTH 1
3768#define R_IRQ_MASK0_CLR__timer1__clr 1
3769#define R_IRQ_MASK0_CLR__timer1__nop 0
3770#define R_IRQ_MASK0_CLR__timer0__BITNR 0
3771#define R_IRQ_MASK0_CLR__timer0__WIDTH 1
3772#define R_IRQ_MASK0_CLR__timer0__clr 1
3773#define R_IRQ_MASK0_CLR__timer0__nop 0
3774
3775#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4)
3776#define R_IRQ_READ0__nmi_pin__BITNR 31
3777#define R_IRQ_READ0__nmi_pin__WIDTH 1
3778#define R_IRQ_READ0__nmi_pin__active 1
3779#define R_IRQ_READ0__nmi_pin__inactive 0
3780#define R_IRQ_READ0__watchdog_nmi__BITNR 30
3781#define R_IRQ_READ0__watchdog_nmi__WIDTH 1
3782#define R_IRQ_READ0__watchdog_nmi__active 1
3783#define R_IRQ_READ0__watchdog_nmi__inactive 0
3784#define R_IRQ_READ0__sqe_test_error__BITNR 29
3785#define R_IRQ_READ0__sqe_test_error__WIDTH 1
3786#define R_IRQ_READ0__sqe_test_error__active 1
3787#define R_IRQ_READ0__sqe_test_error__inactive 0
3788#define R_IRQ_READ0__carrier_loss__BITNR 28
3789#define R_IRQ_READ0__carrier_loss__WIDTH 1
3790#define R_IRQ_READ0__carrier_loss__active 1
3791#define R_IRQ_READ0__carrier_loss__inactive 0
3792#define R_IRQ_READ0__deferred__BITNR 27
3793#define R_IRQ_READ0__deferred__WIDTH 1
3794#define R_IRQ_READ0__deferred__active 1
3795#define R_IRQ_READ0__deferred__inactive 0
3796#define R_IRQ_READ0__late_col__BITNR 26
3797#define R_IRQ_READ0__late_col__WIDTH 1
3798#define R_IRQ_READ0__late_col__active 1
3799#define R_IRQ_READ0__late_col__inactive 0
3800#define R_IRQ_READ0__multiple_col__BITNR 25
3801#define R_IRQ_READ0__multiple_col__WIDTH 1
3802#define R_IRQ_READ0__multiple_col__active 1
3803#define R_IRQ_READ0__multiple_col__inactive 0
3804#define R_IRQ_READ0__single_col__BITNR 24
3805#define R_IRQ_READ0__single_col__WIDTH 1
3806#define R_IRQ_READ0__single_col__active 1
3807#define R_IRQ_READ0__single_col__inactive 0
3808#define R_IRQ_READ0__congestion__BITNR 23
3809#define R_IRQ_READ0__congestion__WIDTH 1
3810#define R_IRQ_READ0__congestion__active 1
3811#define R_IRQ_READ0__congestion__inactive 0
3812#define R_IRQ_READ0__oversize__BITNR 22
3813#define R_IRQ_READ0__oversize__WIDTH 1
3814#define R_IRQ_READ0__oversize__active 1
3815#define R_IRQ_READ0__oversize__inactive 0
3816#define R_IRQ_READ0__alignment_error__BITNR 21
3817#define R_IRQ_READ0__alignment_error__WIDTH 1
3818#define R_IRQ_READ0__alignment_error__active 1
3819#define R_IRQ_READ0__alignment_error__inactive 0
3820#define R_IRQ_READ0__crc_error__BITNR 20
3821#define R_IRQ_READ0__crc_error__WIDTH 1
3822#define R_IRQ_READ0__crc_error__active 1
3823#define R_IRQ_READ0__crc_error__inactive 0
3824#define R_IRQ_READ0__overrun__BITNR 19
3825#define R_IRQ_READ0__overrun__WIDTH 1
3826#define R_IRQ_READ0__overrun__active 1
3827#define R_IRQ_READ0__overrun__inactive 0
3828#define R_IRQ_READ0__underrun__BITNR 18
3829#define R_IRQ_READ0__underrun__WIDTH 1
3830#define R_IRQ_READ0__underrun__active 1
3831#define R_IRQ_READ0__underrun__inactive 0
3832#define R_IRQ_READ0__excessive_col__BITNR 17
3833#define R_IRQ_READ0__excessive_col__WIDTH 1
3834#define R_IRQ_READ0__excessive_col__active 1
3835#define R_IRQ_READ0__excessive_col__inactive 0
3836#define R_IRQ_READ0__mdio__BITNR 16
3837#define R_IRQ_READ0__mdio__WIDTH 1
3838#define R_IRQ_READ0__mdio__active 1
3839#define R_IRQ_READ0__mdio__inactive 0
3840#define R_IRQ_READ0__ata_drq3__BITNR 15
3841#define R_IRQ_READ0__ata_drq3__WIDTH 1
3842#define R_IRQ_READ0__ata_drq3__active 1
3843#define R_IRQ_READ0__ata_drq3__inactive 0
3844#define R_IRQ_READ0__ata_drq2__BITNR 14
3845#define R_IRQ_READ0__ata_drq2__WIDTH 1
3846#define R_IRQ_READ0__ata_drq2__active 1
3847#define R_IRQ_READ0__ata_drq2__inactive 0
3848#define R_IRQ_READ0__ata_drq1__BITNR 13
3849#define R_IRQ_READ0__ata_drq1__WIDTH 1
3850#define R_IRQ_READ0__ata_drq1__active 1
3851#define R_IRQ_READ0__ata_drq1__inactive 0
3852#define R_IRQ_READ0__ata_drq0__BITNR 12
3853#define R_IRQ_READ0__ata_drq0__WIDTH 1
3854#define R_IRQ_READ0__ata_drq0__active 1
3855#define R_IRQ_READ0__ata_drq0__inactive 0
3856#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
3857#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1
3858#define R_IRQ_READ0__par0_ecp_cmd__active 1
3859#define R_IRQ_READ0__par0_ecp_cmd__inactive 0
3860#define R_IRQ_READ0__ata_irq3__BITNR 11
3861#define R_IRQ_READ0__ata_irq3__WIDTH 1
3862#define R_IRQ_READ0__ata_irq3__active 1
3863#define R_IRQ_READ0__ata_irq3__inactive 0
3864#define R_IRQ_READ0__par0_peri__BITNR 10
3865#define R_IRQ_READ0__par0_peri__WIDTH 1
3866#define R_IRQ_READ0__par0_peri__active 1
3867#define R_IRQ_READ0__par0_peri__inactive 0
3868#define R_IRQ_READ0__ata_irq2__BITNR 10
3869#define R_IRQ_READ0__ata_irq2__WIDTH 1
3870#define R_IRQ_READ0__ata_irq2__active 1
3871#define R_IRQ_READ0__ata_irq2__inactive 0
3872#define R_IRQ_READ0__par0_data__BITNR 9
3873#define R_IRQ_READ0__par0_data__WIDTH 1
3874#define R_IRQ_READ0__par0_data__active 1
3875#define R_IRQ_READ0__par0_data__inactive 0
3876#define R_IRQ_READ0__ata_irq1__BITNR 9
3877#define R_IRQ_READ0__ata_irq1__WIDTH 1
3878#define R_IRQ_READ0__ata_irq1__active 1
3879#define R_IRQ_READ0__ata_irq1__inactive 0
3880#define R_IRQ_READ0__par0_ready__BITNR 8
3881#define R_IRQ_READ0__par0_ready__WIDTH 1
3882#define R_IRQ_READ0__par0_ready__active 1
3883#define R_IRQ_READ0__par0_ready__inactive 0
3884#define R_IRQ_READ0__ata_irq0__BITNR 8
3885#define R_IRQ_READ0__ata_irq0__WIDTH 1
3886#define R_IRQ_READ0__ata_irq0__active 1
3887#define R_IRQ_READ0__ata_irq0__inactive 0
3888#define R_IRQ_READ0__mio__BITNR 8
3889#define R_IRQ_READ0__mio__WIDTH 1
3890#define R_IRQ_READ0__mio__active 1
3891#define R_IRQ_READ0__mio__inactive 0
3892#define R_IRQ_READ0__scsi0__BITNR 8
3893#define R_IRQ_READ0__scsi0__WIDTH 1
3894#define R_IRQ_READ0__scsi0__active 1
3895#define R_IRQ_READ0__scsi0__inactive 0
3896#define R_IRQ_READ0__ata_dmaend__BITNR 7
3897#define R_IRQ_READ0__ata_dmaend__WIDTH 1
3898#define R_IRQ_READ0__ata_dmaend__active 1
3899#define R_IRQ_READ0__ata_dmaend__inactive 0
3900#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
3901#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1
3902#define R_IRQ_READ0__irq_ext_vector_nr__active 1
3903#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0
3904#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
3905#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1
3906#define R_IRQ_READ0__irq_int_vector_nr__active 1
3907#define R_IRQ_READ0__irq_int_vector_nr__inactive 0
3908#define R_IRQ_READ0__ext_dma1__BITNR 3
3909#define R_IRQ_READ0__ext_dma1__WIDTH 1
3910#define R_IRQ_READ0__ext_dma1__active 1
3911#define R_IRQ_READ0__ext_dma1__inactive 0
3912#define R_IRQ_READ0__ext_dma0__BITNR 2
3913#define R_IRQ_READ0__ext_dma0__WIDTH 1
3914#define R_IRQ_READ0__ext_dma0__active 1
3915#define R_IRQ_READ0__ext_dma0__inactive 0
3916#define R_IRQ_READ0__timer1__BITNR 1
3917#define R_IRQ_READ0__timer1__WIDTH 1
3918#define R_IRQ_READ0__timer1__active 1
3919#define R_IRQ_READ0__timer1__inactive 0
3920#define R_IRQ_READ0__timer0__BITNR 0
3921#define R_IRQ_READ0__timer0__WIDTH 1
3922#define R_IRQ_READ0__timer0__active 1
3923#define R_IRQ_READ0__timer0__inactive 0
3924
3925#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4)
3926#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
3927#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1
3928#define R_IRQ_MASK0_SET__nmi_pin__set 1
3929#define R_IRQ_MASK0_SET__nmi_pin__nop 0
3930#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
3931#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1
3932#define R_IRQ_MASK0_SET__watchdog_nmi__set 1
3933#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0
3934#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
3935#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1
3936#define R_IRQ_MASK0_SET__sqe_test_error__set 1
3937#define R_IRQ_MASK0_SET__sqe_test_error__nop 0
3938#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
3939#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1
3940#define R_IRQ_MASK0_SET__carrier_loss__set 1
3941#define R_IRQ_MASK0_SET__carrier_loss__nop 0
3942#define R_IRQ_MASK0_SET__deferred__BITNR 27
3943#define R_IRQ_MASK0_SET__deferred__WIDTH 1
3944#define R_IRQ_MASK0_SET__deferred__set 1
3945#define R_IRQ_MASK0_SET__deferred__nop 0
3946#define R_IRQ_MASK0_SET__late_col__BITNR 26
3947#define R_IRQ_MASK0_SET__late_col__WIDTH 1
3948#define R_IRQ_MASK0_SET__late_col__set 1
3949#define R_IRQ_MASK0_SET__late_col__nop 0
3950#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
3951#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1
3952#define R_IRQ_MASK0_SET__multiple_col__set 1
3953#define R_IRQ_MASK0_SET__multiple_col__nop 0
3954#define R_IRQ_MASK0_SET__single_col__BITNR 24
3955#define R_IRQ_MASK0_SET__single_col__WIDTH 1
3956#define R_IRQ_MASK0_SET__single_col__set 1
3957#define R_IRQ_MASK0_SET__single_col__nop 0
3958#define R_IRQ_MASK0_SET__congestion__BITNR 23
3959#define R_IRQ_MASK0_SET__congestion__WIDTH 1
3960#define R_IRQ_MASK0_SET__congestion__set 1
3961#define R_IRQ_MASK0_SET__congestion__nop 0
3962#define R_IRQ_MASK0_SET__oversize__BITNR 22
3963#define R_IRQ_MASK0_SET__oversize__WIDTH 1
3964#define R_IRQ_MASK0_SET__oversize__set 1
3965#define R_IRQ_MASK0_SET__oversize__nop 0
3966#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
3967#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1
3968#define R_IRQ_MASK0_SET__alignment_error__set 1
3969#define R_IRQ_MASK0_SET__alignment_error__nop 0
3970#define R_IRQ_MASK0_SET__crc_error__BITNR 20
3971#define R_IRQ_MASK0_SET__crc_error__WIDTH 1
3972#define R_IRQ_MASK0_SET__crc_error__set 1
3973#define R_IRQ_MASK0_SET__crc_error__nop 0
3974#define R_IRQ_MASK0_SET__overrun__BITNR 19
3975#define R_IRQ_MASK0_SET__overrun__WIDTH 1
3976#define R_IRQ_MASK0_SET__overrun__set 1
3977#define R_IRQ_MASK0_SET__overrun__nop 0
3978#define R_IRQ_MASK0_SET__underrun__BITNR 18
3979#define R_IRQ_MASK0_SET__underrun__WIDTH 1
3980#define R_IRQ_MASK0_SET__underrun__set 1
3981#define R_IRQ_MASK0_SET__underrun__nop 0
3982#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
3983#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1
3984#define R_IRQ_MASK0_SET__excessive_col__set 1
3985#define R_IRQ_MASK0_SET__excessive_col__nop 0
3986#define R_IRQ_MASK0_SET__mdio__BITNR 16
3987#define R_IRQ_MASK0_SET__mdio__WIDTH 1
3988#define R_IRQ_MASK0_SET__mdio__set 1
3989#define R_IRQ_MASK0_SET__mdio__nop 0
3990#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
3991#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1
3992#define R_IRQ_MASK0_SET__ata_drq3__set 1
3993#define R_IRQ_MASK0_SET__ata_drq3__nop 0
3994#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
3995#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1
3996#define R_IRQ_MASK0_SET__ata_drq2__set 1
3997#define R_IRQ_MASK0_SET__ata_drq2__nop 0
3998#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
3999#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1
4000#define R_IRQ_MASK0_SET__ata_drq1__set 1
4001#define R_IRQ_MASK0_SET__ata_drq1__nop 0
4002#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
4003#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1
4004#define R_IRQ_MASK0_SET__ata_drq0__set 1
4005#define R_IRQ_MASK0_SET__ata_drq0__nop 0
4006#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
4007#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1
4008#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1
4009#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0
4010#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
4011#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1
4012#define R_IRQ_MASK0_SET__ata_irq3__set 1
4013#define R_IRQ_MASK0_SET__ata_irq3__nop 0
4014#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
4015#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1
4016#define R_IRQ_MASK0_SET__par0_peri__set 1
4017#define R_IRQ_MASK0_SET__par0_peri__nop 0
4018#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
4019#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
4020#define R_IRQ_MASK0_SET__ata_irq2__set 1
4021#define R_IRQ_MASK0_SET__ata_irq2__nop 0
4022#define R_IRQ_MASK0_SET__par0_data__BITNR 9
4023#define R_IRQ_MASK0_SET__par0_data__WIDTH 1
4024#define R_IRQ_MASK0_SET__par0_data__set 1
4025#define R_IRQ_MASK0_SET__par0_data__nop 0
4026#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
4027#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
4028#define R_IRQ_MASK0_SET__ata_irq1__set 1
4029#define R_IRQ_MASK0_SET__ata_irq1__nop 0
4030#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
4031#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
4032#define R_IRQ_MASK0_SET__par0_ready__set 1
4033#define R_IRQ_MASK0_SET__par0_ready__nop 0
4034#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
4035#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1
4036#define R_IRQ_MASK0_SET__ata_irq0__set 1
4037#define R_IRQ_MASK0_SET__ata_irq0__nop 0
4038#define R_IRQ_MASK0_SET__mio__BITNR 8
4039#define R_IRQ_MASK0_SET__mio__WIDTH 1
4040#define R_IRQ_MASK0_SET__mio__set 1
4041#define R_IRQ_MASK0_SET__mio__nop 0
4042#define R_IRQ_MASK0_SET__scsi0__BITNR 8
4043#define R_IRQ_MASK0_SET__scsi0__WIDTH 1
4044#define R_IRQ_MASK0_SET__scsi0__set 1
4045#define R_IRQ_MASK0_SET__scsi0__nop 0
4046#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
4047#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
4048#define R_IRQ_MASK0_SET__ata_dmaend__set 1
4049#define R_IRQ_MASK0_SET__ata_dmaend__nop 0
4050#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
4051#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1
4052#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1
4053#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0
4054#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
4055#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1
4056#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1
4057#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0
4058#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
4059#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1
4060#define R_IRQ_MASK0_SET__ext_dma1__set 1
4061#define R_IRQ_MASK0_SET__ext_dma1__nop 0
4062#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
4063#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1
4064#define R_IRQ_MASK0_SET__ext_dma0__set 1
4065#define R_IRQ_MASK0_SET__ext_dma0__nop 0
4066#define R_IRQ_MASK0_SET__timer1__BITNR 1
4067#define R_IRQ_MASK0_SET__timer1__WIDTH 1
4068#define R_IRQ_MASK0_SET__timer1__set 1
4069#define R_IRQ_MASK0_SET__timer1__nop 0
4070#define R_IRQ_MASK0_SET__timer0__BITNR 0
4071#define R_IRQ_MASK0_SET__timer0__WIDTH 1
4072#define R_IRQ_MASK0_SET__timer0__set 1
4073#define R_IRQ_MASK0_SET__timer0__nop 0
4074
4075#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8)
4076#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
4077#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1
4078#define R_IRQ_MASK1_RD__sw_int7__active 1
4079#define R_IRQ_MASK1_RD__sw_int7__inactive 0
4080#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
4081#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1
4082#define R_IRQ_MASK1_RD__sw_int6__active 1
4083#define R_IRQ_MASK1_RD__sw_int6__inactive 0
4084#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
4085#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1
4086#define R_IRQ_MASK1_RD__sw_int5__active 1
4087#define R_IRQ_MASK1_RD__sw_int5__inactive 0
4088#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
4089#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1
4090#define R_IRQ_MASK1_RD__sw_int4__active 1
4091#define R_IRQ_MASK1_RD__sw_int4__inactive 0
4092#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
4093#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1
4094#define R_IRQ_MASK1_RD__sw_int3__active 1
4095#define R_IRQ_MASK1_RD__sw_int3__inactive 0
4096#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
4097#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1
4098#define R_IRQ_MASK1_RD__sw_int2__active 1
4099#define R_IRQ_MASK1_RD__sw_int2__inactive 0
4100#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
4101#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1
4102#define R_IRQ_MASK1_RD__sw_int1__active 1
4103#define R_IRQ_MASK1_RD__sw_int1__inactive 0
4104#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
4105#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1
4106#define R_IRQ_MASK1_RD__sw_int0__active 1
4107#define R_IRQ_MASK1_RD__sw_int0__inactive 0
4108#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
4109#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1
4110#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1
4111#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0
4112#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
4113#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1
4114#define R_IRQ_MASK1_RD__par1_peri__active 1
4115#define R_IRQ_MASK1_RD__par1_peri__inactive 0
4116#define R_IRQ_MASK1_RD__par1_data__BITNR 17
4117#define R_IRQ_MASK1_RD__par1_data__WIDTH 1
4118#define R_IRQ_MASK1_RD__par1_data__active 1
4119#define R_IRQ_MASK1_RD__par1_data__inactive 0
4120#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
4121#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1
4122#define R_IRQ_MASK1_RD__par1_ready__active 1
4123#define R_IRQ_MASK1_RD__par1_ready__inactive 0
4124#define R_IRQ_MASK1_RD__scsi1__BITNR 16
4125#define R_IRQ_MASK1_RD__scsi1__WIDTH 1
4126#define R_IRQ_MASK1_RD__scsi1__active 1
4127#define R_IRQ_MASK1_RD__scsi1__inactive 0
4128#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
4129#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1
4130#define R_IRQ_MASK1_RD__ser3_ready__active 1
4131#define R_IRQ_MASK1_RD__ser3_ready__inactive 0
4132#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
4133#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1
4134#define R_IRQ_MASK1_RD__ser3_data__active 1
4135#define R_IRQ_MASK1_RD__ser3_data__inactive 0
4136#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
4137#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1
4138#define R_IRQ_MASK1_RD__ser2_ready__active 1
4139#define R_IRQ_MASK1_RD__ser2_ready__inactive 0
4140#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
4141#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1
4142#define R_IRQ_MASK1_RD__ser2_data__active 1
4143#define R_IRQ_MASK1_RD__ser2_data__inactive 0
4144#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
4145#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1
4146#define R_IRQ_MASK1_RD__ser1_ready__active 1
4147#define R_IRQ_MASK1_RD__ser1_ready__inactive 0
4148#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
4149#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1
4150#define R_IRQ_MASK1_RD__ser1_data__active 1
4151#define R_IRQ_MASK1_RD__ser1_data__inactive 0
4152#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
4153#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1
4154#define R_IRQ_MASK1_RD__ser0_ready__active 1
4155#define R_IRQ_MASK1_RD__ser0_ready__inactive 0
4156#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
4157#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1
4158#define R_IRQ_MASK1_RD__ser0_data__active 1
4159#define R_IRQ_MASK1_RD__ser0_data__inactive 0
4160#define R_IRQ_MASK1_RD__pa7__BITNR 7
4161#define R_IRQ_MASK1_RD__pa7__WIDTH 1
4162#define R_IRQ_MASK1_RD__pa7__active 1
4163#define R_IRQ_MASK1_RD__pa7__inactive 0
4164#define R_IRQ_MASK1_RD__pa6__BITNR 6
4165#define R_IRQ_MASK1_RD__pa6__WIDTH 1
4166#define R_IRQ_MASK1_RD__pa6__active 1
4167#define R_IRQ_MASK1_RD__pa6__inactive 0
4168#define R_IRQ_MASK1_RD__pa5__BITNR 5
4169#define R_IRQ_MASK1_RD__pa5__WIDTH 1
4170#define R_IRQ_MASK1_RD__pa5__active 1
4171#define R_IRQ_MASK1_RD__pa5__inactive 0
4172#define R_IRQ_MASK1_RD__pa4__BITNR 4
4173#define R_IRQ_MASK1_RD__pa4__WIDTH 1
4174#define R_IRQ_MASK1_RD__pa4__active 1
4175#define R_IRQ_MASK1_RD__pa4__inactive 0
4176#define R_IRQ_MASK1_RD__pa3__BITNR 3
4177#define R_IRQ_MASK1_RD__pa3__WIDTH 1
4178#define R_IRQ_MASK1_RD__pa3__active 1
4179#define R_IRQ_MASK1_RD__pa3__inactive 0
4180#define R_IRQ_MASK1_RD__pa2__BITNR 2
4181#define R_IRQ_MASK1_RD__pa2__WIDTH 1
4182#define R_IRQ_MASK1_RD__pa2__active 1
4183#define R_IRQ_MASK1_RD__pa2__inactive 0
4184#define R_IRQ_MASK1_RD__pa1__BITNR 1
4185#define R_IRQ_MASK1_RD__pa1__WIDTH 1
4186#define R_IRQ_MASK1_RD__pa1__active 1
4187#define R_IRQ_MASK1_RD__pa1__inactive 0
4188#define R_IRQ_MASK1_RD__pa0__BITNR 0
4189#define R_IRQ_MASK1_RD__pa0__WIDTH 1
4190#define R_IRQ_MASK1_RD__pa0__active 1
4191#define R_IRQ_MASK1_RD__pa0__inactive 0
4192
4193#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8)
4194#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
4195#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1
4196#define R_IRQ_MASK1_CLR__sw_int7__clr 1
4197#define R_IRQ_MASK1_CLR__sw_int7__nop 0
4198#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
4199#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1
4200#define R_IRQ_MASK1_CLR__sw_int6__clr 1
4201#define R_IRQ_MASK1_CLR__sw_int6__nop 0
4202#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
4203#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1
4204#define R_IRQ_MASK1_CLR__sw_int5__clr 1
4205#define R_IRQ_MASK1_CLR__sw_int5__nop 0
4206#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
4207#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1
4208#define R_IRQ_MASK1_CLR__sw_int4__clr 1
4209#define R_IRQ_MASK1_CLR__sw_int4__nop 0
4210#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
4211#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1
4212#define R_IRQ_MASK1_CLR__sw_int3__clr 1
4213#define R_IRQ_MASK1_CLR__sw_int3__nop 0
4214#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
4215#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1
4216#define R_IRQ_MASK1_CLR__sw_int2__clr 1
4217#define R_IRQ_MASK1_CLR__sw_int2__nop 0
4218#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
4219#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1
4220#define R_IRQ_MASK1_CLR__sw_int1__clr 1
4221#define R_IRQ_MASK1_CLR__sw_int1__nop 0
4222#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
4223#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1
4224#define R_IRQ_MASK1_CLR__sw_int0__clr 1
4225#define R_IRQ_MASK1_CLR__sw_int0__nop 0
4226#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
4227#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1
4228#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1
4229#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0
4230#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
4231#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1
4232#define R_IRQ_MASK1_CLR__par1_peri__clr 1
4233#define R_IRQ_MASK1_CLR__par1_peri__nop 0
4234#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
4235#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1
4236#define R_IRQ_MASK1_CLR__par1_data__clr 1
4237#define R_IRQ_MASK1_CLR__par1_data__nop 0
4238#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
4239#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1
4240#define R_IRQ_MASK1_CLR__par1_ready__clr 1
4241#define R_IRQ_MASK1_CLR__par1_ready__nop 0
4242#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
4243#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1
4244#define R_IRQ_MASK1_CLR__scsi1__clr 1
4245#define R_IRQ_MASK1_CLR__scsi1__nop 0
4246#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
4247#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1
4248#define R_IRQ_MASK1_CLR__ser3_ready__clr 1
4249#define R_IRQ_MASK1_CLR__ser3_ready__nop 0
4250#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
4251#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1
4252#define R_IRQ_MASK1_CLR__ser3_data__clr 1
4253#define R_IRQ_MASK1_CLR__ser3_data__nop 0
4254#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
4255#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1
4256#define R_IRQ_MASK1_CLR__ser2_ready__clr 1
4257#define R_IRQ_MASK1_CLR__ser2_ready__nop 0
4258#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
4259#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1
4260#define R_IRQ_MASK1_CLR__ser2_data__clr 1
4261#define R_IRQ_MASK1_CLR__ser2_data__nop 0
4262#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
4263#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1
4264#define R_IRQ_MASK1_CLR__ser1_ready__clr 1
4265#define R_IRQ_MASK1_CLR__ser1_ready__nop 0
4266#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
4267#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1
4268#define R_IRQ_MASK1_CLR__ser1_data__clr 1
4269#define R_IRQ_MASK1_CLR__ser1_data__nop 0
4270#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
4271#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1
4272#define R_IRQ_MASK1_CLR__ser0_ready__clr 1
4273#define R_IRQ_MASK1_CLR__ser0_ready__nop 0
4274#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
4275#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1
4276#define R_IRQ_MASK1_CLR__ser0_data__clr 1
4277#define R_IRQ_MASK1_CLR__ser0_data__nop 0
4278#define R_IRQ_MASK1_CLR__pa7__BITNR 7
4279#define R_IRQ_MASK1_CLR__pa7__WIDTH 1
4280#define R_IRQ_MASK1_CLR__pa7__clr 1
4281#define R_IRQ_MASK1_CLR__pa7__nop 0
4282#define R_IRQ_MASK1_CLR__pa6__BITNR 6
4283#define R_IRQ_MASK1_CLR__pa6__WIDTH 1
4284#define R_IRQ_MASK1_CLR__pa6__clr 1
4285#define R_IRQ_MASK1_CLR__pa6__nop 0
4286#define R_IRQ_MASK1_CLR__pa5__BITNR 5
4287#define R_IRQ_MASK1_CLR__pa5__WIDTH 1
4288#define R_IRQ_MASK1_CLR__pa5__clr 1
4289#define R_IRQ_MASK1_CLR__pa5__nop 0
4290#define R_IRQ_MASK1_CLR__pa4__BITNR 4
4291#define R_IRQ_MASK1_CLR__pa4__WIDTH 1
4292#define R_IRQ_MASK1_CLR__pa4__clr 1
4293#define R_IRQ_MASK1_CLR__pa4__nop 0
4294#define R_IRQ_MASK1_CLR__pa3__BITNR 3
4295#define R_IRQ_MASK1_CLR__pa3__WIDTH 1
4296#define R_IRQ_MASK1_CLR__pa3__clr 1
4297#define R_IRQ_MASK1_CLR__pa3__nop 0
4298#define R_IRQ_MASK1_CLR__pa2__BITNR 2
4299#define R_IRQ_MASK1_CLR__pa2__WIDTH 1
4300#define R_IRQ_MASK1_CLR__pa2__clr 1
4301#define R_IRQ_MASK1_CLR__pa2__nop 0
4302#define R_IRQ_MASK1_CLR__pa1__BITNR 1
4303#define R_IRQ_MASK1_CLR__pa1__WIDTH 1
4304#define R_IRQ_MASK1_CLR__pa1__clr 1
4305#define R_IRQ_MASK1_CLR__pa1__nop 0
4306#define R_IRQ_MASK1_CLR__pa0__BITNR 0
4307#define R_IRQ_MASK1_CLR__pa0__WIDTH 1
4308#define R_IRQ_MASK1_CLR__pa0__clr 1
4309#define R_IRQ_MASK1_CLR__pa0__nop 0
4310
4311#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc)
4312#define R_IRQ_READ1__sw_int7__BITNR 31
4313#define R_IRQ_READ1__sw_int7__WIDTH 1
4314#define R_IRQ_READ1__sw_int7__active 1
4315#define R_IRQ_READ1__sw_int7__inactive 0
4316#define R_IRQ_READ1__sw_int6__BITNR 30
4317#define R_IRQ_READ1__sw_int6__WIDTH 1
4318#define R_IRQ_READ1__sw_int6__active 1
4319#define R_IRQ_READ1__sw_int6__inactive 0
4320#define R_IRQ_READ1__sw_int5__BITNR 29
4321#define R_IRQ_READ1__sw_int5__WIDTH 1
4322#define R_IRQ_READ1__sw_int5__active 1
4323#define R_IRQ_READ1__sw_int5__inactive 0
4324#define R_IRQ_READ1__sw_int4__BITNR 28
4325#define R_IRQ_READ1__sw_int4__WIDTH 1
4326#define R_IRQ_READ1__sw_int4__active 1
4327#define R_IRQ_READ1__sw_int4__inactive 0
4328#define R_IRQ_READ1__sw_int3__BITNR 27
4329#define R_IRQ_READ1__sw_int3__WIDTH 1
4330#define R_IRQ_READ1__sw_int3__active 1
4331#define R_IRQ_READ1__sw_int3__inactive 0
4332#define R_IRQ_READ1__sw_int2__BITNR 26
4333#define R_IRQ_READ1__sw_int2__WIDTH 1
4334#define R_IRQ_READ1__sw_int2__active 1
4335#define R_IRQ_READ1__sw_int2__inactive 0
4336#define R_IRQ_READ1__sw_int1__BITNR 25
4337#define R_IRQ_READ1__sw_int1__WIDTH 1
4338#define R_IRQ_READ1__sw_int1__active 1
4339#define R_IRQ_READ1__sw_int1__inactive 0
4340#define R_IRQ_READ1__sw_int0__BITNR 24
4341#define R_IRQ_READ1__sw_int0__WIDTH 1
4342#define R_IRQ_READ1__sw_int0__active 1
4343#define R_IRQ_READ1__sw_int0__inactive 0
4344#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
4345#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1
4346#define R_IRQ_READ1__par1_ecp_cmd__active 1
4347#define R_IRQ_READ1__par1_ecp_cmd__inactive 0
4348#define R_IRQ_READ1__par1_peri__BITNR 18
4349#define R_IRQ_READ1__par1_peri__WIDTH 1
4350#define R_IRQ_READ1__par1_peri__active 1
4351#define R_IRQ_READ1__par1_peri__inactive 0
4352#define R_IRQ_READ1__par1_data__BITNR 17
4353#define R_IRQ_READ1__par1_data__WIDTH 1
4354#define R_IRQ_READ1__par1_data__active 1
4355#define R_IRQ_READ1__par1_data__inactive 0
4356#define R_IRQ_READ1__par1_ready__BITNR 16
4357#define R_IRQ_READ1__par1_ready__WIDTH 1
4358#define R_IRQ_READ1__par1_ready__active 1
4359#define R_IRQ_READ1__par1_ready__inactive 0
4360#define R_IRQ_READ1__scsi1__BITNR 16
4361#define R_IRQ_READ1__scsi1__WIDTH 1
4362#define R_IRQ_READ1__scsi1__active 1
4363#define R_IRQ_READ1__scsi1__inactive 0
4364#define R_IRQ_READ1__ser3_ready__BITNR 15
4365#define R_IRQ_READ1__ser3_ready__WIDTH 1
4366#define R_IRQ_READ1__ser3_ready__active 1
4367#define R_IRQ_READ1__ser3_ready__inactive 0
4368#define R_IRQ_READ1__ser3_data__BITNR 14
4369#define R_IRQ_READ1__ser3_data__WIDTH 1
4370#define R_IRQ_READ1__ser3_data__active 1
4371#define R_IRQ_READ1__ser3_data__inactive 0
4372#define R_IRQ_READ1__ser2_ready__BITNR 13
4373#define R_IRQ_READ1__ser2_ready__WIDTH 1
4374#define R_IRQ_READ1__ser2_ready__active 1
4375#define R_IRQ_READ1__ser2_ready__inactive 0
4376#define R_IRQ_READ1__ser2_data__BITNR 12
4377#define R_IRQ_READ1__ser2_data__WIDTH 1
4378#define R_IRQ_READ1__ser2_data__active 1
4379#define R_IRQ_READ1__ser2_data__inactive 0
4380#define R_IRQ_READ1__ser1_ready__BITNR 11
4381#define R_IRQ_READ1__ser1_ready__WIDTH 1
4382#define R_IRQ_READ1__ser1_ready__active 1
4383#define R_IRQ_READ1__ser1_ready__inactive 0
4384#define R_IRQ_READ1__ser1_data__BITNR 10
4385#define R_IRQ_READ1__ser1_data__WIDTH 1
4386#define R_IRQ_READ1__ser1_data__active 1
4387#define R_IRQ_READ1__ser1_data__inactive 0
4388#define R_IRQ_READ1__ser0_ready__BITNR 9
4389#define R_IRQ_READ1__ser0_ready__WIDTH 1
4390#define R_IRQ_READ1__ser0_ready__active 1
4391#define R_IRQ_READ1__ser0_ready__inactive 0
4392#define R_IRQ_READ1__ser0_data__BITNR 8
4393#define R_IRQ_READ1__ser0_data__WIDTH 1
4394#define R_IRQ_READ1__ser0_data__active 1
4395#define R_IRQ_READ1__ser0_data__inactive 0
4396#define R_IRQ_READ1__pa7__BITNR 7
4397#define R_IRQ_READ1__pa7__WIDTH 1
4398#define R_IRQ_READ1__pa7__active 1
4399#define R_IRQ_READ1__pa7__inactive 0
4400#define R_IRQ_READ1__pa6__BITNR 6
4401#define R_IRQ_READ1__pa6__WIDTH 1
4402#define R_IRQ_READ1__pa6__active 1
4403#define R_IRQ_READ1__pa6__inactive 0
4404#define R_IRQ_READ1__pa5__BITNR 5
4405#define R_IRQ_READ1__pa5__WIDTH 1
4406#define R_IRQ_READ1__pa5__active 1
4407#define R_IRQ_READ1__pa5__inactive 0
4408#define R_IRQ_READ1__pa4__BITNR 4
4409#define R_IRQ_READ1__pa4__WIDTH 1
4410#define R_IRQ_READ1__pa4__active 1
4411#define R_IRQ_READ1__pa4__inactive 0
4412#define R_IRQ_READ1__pa3__BITNR 3
4413#define R_IRQ_READ1__pa3__WIDTH 1
4414#define R_IRQ_READ1__pa3__active 1
4415#define R_IRQ_READ1__pa3__inactive 0
4416#define R_IRQ_READ1__pa2__BITNR 2
4417#define R_IRQ_READ1__pa2__WIDTH 1
4418#define R_IRQ_READ1__pa2__active 1
4419#define R_IRQ_READ1__pa2__inactive 0
4420#define R_IRQ_READ1__pa1__BITNR 1
4421#define R_IRQ_READ1__pa1__WIDTH 1
4422#define R_IRQ_READ1__pa1__active 1
4423#define R_IRQ_READ1__pa1__inactive 0
4424#define R_IRQ_READ1__pa0__BITNR 0
4425#define R_IRQ_READ1__pa0__WIDTH 1
4426#define R_IRQ_READ1__pa0__active 1
4427#define R_IRQ_READ1__pa0__inactive 0
4428
4429#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc)
4430#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
4431#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1
4432#define R_IRQ_MASK1_SET__sw_int7__set 1
4433#define R_IRQ_MASK1_SET__sw_int7__nop 0
4434#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
4435#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1
4436#define R_IRQ_MASK1_SET__sw_int6__set 1
4437#define R_IRQ_MASK1_SET__sw_int6__nop 0
4438#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
4439#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1
4440#define R_IRQ_MASK1_SET__sw_int5__set 1
4441#define R_IRQ_MASK1_SET__sw_int5__nop 0
4442#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
4443#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1
4444#define R_IRQ_MASK1_SET__sw_int4__set 1
4445#define R_IRQ_MASK1_SET__sw_int4__nop 0
4446#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
4447#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1
4448#define R_IRQ_MASK1_SET__sw_int3__set 1
4449#define R_IRQ_MASK1_SET__sw_int3__nop 0
4450#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
4451#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1
4452#define R_IRQ_MASK1_SET__sw_int2__set 1
4453#define R_IRQ_MASK1_SET__sw_int2__nop 0
4454#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
4455#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1
4456#define R_IRQ_MASK1_SET__sw_int1__set 1
4457#define R_IRQ_MASK1_SET__sw_int1__nop 0
4458#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
4459#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1
4460#define R_IRQ_MASK1_SET__sw_int0__set 1
4461#define R_IRQ_MASK1_SET__sw_int0__nop 0
4462#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
4463#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1
4464#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1
4465#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0
4466#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
4467#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1
4468#define R_IRQ_MASK1_SET__par1_peri__set 1
4469#define R_IRQ_MASK1_SET__par1_peri__nop 0
4470#define R_IRQ_MASK1_SET__par1_data__BITNR 17
4471#define R_IRQ_MASK1_SET__par1_data__WIDTH 1
4472#define R_IRQ_MASK1_SET__par1_data__set 1
4473#define R_IRQ_MASK1_SET__par1_data__nop 0
4474#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
4475#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1
4476#define R_IRQ_MASK1_SET__par1_ready__set 1
4477#define R_IRQ_MASK1_SET__par1_ready__nop 0
4478#define R_IRQ_MASK1_SET__scsi1__BITNR 16
4479#define R_IRQ_MASK1_SET__scsi1__WIDTH 1
4480#define R_IRQ_MASK1_SET__scsi1__set 1
4481#define R_IRQ_MASK1_SET__scsi1__nop 0
4482#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
4483#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1
4484#define R_IRQ_MASK1_SET__ser3_ready__set 1
4485#define R_IRQ_MASK1_SET__ser3_ready__nop 0
4486#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
4487#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1
4488#define R_IRQ_MASK1_SET__ser3_data__set 1
4489#define R_IRQ_MASK1_SET__ser3_data__nop 0
4490#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
4491#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1
4492#define R_IRQ_MASK1_SET__ser2_ready__set 1
4493#define R_IRQ_MASK1_SET__ser2_ready__nop 0
4494#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
4495#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1
4496#define R_IRQ_MASK1_SET__ser2_data__set 1
4497#define R_IRQ_MASK1_SET__ser2_data__nop 0
4498#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
4499#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1
4500#define R_IRQ_MASK1_SET__ser1_ready__set 1
4501#define R_IRQ_MASK1_SET__ser1_ready__nop 0
4502#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
4503#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1
4504#define R_IRQ_MASK1_SET__ser1_data__set 1
4505#define R_IRQ_MASK1_SET__ser1_data__nop 0
4506#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
4507#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1
4508#define R_IRQ_MASK1_SET__ser0_ready__set 1
4509#define R_IRQ_MASK1_SET__ser0_ready__nop 0
4510#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
4511#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1
4512#define R_IRQ_MASK1_SET__ser0_data__set 1
4513#define R_IRQ_MASK1_SET__ser0_data__nop 0
4514#define R_IRQ_MASK1_SET__pa7__BITNR 7
4515#define R_IRQ_MASK1_SET__pa7__WIDTH 1
4516#define R_IRQ_MASK1_SET__pa7__set 1
4517#define R_IRQ_MASK1_SET__pa7__nop 0
4518#define R_IRQ_MASK1_SET__pa6__BITNR 6
4519#define R_IRQ_MASK1_SET__pa6__WIDTH 1
4520#define R_IRQ_MASK1_SET__pa6__set 1
4521#define R_IRQ_MASK1_SET__pa6__nop 0
4522#define R_IRQ_MASK1_SET__pa5__BITNR 5
4523#define R_IRQ_MASK1_SET__pa5__WIDTH 1
4524#define R_IRQ_MASK1_SET__pa5__set 1
4525#define R_IRQ_MASK1_SET__pa5__nop 0
4526#define R_IRQ_MASK1_SET__pa4__BITNR 4
4527#define R_IRQ_MASK1_SET__pa4__WIDTH 1
4528#define R_IRQ_MASK1_SET__pa4__set 1
4529#define R_IRQ_MASK1_SET__pa4__nop 0
4530#define R_IRQ_MASK1_SET__pa3__BITNR 3
4531#define R_IRQ_MASK1_SET__pa3__WIDTH 1
4532#define R_IRQ_MASK1_SET__pa3__set 1
4533#define R_IRQ_MASK1_SET__pa3__nop 0
4534#define R_IRQ_MASK1_SET__pa2__BITNR 2
4535#define R_IRQ_MASK1_SET__pa2__WIDTH 1
4536#define R_IRQ_MASK1_SET__pa2__set 1
4537#define R_IRQ_MASK1_SET__pa2__nop 0
4538#define R_IRQ_MASK1_SET__pa1__BITNR 1
4539#define R_IRQ_MASK1_SET__pa1__WIDTH 1
4540#define R_IRQ_MASK1_SET__pa1__set 1
4541#define R_IRQ_MASK1_SET__pa1__nop 0
4542#define R_IRQ_MASK1_SET__pa0__BITNR 0
4543#define R_IRQ_MASK1_SET__pa0__WIDTH 1
4544#define R_IRQ_MASK1_SET__pa0__set 1
4545#define R_IRQ_MASK1_SET__pa0__nop 0
4546
4547#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0)
4548#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
4549#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1
4550#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1
4551#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0
4552#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
4553#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1
4554#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1
4555#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0
4556#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
4557#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1
4558#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1
4559#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0
4560#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
4561#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1
4562#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1
4563#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0
4564#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
4565#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1
4566#define R_IRQ_MASK2_RD__dma9_eop__active 1
4567#define R_IRQ_MASK2_RD__dma9_eop__inactive 0
4568#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
4569#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1
4570#define R_IRQ_MASK2_RD__dma9_descr__active 1
4571#define R_IRQ_MASK2_RD__dma9_descr__inactive 0
4572#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
4573#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1
4574#define R_IRQ_MASK2_RD__dma8_eop__active 1
4575#define R_IRQ_MASK2_RD__dma8_eop__inactive 0
4576#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
4577#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1
4578#define R_IRQ_MASK2_RD__dma8_descr__active 1
4579#define R_IRQ_MASK2_RD__dma8_descr__inactive 0
4580#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
4581#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1
4582#define R_IRQ_MASK2_RD__dma7_eop__active 1
4583#define R_IRQ_MASK2_RD__dma7_eop__inactive 0
4584#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
4585#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1
4586#define R_IRQ_MASK2_RD__dma7_descr__active 1
4587#define R_IRQ_MASK2_RD__dma7_descr__inactive 0
4588#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
4589#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1
4590#define R_IRQ_MASK2_RD__dma6_eop__active 1
4591#define R_IRQ_MASK2_RD__dma6_eop__inactive 0
4592#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
4593#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1
4594#define R_IRQ_MASK2_RD__dma6_descr__active 1
4595#define R_IRQ_MASK2_RD__dma6_descr__inactive 0
4596#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
4597#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1
4598#define R_IRQ_MASK2_RD__dma5_eop__active 1
4599#define R_IRQ_MASK2_RD__dma5_eop__inactive 0
4600#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
4601#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1
4602#define R_IRQ_MASK2_RD__dma5_descr__active 1
4603#define R_IRQ_MASK2_RD__dma5_descr__inactive 0
4604#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
4605#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1
4606#define R_IRQ_MASK2_RD__dma4_eop__active 1
4607#define R_IRQ_MASK2_RD__dma4_eop__inactive 0
4608#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
4609#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1
4610#define R_IRQ_MASK2_RD__dma4_descr__active 1
4611#define R_IRQ_MASK2_RD__dma4_descr__inactive 0
4612#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
4613#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1
4614#define R_IRQ_MASK2_RD__dma3_eop__active 1
4615#define R_IRQ_MASK2_RD__dma3_eop__inactive 0
4616#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
4617#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1
4618#define R_IRQ_MASK2_RD__dma3_descr__active 1
4619#define R_IRQ_MASK2_RD__dma3_descr__inactive 0
4620#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
4621#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1
4622#define R_IRQ_MASK2_RD__dma2_eop__active 1
4623#define R_IRQ_MASK2_RD__dma2_eop__inactive 0
4624#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
4625#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1
4626#define R_IRQ_MASK2_RD__dma2_descr__active 1
4627#define R_IRQ_MASK2_RD__dma2_descr__inactive 0
4628#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
4629#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1
4630#define R_IRQ_MASK2_RD__dma1_eop__active 1
4631#define R_IRQ_MASK2_RD__dma1_eop__inactive 0
4632#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
4633#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1
4634#define R_IRQ_MASK2_RD__dma1_descr__active 1
4635#define R_IRQ_MASK2_RD__dma1_descr__inactive 0
4636#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
4637#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1
4638#define R_IRQ_MASK2_RD__dma0_eop__active 1
4639#define R_IRQ_MASK2_RD__dma0_eop__inactive 0
4640#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
4641#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1
4642#define R_IRQ_MASK2_RD__dma0_descr__active 1
4643#define R_IRQ_MASK2_RD__dma0_descr__inactive 0
4644
4645#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0)
4646#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
4647#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1
4648#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1
4649#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0
4650#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
4651#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1
4652#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1
4653#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0
4654#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
4655#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1
4656#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1
4657#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0
4658#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
4659#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1
4660#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1
4661#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0
4662#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
4663#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1
4664#define R_IRQ_MASK2_CLR__dma9_eop__clr 1
4665#define R_IRQ_MASK2_CLR__dma9_eop__nop 0
4666#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
4667#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1
4668#define R_IRQ_MASK2_CLR__dma9_descr__clr 1
4669#define R_IRQ_MASK2_CLR__dma9_descr__nop 0
4670#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
4671#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1
4672#define R_IRQ_MASK2_CLR__dma8_eop__clr 1
4673#define R_IRQ_MASK2_CLR__dma8_eop__nop 0
4674#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
4675#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1
4676#define R_IRQ_MASK2_CLR__dma8_descr__clr 1
4677#define R_IRQ_MASK2_CLR__dma8_descr__nop 0
4678#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
4679#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1
4680#define R_IRQ_MASK2_CLR__dma7_eop__clr 1
4681#define R_IRQ_MASK2_CLR__dma7_eop__nop 0
4682#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
4683#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1
4684#define R_IRQ_MASK2_CLR__dma7_descr__clr 1
4685#define R_IRQ_MASK2_CLR__dma7_descr__nop 0
4686#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
4687#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1
4688#define R_IRQ_MASK2_CLR__dma6_eop__clr 1
4689#define R_IRQ_MASK2_CLR__dma6_eop__nop 0
4690#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
4691#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1
4692#define R_IRQ_MASK2_CLR__dma6_descr__clr 1
4693#define R_IRQ_MASK2_CLR__dma6_descr__nop 0
4694#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
4695#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1
4696#define R_IRQ_MASK2_CLR__dma5_eop__clr 1
4697#define R_IRQ_MASK2_CLR__dma5_eop__nop 0
4698#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
4699#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1
4700#define R_IRQ_MASK2_CLR__dma5_descr__clr 1
4701#define R_IRQ_MASK2_CLR__dma5_descr__nop 0
4702#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
4703#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1
4704#define R_IRQ_MASK2_CLR__dma4_eop__clr 1
4705#define R_IRQ_MASK2_CLR__dma4_eop__nop 0
4706#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
4707#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1
4708#define R_IRQ_MASK2_CLR__dma4_descr__clr 1
4709#define R_IRQ_MASK2_CLR__dma4_descr__nop 0
4710#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
4711#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1
4712#define R_IRQ_MASK2_CLR__dma3_eop__clr 1
4713#define R_IRQ_MASK2_CLR__dma3_eop__nop 0
4714#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
4715#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1
4716#define R_IRQ_MASK2_CLR__dma3_descr__clr 1
4717#define R_IRQ_MASK2_CLR__dma3_descr__nop 0
4718#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
4719#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1
4720#define R_IRQ_MASK2_CLR__dma2_eop__clr 1
4721#define R_IRQ_MASK2_CLR__dma2_eop__nop 0
4722#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
4723#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1
4724#define R_IRQ_MASK2_CLR__dma2_descr__clr 1
4725#define R_IRQ_MASK2_CLR__dma2_descr__nop 0
4726#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
4727#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1
4728#define R_IRQ_MASK2_CLR__dma1_eop__clr 1
4729#define R_IRQ_MASK2_CLR__dma1_eop__nop 0
4730#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
4731#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1
4732#define R_IRQ_MASK2_CLR__dma1_descr__clr 1
4733#define R_IRQ_MASK2_CLR__dma1_descr__nop 0
4734#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
4735#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1
4736#define R_IRQ_MASK2_CLR__dma0_eop__clr 1
4737#define R_IRQ_MASK2_CLR__dma0_eop__nop 0
4738#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
4739#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1
4740#define R_IRQ_MASK2_CLR__dma0_descr__clr 1
4741#define R_IRQ_MASK2_CLR__dma0_descr__nop 0
4742
4743#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4)
4744#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
4745#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1
4746#define R_IRQ_READ2__dma8_sub3_descr__active 1
4747#define R_IRQ_READ2__dma8_sub3_descr__inactive 0
4748#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
4749#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1
4750#define R_IRQ_READ2__dma8_sub2_descr__active 1
4751#define R_IRQ_READ2__dma8_sub2_descr__inactive 0
4752#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
4753#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1
4754#define R_IRQ_READ2__dma8_sub1_descr__active 1
4755#define R_IRQ_READ2__dma8_sub1_descr__inactive 0
4756#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
4757#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1
4758#define R_IRQ_READ2__dma8_sub0_descr__active 1
4759#define R_IRQ_READ2__dma8_sub0_descr__inactive 0
4760#define R_IRQ_READ2__dma9_eop__BITNR 19
4761#define R_IRQ_READ2__dma9_eop__WIDTH 1
4762#define R_IRQ_READ2__dma9_eop__active 1
4763#define R_IRQ_READ2__dma9_eop__inactive 0
4764#define R_IRQ_READ2__dma9_descr__BITNR 18
4765#define R_IRQ_READ2__dma9_descr__WIDTH 1
4766#define R_IRQ_READ2__dma9_descr__active 1
4767#define R_IRQ_READ2__dma9_descr__inactive 0
4768#define R_IRQ_READ2__dma8_eop__BITNR 17
4769#define R_IRQ_READ2__dma8_eop__WIDTH 1
4770#define R_IRQ_READ2__dma8_eop__active 1
4771#define R_IRQ_READ2__dma8_eop__inactive 0
4772#define R_IRQ_READ2__dma8_descr__BITNR 16
4773#define R_IRQ_READ2__dma8_descr__WIDTH 1
4774#define R_IRQ_READ2__dma8_descr__active 1
4775#define R_IRQ_READ2__dma8_descr__inactive 0
4776#define R_IRQ_READ2__dma7_eop__BITNR 15
4777#define R_IRQ_READ2__dma7_eop__WIDTH 1
4778#define R_IRQ_READ2__dma7_eop__active 1
4779#define R_IRQ_READ2__dma7_eop__inactive 0
4780#define R_IRQ_READ2__dma7_descr__BITNR 14
4781#define R_IRQ_READ2__dma7_descr__WIDTH 1
4782#define R_IRQ_READ2__dma7_descr__active 1
4783#define R_IRQ_READ2__dma7_descr__inactive 0
4784#define R_IRQ_READ2__dma6_eop__BITNR 13
4785#define R_IRQ_READ2__dma6_eop__WIDTH 1
4786#define R_IRQ_READ2__dma6_eop__active 1
4787#define R_IRQ_READ2__dma6_eop__inactive 0
4788#define R_IRQ_READ2__dma6_descr__BITNR 12
4789#define R_IRQ_READ2__dma6_descr__WIDTH 1
4790#define R_IRQ_READ2__dma6_descr__active 1
4791#define R_IRQ_READ2__dma6_descr__inactive 0
4792#define R_IRQ_READ2__dma5_eop__BITNR 11
4793#define R_IRQ_READ2__dma5_eop__WIDTH 1
4794#define R_IRQ_READ2__dma5_eop__active 1
4795#define R_IRQ_READ2__dma5_eop__inactive 0
4796#define R_IRQ_READ2__dma5_descr__BITNR 10
4797#define R_IRQ_READ2__dma5_descr__WIDTH 1
4798#define R_IRQ_READ2__dma5_descr__active 1
4799#define R_IRQ_READ2__dma5_descr__inactive 0
4800#define R_IRQ_READ2__dma4_eop__BITNR 9
4801#define R_IRQ_READ2__dma4_eop__WIDTH 1
4802#define R_IRQ_READ2__dma4_eop__active 1
4803#define R_IRQ_READ2__dma4_eop__inactive 0
4804#define R_IRQ_READ2__dma4_descr__BITNR 8
4805#define R_IRQ_READ2__dma4_descr__WIDTH 1
4806#define R_IRQ_READ2__dma4_descr__active 1
4807#define R_IRQ_READ2__dma4_descr__inactive 0
4808#define R_IRQ_READ2__dma3_eop__BITNR 7
4809#define R_IRQ_READ2__dma3_eop__WIDTH 1
4810#define R_IRQ_READ2__dma3_eop__active 1
4811#define R_IRQ_READ2__dma3_eop__inactive 0
4812#define R_IRQ_READ2__dma3_descr__BITNR 6
4813#define R_IRQ_READ2__dma3_descr__WIDTH 1
4814#define R_IRQ_READ2__dma3_descr__active 1
4815#define R_IRQ_READ2__dma3_descr__inactive 0
4816#define R_IRQ_READ2__dma2_eop__BITNR 5
4817#define R_IRQ_READ2__dma2_eop__WIDTH 1
4818#define R_IRQ_READ2__dma2_eop__active 1
4819#define R_IRQ_READ2__dma2_eop__inactive 0
4820#define R_IRQ_READ2__dma2_descr__BITNR 4
4821#define R_IRQ_READ2__dma2_descr__WIDTH 1
4822#define R_IRQ_READ2__dma2_descr__active 1
4823#define R_IRQ_READ2__dma2_descr__inactive 0
4824#define R_IRQ_READ2__dma1_eop__BITNR 3
4825#define R_IRQ_READ2__dma1_eop__WIDTH 1
4826#define R_IRQ_READ2__dma1_eop__active 1
4827#define R_IRQ_READ2__dma1_eop__inactive 0
4828#define R_IRQ_READ2__dma1_descr__BITNR 2
4829#define R_IRQ_READ2__dma1_descr__WIDTH 1
4830#define R_IRQ_READ2__dma1_descr__active 1
4831#define R_IRQ_READ2__dma1_descr__inactive 0
4832#define R_IRQ_READ2__dma0_eop__BITNR 1
4833#define R_IRQ_READ2__dma0_eop__WIDTH 1
4834#define R_IRQ_READ2__dma0_eop__active 1
4835#define R_IRQ_READ2__dma0_eop__inactive 0
4836#define R_IRQ_READ2__dma0_descr__BITNR 0
4837#define R_IRQ_READ2__dma0_descr__WIDTH 1
4838#define R_IRQ_READ2__dma0_descr__active 1
4839#define R_IRQ_READ2__dma0_descr__inactive 0
4840
4841#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4)
4842#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
4843#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1
4844#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1
4845#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0
4846#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
4847#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1
4848#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1
4849#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0
4850#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
4851#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1
4852#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1
4853#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0
4854#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
4855#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1
4856#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1
4857#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0
4858#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
4859#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1
4860#define R_IRQ_MASK2_SET__dma9_eop__set 1
4861#define R_IRQ_MASK2_SET__dma9_eop__nop 0
4862#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
4863#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1
4864#define R_IRQ_MASK2_SET__dma9_descr__set 1
4865#define R_IRQ_MASK2_SET__dma9_descr__nop 0
4866#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
4867#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1
4868#define R_IRQ_MASK2_SET__dma8_eop__set 1
4869#define R_IRQ_MASK2_SET__dma8_eop__nop 0
4870#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
4871#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1
4872#define R_IRQ_MASK2_SET__dma8_descr__set 1
4873#define R_IRQ_MASK2_SET__dma8_descr__nop 0
4874#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
4875#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1
4876#define R_IRQ_MASK2_SET__dma7_eop__set 1
4877#define R_IRQ_MASK2_SET__dma7_eop__nop 0
4878#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
4879#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1
4880#define R_IRQ_MASK2_SET__dma7_descr__set 1
4881#define R_IRQ_MASK2_SET__dma7_descr__nop 0
4882#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
4883#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1
4884#define R_IRQ_MASK2_SET__dma6_eop__set 1
4885#define R_IRQ_MASK2_SET__dma6_eop__nop 0
4886#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
4887#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1
4888#define R_IRQ_MASK2_SET__dma6_descr__set 1
4889#define R_IRQ_MASK2_SET__dma6_descr__nop 0
4890#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
4891#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1
4892#define R_IRQ_MASK2_SET__dma5_eop__set 1
4893#define R_IRQ_MASK2_SET__dma5_eop__nop 0
4894#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
4895#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1
4896#define R_IRQ_MASK2_SET__dma5_descr__set 1
4897#define R_IRQ_MASK2_SET__dma5_descr__nop 0
4898#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
4899#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1
4900#define R_IRQ_MASK2_SET__dma4_eop__set 1
4901#define R_IRQ_MASK2_SET__dma4_eop__nop 0
4902#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
4903#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1
4904#define R_IRQ_MASK2_SET__dma4_descr__set 1
4905#define R_IRQ_MASK2_SET__dma4_descr__nop 0
4906#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
4907#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1
4908#define R_IRQ_MASK2_SET__dma3_eop__set 1
4909#define R_IRQ_MASK2_SET__dma3_eop__nop 0
4910#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
4911#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1
4912#define R_IRQ_MASK2_SET__dma3_descr__set 1
4913#define R_IRQ_MASK2_SET__dma3_descr__nop 0
4914#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
4915#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1
4916#define R_IRQ_MASK2_SET__dma2_eop__set 1
4917#define R_IRQ_MASK2_SET__dma2_eop__nop 0
4918#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
4919#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1
4920#define R_IRQ_MASK2_SET__dma2_descr__set 1
4921#define R_IRQ_MASK2_SET__dma2_descr__nop 0
4922#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
4923#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1
4924#define R_IRQ_MASK2_SET__dma1_eop__set 1
4925#define R_IRQ_MASK2_SET__dma1_eop__nop 0
4926#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
4927#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1
4928#define R_IRQ_MASK2_SET__dma1_descr__set 1
4929#define R_IRQ_MASK2_SET__dma1_descr__nop 0
4930#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
4931#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1
4932#define R_IRQ_MASK2_SET__dma0_eop__set 1
4933#define R_IRQ_MASK2_SET__dma0_eop__nop 0
4934#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
4935#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1
4936#define R_IRQ_MASK2_SET__dma0_descr__set 1
4937#define R_IRQ_MASK2_SET__dma0_descr__nop 0
4938
4939#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8)
4940#define R_VECT_MASK_RD__usb__BITNR 31
4941#define R_VECT_MASK_RD__usb__WIDTH 1
4942#define R_VECT_MASK_RD__usb__active 1
4943#define R_VECT_MASK_RD__usb__inactive 0
4944#define R_VECT_MASK_RD__dma9__BITNR 25
4945#define R_VECT_MASK_RD__dma9__WIDTH 1
4946#define R_VECT_MASK_RD__dma9__active 1
4947#define R_VECT_MASK_RD__dma9__inactive 0
4948#define R_VECT_MASK_RD__dma8__BITNR 24
4949#define R_VECT_MASK_RD__dma8__WIDTH 1
4950#define R_VECT_MASK_RD__dma8__active 1
4951#define R_VECT_MASK_RD__dma8__inactive 0
4952#define R_VECT_MASK_RD__dma7__BITNR 23
4953#define R_VECT_MASK_RD__dma7__WIDTH 1
4954#define R_VECT_MASK_RD__dma7__active 1
4955#define R_VECT_MASK_RD__dma7__inactive 0
4956#define R_VECT_MASK_RD__dma6__BITNR 22
4957#define R_VECT_MASK_RD__dma6__WIDTH 1
4958#define R_VECT_MASK_RD__dma6__active 1
4959#define R_VECT_MASK_RD__dma6__inactive 0
4960#define R_VECT_MASK_RD__dma5__BITNR 21
4961#define R_VECT_MASK_RD__dma5__WIDTH 1
4962#define R_VECT_MASK_RD__dma5__active 1
4963#define R_VECT_MASK_RD__dma5__inactive 0
4964#define R_VECT_MASK_RD__dma4__BITNR 20
4965#define R_VECT_MASK_RD__dma4__WIDTH 1
4966#define R_VECT_MASK_RD__dma4__active 1
4967#define R_VECT_MASK_RD__dma4__inactive 0
4968#define R_VECT_MASK_RD__dma3__BITNR 19
4969#define R_VECT_MASK_RD__dma3__WIDTH 1
4970#define R_VECT_MASK_RD__dma3__active 1
4971#define R_VECT_MASK_RD__dma3__inactive 0
4972#define R_VECT_MASK_RD__dma2__BITNR 18
4973#define R_VECT_MASK_RD__dma2__WIDTH 1
4974#define R_VECT_MASK_RD__dma2__active 1
4975#define R_VECT_MASK_RD__dma2__inactive 0
4976#define R_VECT_MASK_RD__dma1__BITNR 17
4977#define R_VECT_MASK_RD__dma1__WIDTH 1
4978#define R_VECT_MASK_RD__dma1__active 1
4979#define R_VECT_MASK_RD__dma1__inactive 0
4980#define R_VECT_MASK_RD__dma0__BITNR 16
4981#define R_VECT_MASK_RD__dma0__WIDTH 1
4982#define R_VECT_MASK_RD__dma0__active 1
4983#define R_VECT_MASK_RD__dma0__inactive 0
4984#define R_VECT_MASK_RD__ext_dma1__BITNR 13
4985#define R_VECT_MASK_RD__ext_dma1__WIDTH 1
4986#define R_VECT_MASK_RD__ext_dma1__active 1
4987#define R_VECT_MASK_RD__ext_dma1__inactive 0
4988#define R_VECT_MASK_RD__ext_dma0__BITNR 12
4989#define R_VECT_MASK_RD__ext_dma0__WIDTH 1
4990#define R_VECT_MASK_RD__ext_dma0__active 1
4991#define R_VECT_MASK_RD__ext_dma0__inactive 0
4992#define R_VECT_MASK_RD__pa__BITNR 11
4993#define R_VECT_MASK_RD__pa__WIDTH 1
4994#define R_VECT_MASK_RD__pa__active 1
4995#define R_VECT_MASK_RD__pa__inactive 0
4996#define R_VECT_MASK_RD__irq_intnr__BITNR 10
4997#define R_VECT_MASK_RD__irq_intnr__WIDTH 1
4998#define R_VECT_MASK_RD__irq_intnr__active 1
4999#define R_VECT_MASK_RD__irq_intnr__inactive 0
5000#define R_VECT_MASK_RD__sw__BITNR 9
5001#define R_VECT_MASK_RD__sw__WIDTH 1
5002#define R_VECT_MASK_RD__sw__active 1
5003#define R_VECT_MASK_RD__sw__inactive 0
5004#define R_VECT_MASK_RD__serial__BITNR 8
5005#define R_VECT_MASK_RD__serial__WIDTH 1
5006#define R_VECT_MASK_RD__serial__active 1
5007#define R_VECT_MASK_RD__serial__inactive 0
5008#define R_VECT_MASK_RD__snmp__BITNR 7
5009#define R_VECT_MASK_RD__snmp__WIDTH 1
5010#define R_VECT_MASK_RD__snmp__active 1
5011#define R_VECT_MASK_RD__snmp__inactive 0
5012#define R_VECT_MASK_RD__network__BITNR 6
5013#define R_VECT_MASK_RD__network__WIDTH 1
5014#define R_VECT_MASK_RD__network__active 1
5015#define R_VECT_MASK_RD__network__inactive 0
5016#define R_VECT_MASK_RD__scsi1__BITNR 5
5017#define R_VECT_MASK_RD__scsi1__WIDTH 1
5018#define R_VECT_MASK_RD__scsi1__active 1
5019#define R_VECT_MASK_RD__scsi1__inactive 0
5020#define R_VECT_MASK_RD__par1__BITNR 5
5021#define R_VECT_MASK_RD__par1__WIDTH 1
5022#define R_VECT_MASK_RD__par1__active 1
5023#define R_VECT_MASK_RD__par1__inactive 0
5024#define R_VECT_MASK_RD__scsi0__BITNR 4
5025#define R_VECT_MASK_RD__scsi0__WIDTH 1
5026#define R_VECT_MASK_RD__scsi0__active 1
5027#define R_VECT_MASK_RD__scsi0__inactive 0
5028#define R_VECT_MASK_RD__par0__BITNR 4
5029#define R_VECT_MASK_RD__par0__WIDTH 1
5030#define R_VECT_MASK_RD__par0__active 1
5031#define R_VECT_MASK_RD__par0__inactive 0
5032#define R_VECT_MASK_RD__ata__BITNR 4
5033#define R_VECT_MASK_RD__ata__WIDTH 1
5034#define R_VECT_MASK_RD__ata__active 1
5035#define R_VECT_MASK_RD__ata__inactive 0
5036#define R_VECT_MASK_RD__mio__BITNR 4
5037#define R_VECT_MASK_RD__mio__WIDTH 1
5038#define R_VECT_MASK_RD__mio__active 1
5039#define R_VECT_MASK_RD__mio__inactive 0
5040#define R_VECT_MASK_RD__timer1__BITNR 3
5041#define R_VECT_MASK_RD__timer1__WIDTH 1
5042#define R_VECT_MASK_RD__timer1__active 1
5043#define R_VECT_MASK_RD__timer1__inactive 0
5044#define R_VECT_MASK_RD__timer0__BITNR 2
5045#define R_VECT_MASK_RD__timer0__WIDTH 1
5046#define R_VECT_MASK_RD__timer0__active 1
5047#define R_VECT_MASK_RD__timer0__inactive 0
5048#define R_VECT_MASK_RD__nmi__BITNR 1
5049#define R_VECT_MASK_RD__nmi__WIDTH 1
5050#define R_VECT_MASK_RD__nmi__active 1
5051#define R_VECT_MASK_RD__nmi__inactive 0
5052#define R_VECT_MASK_RD__some__BITNR 0
5053#define R_VECT_MASK_RD__some__WIDTH 1
5054#define R_VECT_MASK_RD__some__active 1
5055#define R_VECT_MASK_RD__some__inactive 0
5056
5057#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8)
5058#define R_VECT_MASK_CLR__usb__BITNR 31
5059#define R_VECT_MASK_CLR__usb__WIDTH 1
5060#define R_VECT_MASK_CLR__usb__clr 1
5061#define R_VECT_MASK_CLR__usb__nop 0
5062#define R_VECT_MASK_CLR__dma9__BITNR 25
5063#define R_VECT_MASK_CLR__dma9__WIDTH 1
5064#define R_VECT_MASK_CLR__dma9__clr 1
5065#define R_VECT_MASK_CLR__dma9__nop 0
5066#define R_VECT_MASK_CLR__dma8__BITNR 24
5067#define R_VECT_MASK_CLR__dma8__WIDTH 1
5068#define R_VECT_MASK_CLR__dma8__clr 1
5069#define R_VECT_MASK_CLR__dma8__nop 0
5070#define R_VECT_MASK_CLR__dma7__BITNR 23
5071#define R_VECT_MASK_CLR__dma7__WIDTH 1
5072#define R_VECT_MASK_CLR__dma7__clr 1
5073#define R_VECT_MASK_CLR__dma7__nop 0
5074#define R_VECT_MASK_CLR__dma6__BITNR 22
5075#define R_VECT_MASK_CLR__dma6__WIDTH 1
5076#define R_VECT_MASK_CLR__dma6__clr 1
5077#define R_VECT_MASK_CLR__dma6__nop 0
5078#define R_VECT_MASK_CLR__dma5__BITNR 21
5079#define R_VECT_MASK_CLR__dma5__WIDTH 1
5080#define R_VECT_MASK_CLR__dma5__clr 1
5081#define R_VECT_MASK_CLR__dma5__nop 0
5082#define R_VECT_MASK_CLR__dma4__BITNR 20
5083#define R_VECT_MASK_CLR__dma4__WIDTH 1
5084#define R_VECT_MASK_CLR__dma4__clr 1
5085#define R_VECT_MASK_CLR__dma4__nop 0
5086#define R_VECT_MASK_CLR__dma3__BITNR 19
5087#define R_VECT_MASK_CLR__dma3__WIDTH 1
5088#define R_VECT_MASK_CLR__dma3__clr 1
5089#define R_VECT_MASK_CLR__dma3__nop 0
5090#define R_VECT_MASK_CLR__dma2__BITNR 18
5091#define R_VECT_MASK_CLR__dma2__WIDTH 1
5092#define R_VECT_MASK_CLR__dma2__clr 1
5093#define R_VECT_MASK_CLR__dma2__nop 0
5094#define R_VECT_MASK_CLR__dma1__BITNR 17
5095#define R_VECT_MASK_CLR__dma1__WIDTH 1
5096#define R_VECT_MASK_CLR__dma1__clr 1
5097#define R_VECT_MASK_CLR__dma1__nop 0
5098#define R_VECT_MASK_CLR__dma0__BITNR 16
5099#define R_VECT_MASK_CLR__dma0__WIDTH 1
5100#define R_VECT_MASK_CLR__dma0__clr 1
5101#define R_VECT_MASK_CLR__dma0__nop 0
5102#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
5103#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1
5104#define R_VECT_MASK_CLR__ext_dma1__clr 1
5105#define R_VECT_MASK_CLR__ext_dma1__nop 0
5106#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
5107#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1
5108#define R_VECT_MASK_CLR__ext_dma0__clr 1
5109#define R_VECT_MASK_CLR__ext_dma0__nop 0
5110#define R_VECT_MASK_CLR__pa__BITNR 11
5111#define R_VECT_MASK_CLR__pa__WIDTH 1
5112#define R_VECT_MASK_CLR__pa__clr 1
5113#define R_VECT_MASK_CLR__pa__nop 0
5114#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
5115#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1
5116#define R_VECT_MASK_CLR__irq_intnr__clr 1
5117#define R_VECT_MASK_CLR__irq_intnr__nop 0
5118#define R_VECT_MASK_CLR__sw__BITNR 9
5119#define R_VECT_MASK_CLR__sw__WIDTH 1
5120#define R_VECT_MASK_CLR__sw__clr 1
5121#define R_VECT_MASK_CLR__sw__nop 0
5122#define R_VECT_MASK_CLR__serial__BITNR 8
5123#define R_VECT_MASK_CLR__serial__WIDTH 1
5124#define R_VECT_MASK_CLR__serial__clr 1
5125#define R_VECT_MASK_CLR__serial__nop 0
5126#define R_VECT_MASK_CLR__snmp__BITNR 7
5127#define R_VECT_MASK_CLR__snmp__WIDTH 1
5128#define R_VECT_MASK_CLR__snmp__clr 1
5129#define R_VECT_MASK_CLR__snmp__nop 0
5130#define R_VECT_MASK_CLR__network__BITNR 6
5131#define R_VECT_MASK_CLR__network__WIDTH 1
5132#define R_VECT_MASK_CLR__network__clr 1
5133#define R_VECT_MASK_CLR__network__nop 0
5134#define R_VECT_MASK_CLR__scsi1__BITNR 5
5135#define R_VECT_MASK_CLR__scsi1__WIDTH 1
5136#define R_VECT_MASK_CLR__scsi1__clr 1
5137#define R_VECT_MASK_CLR__scsi1__nop 0
5138#define R_VECT_MASK_CLR__par1__BITNR 5
5139#define R_VECT_MASK_CLR__par1__WIDTH 1
5140#define R_VECT_MASK_CLR__par1__clr 1
5141#define R_VECT_MASK_CLR__par1__nop 0
5142#define R_VECT_MASK_CLR__scsi0__BITNR 4
5143#define R_VECT_MASK_CLR__scsi0__WIDTH 1
5144#define R_VECT_MASK_CLR__scsi0__clr 1
5145#define R_VECT_MASK_CLR__scsi0__nop 0
5146#define R_VECT_MASK_CLR__par0__BITNR 4
5147#define R_VECT_MASK_CLR__par0__WIDTH 1
5148#define R_VECT_MASK_CLR__par0__clr 1
5149#define R_VECT_MASK_CLR__par0__nop 0
5150#define R_VECT_MASK_CLR__ata__BITNR 4
5151#define R_VECT_MASK_CLR__ata__WIDTH 1
5152#define R_VECT_MASK_CLR__ata__clr 1
5153#define R_VECT_MASK_CLR__ata__nop 0
5154#define R_VECT_MASK_CLR__mio__BITNR 4
5155#define R_VECT_MASK_CLR__mio__WIDTH 1
5156#define R_VECT_MASK_CLR__mio__clr 1
5157#define R_VECT_MASK_CLR__mio__nop 0
5158#define R_VECT_MASK_CLR__timer1__BITNR 3
5159#define R_VECT_MASK_CLR__timer1__WIDTH 1
5160#define R_VECT_MASK_CLR__timer1__clr 1
5161#define R_VECT_MASK_CLR__timer1__nop 0
5162#define R_VECT_MASK_CLR__timer0__BITNR 2
5163#define R_VECT_MASK_CLR__timer0__WIDTH 1
5164#define R_VECT_MASK_CLR__timer0__clr 1
5165#define R_VECT_MASK_CLR__timer0__nop 0
5166#define R_VECT_MASK_CLR__nmi__BITNR 1
5167#define R_VECT_MASK_CLR__nmi__WIDTH 1
5168#define R_VECT_MASK_CLR__nmi__clr 1
5169#define R_VECT_MASK_CLR__nmi__nop 0
5170#define R_VECT_MASK_CLR__some__BITNR 0
5171#define R_VECT_MASK_CLR__some__WIDTH 1
5172#define R_VECT_MASK_CLR__some__clr 1
5173#define R_VECT_MASK_CLR__some__nop 0
5174
5175#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc)
5176#define R_VECT_READ__usb__BITNR 31
5177#define R_VECT_READ__usb__WIDTH 1
5178#define R_VECT_READ__usb__active 1
5179#define R_VECT_READ__usb__inactive 0
5180#define R_VECT_READ__dma9__BITNR 25
5181#define R_VECT_READ__dma9__WIDTH 1
5182#define R_VECT_READ__dma9__active 1
5183#define R_VECT_READ__dma9__inactive 0
5184#define R_VECT_READ__dma8__BITNR 24
5185#define R_VECT_READ__dma8__WIDTH 1
5186#define R_VECT_READ__dma8__active 1
5187#define R_VECT_READ__dma8__inactive 0
5188#define R_VECT_READ__dma7__BITNR 23
5189#define R_VECT_READ__dma7__WIDTH 1
5190#define R_VECT_READ__dma7__active 1
5191#define R_VECT_READ__dma7__inactive 0
5192#define R_VECT_READ__dma6__BITNR 22
5193#define R_VECT_READ__dma6__WIDTH 1
5194#define R_VECT_READ__dma6__active 1
5195#define R_VECT_READ__dma6__inactive 0
5196#define R_VECT_READ__dma5__BITNR 21
5197#define R_VECT_READ__dma5__WIDTH 1
5198#define R_VECT_READ__dma5__active 1
5199#define R_VECT_READ__dma5__inactive 0
5200#define R_VECT_READ__dma4__BITNR 20
5201#define R_VECT_READ__dma4__WIDTH 1
5202#define R_VECT_READ__dma4__active 1
5203#define R_VECT_READ__dma4__inactive 0
5204#define R_VECT_READ__dma3__BITNR 19
5205#define R_VECT_READ__dma3__WIDTH 1
5206#define R_VECT_READ__dma3__active 1
5207#define R_VECT_READ__dma3__inactive 0
5208#define R_VECT_READ__dma2__BITNR 18
5209#define R_VECT_READ__dma2__WIDTH 1
5210#define R_VECT_READ__dma2__active 1
5211#define R_VECT_READ__dma2__inactive 0
5212#define R_VECT_READ__dma1__BITNR 17
5213#define R_VECT_READ__dma1__WIDTH 1
5214#define R_VECT_READ__dma1__active 1
5215#define R_VECT_READ__dma1__inactive 0
5216#define R_VECT_READ__dma0__BITNR 16
5217#define R_VECT_READ__dma0__WIDTH 1
5218#define R_VECT_READ__dma0__active 1
5219#define R_VECT_READ__dma0__inactive 0
5220#define R_VECT_READ__ext_dma1__BITNR 13
5221#define R_VECT_READ__ext_dma1__WIDTH 1
5222#define R_VECT_READ__ext_dma1__active 1
5223#define R_VECT_READ__ext_dma1__inactive 0
5224#define R_VECT_READ__ext_dma0__BITNR 12
5225#define R_VECT_READ__ext_dma0__WIDTH 1
5226#define R_VECT_READ__ext_dma0__active 1
5227#define R_VECT_READ__ext_dma0__inactive 0
5228#define R_VECT_READ__pa__BITNR 11
5229#define R_VECT_READ__pa__WIDTH 1
5230#define R_VECT_READ__pa__active 1
5231#define R_VECT_READ__pa__inactive 0
5232#define R_VECT_READ__irq_intnr__BITNR 10
5233#define R_VECT_READ__irq_intnr__WIDTH 1
5234#define R_VECT_READ__irq_intnr__active 1
5235#define R_VECT_READ__irq_intnr__inactive 0
5236#define R_VECT_READ__sw__BITNR 9
5237#define R_VECT_READ__sw__WIDTH 1
5238#define R_VECT_READ__sw__active 1
5239#define R_VECT_READ__sw__inactive 0
5240#define R_VECT_READ__serial__BITNR 8
5241#define R_VECT_READ__serial__WIDTH 1
5242#define R_VECT_READ__serial__active 1
5243#define R_VECT_READ__serial__inactive 0
5244#define R_VECT_READ__snmp__BITNR 7
5245#define R_VECT_READ__snmp__WIDTH 1
5246#define R_VECT_READ__snmp__active 1
5247#define R_VECT_READ__snmp__inactive 0
5248#define R_VECT_READ__network__BITNR 6
5249#define R_VECT_READ__network__WIDTH 1
5250#define R_VECT_READ__network__active 1
5251#define R_VECT_READ__network__inactive 0
5252#define R_VECT_READ__scsi1__BITNR 5
5253#define R_VECT_READ__scsi1__WIDTH 1
5254#define R_VECT_READ__scsi1__active 1
5255#define R_VECT_READ__scsi1__inactive 0
5256#define R_VECT_READ__par1__BITNR 5
5257#define R_VECT_READ__par1__WIDTH 1
5258#define R_VECT_READ__par1__active 1
5259#define R_VECT_READ__par1__inactive 0
5260#define R_VECT_READ__scsi0__BITNR 4
5261#define R_VECT_READ__scsi0__WIDTH 1
5262#define R_VECT_READ__scsi0__active 1
5263#define R_VECT_READ__scsi0__inactive 0
5264#define R_VECT_READ__par0__BITNR 4
5265#define R_VECT_READ__par0__WIDTH 1
5266#define R_VECT_READ__par0__active 1
5267#define R_VECT_READ__par0__inactive 0
5268#define R_VECT_READ__ata__BITNR 4
5269#define R_VECT_READ__ata__WIDTH 1
5270#define R_VECT_READ__ata__active 1
5271#define R_VECT_READ__ata__inactive 0
5272#define R_VECT_READ__mio__BITNR 4
5273#define R_VECT_READ__mio__WIDTH 1
5274#define R_VECT_READ__mio__active 1
5275#define R_VECT_READ__mio__inactive 0
5276#define R_VECT_READ__timer1__BITNR 3
5277#define R_VECT_READ__timer1__WIDTH 1
5278#define R_VECT_READ__timer1__active 1
5279#define R_VECT_READ__timer1__inactive 0
5280#define R_VECT_READ__timer0__BITNR 2
5281#define R_VECT_READ__timer0__WIDTH 1
5282#define R_VECT_READ__timer0__active 1
5283#define R_VECT_READ__timer0__inactive 0
5284#define R_VECT_READ__nmi__BITNR 1
5285#define R_VECT_READ__nmi__WIDTH 1
5286#define R_VECT_READ__nmi__active 1
5287#define R_VECT_READ__nmi__inactive 0
5288#define R_VECT_READ__some__BITNR 0
5289#define R_VECT_READ__some__WIDTH 1
5290#define R_VECT_READ__some__active 1
5291#define R_VECT_READ__some__inactive 0
5292
5293#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc)
5294#define R_VECT_MASK_SET__usb__BITNR 31
5295#define R_VECT_MASK_SET__usb__WIDTH 1
5296#define R_VECT_MASK_SET__usb__set 1
5297#define R_VECT_MASK_SET__usb__nop 0
5298#define R_VECT_MASK_SET__dma9__BITNR 25
5299#define R_VECT_MASK_SET__dma9__WIDTH 1
5300#define R_VECT_MASK_SET__dma9__set 1
5301#define R_VECT_MASK_SET__dma9__nop 0
5302#define R_VECT_MASK_SET__dma8__BITNR 24
5303#define R_VECT_MASK_SET__dma8__WIDTH 1
5304#define R_VECT_MASK_SET__dma8__set 1
5305#define R_VECT_MASK_SET__dma8__nop 0
5306#define R_VECT_MASK_SET__dma7__BITNR 23
5307#define R_VECT_MASK_SET__dma7__WIDTH 1
5308#define R_VECT_MASK_SET__dma7__set 1
5309#define R_VECT_MASK_SET__dma7__nop 0
5310#define R_VECT_MASK_SET__dma6__BITNR 22
5311#define R_VECT_MASK_SET__dma6__WIDTH 1
5312#define R_VECT_MASK_SET__dma6__set 1
5313#define R_VECT_MASK_SET__dma6__nop 0
5314#define R_VECT_MASK_SET__dma5__BITNR 21
5315#define R_VECT_MASK_SET__dma5__WIDTH 1
5316#define R_VECT_MASK_SET__dma5__set 1
5317#define R_VECT_MASK_SET__dma5__nop 0
5318#define R_VECT_MASK_SET__dma4__BITNR 20
5319#define R_VECT_MASK_SET__dma4__WIDTH 1
5320#define R_VECT_MASK_SET__dma4__set 1
5321#define R_VECT_MASK_SET__dma4__nop 0
5322#define R_VECT_MASK_SET__dma3__BITNR 19
5323#define R_VECT_MASK_SET__dma3__WIDTH 1
5324#define R_VECT_MASK_SET__dma3__set 1
5325#define R_VECT_MASK_SET__dma3__nop 0
5326#define R_VECT_MASK_SET__dma2__BITNR 18
5327#define R_VECT_MASK_SET__dma2__WIDTH 1
5328#define R_VECT_MASK_SET__dma2__set 1
5329#define R_VECT_MASK_SET__dma2__nop 0
5330#define R_VECT_MASK_SET__dma1__BITNR 17
5331#define R_VECT_MASK_SET__dma1__WIDTH 1
5332#define R_VECT_MASK_SET__dma1__set 1
5333#define R_VECT_MASK_SET__dma1__nop 0
5334#define R_VECT_MASK_SET__dma0__BITNR 16
5335#define R_VECT_MASK_SET__dma0__WIDTH 1
5336#define R_VECT_MASK_SET__dma0__set 1
5337#define R_VECT_MASK_SET__dma0__nop 0
5338#define R_VECT_MASK_SET__ext_dma1__BITNR 13
5339#define R_VECT_MASK_SET__ext_dma1__WIDTH 1
5340#define R_VECT_MASK_SET__ext_dma1__set 1
5341#define R_VECT_MASK_SET__ext_dma1__nop 0
5342#define R_VECT_MASK_SET__ext_dma0__BITNR 12
5343#define R_VECT_MASK_SET__ext_dma0__WIDTH 1
5344#define R_VECT_MASK_SET__ext_dma0__set 1
5345#define R_VECT_MASK_SET__ext_dma0__nop 0
5346#define R_VECT_MASK_SET__pa__BITNR 11
5347#define R_VECT_MASK_SET__pa__WIDTH 1
5348#define R_VECT_MASK_SET__pa__set 1
5349#define R_VECT_MASK_SET__pa__nop 0
5350#define R_VECT_MASK_SET__irq_intnr__BITNR 10
5351#define R_VECT_MASK_SET__irq_intnr__WIDTH 1
5352#define R_VECT_MASK_SET__irq_intnr__set 1
5353#define R_VECT_MASK_SET__irq_intnr__nop 0
5354#define R_VECT_MASK_SET__sw__BITNR 9
5355#define R_VECT_MASK_SET__sw__WIDTH 1
5356#define R_VECT_MASK_SET__sw__set 1
5357#define R_VECT_MASK_SET__sw__nop 0
5358#define R_VECT_MASK_SET__serial__BITNR 8
5359#define R_VECT_MASK_SET__serial__WIDTH 1
5360#define R_VECT_MASK_SET__serial__set 1
5361#define R_VECT_MASK_SET__serial__nop 0
5362#define R_VECT_MASK_SET__snmp__BITNR 7
5363#define R_VECT_MASK_SET__snmp__WIDTH 1
5364#define R_VECT_MASK_SET__snmp__set 1
5365#define R_VECT_MASK_SET__snmp__nop 0
5366#define R_VECT_MASK_SET__network__BITNR 6
5367#define R_VECT_MASK_SET__network__WIDTH 1
5368#define R_VECT_MASK_SET__network__set 1
5369#define R_VECT_MASK_SET__network__nop 0
5370#define R_VECT_MASK_SET__scsi1__BITNR 5
5371#define R_VECT_MASK_SET__scsi1__WIDTH 1
5372#define R_VECT_MASK_SET__scsi1__set 1
5373#define R_VECT_MASK_SET__scsi1__nop 0
5374#define R_VECT_MASK_SET__par1__BITNR 5
5375#define R_VECT_MASK_SET__par1__WIDTH 1
5376#define R_VECT_MASK_SET__par1__set 1
5377#define R_VECT_MASK_SET__par1__nop 0
5378#define R_VECT_MASK_SET__scsi0__BITNR 4
5379#define R_VECT_MASK_SET__scsi0__WIDTH 1
5380#define R_VECT_MASK_SET__scsi0__set 1
5381#define R_VECT_MASK_SET__scsi0__nop 0
5382#define R_VECT_MASK_SET__par0__BITNR 4
5383#define R_VECT_MASK_SET__par0__WIDTH 1
5384#define R_VECT_MASK_SET__par0__set 1
5385#define R_VECT_MASK_SET__par0__nop 0
5386#define R_VECT_MASK_SET__ata__BITNR 4
5387#define R_VECT_MASK_SET__ata__WIDTH 1
5388#define R_VECT_MASK_SET__ata__set 1
5389#define R_VECT_MASK_SET__ata__nop 0
5390#define R_VECT_MASK_SET__mio__BITNR 4
5391#define R_VECT_MASK_SET__mio__WIDTH 1
5392#define R_VECT_MASK_SET__mio__set 1
5393#define R_VECT_MASK_SET__mio__nop 0
5394#define R_VECT_MASK_SET__timer1__BITNR 3
5395#define R_VECT_MASK_SET__timer1__WIDTH 1
5396#define R_VECT_MASK_SET__timer1__set 1
5397#define R_VECT_MASK_SET__timer1__nop 0
5398#define R_VECT_MASK_SET__timer0__BITNR 2
5399#define R_VECT_MASK_SET__timer0__WIDTH 1
5400#define R_VECT_MASK_SET__timer0__set 1
5401#define R_VECT_MASK_SET__timer0__nop 0
5402#define R_VECT_MASK_SET__nmi__BITNR 1
5403#define R_VECT_MASK_SET__nmi__WIDTH 1
5404#define R_VECT_MASK_SET__nmi__set 1
5405#define R_VECT_MASK_SET__nmi__nop 0
5406#define R_VECT_MASK_SET__some__BITNR 0
5407#define R_VECT_MASK_SET__some__WIDTH 1
5408#define R_VECT_MASK_SET__some__set 1
5409#define R_VECT_MASK_SET__some__nop 0
5410
5411/*
5412!* DMA registers
5413!*/
5414
5415#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c)
5416#define R_SET_EOP__ch9_eop__BITNR 3
5417#define R_SET_EOP__ch9_eop__WIDTH 1
5418#define R_SET_EOP__ch9_eop__set 1
5419#define R_SET_EOP__ch9_eop__nop 0
5420#define R_SET_EOP__ch7_eop__BITNR 2
5421#define R_SET_EOP__ch7_eop__WIDTH 1
5422#define R_SET_EOP__ch7_eop__set 1
5423#define R_SET_EOP__ch7_eop__nop 0
5424#define R_SET_EOP__ch5_eop__BITNR 1
5425#define R_SET_EOP__ch5_eop__WIDTH 1
5426#define R_SET_EOP__ch5_eop__set 1
5427#define R_SET_EOP__ch5_eop__nop 0
5428#define R_SET_EOP__ch3_eop__BITNR 0
5429#define R_SET_EOP__ch3_eop__WIDTH 1
5430#define R_SET_EOP__ch3_eop__set 1
5431#define R_SET_EOP__ch3_eop__nop 0
5432
5433#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100)
5434#define R_DMA_CH0_HWSW__hw__BITNR 16
5435#define R_DMA_CH0_HWSW__hw__WIDTH 16
5436#define R_DMA_CH0_HWSW__sw__BITNR 0
5437#define R_DMA_CH0_HWSW__sw__WIDTH 16
5438
5439#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c)
5440#define R_DMA_CH0_DESCR__descr__BITNR 0
5441#define R_DMA_CH0_DESCR__descr__WIDTH 32
5442
5443#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104)
5444#define R_DMA_CH0_NEXT__next__BITNR 0
5445#define R_DMA_CH0_NEXT__next__WIDTH 32
5446
5447#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108)
5448#define R_DMA_CH0_BUF__buf__BITNR 0
5449#define R_DMA_CH0_BUF__buf__WIDTH 32
5450
5451#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0)
5452#define R_DMA_CH0_FIRST__first__BITNR 0
5453#define R_DMA_CH0_FIRST__first__WIDTH 32
5454
5455#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0)
5456#define R_DMA_CH0_CMD__cmd__BITNR 0
5457#define R_DMA_CH0_CMD__cmd__WIDTH 3
5458#define R_DMA_CH0_CMD__cmd__hold 0
5459#define R_DMA_CH0_CMD__cmd__start 1
5460#define R_DMA_CH0_CMD__cmd__restart 3
5461#define R_DMA_CH0_CMD__cmd__continue 3
5462#define R_DMA_CH0_CMD__cmd__reset 4
5463
5464#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1)
5465#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
5466#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1
5467#define R_DMA_CH0_CLR_INTR__clr_eop__do 1
5468#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0
5469#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
5470#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1
5471#define R_DMA_CH0_CLR_INTR__clr_descr__do 1
5472#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0
5473
5474#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2)
5475#define R_DMA_CH0_STATUS__avail__BITNR 0
5476#define R_DMA_CH0_STATUS__avail__WIDTH 7
5477
5478#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110)
5479#define R_DMA_CH1_HWSW__hw__BITNR 16
5480#define R_DMA_CH1_HWSW__hw__WIDTH 16
5481#define R_DMA_CH1_HWSW__sw__BITNR 0
5482#define R_DMA_CH1_HWSW__sw__WIDTH 16
5483
5484#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c)
5485#define R_DMA_CH1_DESCR__descr__BITNR 0
5486#define R_DMA_CH1_DESCR__descr__WIDTH 32
5487
5488#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114)
5489#define R_DMA_CH1_NEXT__next__BITNR 0
5490#define R_DMA_CH1_NEXT__next__WIDTH 32
5491
5492#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118)
5493#define R_DMA_CH1_BUF__buf__BITNR 0
5494#define R_DMA_CH1_BUF__buf__WIDTH 32
5495
5496#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4)
5497#define R_DMA_CH1_FIRST__first__BITNR 0
5498#define R_DMA_CH1_FIRST__first__WIDTH 32
5499
5500#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4)
5501#define R_DMA_CH1_CMD__cmd__BITNR 0
5502#define R_DMA_CH1_CMD__cmd__WIDTH 3
5503#define R_DMA_CH1_CMD__cmd__hold 0
5504#define R_DMA_CH1_CMD__cmd__start 1
5505#define R_DMA_CH1_CMD__cmd__restart 3
5506#define R_DMA_CH1_CMD__cmd__continue 3
5507#define R_DMA_CH1_CMD__cmd__reset 4
5508
5509#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5)
5510#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
5511#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1
5512#define R_DMA_CH1_CLR_INTR__clr_eop__do 1
5513#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0
5514#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
5515#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1
5516#define R_DMA_CH1_CLR_INTR__clr_descr__do 1
5517#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0
5518
5519#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6)
5520#define R_DMA_CH1_STATUS__avail__BITNR 0
5521#define R_DMA_CH1_STATUS__avail__WIDTH 7
5522
5523#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120)
5524#define R_DMA_CH2_HWSW__hw__BITNR 16
5525#define R_DMA_CH2_HWSW__hw__WIDTH 16
5526#define R_DMA_CH2_HWSW__sw__BITNR 0
5527#define R_DMA_CH2_HWSW__sw__WIDTH 16
5528
5529#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c)
5530#define R_DMA_CH2_DESCR__descr__BITNR 0
5531#define R_DMA_CH2_DESCR__descr__WIDTH 32
5532
5533#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124)
5534#define R_DMA_CH2_NEXT__next__BITNR 0
5535#define R_DMA_CH2_NEXT__next__WIDTH 32
5536
5537#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128)
5538#define R_DMA_CH2_BUF__buf__BITNR 0
5539#define R_DMA_CH2_BUF__buf__WIDTH 32
5540
5541#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8)
5542#define R_DMA_CH2_FIRST__first__BITNR 0
5543#define R_DMA_CH2_FIRST__first__WIDTH 32
5544
5545#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8)
5546#define R_DMA_CH2_CMD__cmd__BITNR 0
5547#define R_DMA_CH2_CMD__cmd__WIDTH 3
5548#define R_DMA_CH2_CMD__cmd__hold 0
5549#define R_DMA_CH2_CMD__cmd__start 1
5550#define R_DMA_CH2_CMD__cmd__restart 3
5551#define R_DMA_CH2_CMD__cmd__continue 3
5552#define R_DMA_CH2_CMD__cmd__reset 4
5553
5554#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9)
5555#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
5556#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1
5557#define R_DMA_CH2_CLR_INTR__clr_eop__do 1
5558#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0
5559#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
5560#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1
5561#define R_DMA_CH2_CLR_INTR__clr_descr__do 1
5562#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0
5563
5564#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da)
5565#define R_DMA_CH2_STATUS__avail__BITNR 0
5566#define R_DMA_CH2_STATUS__avail__WIDTH 7
5567
5568#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130)
5569#define R_DMA_CH3_HWSW__hw__BITNR 16
5570#define R_DMA_CH3_HWSW__hw__WIDTH 16
5571#define R_DMA_CH3_HWSW__sw__BITNR 0
5572#define R_DMA_CH3_HWSW__sw__WIDTH 16
5573
5574#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c)
5575#define R_DMA_CH3_DESCR__descr__BITNR 0
5576#define R_DMA_CH3_DESCR__descr__WIDTH 32
5577
5578#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134)
5579#define R_DMA_CH3_NEXT__next__BITNR 0
5580#define R_DMA_CH3_NEXT__next__WIDTH 32
5581
5582#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138)
5583#define R_DMA_CH3_BUF__buf__BITNR 0
5584#define R_DMA_CH3_BUF__buf__WIDTH 32
5585
5586#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac)
5587#define R_DMA_CH3_FIRST__first__BITNR 0
5588#define R_DMA_CH3_FIRST__first__WIDTH 32
5589
5590#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc)
5591#define R_DMA_CH3_CMD__cmd__BITNR 0
5592#define R_DMA_CH3_CMD__cmd__WIDTH 3
5593#define R_DMA_CH3_CMD__cmd__hold 0
5594#define R_DMA_CH3_CMD__cmd__start 1
5595#define R_DMA_CH3_CMD__cmd__restart 3
5596#define R_DMA_CH3_CMD__cmd__continue 3
5597#define R_DMA_CH3_CMD__cmd__reset 4
5598
5599#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd)
5600#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
5601#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1
5602#define R_DMA_CH3_CLR_INTR__clr_eop__do 1
5603#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0
5604#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
5605#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1
5606#define R_DMA_CH3_CLR_INTR__clr_descr__do 1
5607#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0
5608
5609#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de)
5610#define R_DMA_CH3_STATUS__avail__BITNR 0
5611#define R_DMA_CH3_STATUS__avail__WIDTH 7
5612
5613#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140)
5614#define R_DMA_CH4_HWSW__hw__BITNR 16
5615#define R_DMA_CH4_HWSW__hw__WIDTH 16
5616#define R_DMA_CH4_HWSW__sw__BITNR 0
5617#define R_DMA_CH4_HWSW__sw__WIDTH 16
5618
5619#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c)
5620#define R_DMA_CH4_DESCR__descr__BITNR 0
5621#define R_DMA_CH4_DESCR__descr__WIDTH 32
5622
5623#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144)
5624#define R_DMA_CH4_NEXT__next__BITNR 0
5625#define R_DMA_CH4_NEXT__next__WIDTH 32
5626
5627#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148)
5628#define R_DMA_CH4_BUF__buf__BITNR 0
5629#define R_DMA_CH4_BUF__buf__WIDTH 32
5630
5631#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0)
5632#define R_DMA_CH4_FIRST__first__BITNR 0
5633#define R_DMA_CH4_FIRST__first__WIDTH 32
5634
5635#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0)
5636#define R_DMA_CH4_CMD__cmd__BITNR 0
5637#define R_DMA_CH4_CMD__cmd__WIDTH 3
5638#define R_DMA_CH4_CMD__cmd__hold 0
5639#define R_DMA_CH4_CMD__cmd__start 1
5640#define R_DMA_CH4_CMD__cmd__restart 3
5641#define R_DMA_CH4_CMD__cmd__continue 3
5642#define R_DMA_CH4_CMD__cmd__reset 4
5643
5644#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1)
5645#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
5646#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1
5647#define R_DMA_CH4_CLR_INTR__clr_eop__do 1
5648#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0
5649#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
5650#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1
5651#define R_DMA_CH4_CLR_INTR__clr_descr__do 1
5652#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0
5653
5654#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2)
5655#define R_DMA_CH4_STATUS__avail__BITNR 0
5656#define R_DMA_CH4_STATUS__avail__WIDTH 7
5657
5658#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150)
5659#define R_DMA_CH5_HWSW__hw__BITNR 16
5660#define R_DMA_CH5_HWSW__hw__WIDTH 16
5661#define R_DMA_CH5_HWSW__sw__BITNR 0
5662#define R_DMA_CH5_HWSW__sw__WIDTH 16
5663
5664#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c)
5665#define R_DMA_CH5_DESCR__descr__BITNR 0
5666#define R_DMA_CH5_DESCR__descr__WIDTH 32
5667
5668#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154)
5669#define R_DMA_CH5_NEXT__next__BITNR 0
5670#define R_DMA_CH5_NEXT__next__WIDTH 32
5671
5672#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158)
5673#define R_DMA_CH5_BUF__buf__BITNR 0
5674#define R_DMA_CH5_BUF__buf__WIDTH 32
5675
5676#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4)
5677#define R_DMA_CH5_FIRST__first__BITNR 0
5678#define R_DMA_CH5_FIRST__first__WIDTH 32
5679
5680#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4)
5681#define R_DMA_CH5_CMD__cmd__BITNR 0
5682#define R_DMA_CH5_CMD__cmd__WIDTH 3
5683#define R_DMA_CH5_CMD__cmd__hold 0
5684#define R_DMA_CH5_CMD__cmd__start 1
5685#define R_DMA_CH5_CMD__cmd__restart 3
5686#define R_DMA_CH5_CMD__cmd__continue 3
5687#define R_DMA_CH5_CMD__cmd__reset 4
5688
5689#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5)
5690#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
5691#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1
5692#define R_DMA_CH5_CLR_INTR__clr_eop__do 1
5693#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0
5694#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
5695#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1
5696#define R_DMA_CH5_CLR_INTR__clr_descr__do 1
5697#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0
5698
5699#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6)
5700#define R_DMA_CH5_STATUS__avail__BITNR 0
5701#define R_DMA_CH5_STATUS__avail__WIDTH 7
5702
5703#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160)
5704#define R_DMA_CH6_HWSW__hw__BITNR 16
5705#define R_DMA_CH6_HWSW__hw__WIDTH 16
5706#define R_DMA_CH6_HWSW__sw__BITNR 0
5707#define R_DMA_CH6_HWSW__sw__WIDTH 16
5708
5709#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c)
5710#define R_DMA_CH6_DESCR__descr__BITNR 0
5711#define R_DMA_CH6_DESCR__descr__WIDTH 32
5712
5713#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164)
5714#define R_DMA_CH6_NEXT__next__BITNR 0
5715#define R_DMA_CH6_NEXT__next__WIDTH 32
5716
5717#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168)
5718#define R_DMA_CH6_BUF__buf__BITNR 0
5719#define R_DMA_CH6_BUF__buf__WIDTH 32
5720
5721#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8)
5722#define R_DMA_CH6_FIRST__first__BITNR 0
5723#define R_DMA_CH6_FIRST__first__WIDTH 32
5724
5725#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8)
5726#define R_DMA_CH6_CMD__cmd__BITNR 0
5727#define R_DMA_CH6_CMD__cmd__WIDTH 3
5728#define R_DMA_CH6_CMD__cmd__hold 0
5729#define R_DMA_CH6_CMD__cmd__start 1
5730#define R_DMA_CH6_CMD__cmd__restart 3
5731#define R_DMA_CH6_CMD__cmd__continue 3
5732#define R_DMA_CH6_CMD__cmd__reset 4
5733
5734#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9)
5735#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
5736#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1
5737#define R_DMA_CH6_CLR_INTR__clr_eop__do 1
5738#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0
5739#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
5740#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1
5741#define R_DMA_CH6_CLR_INTR__clr_descr__do 1
5742#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0
5743
5744#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea)
5745#define R_DMA_CH6_STATUS__avail__BITNR 0
5746#define R_DMA_CH6_STATUS__avail__WIDTH 7
5747
5748#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170)
5749#define R_DMA_CH7_HWSW__hw__BITNR 16
5750#define R_DMA_CH7_HWSW__hw__WIDTH 16
5751#define R_DMA_CH7_HWSW__sw__BITNR 0
5752#define R_DMA_CH7_HWSW__sw__WIDTH 16
5753
5754#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c)
5755#define R_DMA_CH7_DESCR__descr__BITNR 0
5756#define R_DMA_CH7_DESCR__descr__WIDTH 32
5757
5758#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174)
5759#define R_DMA_CH7_NEXT__next__BITNR 0
5760#define R_DMA_CH7_NEXT__next__WIDTH 32
5761
5762#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178)
5763#define R_DMA_CH7_BUF__buf__BITNR 0
5764#define R_DMA_CH7_BUF__buf__WIDTH 32
5765
5766#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc)
5767#define R_DMA_CH7_FIRST__first__BITNR 0
5768#define R_DMA_CH7_FIRST__first__WIDTH 32
5769
5770#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec)
5771#define R_DMA_CH7_CMD__cmd__BITNR 0
5772#define R_DMA_CH7_CMD__cmd__WIDTH 3
5773#define R_DMA_CH7_CMD__cmd__hold 0
5774#define R_DMA_CH7_CMD__cmd__start 1
5775#define R_DMA_CH7_CMD__cmd__restart 3
5776#define R_DMA_CH7_CMD__cmd__continue 3
5777#define R_DMA_CH7_CMD__cmd__reset 4
5778
5779#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed)
5780#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
5781#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1
5782#define R_DMA_CH7_CLR_INTR__clr_eop__do 1
5783#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0
5784#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
5785#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1
5786#define R_DMA_CH7_CLR_INTR__clr_descr__do 1
5787#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0
5788
5789#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee)
5790#define R_DMA_CH7_STATUS__avail__BITNR 0
5791#define R_DMA_CH7_STATUS__avail__WIDTH 7
5792
5793#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180)
5794#define R_DMA_CH8_HWSW__hw__BITNR 16
5795#define R_DMA_CH8_HWSW__hw__WIDTH 16
5796#define R_DMA_CH8_HWSW__sw__BITNR 0
5797#define R_DMA_CH8_HWSW__sw__WIDTH 16
5798
5799#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c)
5800#define R_DMA_CH8_DESCR__descr__BITNR 0
5801#define R_DMA_CH8_DESCR__descr__WIDTH 32
5802
5803#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184)
5804#define R_DMA_CH8_NEXT__next__BITNR 0
5805#define R_DMA_CH8_NEXT__next__WIDTH 32
5806
5807#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188)
5808#define R_DMA_CH8_BUF__buf__BITNR 0
5809#define R_DMA_CH8_BUF__buf__WIDTH 32
5810
5811#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0)
5812#define R_DMA_CH8_FIRST__first__BITNR 0
5813#define R_DMA_CH8_FIRST__first__WIDTH 32
5814
5815#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0)
5816#define R_DMA_CH8_CMD__cmd__BITNR 0
5817#define R_DMA_CH8_CMD__cmd__WIDTH 3
5818#define R_DMA_CH8_CMD__cmd__hold 0
5819#define R_DMA_CH8_CMD__cmd__start 1
5820#define R_DMA_CH8_CMD__cmd__restart 3
5821#define R_DMA_CH8_CMD__cmd__continue 3
5822#define R_DMA_CH8_CMD__cmd__reset 4
5823
5824#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1)
5825#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
5826#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1
5827#define R_DMA_CH8_CLR_INTR__clr_eop__do 1
5828#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0
5829#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
5830#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1
5831#define R_DMA_CH8_CLR_INTR__clr_descr__do 1
5832#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0
5833
5834#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2)
5835#define R_DMA_CH8_STATUS__avail__BITNR 0
5836#define R_DMA_CH8_STATUS__avail__WIDTH 7
5837
5838#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c)
5839#define R_DMA_CH8_SUB__sub__BITNR 0
5840#define R_DMA_CH8_SUB__sub__WIDTH 32
5841
5842#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0)
5843#define R_DMA_CH8_NEP__nep__BITNR 0
5844#define R_DMA_CH8_NEP__nep__WIDTH 32
5845
5846#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8)
5847#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
5848#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32
5849
5850#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3)
5851#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
5852#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1
5853#define R_DMA_CH8_SUB0_CMD__cmd__stop 0
5854#define R_DMA_CH8_SUB0_CMD__cmd__start 1
5855
5856#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3)
5857#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
5858#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1
5859#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0
5860#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1
5861
5862#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc)
5863#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
5864#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32
5865
5866#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7)
5867#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
5868#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1
5869#define R_DMA_CH8_SUB1_CMD__cmd__stop 0
5870#define R_DMA_CH8_SUB1_CMD__cmd__start 1
5871
5872#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7)
5873#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
5874#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1
5875#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0
5876#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1
5877
5878#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8)
5879#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
5880#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32
5881
5882#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db)
5883#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
5884#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1
5885#define R_DMA_CH8_SUB2_CMD__cmd__stop 0
5886#define R_DMA_CH8_SUB2_CMD__cmd__start 1
5887
5888#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb)
5889#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
5890#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1
5891#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0
5892#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1
5893
5894#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc)
5895#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
5896#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32
5897
5898#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df)
5899#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
5900#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1
5901#define R_DMA_CH8_SUB3_CMD__cmd__stop 0
5902#define R_DMA_CH8_SUB3_CMD__cmd__start 1
5903
5904#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef)
5905#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
5906#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1
5907#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0
5908#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1
5909
5910#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190)
5911#define R_DMA_CH9_HWSW__hw__BITNR 16
5912#define R_DMA_CH9_HWSW__hw__WIDTH 16
5913#define R_DMA_CH9_HWSW__sw__BITNR 0
5914#define R_DMA_CH9_HWSW__sw__WIDTH 16
5915
5916#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c)
5917#define R_DMA_CH9_DESCR__descr__BITNR 0
5918#define R_DMA_CH9_DESCR__descr__WIDTH 32
5919
5920#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194)
5921#define R_DMA_CH9_NEXT__next__BITNR 0
5922#define R_DMA_CH9_NEXT__next__WIDTH 32
5923
5924#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198)
5925#define R_DMA_CH9_BUF__buf__BITNR 0
5926#define R_DMA_CH9_BUF__buf__WIDTH 32
5927
5928#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4)
5929#define R_DMA_CH9_FIRST__first__BITNR 0
5930#define R_DMA_CH9_FIRST__first__WIDTH 32
5931
5932#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4)
5933#define R_DMA_CH9_CMD__cmd__BITNR 0
5934#define R_DMA_CH9_CMD__cmd__WIDTH 3
5935#define R_DMA_CH9_CMD__cmd__hold 0
5936#define R_DMA_CH9_CMD__cmd__start 1
5937#define R_DMA_CH9_CMD__cmd__restart 3
5938#define R_DMA_CH9_CMD__cmd__continue 3
5939#define R_DMA_CH9_CMD__cmd__reset 4
5940
5941#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5)
5942#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
5943#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1
5944#define R_DMA_CH9_CLR_INTR__clr_eop__do 1
5945#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0
5946#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
5947#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1
5948#define R_DMA_CH9_CLR_INTR__clr_descr__do 1
5949#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0
5950
5951#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6)
5952#define R_DMA_CH9_STATUS__avail__BITNR 0
5953#define R_DMA_CH9_STATUS__avail__WIDTH 7
5954
5955/*
5956!* Test mode registers
5957!*/
5958
5959#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc)
5960#define R_TEST_MODE__single_step__BITNR 19
5961#define R_TEST_MODE__single_step__WIDTH 1
5962#define R_TEST_MODE__single_step__on 1
5963#define R_TEST_MODE__single_step__off 0
5964#define R_TEST_MODE__step_wr__BITNR 18
5965#define R_TEST_MODE__step_wr__WIDTH 1
5966#define R_TEST_MODE__step_wr__on 1
5967#define R_TEST_MODE__step_wr__off 0
5968#define R_TEST_MODE__step_rd__BITNR 17
5969#define R_TEST_MODE__step_rd__WIDTH 1
5970#define R_TEST_MODE__step_rd__on 1
5971#define R_TEST_MODE__step_rd__off 0
5972#define R_TEST_MODE__step_fetch__BITNR 16
5973#define R_TEST_MODE__step_fetch__WIDTH 1
5974#define R_TEST_MODE__step_fetch__on 1
5975#define R_TEST_MODE__step_fetch__off 0
5976#define R_TEST_MODE__mmu_test__BITNR 12
5977#define R_TEST_MODE__mmu_test__WIDTH 1
5978#define R_TEST_MODE__mmu_test__on 1
5979#define R_TEST_MODE__mmu_test__off 0
5980#define R_TEST_MODE__usb_test__BITNR 11
5981#define R_TEST_MODE__usb_test__WIDTH 1
5982#define R_TEST_MODE__usb_test__on 1
5983#define R_TEST_MODE__usb_test__off 0
5984#define R_TEST_MODE__scsi_timer_test__BITNR 10
5985#define R_TEST_MODE__scsi_timer_test__WIDTH 1
5986#define R_TEST_MODE__scsi_timer_test__on 1
5987#define R_TEST_MODE__scsi_timer_test__off 0
5988#define R_TEST_MODE__backoff__BITNR 9
5989#define R_TEST_MODE__backoff__WIDTH 1
5990#define R_TEST_MODE__backoff__on 1
5991#define R_TEST_MODE__backoff__off 0
5992#define R_TEST_MODE__snmp_test__BITNR 8
5993#define R_TEST_MODE__snmp_test__WIDTH 1
5994#define R_TEST_MODE__snmp_test__on 1
5995#define R_TEST_MODE__snmp_test__off 0
5996#define R_TEST_MODE__snmp_inc__BITNR 7
5997#define R_TEST_MODE__snmp_inc__WIDTH 1
5998#define R_TEST_MODE__snmp_inc__do 1
5999#define R_TEST_MODE__snmp_inc__dont 0
6000#define R_TEST_MODE__ser_loop__BITNR 6
6001#define R_TEST_MODE__ser_loop__WIDTH 1
6002#define R_TEST_MODE__ser_loop__on 1
6003#define R_TEST_MODE__ser_loop__off 0
6004#define R_TEST_MODE__baudrate__BITNR 5
6005#define R_TEST_MODE__baudrate__WIDTH 1
6006#define R_TEST_MODE__baudrate__on 1
6007#define R_TEST_MODE__baudrate__off 0
6008#define R_TEST_MODE__timer__BITNR 3
6009#define R_TEST_MODE__timer__WIDTH 2
6010#define R_TEST_MODE__timer__off 0
6011#define R_TEST_MODE__timer__even 1
6012#define R_TEST_MODE__timer__odd 2
6013#define R_TEST_MODE__timer__all 3
6014#define R_TEST_MODE__cache_test__BITNR 2
6015#define R_TEST_MODE__cache_test__WIDTH 1
6016#define R_TEST_MODE__cache_test__normal 0
6017#define R_TEST_MODE__cache_test__test 1
6018#define R_TEST_MODE__tag_test__BITNR 1
6019#define R_TEST_MODE__tag_test__WIDTH 1
6020#define R_TEST_MODE__tag_test__normal 0
6021#define R_TEST_MODE__tag_test__test 1
6022#define R_TEST_MODE__cache_enable__BITNR 0
6023#define R_TEST_MODE__cache_enable__WIDTH 1
6024#define R_TEST_MODE__cache_enable__enable 1
6025#define R_TEST_MODE__cache_enable__disable 0
6026
6027#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe)
6028#define R_SINGLE_STEP__single_step__BITNR 3
6029#define R_SINGLE_STEP__single_step__WIDTH 1
6030#define R_SINGLE_STEP__single_step__on 1
6031#define R_SINGLE_STEP__single_step__off 0
6032#define R_SINGLE_STEP__step_wr__BITNR 2
6033#define R_SINGLE_STEP__step_wr__WIDTH 1
6034#define R_SINGLE_STEP__step_wr__on 1
6035#define R_SINGLE_STEP__step_wr__off 0
6036#define R_SINGLE_STEP__step_rd__BITNR 1
6037#define R_SINGLE_STEP__step_rd__WIDTH 1
6038#define R_SINGLE_STEP__step_rd__on 1
6039#define R_SINGLE_STEP__step_rd__off 0
6040#define R_SINGLE_STEP__step_fetch__BITNR 0
6041#define R_SINGLE_STEP__step_fetch__WIDTH 1
6042#define R_SINGLE_STEP__step_fetch__on 1
6043#define R_SINGLE_STEP__step_fetch__off 0
6044
6045/*
6046!* USB interface control registers
6047!*/
6048
6049#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200)
6050#define R_USB_REVISION__major__BITNR 4
6051#define R_USB_REVISION__major__WIDTH 4
6052#define R_USB_REVISION__minor__BITNR 0
6053#define R_USB_REVISION__minor__WIDTH 4
6054
6055#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201)
6056#define R_USB_COMMAND__port_sel__BITNR 6
6057#define R_USB_COMMAND__port_sel__WIDTH 2
6058#define R_USB_COMMAND__port_sel__nop 0
6059#define R_USB_COMMAND__port_sel__port1 1
6060#define R_USB_COMMAND__port_sel__port2 2
6061#define R_USB_COMMAND__port_sel__both 3
6062#define R_USB_COMMAND__port_cmd__BITNR 4
6063#define R_USB_COMMAND__port_cmd__WIDTH 2
6064#define R_USB_COMMAND__port_cmd__reset 0
6065#define R_USB_COMMAND__port_cmd__disable 1
6066#define R_USB_COMMAND__port_cmd__suspend 2
6067#define R_USB_COMMAND__port_cmd__resume 3
6068#define R_USB_COMMAND__busy__BITNR 3
6069#define R_USB_COMMAND__busy__WIDTH 1
6070#define R_USB_COMMAND__busy__no 0
6071#define R_USB_COMMAND__busy__yes 1
6072#define R_USB_COMMAND__ctrl_cmd__BITNR 0
6073#define R_USB_COMMAND__ctrl_cmd__WIDTH 3
6074#define R_USB_COMMAND__ctrl_cmd__nop 0
6075#define R_USB_COMMAND__ctrl_cmd__reset 1
6076#define R_USB_COMMAND__ctrl_cmd__deconfig 2
6077#define R_USB_COMMAND__ctrl_cmd__host_config 3
6078#define R_USB_COMMAND__ctrl_cmd__dev_config 4
6079#define R_USB_COMMAND__ctrl_cmd__host_nop 5
6080#define R_USB_COMMAND__ctrl_cmd__host_run 6
6081#define R_USB_COMMAND__ctrl_cmd__host_stop 7
6082
6083#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
6084#define R_USB_COMMAND_DEV__port_sel__BITNR 6
6085#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
6086#define R_USB_COMMAND_DEV__port_sel__nop 0
6087#define R_USB_COMMAND_DEV__port_sel__dummy1 1
6088#define R_USB_COMMAND_DEV__port_sel__dummy2 2
6089#define R_USB_COMMAND_DEV__port_sel__any 3
6090#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
6091#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
6092#define R_USB_COMMAND_DEV__port_cmd__active 0
6093#define R_USB_COMMAND_DEV__port_cmd__passive 1
6094#define R_USB_COMMAND_DEV__port_cmd__nop 2
6095#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
6096#define R_USB_COMMAND_DEV__busy__BITNR 3
6097#define R_USB_COMMAND_DEV__busy__WIDTH 1
6098#define R_USB_COMMAND_DEV__busy__no 0
6099#define R_USB_COMMAND_DEV__busy__yes 1
6100#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
6101#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
6102#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
6103#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1
6104#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
6105#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
6106#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
6107#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5
6108#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6
6109#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7
6110
6111#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
6112#define R_USB_STATUS__ourun__BITNR 5
6113#define R_USB_STATUS__ourun__WIDTH 1
6114#define R_USB_STATUS__ourun__no 0
6115#define R_USB_STATUS__ourun__yes 1
6116#define R_USB_STATUS__perror__BITNR 4
6117#define R_USB_STATUS__perror__WIDTH 1
6118#define R_USB_STATUS__perror__no 0
6119#define R_USB_STATUS__perror__yes 1
6120#define R_USB_STATUS__device_mode__BITNR 3
6121#define R_USB_STATUS__device_mode__WIDTH 1
6122#define R_USB_STATUS__device_mode__no 0
6123#define R_USB_STATUS__device_mode__yes 1
6124#define R_USB_STATUS__host_mode__BITNR 2
6125#define R_USB_STATUS__host_mode__WIDTH 1
6126#define R_USB_STATUS__host_mode__no 0
6127#define R_USB_STATUS__host_mode__yes 1
6128#define R_USB_STATUS__started__BITNR 1
6129#define R_USB_STATUS__started__WIDTH 1
6130#define R_USB_STATUS__started__no 0
6131#define R_USB_STATUS__started__yes 1
6132#define R_USB_STATUS__running__BITNR 0
6133#define R_USB_STATUS__running__WIDTH 1
6134#define R_USB_STATUS__running__no 0
6135#define R_USB_STATUS__running__yes 1
6136
6137#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
6138#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
6139#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
6140#define R_USB_IRQ_MASK_SET__iso_eof__nop 0
6141#define R_USB_IRQ_MASK_SET__iso_eof__set 1
6142#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
6143#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
6144#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
6145#define R_USB_IRQ_MASK_SET__intr_eof__set 1
6146#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
6147#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
6148#define R_USB_IRQ_MASK_SET__iso_eot__nop 0
6149#define R_USB_IRQ_MASK_SET__iso_eot__set 1
6150#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
6151#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
6152#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
6153#define R_USB_IRQ_MASK_SET__intr_eot__set 1
6154#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
6155#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
6156#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
6157#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
6158#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
6159#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
6160#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
6161#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
6162#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
6163#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
6164#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
6165#define R_USB_IRQ_MASK_SET__epid_attn__set 1
6166#define R_USB_IRQ_MASK_SET__sof__BITNR 2
6167#define R_USB_IRQ_MASK_SET__sof__WIDTH 1
6168#define R_USB_IRQ_MASK_SET__sof__nop 0
6169#define R_USB_IRQ_MASK_SET__sof__set 1
6170#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
6171#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1
6172#define R_USB_IRQ_MASK_SET__port_status__nop 0
6173#define R_USB_IRQ_MASK_SET__port_status__set 1
6174#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
6175#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1
6176#define R_USB_IRQ_MASK_SET__ctl_status__nop 0
6177#define R_USB_IRQ_MASK_SET__ctl_status__set 1
6178
6179#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
6180#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
6181#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
6182#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
6183#define R_USB_IRQ_MASK_READ__iso_eof__pend 1
6184#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
6185#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
6186#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
6187#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
6188#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
6189#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
6190#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
6191#define R_USB_IRQ_MASK_READ__iso_eot__pend 1
6192#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
6193#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
6194#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
6195#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
6196#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
6197#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
6198#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
6199#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
6200#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
6201#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
6202#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
6203#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
6204#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
6205#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
6206#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
6207#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
6208#define R_USB_IRQ_MASK_READ__sof__BITNR 2
6209#define R_USB_IRQ_MASK_READ__sof__WIDTH 1
6210#define R_USB_IRQ_MASK_READ__sof__no_pend 0
6211#define R_USB_IRQ_MASK_READ__sof__pend 1
6212#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
6213#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1
6214#define R_USB_IRQ_MASK_READ__port_status__no_pend 0
6215#define R_USB_IRQ_MASK_READ__port_status__pend 1
6216#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
6217#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1
6218#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0
6219#define R_USB_IRQ_MASK_READ__ctl_status__pend 1
6220
6221#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
6222#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
6223#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
6224#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
6225#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
6226#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
6227#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
6228#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
6229#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
6230#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
6231#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
6232#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
6233#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
6234#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
6235#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
6236#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
6237#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
6238#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
6239#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
6240#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
6241#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
6242#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
6243#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
6244#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
6245#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
6246#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
6247#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
6248#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
6249#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
6250#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
6251#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
6252#define R_USB_IRQ_MASK_CLR__sof__nop 0
6253#define R_USB_IRQ_MASK_CLR__sof__clr 1
6254#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
6255#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1
6256#define R_USB_IRQ_MASK_CLR__port_status__nop 0
6257#define R_USB_IRQ_MASK_CLR__port_status__clr 1
6258#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
6259#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1
6260#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0
6261#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
6262
6263#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
6264#define R_USB_IRQ_READ__iso_eof__BITNR 13
6265#define R_USB_IRQ_READ__iso_eof__WIDTH 1
6266#define R_USB_IRQ_READ__iso_eof__no_pend 0
6267#define R_USB_IRQ_READ__iso_eof__pend 1
6268#define R_USB_IRQ_READ__intr_eof__BITNR 12
6269#define R_USB_IRQ_READ__intr_eof__WIDTH 1
6270#define R_USB_IRQ_READ__intr_eof__no_pend 0
6271#define R_USB_IRQ_READ__intr_eof__pend 1
6272#define R_USB_IRQ_READ__iso_eot__BITNR 11
6273#define R_USB_IRQ_READ__iso_eot__WIDTH 1
6274#define R_USB_IRQ_READ__iso_eot__no_pend 0
6275#define R_USB_IRQ_READ__iso_eot__pend 1
6276#define R_USB_IRQ_READ__intr_eot__BITNR 10
6277#define R_USB_IRQ_READ__intr_eot__WIDTH 1
6278#define R_USB_IRQ_READ__intr_eot__no_pend 0
6279#define R_USB_IRQ_READ__intr_eot__pend 1
6280#define R_USB_IRQ_READ__ctl_eot__BITNR 9
6281#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
6282#define R_USB_IRQ_READ__ctl_eot__no_pend 0
6283#define R_USB_IRQ_READ__ctl_eot__pend 1
6284#define R_USB_IRQ_READ__bulk_eot__BITNR 8
6285#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
6286#define R_USB_IRQ_READ__bulk_eot__no_pend 0
6287#define R_USB_IRQ_READ__bulk_eot__pend 1
6288#define R_USB_IRQ_READ__epid_attn__BITNR 3
6289#define R_USB_IRQ_READ__epid_attn__WIDTH 1
6290#define R_USB_IRQ_READ__epid_attn__no_pend 0
6291#define R_USB_IRQ_READ__epid_attn__pend 1
6292#define R_USB_IRQ_READ__sof__BITNR 2
6293#define R_USB_IRQ_READ__sof__WIDTH 1
6294#define R_USB_IRQ_READ__sof__no_pend 0
6295#define R_USB_IRQ_READ__sof__pend 1
6296#define R_USB_IRQ_READ__port_status__BITNR 1
6297#define R_USB_IRQ_READ__port_status__WIDTH 1
6298#define R_USB_IRQ_READ__port_status__no_pend 0
6299#define R_USB_IRQ_READ__port_status__pend 1
6300#define R_USB_IRQ_READ__ctl_status__BITNR 0
6301#define R_USB_IRQ_READ__ctl_status__WIDTH 1
6302#define R_USB_IRQ_READ__ctl_status__no_pend 0
6303#define R_USB_IRQ_READ__ctl_status__pend 1
6304
6305#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
6306#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
6307#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
6308#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
6309#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
6310#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
6311#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
6312#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
6313#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
6314#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
6315#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
6316#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
6317#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
6318#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
6319#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
6320#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
6321#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
6322#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
6323#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
6324#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
6325#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
6326#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
6327#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
6328#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
6329#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
6330#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
6331#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
6332#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
6333#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
6334#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
6335#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
6336#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
6337#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
6338#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
6339#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
6340#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
6341#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
6342
6343#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
6344#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
6345#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
6346#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
6347#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
6348#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
6349#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
6350#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
6351#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
6352#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
6353#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
6354#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
6355#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
6356#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
6357#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
6358#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
6359#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
6360#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
6361#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
6362#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
6363#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
6364#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
6365#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
6366#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
6367#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
6368#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
6369#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
6370#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
6371#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
6372#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
6373#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
6374#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
6375#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
6376#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
6377#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
6378#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
6379#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
6380
6381#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
6382#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
6383#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
6384#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
6385#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
6386#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
6387#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
6388#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
6389#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
6390#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
6391#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
6392#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
6393#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
6394#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
6395#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
6396#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
6397#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
6398#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
6399#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
6400#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
6401#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
6402#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
6403#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
6404#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
6405#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
6406#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
6407#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
6408#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
6409#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
6410#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
6411#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
6412#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
6413#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
6414#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
6415#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
6416#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
6417#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
6418
6419#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
6420#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
6421#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
6422#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
6423#define R_USB_IRQ_READ_DEV__out_eot__pend 1
6424#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
6425#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
6426#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
6427#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
6428#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
6429#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
6430#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
6431#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
6432#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
6433#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
6434#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
6435#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
6436#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
6437#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
6438#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
6439#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
6440#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
6441#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
6442#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
6443#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
6444#define R_USB_IRQ_READ_DEV__sof__BITNR 2
6445#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
6446#define R_USB_IRQ_READ_DEV__sof__no_pend 0
6447#define R_USB_IRQ_READ_DEV__sof__pend 1
6448#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
6449#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
6450#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
6451#define R_USB_IRQ_READ_DEV__port_status__pend 1
6452#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
6453#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
6454#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
6455#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
6456
6457#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
6458#define R_USB_FM_NUMBER__value__BITNR 0
6459#define R_USB_FM_NUMBER__value__WIDTH 32
6460
6461#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210)
6462#define R_USB_FM_INTERVAL__fixed__BITNR 6
6463#define R_USB_FM_INTERVAL__fixed__WIDTH 8
6464#define R_USB_FM_INTERVAL__adj__BITNR 0
6465#define R_USB_FM_INTERVAL__adj__WIDTH 6
6466
6467#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212)
6468#define R_USB_FM_REMAINING__value__BITNR 0
6469#define R_USB_FM_REMAINING__value__WIDTH 14
6470
6471#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214)
6472#define R_USB_FM_PSTART__value__BITNR 0
6473#define R_USB_FM_PSTART__value__WIDTH 14
6474
6475#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
6476#define R_USB_RH_STATUS__babble2__BITNR 7
6477#define R_USB_RH_STATUS__babble2__WIDTH 1
6478#define R_USB_RH_STATUS__babble2__no 0
6479#define R_USB_RH_STATUS__babble2__yes 1
6480#define R_USB_RH_STATUS__babble1__BITNR 6
6481#define R_USB_RH_STATUS__babble1__WIDTH 1
6482#define R_USB_RH_STATUS__babble1__no 0
6483#define R_USB_RH_STATUS__babble1__yes 1
6484#define R_USB_RH_STATUS__bus1__BITNR 4
6485#define R_USB_RH_STATUS__bus1__WIDTH 2
6486#define R_USB_RH_STATUS__bus1__SE0 0
6487#define R_USB_RH_STATUS__bus1__Diff0 1
6488#define R_USB_RH_STATUS__bus1__Diff1 2
6489#define R_USB_RH_STATUS__bus1__SE1 3
6490#define R_USB_RH_STATUS__bus2__BITNR 2
6491#define R_USB_RH_STATUS__bus2__WIDTH 2
6492#define R_USB_RH_STATUS__bus2__SE0 0
6493#define R_USB_RH_STATUS__bus2__Diff0 1
6494#define R_USB_RH_STATUS__bus2__Diff1 2
6495#define R_USB_RH_STATUS__bus2__SE1 3
6496#define R_USB_RH_STATUS__nports__BITNR 0
6497#define R_USB_RH_STATUS__nports__WIDTH 2
6498
6499#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218)
6500#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
6501#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1
6502#define R_USB_RH_PORT_STATUS_1__speed__full 0
6503#define R_USB_RH_PORT_STATUS_1__speed__low 1
6504#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
6505#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1
6506#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
6507#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
6508#define R_USB_RH_PORT_STATUS_1__reset__no 0
6509#define R_USB_RH_PORT_STATUS_1__reset__yes 1
6510#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
6511#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
6512#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
6513#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
6514#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
6515#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
6516#define R_USB_RH_PORT_STATUS_1__suspended__no 0
6517#define R_USB_RH_PORT_STATUS_1__suspended__yes 1
6518#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
6519#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1
6520#define R_USB_RH_PORT_STATUS_1__enabled__no 0
6521#define R_USB_RH_PORT_STATUS_1__enabled__yes 1
6522#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
6523#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1
6524#define R_USB_RH_PORT_STATUS_1__connected__no 0
6525#define R_USB_RH_PORT_STATUS_1__connected__yes 1
6526
6527#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a)
6528#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
6529#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1
6530#define R_USB_RH_PORT_STATUS_2__speed__full 0
6531#define R_USB_RH_PORT_STATUS_2__speed__low 1
6532#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
6533#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1
6534#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
6535#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
6536#define R_USB_RH_PORT_STATUS_2__reset__no 0
6537#define R_USB_RH_PORT_STATUS_2__reset__yes 1
6538#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
6539#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
6540#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
6541#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
6542#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
6543#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
6544#define R_USB_RH_PORT_STATUS_2__suspended__no 0
6545#define R_USB_RH_PORT_STATUS_2__suspended__yes 1
6546#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
6547#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1
6548#define R_USB_RH_PORT_STATUS_2__enabled__no 0
6549#define R_USB_RH_PORT_STATUS_2__enabled__yes 1
6550#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
6551#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1
6552#define R_USB_RH_PORT_STATUS_2__connected__no 0
6553#define R_USB_RH_PORT_STATUS_2__connected__yes 1
6554
6555#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208)
6556#define R_USB_EPT_INDEX__value__BITNR 0
6557#define R_USB_EPT_INDEX__value__WIDTH 5
6558
6559#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c)
6560#define R_USB_EPT_DATA__valid__BITNR 31
6561#define R_USB_EPT_DATA__valid__WIDTH 1
6562#define R_USB_EPT_DATA__valid__no 0
6563#define R_USB_EPT_DATA__valid__yes 1
6564#define R_USB_EPT_DATA__hold__BITNR 30
6565#define R_USB_EPT_DATA__hold__WIDTH 1
6566#define R_USB_EPT_DATA__hold__no 0
6567#define R_USB_EPT_DATA__hold__yes 1
6568#define R_USB_EPT_DATA__error_count_in__BITNR 28
6569#define R_USB_EPT_DATA__error_count_in__WIDTH 2
6570#define R_USB_EPT_DATA__t_in__BITNR 27
6571#define R_USB_EPT_DATA__t_in__WIDTH 1
6572#define R_USB_EPT_DATA__low_speed__BITNR 26
6573#define R_USB_EPT_DATA__low_speed__WIDTH 1
6574#define R_USB_EPT_DATA__low_speed__no 0
6575#define R_USB_EPT_DATA__low_speed__yes 1
6576#define R_USB_EPT_DATA__port__BITNR 24
6577#define R_USB_EPT_DATA__port__WIDTH 2
6578#define R_USB_EPT_DATA__port__any 0
6579#define R_USB_EPT_DATA__port__p1 1
6580#define R_USB_EPT_DATA__port__p2 2
6581#define R_USB_EPT_DATA__port__undef 3
6582#define R_USB_EPT_DATA__error_code__BITNR 22
6583#define R_USB_EPT_DATA__error_code__WIDTH 2
6584#define R_USB_EPT_DATA__error_code__no_error 0
6585#define R_USB_EPT_DATA__error_code__stall 1
6586#define R_USB_EPT_DATA__error_code__bus_error 2
6587#define R_USB_EPT_DATA__error_code__buffer_error 3
6588#define R_USB_EPT_DATA__t_out__BITNR 21
6589#define R_USB_EPT_DATA__t_out__WIDTH 1
6590#define R_USB_EPT_DATA__error_count_out__BITNR 19
6591#define R_USB_EPT_DATA__error_count_out__WIDTH 2
6592#define R_USB_EPT_DATA__max_len__BITNR 11
6593#define R_USB_EPT_DATA__max_len__WIDTH 7
6594#define R_USB_EPT_DATA__ep__BITNR 7
6595#define R_USB_EPT_DATA__ep__WIDTH 4
6596#define R_USB_EPT_DATA__dev__BITNR 0
6597#define R_USB_EPT_DATA__dev__WIDTH 7
6598
6599#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c)
6600#define R_USB_EPT_DATA_ISO__valid__BITNR 31
6601#define R_USB_EPT_DATA_ISO__valid__WIDTH 1
6602#define R_USB_EPT_DATA_ISO__valid__no 0
6603#define R_USB_EPT_DATA_ISO__valid__yes 1
6604#define R_USB_EPT_DATA_ISO__port__BITNR 24
6605#define R_USB_EPT_DATA_ISO__port__WIDTH 2
6606#define R_USB_EPT_DATA_ISO__port__any 0
6607#define R_USB_EPT_DATA_ISO__port__p1 1
6608#define R_USB_EPT_DATA_ISO__port__p2 2
6609#define R_USB_EPT_DATA_ISO__port__undef 3
6610#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
6611#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2
6612#define R_USB_EPT_DATA_ISO__error_code__no_error 0
6613#define R_USB_EPT_DATA_ISO__error_code__stall 1
6614#define R_USB_EPT_DATA_ISO__error_code__bus_error 2
6615#define R_USB_EPT_DATA_ISO__error_code__TBD3 3
6616#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
6617#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10
6618#define R_USB_EPT_DATA_ISO__ep__BITNR 7
6619#define R_USB_EPT_DATA_ISO__ep__WIDTH 4
6620#define R_USB_EPT_DATA_ISO__dev__BITNR 0
6621#define R_USB_EPT_DATA_ISO__dev__WIDTH 7
6622
6623#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c)
6624#define R_USB_EPT_DATA_DEV__valid__BITNR 31
6625#define R_USB_EPT_DATA_DEV__valid__WIDTH 1
6626#define R_USB_EPT_DATA_DEV__valid__no 0
6627#define R_USB_EPT_DATA_DEV__valid__yes 1
6628#define R_USB_EPT_DATA_DEV__hold__BITNR 30
6629#define R_USB_EPT_DATA_DEV__hold__WIDTH 1
6630#define R_USB_EPT_DATA_DEV__hold__no 0
6631#define R_USB_EPT_DATA_DEV__hold__yes 1
6632#define R_USB_EPT_DATA_DEV__stall__BITNR 29
6633#define R_USB_EPT_DATA_DEV__stall__WIDTH 1
6634#define R_USB_EPT_DATA_DEV__stall__no 0
6635#define R_USB_EPT_DATA_DEV__stall__yes 1
6636#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
6637#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
6638#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
6639#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
6640#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
6641#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
6642#define R_USB_EPT_DATA_DEV__ctrl__no 0
6643#define R_USB_EPT_DATA_DEV__ctrl__yes 1
6644#define R_USB_EPT_DATA_DEV__iso__BITNR 26
6645#define R_USB_EPT_DATA_DEV__iso__WIDTH 1
6646#define R_USB_EPT_DATA_DEV__iso__no 0
6647#define R_USB_EPT_DATA_DEV__iso__yes 1
6648#define R_USB_EPT_DATA_DEV__port__BITNR 24
6649#define R_USB_EPT_DATA_DEV__port__WIDTH 2
6650#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
6651#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
6652#define R_USB_EPT_DATA_DEV__t__BITNR 21
6653#define R_USB_EPT_DATA_DEV__t__WIDTH 1
6654#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
6655#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10
6656#define R_USB_EPT_DATA_DEV__ep__BITNR 7
6657#define R_USB_EPT_DATA_DEV__ep__WIDTH 4
6658#define R_USB_EPT_DATA_DEV__dev__BITNR 0
6659#define R_USB_EPT_DATA_DEV__dev__WIDTH 7
6660
6661#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220)
6662#define R_USB_SNMP_TERROR__value__BITNR 0
6663#define R_USB_SNMP_TERROR__value__WIDTH 32
6664
6665#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
6666#define R_USB_EPID_ATTN__value__BITNR 0
6667#define R_USB_EPID_ATTN__value__WIDTH 32
6668
6669#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
6670#define R_USB_PORT1_DISABLE__disable__BITNR 0
6671#define R_USB_PORT1_DISABLE__disable__WIDTH 1
6672#define R_USB_PORT1_DISABLE__disable__yes 0
6673#define R_USB_PORT1_DISABLE__disable__no 1
6674
6675#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
6676#define R_USB_PORT2_DISABLE__disable__BITNR 0
6677#define R_USB_PORT2_DISABLE__disable__WIDTH 1
6678#define R_USB_PORT2_DISABLE__disable__yes 0
6679#define R_USB_PORT2_DISABLE__disable__no 1
6680
6681/*
6682!* MMU registers
6683!*/
6684
6685#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240)
6686#define R_MMU_CONFIG__mmu_enable__BITNR 31
6687#define R_MMU_CONFIG__mmu_enable__WIDTH 1
6688#define R_MMU_CONFIG__mmu_enable__enable 1
6689#define R_MMU_CONFIG__mmu_enable__disable 0
6690#define R_MMU_CONFIG__inv_excp__BITNR 18
6691#define R_MMU_CONFIG__inv_excp__WIDTH 1
6692#define R_MMU_CONFIG__inv_excp__enable 1
6693#define R_MMU_CONFIG__inv_excp__disable 0
6694#define R_MMU_CONFIG__acc_excp__BITNR 17
6695#define R_MMU_CONFIG__acc_excp__WIDTH 1
6696#define R_MMU_CONFIG__acc_excp__enable 1
6697#define R_MMU_CONFIG__acc_excp__disable 0
6698#define R_MMU_CONFIG__we_excp__BITNR 16
6699#define R_MMU_CONFIG__we_excp__WIDTH 1
6700#define R_MMU_CONFIG__we_excp__enable 1
6701#define R_MMU_CONFIG__we_excp__disable 0
6702#define R_MMU_CONFIG__seg_f__BITNR 15
6703#define R_MMU_CONFIG__seg_f__WIDTH 1
6704#define R_MMU_CONFIG__seg_f__seg 1
6705#define R_MMU_CONFIG__seg_f__page 0
6706#define R_MMU_CONFIG__seg_e__BITNR 14
6707#define R_MMU_CONFIG__seg_e__WIDTH 1
6708#define R_MMU_CONFIG__seg_e__seg 1
6709#define R_MMU_CONFIG__seg_e__page 0
6710#define R_MMU_CONFIG__seg_d__BITNR 13
6711#define R_MMU_CONFIG__seg_d__WIDTH 1
6712#define R_MMU_CONFIG__seg_d__seg 1
6713#define R_MMU_CONFIG__seg_d__page 0
6714#define R_MMU_CONFIG__seg_c__BITNR 12
6715#define R_MMU_CONFIG__seg_c__WIDTH 1
6716#define R_MMU_CONFIG__seg_c__seg 1
6717#define R_MMU_CONFIG__seg_c__page 0
6718#define R_MMU_CONFIG__seg_b__BITNR 11
6719#define R_MMU_CONFIG__seg_b__WIDTH 1
6720#define R_MMU_CONFIG__seg_b__seg 1
6721#define R_MMU_CONFIG__seg_b__page 0
6722#define R_MMU_CONFIG__seg_a__BITNR 10
6723#define R_MMU_CONFIG__seg_a__WIDTH 1
6724#define R_MMU_CONFIG__seg_a__seg 1
6725#define R_MMU_CONFIG__seg_a__page 0
6726#define R_MMU_CONFIG__seg_9__BITNR 9
6727#define R_MMU_CONFIG__seg_9__WIDTH 1
6728#define R_MMU_CONFIG__seg_9__seg 1
6729#define R_MMU_CONFIG__seg_9__page 0
6730#define R_MMU_CONFIG__seg_8__BITNR 8
6731#define R_MMU_CONFIG__seg_8__WIDTH 1
6732#define R_MMU_CONFIG__seg_8__seg 1
6733#define R_MMU_CONFIG__seg_8__page 0
6734#define R_MMU_CONFIG__seg_7__BITNR 7
6735#define R_MMU_CONFIG__seg_7__WIDTH 1
6736#define R_MMU_CONFIG__seg_7__seg 1
6737#define R_MMU_CONFIG__seg_7__page 0
6738#define R_MMU_CONFIG__seg_6__BITNR 6
6739#define R_MMU_CONFIG__seg_6__WIDTH 1
6740#define R_MMU_CONFIG__seg_6__seg 1
6741#define R_MMU_CONFIG__seg_6__page 0
6742#define R_MMU_CONFIG__seg_5__BITNR 5
6743#define R_MMU_CONFIG__seg_5__WIDTH 1
6744#define R_MMU_CONFIG__seg_5__seg 1
6745#define R_MMU_CONFIG__seg_5__page 0
6746#define R_MMU_CONFIG__seg_4__BITNR 4
6747#define R_MMU_CONFIG__seg_4__WIDTH 1
6748#define R_MMU_CONFIG__seg_4__seg 1
6749#define R_MMU_CONFIG__seg_4__page 0
6750#define R_MMU_CONFIG__seg_3__BITNR 3
6751#define R_MMU_CONFIG__seg_3__WIDTH 1
6752#define R_MMU_CONFIG__seg_3__seg 1
6753#define R_MMU_CONFIG__seg_3__page 0
6754#define R_MMU_CONFIG__seg_2__BITNR 2
6755#define R_MMU_CONFIG__seg_2__WIDTH 1
6756#define R_MMU_CONFIG__seg_2__seg 1
6757#define R_MMU_CONFIG__seg_2__page 0
6758#define R_MMU_CONFIG__seg_1__BITNR 1
6759#define R_MMU_CONFIG__seg_1__WIDTH 1
6760#define R_MMU_CONFIG__seg_1__seg 1
6761#define R_MMU_CONFIG__seg_1__page 0
6762#define R_MMU_CONFIG__seg_0__BITNR 0
6763#define R_MMU_CONFIG__seg_0__WIDTH 1
6764#define R_MMU_CONFIG__seg_0__seg 1
6765#define R_MMU_CONFIG__seg_0__page 0
6766
6767#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240)
6768#define R_MMU_KSEG__seg_f__BITNR 15
6769#define R_MMU_KSEG__seg_f__WIDTH 1
6770#define R_MMU_KSEG__seg_f__seg 1
6771#define R_MMU_KSEG__seg_f__page 0
6772#define R_MMU_KSEG__seg_e__BITNR 14
6773#define R_MMU_KSEG__seg_e__WIDTH 1
6774#define R_MMU_KSEG__seg_e__seg 1
6775#define R_MMU_KSEG__seg_e__page 0
6776#define R_MMU_KSEG__seg_d__BITNR 13
6777#define R_MMU_KSEG__seg_d__WIDTH 1
6778#define R_MMU_KSEG__seg_d__seg 1
6779#define R_MMU_KSEG__seg_d__page 0
6780#define R_MMU_KSEG__seg_c__BITNR 12
6781#define R_MMU_KSEG__seg_c__WIDTH 1
6782#define R_MMU_KSEG__seg_c__seg 1
6783#define R_MMU_KSEG__seg_c__page 0
6784#define R_MMU_KSEG__seg_b__BITNR 11
6785#define R_MMU_KSEG__seg_b__WIDTH 1
6786#define R_MMU_KSEG__seg_b__seg 1
6787#define R_MMU_KSEG__seg_b__page 0
6788#define R_MMU_KSEG__seg_a__BITNR 10
6789#define R_MMU_KSEG__seg_a__WIDTH 1
6790#define R_MMU_KSEG__seg_a__seg 1
6791#define R_MMU_KSEG__seg_a__page 0
6792#define R_MMU_KSEG__seg_9__BITNR 9
6793#define R_MMU_KSEG__seg_9__WIDTH 1
6794#define R_MMU_KSEG__seg_9__seg 1
6795#define R_MMU_KSEG__seg_9__page 0
6796#define R_MMU_KSEG__seg_8__BITNR 8
6797#define R_MMU_KSEG__seg_8__WIDTH 1
6798#define R_MMU_KSEG__seg_8__seg 1
6799#define R_MMU_KSEG__seg_8__page 0
6800#define R_MMU_KSEG__seg_7__BITNR 7
6801#define R_MMU_KSEG__seg_7__WIDTH 1
6802#define R_MMU_KSEG__seg_7__seg 1
6803#define R_MMU_KSEG__seg_7__page 0
6804#define R_MMU_KSEG__seg_6__BITNR 6
6805#define R_MMU_KSEG__seg_6__WIDTH 1
6806#define R_MMU_KSEG__seg_6__seg 1
6807#define R_MMU_KSEG__seg_6__page 0
6808#define R_MMU_KSEG__seg_5__BITNR 5
6809#define R_MMU_KSEG__seg_5__WIDTH 1
6810#define R_MMU_KSEG__seg_5__seg 1
6811#define R_MMU_KSEG__seg_5__page 0
6812#define R_MMU_KSEG__seg_4__BITNR 4
6813#define R_MMU_KSEG__seg_4__WIDTH 1
6814#define R_MMU_KSEG__seg_4__seg 1
6815#define R_MMU_KSEG__seg_4__page 0
6816#define R_MMU_KSEG__seg_3__BITNR 3
6817#define R_MMU_KSEG__seg_3__WIDTH 1
6818#define R_MMU_KSEG__seg_3__seg 1
6819#define R_MMU_KSEG__seg_3__page 0
6820#define R_MMU_KSEG__seg_2__BITNR 2
6821#define R_MMU_KSEG__seg_2__WIDTH 1
6822#define R_MMU_KSEG__seg_2__seg 1
6823#define R_MMU_KSEG__seg_2__page 0
6824#define R_MMU_KSEG__seg_1__BITNR 1
6825#define R_MMU_KSEG__seg_1__WIDTH 1
6826#define R_MMU_KSEG__seg_1__seg 1
6827#define R_MMU_KSEG__seg_1__page 0
6828#define R_MMU_KSEG__seg_0__BITNR 0
6829#define R_MMU_KSEG__seg_0__WIDTH 1
6830#define R_MMU_KSEG__seg_0__seg 1
6831#define R_MMU_KSEG__seg_0__page 0
6832
6833#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242)
6834#define R_MMU_CTRL__inv_excp__BITNR 2
6835#define R_MMU_CTRL__inv_excp__WIDTH 1
6836#define R_MMU_CTRL__inv_excp__enable 1
6837#define R_MMU_CTRL__inv_excp__disable 0
6838#define R_MMU_CTRL__acc_excp__BITNR 1
6839#define R_MMU_CTRL__acc_excp__WIDTH 1
6840#define R_MMU_CTRL__acc_excp__enable 1
6841#define R_MMU_CTRL__acc_excp__disable 0
6842#define R_MMU_CTRL__we_excp__BITNR 0
6843#define R_MMU_CTRL__we_excp__WIDTH 1
6844#define R_MMU_CTRL__we_excp__enable 1
6845#define R_MMU_CTRL__we_excp__disable 0
6846
6847#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243)
6848#define R_MMU_ENABLE__mmu_enable__BITNR 7
6849#define R_MMU_ENABLE__mmu_enable__WIDTH 1
6850#define R_MMU_ENABLE__mmu_enable__enable 1
6851#define R_MMU_ENABLE__mmu_enable__disable 0
6852
6853#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244)
6854#define R_MMU_KBASE_LO__base_7__BITNR 28
6855#define R_MMU_KBASE_LO__base_7__WIDTH 4
6856#define R_MMU_KBASE_LO__base_6__BITNR 24
6857#define R_MMU_KBASE_LO__base_6__WIDTH 4
6858#define R_MMU_KBASE_LO__base_5__BITNR 20
6859#define R_MMU_KBASE_LO__base_5__WIDTH 4
6860#define R_MMU_KBASE_LO__base_4__BITNR 16
6861#define R_MMU_KBASE_LO__base_4__WIDTH 4
6862#define R_MMU_KBASE_LO__base_3__BITNR 12
6863#define R_MMU_KBASE_LO__base_3__WIDTH 4
6864#define R_MMU_KBASE_LO__base_2__BITNR 8
6865#define R_MMU_KBASE_LO__base_2__WIDTH 4
6866#define R_MMU_KBASE_LO__base_1__BITNR 4
6867#define R_MMU_KBASE_LO__base_1__WIDTH 4
6868#define R_MMU_KBASE_LO__base_0__BITNR 0
6869#define R_MMU_KBASE_LO__base_0__WIDTH 4
6870
6871#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248)
6872#define R_MMU_KBASE_HI__base_f__BITNR 28
6873#define R_MMU_KBASE_HI__base_f__WIDTH 4
6874#define R_MMU_KBASE_HI__base_e__BITNR 24
6875#define R_MMU_KBASE_HI__base_e__WIDTH 4
6876#define R_MMU_KBASE_HI__base_d__BITNR 20
6877#define R_MMU_KBASE_HI__base_d__WIDTH 4
6878#define R_MMU_KBASE_HI__base_c__BITNR 16
6879#define R_MMU_KBASE_HI__base_c__WIDTH 4
6880#define R_MMU_KBASE_HI__base_b__BITNR 12
6881#define R_MMU_KBASE_HI__base_b__WIDTH 4
6882#define R_MMU_KBASE_HI__base_a__BITNR 8
6883#define R_MMU_KBASE_HI__base_a__WIDTH 4
6884#define R_MMU_KBASE_HI__base_9__BITNR 4
6885#define R_MMU_KBASE_HI__base_9__WIDTH 4
6886#define R_MMU_KBASE_HI__base_8__BITNR 0
6887#define R_MMU_KBASE_HI__base_8__WIDTH 4
6888
6889#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c)
6890#define R_MMU_CONTEXT__page_id__BITNR 0
6891#define R_MMU_CONTEXT__page_id__WIDTH 6
6892
6893#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250)
6894#define R_MMU_CAUSE__vpn__BITNR 13
6895#define R_MMU_CAUSE__vpn__WIDTH 19
6896#define R_MMU_CAUSE__miss_excp__BITNR 12
6897#define R_MMU_CAUSE__miss_excp__WIDTH 1
6898#define R_MMU_CAUSE__miss_excp__yes 1
6899#define R_MMU_CAUSE__miss_excp__no 0
6900#define R_MMU_CAUSE__inv_excp__BITNR 11
6901#define R_MMU_CAUSE__inv_excp__WIDTH 1
6902#define R_MMU_CAUSE__inv_excp__yes 1
6903#define R_MMU_CAUSE__inv_excp__no 0
6904#define R_MMU_CAUSE__acc_excp__BITNR 10
6905#define R_MMU_CAUSE__acc_excp__WIDTH 1
6906#define R_MMU_CAUSE__acc_excp__yes 1
6907#define R_MMU_CAUSE__acc_excp__no 0
6908#define R_MMU_CAUSE__we_excp__BITNR 9
6909#define R_MMU_CAUSE__we_excp__WIDTH 1
6910#define R_MMU_CAUSE__we_excp__yes 1
6911#define R_MMU_CAUSE__we_excp__no 0
6912#define R_MMU_CAUSE__wr_rd__BITNR 8
6913#define R_MMU_CAUSE__wr_rd__WIDTH 1
6914#define R_MMU_CAUSE__wr_rd__write 1
6915#define R_MMU_CAUSE__wr_rd__read 0
6916#define R_MMU_CAUSE__page_id__BITNR 0
6917#define R_MMU_CAUSE__page_id__WIDTH 6
6918
6919#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254)
6920#define R_TLB_SELECT__index__BITNR 0
6921#define R_TLB_SELECT__index__WIDTH 6
6922
6923#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258)
6924#define R_TLB_LO__pfn__BITNR 13
6925#define R_TLB_LO__pfn__WIDTH 19
6926#define R_TLB_LO__global__BITNR 3
6927#define R_TLB_LO__global__WIDTH 1
6928#define R_TLB_LO__global__yes 1
6929#define R_TLB_LO__global__no 0
6930#define R_TLB_LO__valid__BITNR 2
6931#define R_TLB_LO__valid__WIDTH 1
6932#define R_TLB_LO__valid__yes 1
6933#define R_TLB_LO__valid__no 0
6934#define R_TLB_LO__kernel__BITNR 1
6935#define R_TLB_LO__kernel__WIDTH 1
6936#define R_TLB_LO__kernel__yes 1
6937#define R_TLB_LO__kernel__no 0
6938#define R_TLB_LO__we__BITNR 0
6939#define R_TLB_LO__we__WIDTH 1
6940#define R_TLB_LO__we__yes 1
6941#define R_TLB_LO__we__no 0
6942
6943#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c)
6944#define R_TLB_HI__vpn__BITNR 13
6945#define R_TLB_HI__vpn__WIDTH 19
6946#define R_TLB_HI__page_id__BITNR 0
6947#define R_TLB_HI__page_id__WIDTH 6
6948
6949/*
6950!* Syncrounous serial port registers
6951!*/
6952
6953#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c)
6954#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
6955#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32
6956
6957#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c)
6958#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
6959#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16
6960
6961#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c)
6962#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
6963#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8
6964
6965#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068)
6966#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
6967#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1
6968#define R_SYNC_SERIAL1_STATUS__rec_status__running 0
6969#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1
6970#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
6971#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1
6972#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1
6973#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0
6974#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
6975#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1
6976#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0
6977#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1
6978#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
6979#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1
6980#define R_SYNC_SERIAL1_STATUS__pin_1__low 0
6981#define R_SYNC_SERIAL1_STATUS__pin_1__high 1
6982#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
6983#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1
6984#define R_SYNC_SERIAL1_STATUS__pin_0__low 0
6985#define R_SYNC_SERIAL1_STATUS__pin_0__high 1
6986#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
6987#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1
6988#define R_SYNC_SERIAL1_STATUS__underflow__no 0
6989#define R_SYNC_SERIAL1_STATUS__underflow__yes 1
6990#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
6991#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1
6992#define R_SYNC_SERIAL1_STATUS__overrun__no 0
6993#define R_SYNC_SERIAL1_STATUS__overrun__yes 1
6994#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
6995#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1
6996#define R_SYNC_SERIAL1_STATUS__data_avail__no 0
6997#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1
6998#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
6999#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8
7000
7001#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c)
7002#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
7003#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32
7004
7005#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c)
7006#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
7007#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16
7008
7009#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c)
7010#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
7011#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8
7012
7013#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
7014#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
7015#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4
7016#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0
7017#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1
7018#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2
7019#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3
7020#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4
7021#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5
7022#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6
7023#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7
7024#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8
7025#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9
7026#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10
7027#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11
7028#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12
7029#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13
7030#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14
7031#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15
7032#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
7033#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1
7034#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1
7035#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0
7036#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
7037#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3
7038#define R_SYNC_SERIAL1_CTRL__mode__master_output 0
7039#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1
7040#define R_SYNC_SERIAL1_CTRL__mode__master_input 2
7041#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3
7042#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4
7043#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5
7044#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
7045#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1
7046#define R_SYNC_SERIAL1_CTRL__error__normal 0
7047#define R_SYNC_SERIAL1_CTRL__error__ignore 1
7048#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
7049#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1
7050#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0
7051#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1
7052#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
7053#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1
7054#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0
7055#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1
7056#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
7057#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2
7058#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0
7059#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1
7060#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2
7061#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3
7062#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
7063#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1
7064#define R_SYNC_SERIAL1_CTRL__f_sync__on 0
7065#define R_SYNC_SERIAL1_CTRL__f_sync__off 1
7066#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
7067#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1
7068#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0
7069#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1
7070#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
7071#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1
7072#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0
7073#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1
7074#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
7075#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1
7076#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0
7077#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1
7078#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
7079#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1
7080#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0
7081#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1
7082#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
7083#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3
7084#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0
7085#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1
7086#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2
7087#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3
7088#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4
7089#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
7090#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1
7091#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0
7092#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1
7093#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
7094#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1
7095#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0
7096#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1
7097#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
7098#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1
7099#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0
7100#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1
7101#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
7102#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1
7103#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0
7104#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1
7105#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
7106#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1
7107#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0
7108#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1
7109#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
7110#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1
7111#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0
7112#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1
7113#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
7114#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1
7115#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0
7116#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1
7117#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
7118#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1
7119#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0
7120#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1
7121#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
7122#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1
7123#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0
7124#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1
7125#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
7126#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1
7127#define R_SYNC_SERIAL1_CTRL__def_out0__high 1
7128#define R_SYNC_SERIAL1_CTRL__def_out0__low 0
7129
7130#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c)
7131#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
7132#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32
7133
7134#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c)
7135#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
7136#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16
7137
7138#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c)
7139#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
7140#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8
7141
7142#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078)
7143#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
7144#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1
7145#define R_SYNC_SERIAL3_STATUS__rec_status__running 0
7146#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1
7147#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
7148#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1
7149#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1
7150#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0
7151#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
7152#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1
7153#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0
7154#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1
7155#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
7156#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1
7157#define R_SYNC_SERIAL3_STATUS__pin_1__low 0
7158#define R_SYNC_SERIAL3_STATUS__pin_1__high 1
7159#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
7160#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1
7161#define R_SYNC_SERIAL3_STATUS__pin_0__low 0
7162#define R_SYNC_SERIAL3_STATUS__pin_0__high 1
7163#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
7164#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1
7165#define R_SYNC_SERIAL3_STATUS__underflow__no 0
7166#define R_SYNC_SERIAL3_STATUS__underflow__yes 1
7167#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
7168#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1
7169#define R_SYNC_SERIAL3_STATUS__overrun__no 0
7170#define R_SYNC_SERIAL3_STATUS__overrun__yes 1
7171#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
7172#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1
7173#define R_SYNC_SERIAL3_STATUS__data_avail__no 0
7174#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1
7175#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
7176#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8
7177
7178#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c)
7179#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
7180#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32
7181
7182#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c)
7183#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
7184#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16
7185
7186#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c)
7187#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
7188#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8
7189
7190#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
7191#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
7192#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4
7193#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0
7194#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1
7195#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2
7196#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3
7197#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4
7198#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5
7199#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6
7200#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7
7201#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8
7202#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9
7203#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10
7204#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11
7205#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12
7206#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13
7207#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14
7208#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15
7209#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
7210#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1
7211#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1
7212#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0
7213#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
7214#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3
7215#define R_SYNC_SERIAL3_CTRL__mode__master_output 0
7216#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1
7217#define R_SYNC_SERIAL3_CTRL__mode__master_input 2
7218#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3
7219#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4
7220#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5
7221#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
7222#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1
7223#define R_SYNC_SERIAL3_CTRL__error__normal 0
7224#define R_SYNC_SERIAL3_CTRL__error__ignore 1
7225#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
7226#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1
7227#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0
7228#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1
7229#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
7230#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1
7231#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0
7232#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1
7233#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
7234#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2
7235#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0
7236#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1
7237#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2
7238#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3
7239#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
7240#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1
7241#define R_SYNC_SERIAL3_CTRL__f_sync__on 0
7242#define R_SYNC_SERIAL3_CTRL__f_sync__off 1
7243#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
7244#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1
7245#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0
7246#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1
7247#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
7248#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1
7249#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0
7250#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1
7251#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
7252#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1
7253#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0
7254#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1
7255#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
7256#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1
7257#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0
7258#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1
7259#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
7260#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3
7261#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0
7262#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1
7263#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2
7264#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3
7265#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4
7266#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
7267#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1
7268#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0
7269#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1
7270#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
7271#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1
7272#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0
7273#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1
7274#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
7275#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1
7276#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0
7277#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1
7278#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
7279#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1
7280#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0
7281#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1
7282#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
7283#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1
7284#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0
7285#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1
7286#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
7287#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1
7288#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0
7289#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1
7290#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
7291#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1
7292#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0
7293#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1
7294#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
7295#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1
7296#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0
7297#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1
7298#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
7299#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1
7300#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0
7301#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1
7302#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
7303#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1
7304#define R_SYNC_SERIAL3_CTRL__def_out0__high 1
7305#define R_SYNC_SERIAL3_CTRL__def_out0__low 0
7306
diff --git a/arch/cris/include/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/arch-v10/arch/sv_addr_ag.h
new file mode 100644
index 000000000000..e4a6b68b8982
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/sv_addr_ag.h
@@ -0,0 +1,139 @@
1/*!**************************************************************************
2*!
3*! MACROS:
4*! IO_MASK(reg,field)
5*! IO_STATE(reg,field,state)
6*! IO_EXTRACT(reg,field,val)
7*! IO_STATE_VALUE(reg,field,state)
8*! IO_BITNR(reg,field)
9*! IO_WIDTH(reg,field)
10*! IO_FIELD(reg,field,val)
11*! IO_RD(reg)
12*! All moderegister addresses and fields of these.
13*!
14*!**************************************************************************/
15
16#ifndef __sv_addr_ag_h__
17#define __sv_addr_ag_h__
18
19
20#define __test_sv_addr__ 0
21
22/*------------------------------------------------------------
23!* General macros to manipulate moderegisters.
24!*-----------------------------------------------------------*/
25
26/* IO_MASK returns a mask for a specified bitfield in a register.
27 Note that this macro doesn't work when field width is 32 bits. */
28#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
29#define IO_MASK_(reg_, field_) \
30 ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
31
32/* IO_STATE returns a constant corresponding to a one of the symbolic
33 states that the bitfield can have. (Shifted to correct position) */
34#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
35#define IO_STATE_(reg_, field_, _state) \
36 ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
37
38/* IO_EXTRACT returns the masked and shifted value corresponding to the
39 bitfield can have. */
40#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
41#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
42 - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
43
44/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
45 states that the bitfield can have. (Not shifted) */
46#define IO_STATE_VALUE(reg, field, state) \
47 IO_STATE_VALUE_ (reg##_, field##_, _##state)
48#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
49
50/* IO_FIELD shifts the val parameter to be aligned with the bitfield
51 specified. */
52#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
53#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR)
54
55/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
56 LSB and the returned bitnumber is LSB of the field. */
57#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
58#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR)
59
60/* IO_WIDTH returns the width, in bits, of a bitfield. */
61#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
62#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
63
64/*--- Obsolete. Kept for backw compatibility. ---*/
65/* Reads (or writes) a byte/uword/udword from the specified mode
66 register. */
67#define IO_RD(reg) (*(volatile u32*)(reg))
68#define IO_RD_B(reg) (*(volatile u8*)(reg))
69#define IO_RD_W(reg) (*(volatile u16*)(reg))
70#define IO_RD_D(reg) (*(volatile u32*)(reg))
71
72/*------------------------------------------------------------
73!* Start addresses of the different memory areas.
74!*-----------------------------------------------------------*/
75
76#define MEM_CSE0_START (0x00000000)
77#define MEM_CSE0_SIZE (0x04000000)
78#define MEM_CSE1_START (0x04000000)
79#define MEM_CSE1_SIZE (0x04000000)
80#define MEM_CSR0_START (0x08000000)
81#define MEM_CSR1_START (0x0c000000)
82#define MEM_CSP0_START (0x10000000)
83#define MEM_CSP1_START (0x14000000)
84#define MEM_CSP2_START (0x18000000)
85#define MEM_CSP3_START (0x1c000000)
86#define MEM_CSP4_START (0x20000000)
87#define MEM_CSP5_START (0x24000000)
88#define MEM_CSP6_START (0x28000000)
89#define MEM_CSP7_START (0x2c000000)
90#define MEM_DRAM_START (0x40000000)
91
92#define MEM_NON_CACHEABLE (0x80000000)
93
94/*------------------------------------------------------------
95!* Type casts used in mode register macros, making pointer
96!* dereferencing possible. Empty in assembler.
97!*-----------------------------------------------------------*/
98
99#ifndef __ASSEMBLER__
100# define IO_TYPECAST_UDWORD (volatile u32*)
101# define IO_TYPECAST_RO_UDWORD (const volatile u32*)
102# define IO_TYPECAST_UWORD (volatile u16*)
103# define IO_TYPECAST_RO_UWORD (const volatile u16*)
104# define IO_TYPECAST_BYTE (volatile u8*)
105# define IO_TYPECAST_RO_BYTE (const volatile u8*)
106#else
107# define IO_TYPECAST_UDWORD
108# define IO_TYPECAST_RO_UDWORD
109# define IO_TYPECAST_UWORD
110# define IO_TYPECAST_RO_UWORD
111# define IO_TYPECAST_BYTE
112# define IO_TYPECAST_RO_BYTE
113#endif
114
115/*------------------------------------------------------------*/
116
117#include "sv_addr.agh"
118
119#if __test_sv_addr__
120/* IO_MASK( R_BUS_CONFIG , CE ) */
121IO_MASK( R_WAITSTATES , SRAM_WS )
122IO_MASK( R_TEST , W32 )
123
124IO_STATE( R_BUS_CONFIG, CE, DISABLE )
125IO_STATE( R_BUS_CONFIG, CE, ENABLE )
126
127IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
128
129IO_MASK( R_DRAM_TIMING, REF )
130
131IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
132
133IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S )
134 == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
135#endif
136
137
138#endif /* ifndef __sv_addr_ag_h__ */
139
diff --git a/arch/cris/include/arch-v10/arch/svinto.h b/arch/cris/include/arch-v10/arch/svinto.h
new file mode 100644
index 000000000000..0881a1af7cee
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/svinto.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_CRIS_SVINTO_H
2#define _ASM_CRIS_SVINTO_H
3
4#include "sv_addr_ag.h"
5
6extern unsigned int genconfig_shadow; /* defined and set in head.S */
7
8/* dma stuff */
9
10enum { /* Available in: */
11 d_eol = (1 << 0), /* flags */
12 d_eop = (1 << 1), /* flags & status */
13 d_wait = (1 << 2), /* flags */
14 d_int = (1 << 3), /* flags */
15 d_txerr = (1 << 4), /* flags */
16 d_stop = (1 << 4), /* status */
17 d_ecp = (1 << 4), /* flags & status */
18 d_pri = (1 << 5), /* flags & status */
19 d_alignerr = (1 << 6), /* status */
20 d_crcerr = (1 << 7) /* status */
21};
22
23/* Do remember that DMA does not go through the MMU and needs
24 * a real physical address, not an address virtually mapped or
25 * paged. Therefore the buf/next ptrs below are unsigned long instead
26 * of void * to give a warning if you try to put a pointer directly
27 * to them instead of going through virt_to_phys/phys_to_virt.
28 */
29
30typedef struct etrax_dma_descr {
31 unsigned short sw_len; /* 0-1 */
32 unsigned short ctrl; /* 2-3 */
33 unsigned long next; /* 4-7 */
34 unsigned long buf; /* 8-11 */
35 unsigned short hw_len; /* 12-13 */
36 unsigned char status; /* 14 */
37 unsigned char fifo_len; /* 15 */
38} etrax_dma_descr;
39
40
41/* Use this for constant numbers only */
42#define RESET_DMA_NUM( n ) \
43 *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset )
44
45/* Use this for constant numbers or symbols,
46 * having two macros makes it possible to use constant expressions.
47 */
48#define RESET_DMA( n ) RESET_DMA_NUM( n )
49
50
51/* Use this for constant numbers only */
52#define WAIT_DMA_NUM( n ) \
53 while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \
54 IO_STATE( R_DMA_CH0_CMD, cmd, hold ) )
55
56/* Use this for constant numbers or symbols
57 * having two macros makes it possible to use constant expressions.
58 */
59#define WAIT_DMA( n ) WAIT_DMA_NUM( n )
60
61extern void prepare_rx_descriptor(struct etrax_dma_descr *desc);
62extern void flush_etrax_cache(void);
63
64#endif
diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h
new file mode 100644
index 000000000000..4a9cd36c9e16
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/system.h
@@ -0,0 +1,63 @@
1#ifndef __ASM_CRIS_ARCH_SYSTEM_H
2#define __ASM_CRIS_ARCH_SYSTEM_H
3
4
5/* read the CPU version register */
6
7static inline unsigned long rdvr(void) {
8 unsigned char vr;
9 __asm__ volatile ("move $vr,%0" : "=rm" (vr));
10 return vr;
11}
12
13#define cris_machine_name "cris"
14
15/* read/write the user-mode stackpointer */
16
17static inline unsigned long rdusp(void) {
18 unsigned long usp;
19 __asm__ __volatile__("move $usp,%0" : "=rm" (usp));
20 return usp;
21}
22
23#define wrusp(usp) \
24 __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp))
25
26/* read the current stackpointer */
27
28static inline unsigned long rdsp(void) {
29 unsigned long sp;
30 __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp));
31 return sp;
32}
33
34static inline unsigned long _get_base(char * addr)
35{
36 return 0;
37}
38
39#define nop() __asm__ __volatile__ ("nop");
40
41#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
42#define tas(ptr) (xchg((ptr),1))
43
44struct __xchg_dummy { unsigned long a[100]; };
45#define __xg(x) ((struct __xchg_dummy *)(x))
46
47/* interrupt control.. */
48#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory");
49#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory");
50#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory");
51#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory");
52
53#define irqs_disabled() \
54({ \
55 unsigned long flags; \
56 local_save_flags(flags); \
57 !(flags & (1<<5)); \
58})
59
60/* For spinlocks etc */
61#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory");
62
63#endif
diff --git a/arch/cris/include/arch-v10/arch/thread_info.h b/arch/cris/include/arch-v10/arch/thread_info.h
new file mode 100644
index 000000000000..218f4152d3e5
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/thread_info.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_ARCH_THREAD_INFO_H
2#define _ASM_ARCH_THREAD_INFO_H
3
4/* how to get the thread information struct from C */
5static inline struct thread_info *current_thread_info(void)
6{
7 struct thread_info *ti;
8 __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL));
9 return ti;
10}
11
12#endif
diff --git a/arch/cris/include/arch-v10/arch/timex.h b/arch/cris/include/arch-v10/arch/timex.h
new file mode 100644
index 000000000000..e48447d94faf
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/timex.h
@@ -0,0 +1,30 @@
1/*
2 * Use prescale timer at 25000 Hz instead of the baudrate timer at
3 * 19200 to get rid of the 64ppm to fast timer (and we get better
4 * resolution within a jiffie as well.
5 */
6#ifndef _ASM_CRIS_ARCH_TIMEX_H
7#define _ASM_CRIS_ARCH_TIMEX_H
8
9/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */
10/* If you change anything here you must check time.c as well... */
11#define PRESCALE_FREQ 25000000
12#define PRESCALE_VALUE 1000
13#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */
14/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/
15#define TIMER0_FREQ (CLOCK_TICK_RATE)
16#define TIMER0_CLKSEL flexible
17#define TIMER0_DIV (TIMER0_FREQ/(HZ))
18
19
20#define GET_JIFFIES_USEC() \
21 ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV )
22
23unsigned long get_ns_in_jiffie(void);
24
25static inline unsigned long get_us_in_jiffie_highres(void)
26{
27 return get_ns_in_jiffie()/1000;
28}
29
30#endif
diff --git a/arch/cris/include/arch-v10/arch/tlb.h b/arch/cris/include/arch-v10/arch/tlb.h
new file mode 100644
index 000000000000..31525bbe75c3
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/tlb.h
@@ -0,0 +1,13 @@
1#ifndef _CRIS_ARCH_TLB_H
2#define _CRIS_ARCH_TLB_H
3
4/* The TLB can host up to 64 different mm contexts at the same time.
5 * The last page_id is never running - it is used as an invalid page_id
6 * so we can make TLB entries that will never match.
7 */
8#define NUM_TLB_ENTRIES 64
9#define NUM_PAGEID 64
10#define INVALID_PAGEID 63
11#define NO_CONTEXT -1
12
13#endif
diff --git a/arch/cris/include/arch-v10/arch/uaccess.h b/arch/cris/include/arch-v10/arch/uaccess.h
new file mode 100644
index 000000000000..65b02d9b605a
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/uaccess.h
@@ -0,0 +1,660 @@
1/*
2 * Authors: Bjorn Wesen (bjornw@axis.com)
3 * Hans-Peter Nilsson (hp@axis.com)
4 *
5 */
6#ifndef _CRIS_ARCH_UACCESS_H
7#define _CRIS_ARCH_UACCESS_H
8
9/*
10 * We don't tell gcc that we are accessing memory, but this is OK
11 * because we do not write to any memory gcc knows about, so there
12 * are no aliasing issues.
13 *
14 * Note that PC at a fault is the address *after* the faulting
15 * instruction.
16 */
17#define __put_user_asm(x, addr, err, op) \
18 __asm__ __volatile__( \
19 " "op" %1,[%2]\n" \
20 "2:\n" \
21 " .section .fixup,\"ax\"\n" \
22 "3: move.d %3,%0\n" \
23 " jump 2b\n" \
24 " .previous\n" \
25 " .section __ex_table,\"a\"\n" \
26 " .dword 2b,3b\n" \
27 " .previous\n" \
28 : "=r" (err) \
29 : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
30
31#define __put_user_asm_64(x, addr, err) \
32 __asm__ __volatile__( \
33 " move.d %M1,[%2]\n" \
34 "2: move.d %H1,[%2+4]\n" \
35 "4:\n" \
36 " .section .fixup,\"ax\"\n" \
37 "3: move.d %3,%0\n" \
38 " jump 4b\n" \
39 " .previous\n" \
40 " .section __ex_table,\"a\"\n" \
41 " .dword 2b,3b\n" \
42 " .dword 4b,3b\n" \
43 " .previous\n" \
44 : "=r" (err) \
45 : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
46
47/* See comment before __put_user_asm. */
48
49#define __get_user_asm(x, addr, err, op) \
50 __asm__ __volatile__( \
51 " "op" [%2],%1\n" \
52 "2:\n" \
53 " .section .fixup,\"ax\"\n" \
54 "3: move.d %3,%0\n" \
55 " moveq 0,%1\n" \
56 " jump 2b\n" \
57 " .previous\n" \
58 " .section __ex_table,\"a\"\n" \
59 " .dword 2b,3b\n" \
60 " .previous\n" \
61 : "=r" (err), "=r" (x) \
62 : "r" (addr), "g" (-EFAULT), "0" (err))
63
64#define __get_user_asm_64(x, addr, err) \
65 __asm__ __volatile__( \
66 " move.d [%2],%M1\n" \
67 "2: move.d [%2+4],%H1\n" \
68 "4:\n" \
69 " .section .fixup,\"ax\"\n" \
70 "3: move.d %3,%0\n" \
71 " moveq 0,%1\n" \
72 " jump 4b\n" \
73 " .previous\n" \
74 " .section __ex_table,\"a\"\n" \
75 " .dword 2b,3b\n" \
76 " .dword 4b,3b\n" \
77 " .previous\n" \
78 : "=r" (err), "=r" (x) \
79 : "r" (addr), "g" (-EFAULT), "0" (err))
80
81/*
82 * Copy a null terminated string from userspace.
83 *
84 * Must return:
85 * -EFAULT for an exception
86 * count if we hit the buffer limit
87 * bytes copied if we hit a null byte
88 * (without the null byte)
89 */
90static inline long
91__do_strncpy_from_user(char *dst, const char *src, long count)
92{
93 long res;
94
95 if (count == 0)
96 return 0;
97
98 /*
99 * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
100 * So do we.
101 *
102 * This code is deduced from:
103 *
104 * char tmp2;
105 * long tmp1, tmp3
106 * tmp1 = count;
107 * while ((*dst++ = (tmp2 = *src++)) != 0
108 * && --tmp1)
109 * ;
110 *
111 * res = count - tmp1;
112 *
113 * with tweaks.
114 */
115
116 __asm__ __volatile__ (
117 " move.d %3,%0\n"
118 " move.b [%2+],$r9\n"
119 "1: beq 2f\n"
120 " move.b $r9,[%1+]\n"
121
122 " subq 1,%0\n"
123 " bne 1b\n"
124 " move.b [%2+],$r9\n"
125
126 "2: sub.d %3,%0\n"
127 " neg.d %0,%0\n"
128 "3:\n"
129 " .section .fixup,\"ax\"\n"
130 "4: move.d %7,%0\n"
131 " jump 3b\n"
132
133 /* There's one address for a fault at the first move, and
134 two possible PC values for a fault at the second move,
135 being a delay-slot filler. However, the branch-target
136 for the second move is the same as the first address.
137 Just so you don't get confused... */
138 " .previous\n"
139 " .section __ex_table,\"a\"\n"
140 " .dword 1b,4b\n"
141 " .dword 2b,4b\n"
142 " .previous"
143 : "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
144 : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
145 : "r9");
146
147 return res;
148}
149
150/* A few copy asms to build up the more complex ones from.
151
152 Note again, a post-increment is performed regardless of whether a bus
153 fault occurred in that instruction, and PC for a faulted insn is the
154 address *after* the insn. */
155
156#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
157 __asm__ __volatile__ ( \
158 COPY \
159 "1:\n" \
160 " .section .fixup,\"ax\"\n" \
161 FIXUP \
162 " jump 1b\n" \
163 " .previous\n" \
164 " .section __ex_table,\"a\"\n" \
165 TENTRY \
166 " .previous\n" \
167 : "=r" (to), "=r" (from), "=r" (ret) \
168 : "0" (to), "1" (from), "2" (ret) \
169 : "r9", "memory")
170
171#define __asm_copy_from_user_1(to, from, ret) \
172 __asm_copy_user_cont(to, from, ret, \
173 " move.b [%1+],$r9\n" \
174 "2: move.b $r9,[%0+]\n", \
175 "3: addq 1,%2\n" \
176 " clear.b [%0+]\n", \
177 " .dword 2b,3b\n")
178
179#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
180 __asm_copy_user_cont(to, from, ret, \
181 " move.w [%1+],$r9\n" \
182 "2: move.w $r9,[%0+]\n" COPY, \
183 "3: addq 2,%2\n" \
184 " clear.w [%0+]\n" FIXUP, \
185 " .dword 2b,3b\n" TENTRY)
186
187#define __asm_copy_from_user_2(to, from, ret) \
188 __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
189
190#define __asm_copy_from_user_3(to, from, ret) \
191 __asm_copy_from_user_2x_cont(to, from, ret, \
192 " move.b [%1+],$r9\n" \
193 "4: move.b $r9,[%0+]\n", \
194 "5: addq 1,%2\n" \
195 " clear.b [%0+]\n", \
196 " .dword 4b,5b\n")
197
198#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
199 __asm_copy_user_cont(to, from, ret, \
200 " move.d [%1+],$r9\n" \
201 "2: move.d $r9,[%0+]\n" COPY, \
202 "3: addq 4,%2\n" \
203 " clear.d [%0+]\n" FIXUP, \
204 " .dword 2b,3b\n" TENTRY)
205
206#define __asm_copy_from_user_4(to, from, ret) \
207 __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
208
209#define __asm_copy_from_user_5(to, from, ret) \
210 __asm_copy_from_user_4x_cont(to, from, ret, \
211 " move.b [%1+],$r9\n" \
212 "4: move.b $r9,[%0+]\n", \
213 "5: addq 1,%2\n" \
214 " clear.b [%0+]\n", \
215 " .dword 4b,5b\n")
216
217#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
218 __asm_copy_from_user_4x_cont(to, from, ret, \
219 " move.w [%1+],$r9\n" \
220 "4: move.w $r9,[%0+]\n" COPY, \
221 "5: addq 2,%2\n" \
222 " clear.w [%0+]\n" FIXUP, \
223 " .dword 4b,5b\n" TENTRY)
224
225#define __asm_copy_from_user_6(to, from, ret) \
226 __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
227
228#define __asm_copy_from_user_7(to, from, ret) \
229 __asm_copy_from_user_6x_cont(to, from, ret, \
230 " move.b [%1+],$r9\n" \
231 "6: move.b $r9,[%0+]\n", \
232 "7: addq 1,%2\n" \
233 " clear.b [%0+]\n", \
234 " .dword 6b,7b\n")
235
236#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
237 __asm_copy_from_user_4x_cont(to, from, ret, \
238 " move.d [%1+],$r9\n" \
239 "4: move.d $r9,[%0+]\n" COPY, \
240 "5: addq 4,%2\n" \
241 " clear.d [%0+]\n" FIXUP, \
242 " .dword 4b,5b\n" TENTRY)
243
244#define __asm_copy_from_user_8(to, from, ret) \
245 __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
246
247#define __asm_copy_from_user_9(to, from, ret) \
248 __asm_copy_from_user_8x_cont(to, from, ret, \
249 " move.b [%1+],$r9\n" \
250 "6: move.b $r9,[%0+]\n", \
251 "7: addq 1,%2\n" \
252 " clear.b [%0+]\n", \
253 " .dword 6b,7b\n")
254
255#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
256 __asm_copy_from_user_8x_cont(to, from, ret, \
257 " move.w [%1+],$r9\n" \
258 "6: move.w $r9,[%0+]\n" COPY, \
259 "7: addq 2,%2\n" \
260 " clear.w [%0+]\n" FIXUP, \
261 " .dword 6b,7b\n" TENTRY)
262
263#define __asm_copy_from_user_10(to, from, ret) \
264 __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
265
266#define __asm_copy_from_user_11(to, from, ret) \
267 __asm_copy_from_user_10x_cont(to, from, ret, \
268 " move.b [%1+],$r9\n" \
269 "8: move.b $r9,[%0+]\n", \
270 "9: addq 1,%2\n" \
271 " clear.b [%0+]\n", \
272 " .dword 8b,9b\n")
273
274#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
275 __asm_copy_from_user_8x_cont(to, from, ret, \
276 " move.d [%1+],$r9\n" \
277 "6: move.d $r9,[%0+]\n" COPY, \
278 "7: addq 4,%2\n" \
279 " clear.d [%0+]\n" FIXUP, \
280 " .dword 6b,7b\n" TENTRY)
281
282#define __asm_copy_from_user_12(to, from, ret) \
283 __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
284
285#define __asm_copy_from_user_13(to, from, ret) \
286 __asm_copy_from_user_12x_cont(to, from, ret, \
287 " move.b [%1+],$r9\n" \
288 "8: move.b $r9,[%0+]\n", \
289 "9: addq 1,%2\n" \
290 " clear.b [%0+]\n", \
291 " .dword 8b,9b\n")
292
293#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
294 __asm_copy_from_user_12x_cont(to, from, ret, \
295 " move.w [%1+],$r9\n" \
296 "8: move.w $r9,[%0+]\n" COPY, \
297 "9: addq 2,%2\n" \
298 " clear.w [%0+]\n" FIXUP, \
299 " .dword 8b,9b\n" TENTRY)
300
301#define __asm_copy_from_user_14(to, from, ret) \
302 __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
303
304#define __asm_copy_from_user_15(to, from, ret) \
305 __asm_copy_from_user_14x_cont(to, from, ret, \
306 " move.b [%1+],$r9\n" \
307 "10: move.b $r9,[%0+]\n", \
308 "11: addq 1,%2\n" \
309 " clear.b [%0+]\n", \
310 " .dword 10b,11b\n")
311
312#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
313 __asm_copy_from_user_12x_cont(to, from, ret, \
314 " move.d [%1+],$r9\n" \
315 "8: move.d $r9,[%0+]\n" COPY, \
316 "9: addq 4,%2\n" \
317 " clear.d [%0+]\n" FIXUP, \
318 " .dword 8b,9b\n" TENTRY)
319
320#define __asm_copy_from_user_16(to, from, ret) \
321 __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
322
323#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
324 __asm_copy_from_user_16x_cont(to, from, ret, \
325 " move.d [%1+],$r9\n" \
326 "10: move.d $r9,[%0+]\n" COPY, \
327 "11: addq 4,%2\n" \
328 " clear.d [%0+]\n" FIXUP, \
329 " .dword 10b,11b\n" TENTRY)
330
331#define __asm_copy_from_user_20(to, from, ret) \
332 __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
333
334#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
335 __asm_copy_from_user_20x_cont(to, from, ret, \
336 " move.d [%1+],$r9\n" \
337 "12: move.d $r9,[%0+]\n" COPY, \
338 "13: addq 4,%2\n" \
339 " clear.d [%0+]\n" FIXUP, \
340 " .dword 12b,13b\n" TENTRY)
341
342#define __asm_copy_from_user_24(to, from, ret) \
343 __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
344
345/* And now, the to-user ones. */
346
347#define __asm_copy_to_user_1(to, from, ret) \
348 __asm_copy_user_cont(to, from, ret, \
349 " move.b [%1+],$r9\n" \
350 " move.b $r9,[%0+]\n2:\n", \
351 "3: addq 1,%2\n", \
352 " .dword 2b,3b\n")
353
354#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
355 __asm_copy_user_cont(to, from, ret, \
356 " move.w [%1+],$r9\n" \
357 " move.w $r9,[%0+]\n2:\n" COPY, \
358 "3: addq 2,%2\n" FIXUP, \
359 " .dword 2b,3b\n" TENTRY)
360
361#define __asm_copy_to_user_2(to, from, ret) \
362 __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
363
364#define __asm_copy_to_user_3(to, from, ret) \
365 __asm_copy_to_user_2x_cont(to, from, ret, \
366 " move.b [%1+],$r9\n" \
367 " move.b $r9,[%0+]\n4:\n", \
368 "5: addq 1,%2\n", \
369 " .dword 4b,5b\n")
370
371#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
372 __asm_copy_user_cont(to, from, ret, \
373 " move.d [%1+],$r9\n" \
374 " move.d $r9,[%0+]\n2:\n" COPY, \
375 "3: addq 4,%2\n" FIXUP, \
376 " .dword 2b,3b\n" TENTRY)
377
378#define __asm_copy_to_user_4(to, from, ret) \
379 __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
380
381#define __asm_copy_to_user_5(to, from, ret) \
382 __asm_copy_to_user_4x_cont(to, from, ret, \
383 " move.b [%1+],$r9\n" \
384 " move.b $r9,[%0+]\n4:\n", \
385 "5: addq 1,%2\n", \
386 " .dword 4b,5b\n")
387
388#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
389 __asm_copy_to_user_4x_cont(to, from, ret, \
390 " move.w [%1+],$r9\n" \
391 " move.w $r9,[%0+]\n4:\n" COPY, \
392 "5: addq 2,%2\n" FIXUP, \
393 " .dword 4b,5b\n" TENTRY)
394
395#define __asm_copy_to_user_6(to, from, ret) \
396 __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
397
398#define __asm_copy_to_user_7(to, from, ret) \
399 __asm_copy_to_user_6x_cont(to, from, ret, \
400 " move.b [%1+],$r9\n" \
401 " move.b $r9,[%0+]\n6:\n", \
402 "7: addq 1,%2\n", \
403 " .dword 6b,7b\n")
404
405#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
406 __asm_copy_to_user_4x_cont(to, from, ret, \
407 " move.d [%1+],$r9\n" \
408 " move.d $r9,[%0+]\n4:\n" COPY, \
409 "5: addq 4,%2\n" FIXUP, \
410 " .dword 4b,5b\n" TENTRY)
411
412#define __asm_copy_to_user_8(to, from, ret) \
413 __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
414
415#define __asm_copy_to_user_9(to, from, ret) \
416 __asm_copy_to_user_8x_cont(to, from, ret, \
417 " move.b [%1+],$r9\n" \
418 " move.b $r9,[%0+]\n6:\n", \
419 "7: addq 1,%2\n", \
420 " .dword 6b,7b\n")
421
422#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
423 __asm_copy_to_user_8x_cont(to, from, ret, \
424 " move.w [%1+],$r9\n" \
425 " move.w $r9,[%0+]\n6:\n" COPY, \
426 "7: addq 2,%2\n" FIXUP, \
427 " .dword 6b,7b\n" TENTRY)
428
429#define __asm_copy_to_user_10(to, from, ret) \
430 __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
431
432#define __asm_copy_to_user_11(to, from, ret) \
433 __asm_copy_to_user_10x_cont(to, from, ret, \
434 " move.b [%1+],$r9\n" \
435 " move.b $r9,[%0+]\n8:\n", \
436 "9: addq 1,%2\n", \
437 " .dword 8b,9b\n")
438
439#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
440 __asm_copy_to_user_8x_cont(to, from, ret, \
441 " move.d [%1+],$r9\n" \
442 " move.d $r9,[%0+]\n6:\n" COPY, \
443 "7: addq 4,%2\n" FIXUP, \
444 " .dword 6b,7b\n" TENTRY)
445
446#define __asm_copy_to_user_12(to, from, ret) \
447 __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
448
449#define __asm_copy_to_user_13(to, from, ret) \
450 __asm_copy_to_user_12x_cont(to, from, ret, \
451 " move.b [%1+],$r9\n" \
452 " move.b $r9,[%0+]\n8:\n", \
453 "9: addq 1,%2\n", \
454 " .dword 8b,9b\n")
455
456#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
457 __asm_copy_to_user_12x_cont(to, from, ret, \
458 " move.w [%1+],$r9\n" \
459 " move.w $r9,[%0+]\n8:\n" COPY, \
460 "9: addq 2,%2\n" FIXUP, \
461 " .dword 8b,9b\n" TENTRY)
462
463#define __asm_copy_to_user_14(to, from, ret) \
464 __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
465
466#define __asm_copy_to_user_15(to, from, ret) \
467 __asm_copy_to_user_14x_cont(to, from, ret, \
468 " move.b [%1+],$r9\n" \
469 " move.b $r9,[%0+]\n10:\n", \
470 "11: addq 1,%2\n", \
471 " .dword 10b,11b\n")
472
473#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
474 __asm_copy_to_user_12x_cont(to, from, ret, \
475 " move.d [%1+],$r9\n" \
476 " move.d $r9,[%0+]\n8:\n" COPY, \
477 "9: addq 4,%2\n" FIXUP, \
478 " .dword 8b,9b\n" TENTRY)
479
480#define __asm_copy_to_user_16(to, from, ret) \
481 __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
482
483#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
484 __asm_copy_to_user_16x_cont(to, from, ret, \
485 " move.d [%1+],$r9\n" \
486 " move.d $r9,[%0+]\n10:\n" COPY, \
487 "11: addq 4,%2\n" FIXUP, \
488 " .dword 10b,11b\n" TENTRY)
489
490#define __asm_copy_to_user_20(to, from, ret) \
491 __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
492
493#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
494 __asm_copy_to_user_20x_cont(to, from, ret, \
495 " move.d [%1+],$r9\n" \
496 " move.d $r9,[%0+]\n12:\n" COPY, \
497 "13: addq 4,%2\n" FIXUP, \
498 " .dword 12b,13b\n" TENTRY)
499
500#define __asm_copy_to_user_24(to, from, ret) \
501 __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
502
503/* Define a few clearing asms with exception handlers. */
504
505/* This frame-asm is like the __asm_copy_user_cont one, but has one less
506 input. */
507
508#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
509 __asm__ __volatile__ ( \
510 CLEAR \
511 "1:\n" \
512 " .section .fixup,\"ax\"\n" \
513 FIXUP \
514 " jump 1b\n" \
515 " .previous\n" \
516 " .section __ex_table,\"a\"\n" \
517 TENTRY \
518 " .previous" \
519 : "=r" (to), "=r" (ret) \
520 : "0" (to), "1" (ret) \
521 : "memory")
522
523#define __asm_clear_1(to, ret) \
524 __asm_clear(to, ret, \
525 " clear.b [%0+]\n2:\n", \
526 "3: addq 1,%1\n", \
527 " .dword 2b,3b\n")
528
529#define __asm_clear_2(to, ret) \
530 __asm_clear(to, ret, \
531 " clear.w [%0+]\n2:\n", \
532 "3: addq 2,%1\n", \
533 " .dword 2b,3b\n")
534
535#define __asm_clear_3(to, ret) \
536 __asm_clear(to, ret, \
537 " clear.w [%0+]\n" \
538 "2: clear.b [%0+]\n3:\n", \
539 "4: addq 2,%1\n" \
540 "5: addq 1,%1\n", \
541 " .dword 2b,4b\n" \
542 " .dword 3b,5b\n")
543
544#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
545 __asm_clear(to, ret, \
546 " clear.d [%0+]\n2:\n" CLEAR, \
547 "3: addq 4,%1\n" FIXUP, \
548 " .dword 2b,3b\n" TENTRY)
549
550#define __asm_clear_4(to, ret) \
551 __asm_clear_4x_cont(to, ret, "", "", "")
552
553#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
554 __asm_clear_4x_cont(to, ret, \
555 " clear.d [%0+]\n4:\n" CLEAR, \
556 "5: addq 4,%1\n" FIXUP, \
557 " .dword 4b,5b\n" TENTRY)
558
559#define __asm_clear_8(to, ret) \
560 __asm_clear_8x_cont(to, ret, "", "", "")
561
562#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
563 __asm_clear_8x_cont(to, ret, \
564 " clear.d [%0+]\n6:\n" CLEAR, \
565 "7: addq 4,%1\n" FIXUP, \
566 " .dword 6b,7b\n" TENTRY)
567
568#define __asm_clear_12(to, ret) \
569 __asm_clear_12x_cont(to, ret, "", "", "")
570
571#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
572 __asm_clear_12x_cont(to, ret, \
573 " clear.d [%0+]\n8:\n" CLEAR, \
574 "9: addq 4,%1\n" FIXUP, \
575 " .dword 8b,9b\n" TENTRY)
576
577#define __asm_clear_16(to, ret) \
578 __asm_clear_16x_cont(to, ret, "", "", "")
579
580#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
581 __asm_clear_16x_cont(to, ret, \
582 " clear.d [%0+]\n10:\n" CLEAR, \
583 "11: addq 4,%1\n" FIXUP, \
584 " .dword 10b,11b\n" TENTRY)
585
586#define __asm_clear_20(to, ret) \
587 __asm_clear_20x_cont(to, ret, "", "", "")
588
589#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
590 __asm_clear_20x_cont(to, ret, \
591 " clear.d [%0+]\n12:\n" CLEAR, \
592 "13: addq 4,%1\n" FIXUP, \
593 " .dword 12b,13b\n" TENTRY)
594
595#define __asm_clear_24(to, ret) \
596 __asm_clear_24x_cont(to, ret, "", "", "")
597
598/*
599 * Return the size of a string (including the ending 0)
600 *
601 * Return length of string in userspace including terminating 0
602 * or 0 for error. Return a value greater than N if too long.
603 */
604
605static inline long
606strnlen_user(const char *s, long n)
607{
608 long res, tmp1;
609
610 if (!access_ok(VERIFY_READ, s, 0))
611 return 0;
612
613 /*
614 * This code is deduced from:
615 *
616 * tmp1 = n;
617 * while (tmp1-- > 0 && *s++)
618 * ;
619 *
620 * res = n - tmp1;
621 *
622 * (with tweaks).
623 */
624
625 __asm__ __volatile__ (
626 " move.d %1,$r9\n"
627 "0:\n"
628 " ble 1f\n"
629 " subq 1,$r9\n"
630
631 " test.b [%0+]\n"
632 " bne 0b\n"
633 " test.d $r9\n"
634 "1:\n"
635 " move.d %1,%0\n"
636 " sub.d $r9,%0\n"
637 "2:\n"
638 " .section .fixup,\"ax\"\n"
639
640 "3: clear.d %0\n"
641 " jump 2b\n"
642
643 /* There's one address for a fault at the first move, and
644 two possible PC values for a fault at the second move,
645 being a delay-slot filler. However, the branch-target
646 for the second move is the same as the first address.
647 Just so you don't get confused... */
648 " .previous\n"
649 " .section __ex_table,\"a\"\n"
650 " .dword 0b,3b\n"
651 " .dword 1b,3b\n"
652 " .previous\n"
653 : "=r" (res), "=r" (tmp1)
654 : "0" (s), "1" (n)
655 : "r9");
656
657 return res;
658}
659
660#endif
diff --git a/arch/cris/include/arch-v10/arch/unistd.h b/arch/cris/include/arch-v10/arch/unistd.h
new file mode 100644
index 000000000000..d1a38b9e6264
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/unistd.h
@@ -0,0 +1,148 @@
1#ifndef _ASM_CRIS_ARCH_UNISTD_H_
2#define _ASM_CRIS_ARCH_UNISTD_H_
3
4/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
5/*
6 * Don't remove the .ifnc tests; they are an insurance against
7 * any hard-to-spot gcc register allocation bugs.
8 */
9#define _syscall0(type,name) \
10type name(void) \
11{ \
12 register long __a __asm__ ("r10"); \
13 register long __n_ __asm__ ("r9") = (__NR_##name); \
14 __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
15 ".err\n\t" \
16 ".endif\n\t" \
17 "break 13" \
18 : "=r" (__a) \
19 : "r" (__n_)); \
20 if (__a >= 0) \
21 return (type) __a; \
22 errno = -__a; \
23 return (type) -1; \
24}
25
26#define _syscall1(type,name,type1,arg1) \
27type name(type1 arg1) \
28{ \
29 register long __a __asm__ ("r10") = (long) arg1; \
30 register long __n_ __asm__ ("r9") = (__NR_##name); \
31 __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
32 ".err\n\t" \
33 ".endif\n\t" \
34 "break 13" \
35 : "=r" (__a) \
36 : "r" (__n_), "0" (__a)); \
37 if (__a >= 0) \
38 return (type) __a; \
39 errno = -__a; \
40 return (type) -1; \
41}
42
43#define _syscall2(type,name,type1,arg1,type2,arg2) \
44type name(type1 arg1,type2 arg2) \
45{ \
46 register long __a __asm__ ("r10") = (long) arg1; \
47 register long __b __asm__ ("r11") = (long) arg2; \
48 register long __n_ __asm__ ("r9") = (__NR_##name); \
49 __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
50 ".err\n\t" \
51 ".endif\n\t" \
52 "break 13" \
53 : "=r" (__a) \
54 : "r" (__n_), "0" (__a), "r" (__b)); \
55 if (__a >= 0) \
56 return (type) __a; \
57 errno = -__a; \
58 return (type) -1; \
59}
60
61#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
62type name(type1 arg1,type2 arg2,type3 arg3) \
63{ \
64 register long __a __asm__ ("r10") = (long) arg1; \
65 register long __b __asm__ ("r11") = (long) arg2; \
66 register long __c __asm__ ("r12") = (long) arg3; \
67 register long __n_ __asm__ ("r9") = (__NR_##name); \
68 __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
69 ".err\n\t" \
70 ".endif\n\t" \
71 "break 13" \
72 : "=r" (__a) \
73 : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
74 if (__a >= 0) \
75 return (type) __a; \
76 errno = -__a; \
77 return (type) -1; \
78}
79
80#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
81type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
82{ \
83 register long __a __asm__ ("r10") = (long) arg1; \
84 register long __b __asm__ ("r11") = (long) arg2; \
85 register long __c __asm__ ("r12") = (long) arg3; \
86 register long __d __asm__ ("r13") = (long) arg4; \
87 register long __n_ __asm__ ("r9") = (__NR_##name); \
88 __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
89 ".err\n\t" \
90 ".endif\n\t" \
91 "break 13" \
92 : "=r" (__a) \
93 : "r" (__n_), "0" (__a), "r" (__b), \
94 "r" (__c), "r" (__d)); \
95 if (__a >= 0) \
96 return (type) __a; \
97 errno = -__a; \
98 return (type) -1; \
99}
100
101#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
102 type5,arg5) \
103type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
104{ \
105 register long __a __asm__ ("r10") = (long) arg1; \
106 register long __b __asm__ ("r11") = (long) arg2; \
107 register long __c __asm__ ("r12") = (long) arg3; \
108 register long __d __asm__ ("r13") = (long) arg4; \
109 register long __n_ __asm__ ("r9") = (__NR_##name); \
110 __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
111 ".err\n\t" \
112 ".endif\n\t" \
113 "move %6,$mof\n\t" \
114 "break 13" \
115 : "=r" (__a) \
116 : "r" (__n_), "0" (__a), "r" (__b), \
117 "r" (__c), "r" (__d), "g" (arg5)); \
118 if (__a >= 0) \
119 return (type) __a; \
120 errno = -__a; \
121 return (type) -1; \
122}
123
124#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
125 type5,arg5,type6,arg6) \
126type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
127{ \
128 register long __a __asm__ ("r10") = (long) arg1; \
129 register long __b __asm__ ("r11") = (long) arg2; \
130 register long __c __asm__ ("r12") = (long) arg3; \
131 register long __d __asm__ ("r13") = (long) arg4; \
132 register long __n_ __asm__ ("r9") = (__NR_##name); \
133 __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
134 ".err\n\t" \
135 ".endif\n\t" \
136 "move %6,$mof\n\tmove %7,$srp\n\t" \
137 "break 13" \
138 : "=r" (__a) \
139 : "r" (__n_), "0" (__a), "r" (__b), \
140 "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\
141 : "srp"); \
142 if (__a >= 0) \
143 return (type) __a; \
144 errno = -__a; \
145 return (type) -1; \
146}
147
148#endif
diff --git a/arch/cris/include/arch-v10/arch/user.h b/arch/cris/include/arch-v10/arch/user.h
new file mode 100644
index 000000000000..9303ea77c915
--- /dev/null
+++ b/arch/cris/include/arch-v10/arch/user.h
@@ -0,0 +1,46 @@
1#ifndef __ASM_CRIS_ARCH_USER_H
2#define __ASM_CRIS_ARCH_USER_H
3
4/* User mode registers, used for core dumps. In order to keep ELF_NGREG
5 sensible we let all registers be 32 bits. The csr registers are included
6 for future use. */
7struct user_regs_struct {
8 unsigned long r0; /* General registers. */
9 unsigned long r1;
10 unsigned long r2;
11 unsigned long r3;
12 unsigned long r4;
13 unsigned long r5;
14 unsigned long r6;
15 unsigned long r7;
16 unsigned long r8;
17 unsigned long r9;
18 unsigned long r10;
19 unsigned long r11;
20 unsigned long r12;
21 unsigned long r13;
22 unsigned long sp; /* Stack pointer. */
23 unsigned long pc; /* Program counter. */
24 unsigned long p0; /* Constant zero (only 8 bits). */
25 unsigned long vr; /* Version register (only 8 bits). */
26 unsigned long p2; /* Reserved. */
27 unsigned long p3; /* Reserved. */
28 unsigned long p4; /* Constant zero (only 16 bits). */
29 unsigned long ccr; /* Condition code register (only 16 bits). */
30 unsigned long p6; /* Reserved. */
31 unsigned long mof; /* Multiply overflow register. */
32 unsigned long p8; /* Constant zero. */
33 unsigned long ibr; /* Not accessible. */
34 unsigned long irp; /* Not accessible. */
35 unsigned long srp; /* Subroutine return pointer. */
36 unsigned long bar; /* Not accessible. */
37 unsigned long dccr; /* Dword condition code register. */
38 unsigned long brp; /* Not accessible. */
39 unsigned long usp; /* User-mode stack pointer. Same as sp when
40 in user mode. */
41 unsigned long csrinstr; /* Internal status registers. */
42 unsigned long csraddr;
43 unsigned long csrdata;
44};
45
46#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 01:08:54 -0500