diff options
author | Jesper Nilsson <jesper.nilsson@axis.com> | 2010-08-03 07:52:45 -0400 |
---|---|---|
committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2010-08-04 07:00:45 -0400 |
commit | e75a320edab4170f28f6cce22d4ea5c15f13ecfa (patch) | |
tree | 8eb7854641ecedddb74b56ad19d9cd576ecec59d /arch/cris/arch-v32 | |
parent | 403a1c4f1380b4ec842df5f4aa86e86ba02904f3 (diff) |
CRIS: v32: Better irq mapping code
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch/cris/arch-v32')
-rw-r--r-- | arch/cris/arch-v32/kernel/irq.c | 47 |
1 files changed, 22 insertions, 25 deletions
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index 0b1febe44aa3..2ed48ae3d313 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c | |||
@@ -97,7 +97,11 @@ extern void breakh_BUG(void); | |||
97 | /* | 97 | /* |
98 | * Build the IRQ handler stubs using macros from irq.h. | 98 | * Build the IRQ handler stubs using macros from irq.h. |
99 | */ | 99 | */ |
100 | #ifdef CONFIG_CRIS_MACH_ARTPEC3 | ||
101 | BUILD_TIMER_IRQ(0x31, 0) | ||
102 | #else | ||
100 | BUILD_IRQ(0x31) | 103 | BUILD_IRQ(0x31) |
104 | #endif | ||
101 | BUILD_IRQ(0x32) | 105 | BUILD_IRQ(0x32) |
102 | BUILD_IRQ(0x33) | 106 | BUILD_IRQ(0x33) |
103 | BUILD_IRQ(0x34) | 107 | BUILD_IRQ(0x34) |
@@ -123,7 +127,11 @@ BUILD_IRQ(0x47) | |||
123 | BUILD_IRQ(0x48) | 127 | BUILD_IRQ(0x48) |
124 | BUILD_IRQ(0x49) | 128 | BUILD_IRQ(0x49) |
125 | BUILD_IRQ(0x4a) | 129 | BUILD_IRQ(0x4a) |
130 | #ifdef CONFIG_ETRAXFS | ||
131 | BUILD_TIMER_IRQ(0x4b, 0) | ||
132 | #else | ||
126 | BUILD_IRQ(0x4b) | 133 | BUILD_IRQ(0x4b) |
134 | #endif | ||
127 | BUILD_IRQ(0x4c) | 135 | BUILD_IRQ(0x4c) |
128 | BUILD_IRQ(0x4d) | 136 | BUILD_IRQ(0x4d) |
129 | BUILD_IRQ(0x4e) | 137 | BUILD_IRQ(0x4e) |
@@ -199,25 +207,20 @@ block_irq(int irq, int cpu) | |||
199 | unsigned long flags; | 207 | unsigned long flags; |
200 | 208 | ||
201 | spin_lock_irqsave(&irq_lock, flags); | 209 | spin_lock_irqsave(&irq_lock, flags); |
202 | if (irq - FIRST_IRQ < 32) | 210 | /* Remember, 1 let thru, 0 block. */ |
211 | if (irq - FIRST_IRQ < 32) { | ||
203 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | 212 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], |
204 | rw_mask, 0); | 213 | rw_mask, 0); |
205 | else | ||
206 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | ||
207 | rw_mask, 1); | ||
208 | |||
209 | /* Remember; 1 let thru, 0 block. */ | ||
210 | if (irq - FIRST_IRQ < 32) | ||
211 | intr_mask &= ~(1 << (irq - FIRST_IRQ)); | 214 | intr_mask &= ~(1 << (irq - FIRST_IRQ)); |
212 | else | ||
213 | intr_mask &= ~(1 << (irq - FIRST_IRQ - 32)); | ||
214 | |||
215 | if (irq - FIRST_IRQ < 32) | ||
216 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, | 215 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, |
217 | 0, intr_mask); | 216 | 0, intr_mask); |
218 | else | 217 | } else { |
218 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | ||
219 | rw_mask, 1); | ||
220 | intr_mask &= ~(1 << (irq - FIRST_IRQ - 32)); | ||
219 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, | 221 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, |
220 | 1, intr_mask); | 222 | 1, intr_mask); |
223 | } | ||
221 | spin_unlock_irqrestore(&irq_lock, flags); | 224 | spin_unlock_irqrestore(&irq_lock, flags); |
222 | } | 225 | } |
223 | 226 | ||
@@ -228,26 +231,20 @@ unblock_irq(int irq, int cpu) | |||
228 | unsigned long flags; | 231 | unsigned long flags; |
229 | 232 | ||
230 | spin_lock_irqsave(&irq_lock, flags); | 233 | spin_lock_irqsave(&irq_lock, flags); |
231 | if (irq - FIRST_IRQ < 32) | 234 | /* Remember, 1 let thru, 0 block. */ |
235 | if (irq - FIRST_IRQ < 32) { | ||
232 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | 236 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], |
233 | rw_mask, 0); | 237 | rw_mask, 0); |
234 | else | ||
235 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | ||
236 | rw_mask, 1); | ||
237 | |||
238 | /* Remember; 1 let thru, 0 block. */ | ||
239 | if (irq - FIRST_IRQ < 32) | ||
240 | intr_mask |= (1 << (irq - FIRST_IRQ)); | 238 | intr_mask |= (1 << (irq - FIRST_IRQ)); |
241 | else | ||
242 | intr_mask |= (1 << (irq - FIRST_IRQ - 32)); | ||
243 | |||
244 | if (irq - FIRST_IRQ < 32) | ||
245 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, | 239 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, |
246 | 0, intr_mask); | 240 | 0, intr_mask); |
247 | else | 241 | } else { |
242 | intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], | ||
243 | rw_mask, 1); | ||
244 | intr_mask |= (1 << (irq - FIRST_IRQ - 32)); | ||
248 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, | 245 | REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, |
249 | 1, intr_mask); | 246 | 1, intr_mask); |
250 | 247 | } | |
251 | spin_unlock_irqrestore(&irq_lock, flags); | 248 | spin_unlock_irqrestore(&irq_lock, flags); |
252 | } | 249 | } |
253 | 250 | ||