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authorJesper Nilsson <jespern@stork.se.axis.com>2007-11-29 11:11:23 -0500
committerJesper Nilsson <jesper.nilsson@axis.com>2008-02-08 05:06:23 -0500
commit035e111f9a9b29843bc899f03d56f19d94bebb53 (patch)
treecb46b3c0eb6d9f2cc915522153454d3acaa7fcda /arch/cris/arch-v32/kernel
parent6107c61fd3e6b47106b078db1726ad814564efef (diff)
CRIS v32: Add new machine dependent files for Etrax-FS and Artpec-3.
The two chips are somewhat different, and needs different handling. Adds handing of the dma, dram initialization, hardware settings, io, memory arbiter and pinmux Also moves the dma, dram initialization and io from CRIS v32 common files.
Diffstat (limited to 'arch/cris/arch-v32/kernel')
-rw-r--r--arch/cris/arch-v32/kernel/dma.c224
-rw-r--r--arch/cris/arch-v32/kernel/io.c153
2 files changed, 0 insertions, 377 deletions
diff --git a/arch/cris/arch-v32/kernel/dma.c b/arch/cris/arch-v32/kernel/dma.c
deleted file mode 100644
index 570e19128ffd..000000000000
--- a/arch/cris/arch-v32/kernel/dma.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* Wrapper for DMA channel allocator that starts clocks etc */
2
3#include <linux/kernel.h>
4#include <linux/spinlock.h>
5#include <asm/dma.h>
6#include <asm/arch/hwregs/reg_map.h>
7#include <asm/arch/hwregs/reg_rdwr.h>
8#include <asm/arch/hwregs/marb_defs.h>
9#include <asm/arch/hwregs/config_defs.h>
10#include <asm/arch/hwregs/strmux_defs.h>
11#include <linux/errno.h>
12#include <asm/system.h>
13#include <asm/arch/arbiter.h>
14
15static char used_dma_channels[MAX_DMA_CHANNELS];
16static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
17
18static DEFINE_SPINLOCK(dma_lock);
19
20int crisv32_request_dma(unsigned int dmanr, const char * device_id,
21 unsigned options, unsigned int bandwidth,
22 enum dma_owner owner)
23{
24 unsigned long flags;
25 reg_config_rw_clk_ctrl clk_ctrl;
26 reg_strmux_rw_cfg strmux_cfg;
27
28 if (crisv32_arbiter_allocate_bandwidth(dmanr,
29 options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
30 bandwidth))
31 return -ENOMEM;
32
33 spin_lock_irqsave(&dma_lock, flags);
34
35 if (used_dma_channels[dmanr]) {
36 spin_unlock_irqrestore(&dma_lock, flags);
37 if (options & DMA_VERBOSE_ON_ERROR) {
38 printk("Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
39 }
40 if (options & DMA_PANIC_ON_ERROR)
41 panic("request_dma error!");
42 return -EBUSY;
43 }
44 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
45 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
46
47 switch(dmanr)
48 {
49 case 0:
50 case 1:
51 clk_ctrl.dma01_eth0 = 1;
52 break;
53 case 2:
54 case 3:
55 clk_ctrl.dma23 = 1;
56 break;
57 case 4:
58 case 5:
59 clk_ctrl.dma45 = 1;
60 break;
61 case 6:
62 case 7:
63 clk_ctrl.dma67 = 1;
64 break;
65 case 8:
66 case 9:
67 clk_ctrl.dma89_strcop = 1;
68 break;
69#if MAX_DMA_CHANNELS-1 != 9
70#error Check dma.c
71#endif
72 default:
73 spin_unlock_irqrestore(&dma_lock, flags);
74 if (options & DMA_VERBOSE_ON_ERROR) {
75 printk("Failed to request DMA %i for %s, only 0-%i valid)\n", dmanr, device_id, MAX_DMA_CHANNELS-1);
76 }
77
78 if (options & DMA_PANIC_ON_ERROR)
79 panic("request_dma error!");
80 return -EINVAL;
81 }
82
83 switch(owner)
84 {
85 case dma_eth0:
86 if (dmanr == 0)
87 strmux_cfg.dma0 = regk_strmux_eth0;
88 else if (dmanr == 1)
89 strmux_cfg.dma1 = regk_strmux_eth0;
90 else
91 panic("Invalid DMA channel for eth0\n");
92 break;
93 case dma_eth1:
94 if (dmanr == 6)
95 strmux_cfg.dma6 = regk_strmux_eth1;
96 else if (dmanr == 7)
97 strmux_cfg.dma7 = regk_strmux_eth1;
98 else
99 panic("Invalid DMA channel for eth1\n");
100 break;
101 case dma_iop0:
102 if (dmanr == 2)
103 strmux_cfg.dma2 = regk_strmux_iop0;
104 else if (dmanr == 3)
105 strmux_cfg.dma3 = regk_strmux_iop0;
106 else
107 panic("Invalid DMA channel for iop0\n");
108 break;
109 case dma_iop1:
110 if (dmanr == 4)
111 strmux_cfg.dma4 = regk_strmux_iop1;
112 else if (dmanr == 5)
113 strmux_cfg.dma5 = regk_strmux_iop1;
114 else
115 panic("Invalid DMA channel for iop1\n");
116 break;
117 case dma_ser0:
118 if (dmanr == 6)
119 strmux_cfg.dma6 = regk_strmux_ser0;
120 else if (dmanr == 7)
121 strmux_cfg.dma7 = regk_strmux_ser0;
122 else
123 panic("Invalid DMA channel for ser0\n");
124 break;
125 case dma_ser1:
126 if (dmanr == 4)
127 strmux_cfg.dma4 = regk_strmux_ser1;
128 else if (dmanr == 5)
129 strmux_cfg.dma5 = regk_strmux_ser1;
130 else
131 panic("Invalid DMA channel for ser1\n");
132 break;
133 case dma_ser2:
134 if (dmanr == 2)
135 strmux_cfg.dma2 = regk_strmux_ser2;
136 else if (dmanr == 3)
137 strmux_cfg.dma3 = regk_strmux_ser2;
138 else
139 panic("Invalid DMA channel for ser2\n");
140 break;
141 case dma_ser3:
142 if (dmanr == 8)
143 strmux_cfg.dma8 = regk_strmux_ser3;
144 else if (dmanr == 9)
145 strmux_cfg.dma9 = regk_strmux_ser3;
146 else
147 panic("Invalid DMA channel for ser3\n");
148 break;
149 case dma_sser0:
150 if (dmanr == 4)
151 strmux_cfg.dma4 = regk_strmux_sser0;
152 else if (dmanr == 5)
153 strmux_cfg.dma5 = regk_strmux_sser0;
154 else
155 panic("Invalid DMA channel for sser0\n");
156 break;
157 case dma_sser1:
158 if (dmanr == 6)
159 strmux_cfg.dma6 = regk_strmux_sser1;
160 else if (dmanr == 7)
161 strmux_cfg.dma7 = regk_strmux_sser1;
162 else
163 panic("Invalid DMA channel for sser1\n");
164 break;
165 case dma_ata:
166 if (dmanr == 2)
167 strmux_cfg.dma2 = regk_strmux_ata;
168 else if (dmanr == 3)
169 strmux_cfg.dma3 = regk_strmux_ata;
170 else
171 panic("Invalid DMA channel for ata\n");
172 break;
173 case dma_strp:
174 if (dmanr == 8)
175 strmux_cfg.dma8 = regk_strmux_strcop;
176 else if (dmanr == 9)
177 strmux_cfg.dma9 = regk_strmux_strcop;
178 else
179 panic("Invalid DMA channel for strp\n");
180 break;
181 case dma_ext0:
182 if (dmanr == 6)
183 strmux_cfg.dma6 = regk_strmux_ext0;
184 else
185 panic("Invalid DMA channel for ext0\n");
186 break;
187 case dma_ext1:
188 if (dmanr == 7)
189 strmux_cfg.dma7 = regk_strmux_ext1;
190 else
191 panic("Invalid DMA channel for ext1\n");
192 break;
193 case dma_ext2:
194 if (dmanr == 2)
195 strmux_cfg.dma2 = regk_strmux_ext2;
196 else if (dmanr == 8)
197 strmux_cfg.dma8 = regk_strmux_ext2;
198 else
199 panic("Invalid DMA channel for ext2\n");
200 break;
201 case dma_ext3:
202 if (dmanr == 3)
203 strmux_cfg.dma3 = regk_strmux_ext3;
204 else if (dmanr == 9)
205 strmux_cfg.dma9 = regk_strmux_ext2;
206 else
207 panic("Invalid DMA channel for ext2\n");
208 break;
209 }
210
211 used_dma_channels[dmanr] = 1;
212 used_dma_channels_users[dmanr] = device_id;
213 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
214 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
215 spin_unlock_irqrestore(&dma_lock,flags);
216 return 0;
217}
218
219void crisv32_free_dma(unsigned int dmanr)
220{
221 spin_lock(&dma_lock);
222 used_dma_channels[dmanr] = 0;
223 spin_unlock(&dma_lock);
224}
diff --git a/arch/cris/arch-v32/kernel/io.c b/arch/cris/arch-v32/kernel/io.c
deleted file mode 100644
index a22a9e02e093..000000000000
--- a/arch/cris/arch-v32/kernel/io.c
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Helper functions for I/O pins.
3 *
4 * Copyright (c) 2004 Axis Communications AB.
5 */
6
7#include <linux/types.h>
8#include <linux/errno.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/ctype.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/io.h>
15#include <asm/arch/pinmux.h>
16#include <asm/arch/hwregs/gio_defs.h>
17
18struct crisv32_ioport crisv32_ioports[] =
19{
20 {
21 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_oe),
22 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_dout),
23 (unsigned long*)REG_ADDR(gio, regi_gio, r_pa_din),
24 8
25 },
26 {
27 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_oe),
28 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_dout),
29 (unsigned long*)REG_ADDR(gio, regi_gio, r_pb_din),
30 18
31 },
32 {
33 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_oe),
34 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_dout),
35 (unsigned long*)REG_ADDR(gio, regi_gio, r_pc_din),
36 18
37 },
38 {
39 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_oe),
40 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_dout),
41 (unsigned long*)REG_ADDR(gio, regi_gio, r_pd_din),
42 18
43 },
44 {
45 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_oe),
46 (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_dout),
47 (unsigned long*)REG_ADDR(gio, regi_gio, r_pe_din),
48 18
49 }
50};
51
52#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
53
54struct crisv32_iopin crisv32_led1_green;
55struct crisv32_iopin crisv32_led1_red;
56struct crisv32_iopin crisv32_led2_green;
57struct crisv32_iopin crisv32_led2_red;
58struct crisv32_iopin crisv32_led3_green;
59struct crisv32_iopin crisv32_led3_red;
60
61/* Dummy port used when green LED and red LED is on the same bit */
62static unsigned long io_dummy;
63static struct crisv32_ioport dummy_port =
64{
65 &io_dummy,
66 &io_dummy,
67 &io_dummy,
68 18
69};
70static struct crisv32_iopin dummy_led =
71{
72 &dummy_port,
73 0
74};
75
76static int __init crisv32_io_init(void)
77{
78 int ret = 0;
79 /* Initialize LEDs */
80 ret += crisv32_io_get_name(&crisv32_led1_green, CONFIG_ETRAX_LED1G);
81 ret += crisv32_io_get_name(&crisv32_led1_red, CONFIG_ETRAX_LED1R);
82 ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_LED2G);
83 ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_LED2R);
84 ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_LED3G);
85 ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_LED3R);
86 crisv32_io_set_dir(&crisv32_led1_green, crisv32_io_dir_out);
87 crisv32_io_set_dir(&crisv32_led1_red, crisv32_io_dir_out);
88 crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
89 crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
90 crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
91 crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
92
93 if (!strcmp(CONFIG_ETRAX_LED1G, CONFIG_ETRAX_LED1R))
94 crisv32_led1_red = dummy_led;
95 if (!strcmp(CONFIG_ETRAX_LED2G, CONFIG_ETRAX_LED2R))
96 crisv32_led2_red = dummy_led;
97
98 return ret;
99}
100
101__initcall(crisv32_io_init);
102
103int crisv32_io_get(struct crisv32_iopin* iopin,
104 unsigned int port, unsigned int pin)
105{
106 if (port > NBR_OF_PORTS)
107 return -EINVAL;
108 if (port > crisv32_ioports[port].pin_count)
109 return -EINVAL;
110
111 iopin->bit = 1 << pin;
112 iopin->port = &crisv32_ioports[port];
113
114 if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
115 return -EIO;
116
117 return 0;
118}
119
120int crisv32_io_get_name(struct crisv32_iopin* iopin,
121 char* name)
122{
123 int port;
124 int pin;
125
126 if (toupper(*name) == 'P')
127 name++;
128
129 if (toupper(*name) < 'A' || toupper(*name) > 'E')
130 return -EINVAL;
131
132 port = toupper(*name) - 'A';
133 name++;
134 pin = simple_strtoul(name, NULL, 10);
135
136 if (pin < 0 || pin > crisv32_ioports[port].pin_count)
137 return -EINVAL;
138
139 iopin->bit = 1 << pin;
140 iopin->port = &crisv32_ioports[port];
141
142 if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
143 return -EIO;
144
145 return 0;
146}
147
148#ifdef CONFIG_PCI
149/* PCI I/O access stuff */
150struct cris_io_operations* cris_iops = NULL;
151EXPORT_SYMBOL(cris_iops);
152#endif
153
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