Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

9 files changed, 5068 insertions, 0 deletions

diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
new file mode 100644
index 000000000000..748374f25b87
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/Kconfig
@@ -0,0 +1,963 @@
+config ETRAX_ETHERNET
+        bool "Ethernet support"
+        depends on ETRAX_ARCH_V10
+        help
+          This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
+          controller.
+
+# this is just so that the user does not have to go into the
+# normal ethernet driver section just to enable ethernetworking
+config NET_ETHERNET
+        bool
+        depends on ETRAX_ETHERNET
+        default y
+
+choice
+        prompt "Network LED behavior"
+        depends on ETRAX_ETHERNET
+        default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+
+config ETRAX_NETWORK_LED_ON_WHEN_LINK
+        bool "LED_on_when_link"
+        help
+          Selecting LED_on_when_link will light the LED when there is a 
+          connection and will flash off when there is activity. 
+
+          Selecting LED_on_when_activity will light the LED only when 
+          there is activity.
+
+          This setting will also affect the behaviour of other activity LEDs 
+          e.g. Bluetooth. 
+
+config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+        bool "LED_on_when_activity"
+        help
+          Selecting LED_on_when_link will light the LED when there is a 
+          connection and will flash off when there is activity. 
+
+          Selecting LED_on_when_activity will light the LED only when 
+          there is activity.
+
+          This setting will also affect the behaviour of other activity LEDs 
+          e.g. Bluetooth. 
+
+endchoice
+
+config ETRAX_SERIAL
+        bool "Serial-port support"
+        depends on ETRAX_ARCH_V10
+        help
+          Enables the ETRAX 100 serial driver for ser0 (ttyS0)
+          You probably want this enabled.
+
+config ETRAX_SERIAL_FAST_TIMER
+        bool "Use fast timers for serial DMA flush (experimental)"
+        depends on ETRAX_SERIAL
+        help
+          Select this to have the serial DMAs flushed at a higher rate than
+          normally, possible by using the fast timer API, the timeout is
+          approx. 4 character times.
+          If unsure, say N.
+
+config ETRAX_SERIAL_FLUSH_DMA_FAST
+        bool "Fast serial port DMA flush"
+        depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER
+        help
+          Select this to have the serial DMAs flushed at a higher rate than
+          normally possible through a fast timer interrupt (currently at
+          15360 Hz).
+          If unsure, say N.
+
+config ETRAX_SERIAL_RX_TIMEOUT_TICKS
+        int "Receive flush timeout (ticks) "
+        depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER && !ETRAX_SERIAL_FLUSH_DMA_FAST
+        default "5"
+        help
+          Number of timer ticks between flush of receive fifo (1 tick = 10ms).
+          Try 0-3 for low latency applications.  Approx 5 for high load
+          applications (e.g. PPP).  Maybe this should be more adaptive some
+          day...
+
+config ETRAX_SERIAL_PORT0
+        bool "Serial port 0 enabled"
+        depends on ETRAX_SERIAL
+        help
+          Enables the ETRAX 100 serial driver for ser0 (ttyS0)
+          Normally you want this on, unless you use external DMA 1 that uses
+          the same DMA channels.
+
+choice
+        prompt "Ser0 DMA out assignment"
+        depends on ETRAX_SERIAL_PORT0
+        default ETRAX_SERIAL_PORT0_DMA6_OUT
+
+config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT
+       bool "No DMA out"
+
+config CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
+       bool "DMA 6"
+
+endchoice
+
+choice
+        prompt "Ser0 DMA in assignment"
+        depends on ETRAX_SERIAL_PORT0
+        default ETRAX_SERIAL_PORT0_DMA7_IN
+
+config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN
+       bool "No DMA in"
+
+config CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
+       bool "DMA 7"
+
+endchoice
+
+choice
+        prompt "Ser0 DTR, RI, DSR and CD assignment"
+        depends on ETRAX_SERIAL_PORT0
+        default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
+
+config ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
+        bool "No_DTR_RI_DSR_CD"
+
+config ETRAX_SER0_DTR_RI_DSR_CD_ON_PA
+        bool "DTR_RI_DSR_CD_on_PA"
+
+config ETRAX_SER0_DTR_RI_DSR_CD_ON_PB
+        bool "DTR_RI_DSR_CD_on_PB"
+        help
+          Enables the status and control signals DTR, RI, DSR and CD on PB for
+          ser0.
+
+config ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
+
+endchoice
+
+config ETRAX_SER0_DTR_ON_PA_BIT
+        int "Ser0 DTR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER0_RI_ON_PA_BIT
+        int "Ser0 RI  on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER0_DSR_ON_PA_BIT
+        int "Ser0 DSR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER0_CD_ON_PA_BIT
+        int "Ser0 CD  on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER0_DTR_ON_PB_BIT
+        int "Ser0 DTR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the DTR signal for serial
+          port 0.
+
+config ETRAX_SER0_RI_ON_PB_BIT
+        int "Ser0 RI  on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the RI signal for serial
+          port 0.
+
+config ETRAX_SER0_DSR_ON_PB_BIT
+        int "Ser0 DSR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the DSR signal for serial
+          port 0.
+
+config ETRAX_SER0_CD_ON_PB_BIT
+        int "Ser0 CD  on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT0
+        default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the CD signal for serial
+          port 0.
+
+config ETRAX_SERIAL_PORT1
+        bool "Serial port 1 enabled"
+        depends on ETRAX_SERIAL
+        help
+          Enables the ETRAX 100 serial driver for ser1 (ttyS1).
+
+choice
+        prompt "Ser1 DMA out assignment"
+        depends on ETRAX_SERIAL_PORT1
+        default ETRAX_SERIAL_PORT1_DMA8_OUT
+
+config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_OUT
+       bool "No DMA out"
+
+config CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
+       bool "DMA 8"
+
+endchoice
+
+choice
+        prompt "Ser1 DMA in assignment"
+        depends on ETRAX_SERIAL_PORT1
+        default ETRAX_SERIAL_PORT1_DMA9_IN
+
+config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_IN
+       bool "No DMA in"
+
+config CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
+       bool "DMA 9"
+
+endchoice
+
+choice
+        prompt "Ser1 DTR, RI, DSR and CD assignment"
+        depends on ETRAX_SERIAL_PORT1
+        default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
+
+config ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
+        bool "No_DTR_RI_DSR_CD"
+
+config ETRAX_SER1_DTR_RI_DSR_CD_ON_PA
+        bool "DTR_RI_DSR_CD_on_PA"
+
+config ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
+        bool "DTR_RI_DSR_CD_on_PB"
+        help
+          Enables the status and control signals DTR, RI, DSR and CD on PB for
+          ser1.
+
+config ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
+
+endchoice
+
+config ETRAX_SER1_DTR_ON_PA_BIT
+        int "Ser1 DTR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER1_RI_ON_PA_BIT
+        int "Ser1 RI  on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER1_DSR_ON_PA_BIT
+        int "Ser1 DSR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER1_CD_ON_PA_BIT
+        int "Ser1 CD  on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER1_DTR_ON_PB_BIT
+        int "Ser1 DTR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the DTR signal for serial
+          port 1.
+
+config ETRAX_SER1_RI_ON_PB_BIT
+        int "Ser1 RI  on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the RI signal for serial
+          port 1.
+
+config ETRAX_SER1_DSR_ON_PB_BIT
+        int "Ser1 DSR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the DSR signal for serial
+          port 1.
+
+config ETRAX_SER1_CD_ON_PB_BIT
+        int "Ser1 CD  on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT1
+        default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PB port to carry the CD signal for serial
+          port 1.
+
+comment "Make sure you dont have the same PB bits more than once!"
+        depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
+
+config ETRAX_SERIAL_PORT2
+        bool "Serial port 2 enabled"
+        depends on ETRAX_SERIAL
+        help
+          Enables the ETRAX 100 serial driver for ser2 (ttyS2).
+
+choice
+        prompt "Ser2 DMA out assignment"
+        depends on ETRAX_SERIAL_PORT2
+        default ETRAX_SERIAL_PORT2_DMA2_OUT
+
+config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT
+       bool "No DMA out"
+
+config CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
+       bool "DMA 2"
+
+endchoice
+
+choice
+        prompt "Ser2 DMA in assignment"
+        depends on ETRAX_SERIAL_PORT2
+        default ETRAX_SERIAL_PORT2_DMA3_IN
+
+config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN
+       bool "No DMA in"
+
+config CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
+       bool "DMA 3"
+
+endchoice
+
+choice
+        prompt "Ser2 DTR, RI, DSR and CD assignment"
+        depends on ETRAX_SERIAL_PORT2
+        default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
+
+config ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
+        bool "No_DTR_RI_DSR_CD"
+
+config ETRAX_SER2_DTR_RI_DSR_CD_ON_PA
+        bool "DTR_RI_DSR_CD_on_PA"
+        help
+          Enables the status and control signals DTR, RI, DSR and CD on PA for
+          ser2.
+
+config ETRAX_SER2_DTR_RI_DSR_CD_ON_PB
+        bool "DTR_RI_DSR_CD_on_PB"
+
+config ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
+
+endchoice
+
+config ETRAX_SER2_DTR_ON_PA_BIT
+        int "Ser2 DTR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PA port to carry the DTR signal for serial
+          port 2.
+
+config ETRAX_SER2_RI_ON_PA_BIT
+        int "Ser2 RI  on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PA port to carry the RI signal for serial
+          port 2.
+
+config ETRAX_SER2_DSR_ON_PA_BIT
+        int "Ser2 DSR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PA port to carry the DTR signal for serial
+          port 2.
+
+config ETRAX_SER2_CD_ON_PA_BIT
+        int "Ser2 CD  on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        help
+          Specify the pin of the PA port to carry the CD signal for serial
+          port 2.
+
+config ETRAX_SER2_DTR_ON_PB_BIT
+        int "Ser2 DTR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER2_RI_ON_PB_BIT
+        int "Ser2 RI  on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER2_DSR_ON_PB_BIT
+        int "Ser2 DSR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SER2_CD_ON_PB_BIT
+        int "Ser2 CD  on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT2
+        default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+        default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
+
+config ETRAX_SERIAL_PORT3
+        bool "Serial port 3 enabled"
+        depends on ETRAX_SERIAL
+        help
+          Enables the ETRAX 100 serial driver for ser3 (ttyS3).
+
+choice
+        prompt "Ser3 DMA out assignment"
+        depends on ETRAX_SERIAL_PORT3
+        default ETRAX_SERIAL_PORT3_DMA4_OUT
+
+config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_OUT
+       bool "No DMA out"
+
+config CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
+       bool "DMA 4"
+
+endchoice
+
+choice
+        prompt "Ser3 DMA in assignment"
+        depends on ETRAX_SERIAL_PORT3
+        default ETRAX_SERIAL_PORT3_DMA5_IN
+
+config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_IN
+       bool "No DMA in"
+
+config CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
+       bool "DMA 5"
+
+endchoice
+
+choice
+        prompt "Ser3 DTR, RI, DSR and CD assignment"
+        depends on ETRAX_SERIAL_PORT3
+        default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
+
+config ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
+        bool "No_DTR_RI_DSR_CD"
+
+config ETRAX_SER3_DTR_RI_DSR_CD_ON_PA
+        bool "DTR_RI_DSR_CD_on_PA"
+
+config ETRAX_SER3_DTR_RI_DSR_CD_ON_PB
+        bool "DTR_RI_DSR_CD_on_PB"
+
+config ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
+
+endchoice
+
+config ETRAX_SER3_DTR_ON_PA_BIT
+        int "Ser3 DTR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_RI_ON_PA_BIT
+        int "Ser3 RI  on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_DSR_ON_PA_BIT
+        int "Ser3 DSR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_CD_ON_PA_BIT
+        int "Ser3 CD  on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_DTR_ON_PB_BIT
+        int "Ser3 DTR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_RI_ON_PB_BIT
+        int "Ser3 RI  on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_DSR_ON_PB_BIT
+        int "Ser3 DSR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_SER3_CD_ON_PB_BIT
+        int "Ser3 CD  on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
+        depends on ETRAX_SERIAL_PORT3
+        default "-1"
+
+config ETRAX_RS485
+        bool "RS-485 support"
+        depends on ETRAX_SERIAL
+        help
+          Enables support for RS-485 serial communication.  For a primer on
+          RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
+
+config ETRAX_RS485_ON_PA
+        bool "RS-485 mode on PA"
+        depends on ETRAX_RS485
+        help
+          Control Driver Output Enable on RS485 transceiver using a pin on PA
+          port:
+          Axis 2400/2401 uses PA 3.
+
+config ETRAX_RS485_ON_PA_BIT
+        int "RS-485 mode on PA bit"
+        depends on ETRAX_RS485_ON_PA
+        default "3"
+        help
+          Control Driver Output Enable on RS485 transceiver using a this bit
+          on PA port.
+
+config ETRAX_RS485_DISABLE_RECEIVER
+        bool "Disable serial receiver"
+        depends on ETRAX_RS485
+        help
+          It's necessary to disable the serial receiver to avoid serial
+          loopback.  Not all products are able to do this in software only.
+          Axis 2400/2401 must disable receiver.
+
+config ETRAX_IDE
+        bool "ATA/IDE support"
+        select IDE
+        select BLK_DEV_IDE
+        select BLK_DEV_IDEDISK
+        select BLK_DEV_IDECD
+        select BLK_DEV_IDEDMA
+        select DMA_NONPCI
+        help
+          Enable this to get support for ATA/IDE.
+          You can't use paralell ports or SCSI ports
+          at the same time.
+
+
+config ETRAX_IDE_DELAY
+        int "Delay for drives to regain consciousness"
+        depends on ETRAX_IDE
+        default 15
+        help
+          Number of seconds to wait for IDE drives to spin up after an IDE
+          reset.
+choice
+        prompt "IDE reset pin"
+        depends on ETRAX_IDE
+        default ETRAX_IDE_PB7_RESET
+
+config ETRAX_IDE_PB7_RESET
+        bool "Port_PB_Bit_7"
+        help
+          IDE reset on pin 7 on port B
+
+config ETRAX_IDE_G27_RESET
+        bool "Port_G_Bit_27"
+        help
+          IDE reset on pin 27 on port G
+
+endchoice
+
+
+config ETRAX_USB_HOST
+        bool "USB host"
+        help
+           This option enables the host functionality of the ETRAX 100LX
+           built-in USB controller. In host mode the controller is designed
+           for CTRL and BULK traffic only, INTR traffic may work as well
+           however (depending on the requirements of timeliness).
+
+config USB
+       tristate
+       depends on ETRAX_USB_HOST
+       default y
+
+config ETRAX_USB_HOST_PORT1
+       bool "  USB port 1 enabled"
+       depends on ETRAX_USB_HOST
+       default n
+
+config ETRAX_USB_HOST_PORT2
+       bool "  USB port 2 enabled"
+       depends on ETRAX_USB_HOST
+       default n
+
+config ETRAX_AXISFLASHMAP
+        bool "Axis flash-map support"
+        depends on ETRAX_ARCH_V10
+        help
+          This option enables MTD mapping of flash devices.  Needed to use
+          flash memories.  If unsure, say Y.
+
+config ETRAX_PTABLE_SECTOR
+        int "Byte-offset of partition table sector"
+        depends on ETRAX_AXISFLASHMAP
+        default "65536"
+        help
+          Byte-offset of the partition table in the first flash chip.
+          The default value is 64kB and should not be changed unless
+          you know exactly what you are doing. The only valid reason
+          for changing this is when the flash block size is bigger
+          than 64kB (e.g. when using two parallel 16 bit flashes).
+
+# here we define the CONFIG_'s necessary to enable MTD support
+# for the flash
+config MTD
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          Memory Technology Devices are flash, RAM and similar chips, often
+          used for solid state file systems on embedded devices. This option
+          will provide the generic support for MTD drivers to register
+          themselves with the kernel and for potential users of MTD devices
+          to enumerate the devices which are present and obtain a handle on
+          them. It will also allow you to select individual drivers for 
+          particular hardware and users of MTD devices. If unsure, say N.
+
+config MTD_CFI
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          The Common Flash Interface specification was developed by Intel,
+          AMD and other flash manufactures that provides a universal method
+          for probing the capabilities of flash devices. If you wish to
+          support any device that is CFI-compliant, you need to enable this
+          option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
+          for more information on CFI.
+
+config MTD_CFI_AMDSTD
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          The Common Flash Interface defines a number of different command
+          sets which a CFI-compliant chip may claim to implement. This code
+          provides support for one of those command sets, used on chips 
+          chips including the AMD Am29LV320.
+
+config MTD_OBSOLETE_CHIPS
+        bool
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          This option does not enable any code directly, but will allow you to
+          select some other chip drivers which are now considered obsolete,
+          because the generic CONFIG_JEDEC_PROBE code above should now detect
+          the chips which are supported by these drivers, and allow the generic
+          CFI-compatible drivers to drive the chips. Say 'N' here unless you have
+          already tried the CONFIG_JEDEC_PROBE method and reported its failure
+          to the MTD mailing list at <linux-mtd@lists.infradead.org>
+
+config MTD_AMDSTD
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          This option enables support for flash chips using AMD-compatible
+          commands, including some which are not CFI-compatible and hence 
+          cannot be used with the CONFIG_MTD_CFI_AMDSTD option.
+
+          It also works on AMD compatible chips that do conform to CFI.
+
+config MTD_CHAR
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          This provides a character device for each MTD device present in
+          the system, allowing the user to read and write directly to the
+          memory chips, and also use ioctl() to obtain information about
+          the device, or to erase parts of it.
+
+config MTD_BLOCK
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        ---help---
+          Although most flash chips have an erase size too large to be useful
+          as block devices, it is possible to use MTD devices which are based
+          on RAM chips in this manner. This block device is a user of MTD
+          devices performing that function.
+
+          At the moment, it is also required for the Journalling Flash File
+          System(s) to obtain a handle on the MTD device when it's mounted
+          (although JFFS and JFFS2 don't actually use any of the functionality
+          of the mtdblock device).
+
+          Later, it may be extended to perform read/erase/modify/write cycles
+          on flash chips to emulate a smaller block size. Needless to say,
+          this is very unsafe, but could be useful for file systems which are
+          almost never written to.
+
+          You do not need this option for use with the DiskOnChip devices. For
+          those, enable NFTL support (CONFIG_NFTL) instead.
+
+config MTD_PARTITIONS
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+        help
+          If you have a device which needs to divide its flash chip(s) up
+          into multiple 'partitions', each of which appears to the user as
+          a separate MTD device, you require this option to be enabled. If
+          unsure, say 'Y'.
+
+          Note, however, that you don't need this option for the DiskOnChip
+          devices. Partitioning on NFTL 'devices' is a different - that's the
+          'normal' form of partitioning used on a block device.
+
+config MTD_CONCAT
+        tristate
+        depends on ETRAX_AXISFLASHMAP
+        default y
+
+config ETRAX_I2C
+        bool "I2C support"
+        depends on ETRAX_ARCH_V10
+        help
+          Enables an I2C driver on ETRAX100.
+          EXAMPLE usage:
+          i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
+          ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
+          i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
+          val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
+
+# this is true for most products since PB-I2C seems to be somewhat
+# flawed.. 
+config ETRAX_I2C_USES_PB_NOT_PB_I2C
+        bool "I2C uses PB not PB-I2C"
+        depends on ETRAX_I2C
+        help
+          Select whether to use the special I2C mode in the PB I/O register or
+          not.  This option needs to be selected in order to use some drivers
+          that access the I2C I/O pins directly instead of going through the
+          I2C driver, like the DS1302 realtime-clock driver.  If you are
+          uncertain, choose Y here.
+
+config ETRAX_I2C_DATA_PORT
+        int "I2C SDA bit number"
+        depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
+        default "0"
+        help
+          Selects the pin on Port B where the data pin is connected
+
+config ETRAX_I2C_CLK_PORT
+        int "I2C SCL bit number"
+        depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
+        default "1"
+        help
+          Select the pin on Port B where the clock pin is connected
+
+config ETRAX_I2C_EEPROM
+        bool "I2C EEPROM (non-volatile RAM) support"
+        depends on ETRAX_I2C
+        help
+          Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C
+          driver.  Select size option: Probed, 2k, 8k, 16k.
+          (Probing works for 2k and 8k but not that well for 16k)
+
+choice
+        prompt "EEPROM size"
+        depends on ETRAX_I2C_EEPROM
+        default ETRAX_I2C_EEPROM_PROBE
+
+config ETRAX_I2C_EEPROM_PROBE
+        bool "Probed"
+        help
+          Specifies size or auto probe of the EEPROM size.
+          Options: Probed, 2k, 8k, 16k.
+          (Probing works for 2k and 8k but not that well for 16k)
+
+config ETRAX_I2C_EEPROM_2KB
+        bool "2kB"
+        help
+          Use a 2kB EEPROM.
+
+config ETRAX_I2C_EEPROM_8KB
+        bool "8kB"
+        help
+          Use a 8kB EEPROM.
+
+config ETRAX_I2C_EEPROM_16KB
+        bool "16kB"
+        help
+          Use a 16kB EEPROM.
+
+endchoice
+
+config ETRAX_GPIO
+        bool "GPIO support"
+        depends on ETRAX_ARCH_V10
+        ---help---
+          Enables the ETRAX general port device (major 120, minors 0 and 1).
+          You can use this driver to access the general port bits. It supports
+          these ioctl's:
+          #include <linux/etraxgpio.h>
+          fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
+          ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
+          ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
+          val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL);
+          Remember that you need to setup the port directions appropriately in
+          the General configuration.
+
+config ETRAX_PA_BUTTON_BITMASK
+        hex "PA-buttons bitmask"
+        depends on ETRAX_GPIO
+        default "02"
+        help
+          This is a bitmask with information about what bits on PA that
+          are used for buttons.
+          Most products has a so called TEST button on PA1, if that's true
+          use 02 here.
+          Use 00 if there are no buttons on PA.
+          If the bitmask is <> 00 a button driver will be included in the gpio
+          driver. ETRAX general I/O support must be enabled.
+
+config ETRAX_PA_CHANGEABLE_DIR
+        hex "PA user changeable dir mask"
+        depends on ETRAX_GPIO
+        default "00"
+        help
+          This is a bitmask with information of what bits in PA that a user
+          can change direction on using ioctl's.
+          Bit set = changeable.
+          You probably want 00 here.
+
+config ETRAX_PA_CHANGEABLE_BITS
+        hex "PA user changeable bits mask"
+        depends on ETRAX_GPIO
+        default "FF"
+        help
+          This is a bitmask with information of what bits in PA that a user
+          can change change the value on using ioctl's.
+          Bit set = changeable.
+          You probably want 00 here.
+
+config ETRAX_PB_CHANGEABLE_DIR
+        hex "PB user changeable dir mask"
+        depends on ETRAX_GPIO
+        default "00"
+        help
+          This is a bitmask with information of what bits in PB that a user
+          can change direction on using ioctl's.
+          Bit set = changeable.
+          You probably want 00 here.
+
+config ETRAX_PB_CHANGEABLE_BITS
+        hex "PB user changeable bits mask"
+        depends on ETRAX_GPIO
+        default "FF"
+        help
+          This is a bitmask with information of what bits in PB that a user
+          can change the value on using ioctl's.
+          Bit set = changeable.
+          You probably want 00 here.
+
+config ETRAX_RTC
+        bool "Real Time Clock support"
+        depends on ETRAX_ARCH_V10
+        help
+          Enables drivers for the Real-Time Clock battery-backed chips on 
+          some products. The kernel reads the time when booting, and
+          the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
+          rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
+          device, major 121.  You can check the time with cat /proc/rtc, but
+          normal time reading should be done using libc function time and
+          friends.
+
+choice
+        prompt "RTC chip"
+        depends on ETRAX_RTC
+        default ETRAX_DS1302
+
+config ETRAX_DS1302
+        bool "DS1302"
+        help
+          Enables the driver for the DS1302 Real-Time Clock battery-backed
+          chip on some products. 
+
+config ETRAX_PCF8563
+        bool "PCF8563"
+        help
+          Enables the driver for the PCF8563 Real-Time Clock battery-backed
+          chip on some products.  
+
+endchoice
+
+config ETRAX_DS1302_RST_ON_GENERIC_PORT
+        bool "DS1302 RST on Generic Port"
+        depends on ETRAX_DS1302
+        help
+          If your product has the RST signal line for the DS1302 RTC on the
+          Generic Port then say Y here, otherwise leave it as N in which
+          case the RST signal line is assumed to be connected to Port PB
+          (just like the SCL and SDA lines).
+
+config ETRAX_DS1302_RSTBIT
+        int "DS1302 RST bit number"
+        depends on ETRAX_DS1302
+        default "2"
+        help
+          This is the bit number for the RST signal line of the DS1302 RTC on
+          the selected port. If you have selected the generic port then it
+          should be bit 27, otherwise your best bet is bit 5.
+
+config ETRAX_DS1302_SCLBIT
+        int "DS1302 SCL bit number"
+        depends on ETRAX_DS1302
+        default "1"
+        help
+          This is the bit number for the SCL signal line of the DS1302 RTC on
+          Port PB. This is probably best left at 3.
+
+config ETRAX_DS1302_SDABIT
+        int "DS1302 SDA bit number"
+        depends on ETRAX_DS1302
+        default "0"
+        help
+          This is the bit number for the SDA signal line of the DS1302 RTC on
+          Port PB. This is probably best left at 2.
+
+config ETRAX_DS1302_TRICKLE_CHARGE
+        int "DS1302 Trickle charger value"
+        depends on ETRAX_DS1302
+        default "0"
+        help
+          This controls the initial value of the trickle charge register.
+          0 = disabled (use this if you are unsure or have a non rechargable battery)
+          Otherwise the following values can be OR:ed together to control the 
+          charge current:
+          1 = 2kohm, 2 = 4kohm, 3 = 4kohm
+          4 = 1 diode, 8 = 2 diodes
+          Allowed values are (increasing current): 0, 11, 10, 9, 7, 6, 5
+
+
diff --git a/arch/cris/arch-v10/drivers/Makefile b/arch/cris/arch-v10/drivers/Makefile
new file mode 100644
index 000000000000..20258e36f384
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for Etrax-specific drivers
+#
+
+obj-$(CONFIG_ETRAX_AXISFLASHMAP)        += axisflashmap.o
+obj-$(CONFIG_ETRAX_I2C)                 += i2c.o
+obj-$(CONFIG_ETRAX_I2C_EEPROM)          += eeprom.o
+obj-$(CONFIG_ETRAX_GPIO)                += gpio.o
+obj-$(CONFIG_ETRAX_DS1302)              += ds1302.o
+obj-$(CONFIG_ETRAX_PCF8563)             += pcf8563.o
+
+
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
new file mode 100644
index 000000000000..fb7d4855ea62
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/axisflashmap.c
@@ -0,0 +1,541 @@
+/*
+ * Physical mapping layer for MTD using the Axis partitiontable format
+ *
+ * Copyright (c) 2001, 2002 Axis Communications AB
+ *
+ * This file is under the GPL.
+ *
+ * First partition is always sector 0 regardless of if we find a partitiontable
+ * or not. In the start of the next sector, there can be a partitiontable that
+ * tells us what other partitions to define. If there isn't, we use a default
+ * partition split defined below.
+ *
+ * $Log: axisflashmap.c,v $
+ * Revision 1.10  2004/08/16 12:37:22  starvik
+ * Merge of Linux 2.6.8
+ *
+ * Revision 1.8  2004/05/14 07:58:03  starvik
+ * Merge of changes from 2.4
+ *
+ * Revision 1.6  2003/07/04 08:27:37  starvik
+ * Merge of Linux 2.5.74
+ *
+ * Revision 1.5  2002/12/11 13:13:57  starvik
+ * Added arch/ to v10 specific includes
+ * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
+ *
+ * Revision 1.4  2002/11/20 11:56:10  starvik
+ * Merge of Linux 2.5.48
+ *
+ * Revision 1.3  2002/11/13 14:54:13  starvik
+ * Copied from linux 2.4
+ *
+ * Revision 1.28  2002/10/01 08:08:43  jonashg
+ * The first partition ends at the start of the partition table.
+ *
+ * Revision 1.27  2002/08/21 09:23:13  jonashg
+ * Speling.
+ *
+ * Revision 1.26  2002/08/21 08:35:20  jonashg
+ * Cosmetic change to printouts.
+ *
+ * Revision 1.25  2002/08/21 08:15:42  jonashg
+ * Made it compile even without CONFIG_MTD_CONCAT defined.
+ *
+ * Revision 1.24  2002/08/20 13:12:35  jonashg
+ * * New approach to probing. Probe cse0 and cse1 separately and (mtd)concat
+ *   the results.
+ * * Removed compile time tests concerning how the mtdram driver has been
+ *   configured. The user will know about the misconfiguration at runtime
+ *   instead. (The old approach made it impossible to use mtdram for anything
+ *   else than RAM boot).
+ *
+ * Revision 1.23  2002/05/13 12:12:28  johana
+ * Allow compile without CONFIG_MTD_MTDRAM but warn at compiletime and
+ * be informative at runtime.
+ *
+ * Revision 1.22  2002/05/13 10:24:44  johana
+ * Added #if checks on MTDRAM CONFIG
+ *
+ * Revision 1.21  2002/05/06 16:05:20  johana
+ * Removed debug printout.
+ *
+ * Revision 1.20  2002/05/06 16:03:00  johana
+ * No more cramfs as root hack in generic code.
+ * It's handled by axisflashmap using mtdram.
+ *
+ * Revision 1.19  2002/03/15 17:10:28  bjornw
+ * Changed comment about cached access since we changed this before
+ *
+ * Revision 1.18  2002/03/05 17:06:15  jonashg
+ * Try amd_flash probe before cfi_probe since amd_flash driver can handle two
+ * (or more) flash chips of different model and the cfi driver cannot.
+ *
+ * Revision 1.17  2001/11/12 19:42:38  pkj
+ * Fixed compiler warnings.
+ *
+ * Revision 1.16  2001/11/08 11:18:58  jonashg
+ * Always read from uncached address to avoid problems with flushing
+ * cachelines after write and MTD-erase. No performance loss have been
+ * seen yet.
+ *
+ * Revision 1.15  2001/10/19 12:41:04  jonashg
+ * Name of probe has changed in MTD.
+ *
+ * Revision 1.14  2001/09/21 07:14:10  jonashg
+ * Made root filesystem (cramfs) use mtdblock driver when booting from flash.
+ *
+ * Revision 1.13  2001/08/15 13:57:35  jonashg
+ * Entire MTD updated to the linux 2.4.7 version.
+ *
+ * Revision 1.12  2001/06/11 09:50:30  jonashg
+ * Oops, 2MB is 0x200000 bytes.
+ *
+ * Revision 1.11  2001/06/08 11:39:44  jonashg
+ * Changed sizes and offsets in axis_default_partitions to use
+ * CONFIG_ETRAX_PTABLE_SECTOR.
+ *
+ * Revision 1.10  2001/05/29 09:42:03  jonashg
+ * Use macro for end marker length instead of sizeof.
+ *
+ * Revision 1.9  2001/05/29 08:52:52  jonashg
+ * Gave names to the magic fours (size of the ptable end marker).
+ *
+ * Revision 1.8  2001/05/28 15:36:20  jonashg
+ * * Removed old comment about ptable location in flash (it's a CONFIG_ option).
+ * * Variable ptable was initialized twice to the same value.
+ *
+ * Revision 1.7  2001/04/05 13:41:46  markusl
+ * Updated according to review remarks
+ *
+ * Revision 1.6  2001/03/07 09:21:21  bjornw
+ * No need to waste .data
+ *
+ * Revision 1.5  2001/03/06 16:27:01  jonashg
+ * Probe the entire flash area for flash devices.
+ *
+ * Revision 1.4  2001/02/23 12:47:15  bjornw
+ * Uncached flash in LOW_MAP moved from 0xe to 0x8
+ *
+ * Revision 1.3  2001/02/16 12:11:45  jonashg
+ * MTD driver amd_flash is now included in MTD CVS repository.
+ * (It's now in drivers/mtd).
+ *
+ * Revision 1.2  2001/02/09 11:12:22  jonashg
+ * Support for AMD compatible non-CFI flash chips.
+ * Only tested with Toshiba TC58FVT160 so far.
+ *
+ * Revision 1.1  2001/01/12 17:01:18  bjornw
+ * * Added axisflashmap.c, a physical mapping for MTD that reads and understands
+ *   Axis partition-table format.
+ *
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <linux/mtd/concat.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/mtdram.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/axisflashmap.h>
+#include <asm/mmu.h>
+#include <asm/arch/sv_addr_ag.h>
+
+#ifdef CONFIG_CRIS_LOW_MAP
+#define FLASH_UNCACHED_ADDR  KSEG_8
+#define FLASH_CACHED_ADDR    KSEG_5
+#else
+#define FLASH_UNCACHED_ADDR  KSEG_E
+#define FLASH_CACHED_ADDR    KSEG_F
+#endif
+
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
+#define flash_data __u8
+#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
+#define flash_data __u16
+#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
+#define flash_data __u16
+#endif
+
+/* From head.S */
+extern unsigned long romfs_start, romfs_length, romfs_in_flash;
+
+/* The master mtd for the entire flash. */
+struct mtd_info* axisflash_mtd = NULL;
+
+/* Map driver functions. */
+
+static map_word flash_read(struct map_info *map, unsigned long ofs)
+{
+        map_word tmp;
+        tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
+        return tmp;
+}
+
+static void flash_copy_from(struct map_info *map, void *to,
+                            unsigned long from, ssize_t len)
+{
+        memcpy(to, (void *)(map->map_priv_1 + from), len);
+}
+
+static void flash_write(struct map_info *map, map_word d, unsigned long adr)
+{
+        *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
+}
+
+/*
+ * The map for chip select e0.
+ *
+ * We run into tricky coherence situations if we mix cached with uncached
+ * accesses to we only use the uncached version here.
+ *
+ * The size field is the total size where the flash chips may be mapped on the
+ * chip select. MTD probes should find all devices there and it does not matter
+ * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
+ * probes will ignore them.
+ *
+ * The start address in map_priv_1 is in virtual memory so we cannot use
+ * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
+ * address of cse0.
+ */
+static struct map_info map_cse0 = {
+        .name = "cse0",
+        .size = MEM_CSE0_SIZE,
+        .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
+        .read = flash_read,
+        .copy_from = flash_copy_from,
+        .write = flash_write,
+        .map_priv_1 = FLASH_UNCACHED_ADDR
+};
+
+/*
+ * The map for chip select e1.
+ *
+ * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
+ * address, but there isn't.
+ */
+static struct map_info map_cse1 = {
+        .name = "cse1",
+        .size = MEM_CSE1_SIZE,
+        .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
+        .read = flash_read,
+        .copy_from = flash_copy_from,
+        .write = flash_write,
+        .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
+};
+
+/* If no partition-table was found, we use this default-set. */
+#define MAX_PARTITIONS         7  
+#define NUM_DEFAULT_PARTITIONS 3
+
+/*
+ * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
+ * size of one flash block and "filesystem"-partition needs 5 blocks to be able
+ * to use JFFS.
+ */
+static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
+        {
+                .name = "boot firmware",
+                .size = CONFIG_ETRAX_PTABLE_SECTOR,
+                .offset = 0
+        },
+        {
+                .name = "kernel",
+                .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
+                .offset = CONFIG_ETRAX_PTABLE_SECTOR
+        },
+        {
+                .name = "filesystem",
+                .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
+                .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
+        }
+};
+
+/* Initialize the ones normally used. */
+static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
+        {
+                .name = "part0",
+                .size = CONFIG_ETRAX_PTABLE_SECTOR,
+                .offset = 0
+        },
+        {
+                .name = "part1",
+                .size = 0,
+                .offset = 0
+        },
+        {
+                .name = "part2",
+                .size = 0,
+                .offset = 0
+        },
+        {
+                .name = "part3",
+                .size = 0,
+                .offset = 0
+        },
+        {
+                .name = "part4",
+                .size = 0,
+                .offset = 0
+        },
+        {
+                .name = "part5",
+                .size = 0,
+                .offset = 0
+        },
+        {
+                .name = "part6",
+                .size = 0,
+                .offset = 0
+        },
+};
+
+/*
+ * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
+ * chips in that order (because the amd_flash-driver is faster).
+ */
+static struct mtd_info *probe_cs(struct map_info *map_cs)
+{
+        struct mtd_info *mtd_cs = NULL;
+
+        printk(KERN_INFO
+               "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
+               map_cs->name, map_cs->size, map_cs->map_priv_1);
+
+#ifdef CONFIG_MTD_AMDSTD
+        mtd_cs = do_map_probe("amd_flash", map_cs);
+#endif
+#ifdef CONFIG_MTD_CFI
+        if (!mtd_cs) {
+                mtd_cs = do_map_probe("cfi_probe", map_cs);
+        }
+#endif
+
+        return mtd_cs;
+}
+
+/* 
+ * Probe each chip select individually for flash chips. If there are chips on
+ * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
+ * so that MTD partitions can cross chip boundries.
+ *
+ * The only known restriction to how you can mount your chips is that each
+ * chip select must hold similar flash chips. But you need external hardware
+ * to do that anyway and you can put totally different chips on cse0 and cse1
+ * so it isn't really much of a restriction.
+ */
+static struct mtd_info *flash_probe(void)
+{
+        struct mtd_info *mtd_cse0;
+        struct mtd_info *mtd_cse1;
+        struct mtd_info *mtd_cse;
+
+        mtd_cse0 = probe_cs(&map_cse0);
+        mtd_cse1 = probe_cs(&map_cse1);
+
+        if (!mtd_cse0 && !mtd_cse1) {
+                /* No chip found. */
+                return NULL;
+        }
+
+        if (mtd_cse0 && mtd_cse1) {
+#ifdef CONFIG_MTD_CONCAT
+                struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 };
+                
+                /* Since the concatenation layer adds a small overhead we
+                 * could try to figure out if the chips in cse0 and cse1 are
+                 * identical and reprobe the whole cse0+cse1 window. But since
+                 * flash chips are slow, the overhead is relatively small.
+                 * So we use the MTD concatenation layer instead of further
+                 * complicating the probing procedure.
+                 */
+                mtd_cse = mtd_concat_create(mtds,
+                                            sizeof(mtds) / sizeof(mtds[0]),
+                                            "cse0+cse1");
+#else
+                printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel "
+                       "(mis)configuration!\n", map_cse0.name, map_cse1.name);
+                mtd_cse = NULL;
+#endif
+                if (!mtd_cse) {
+                        printk(KERN_ERR "%s and %s: Concatenation failed!\n",
+                               map_cse0.name, map_cse1.name);
+
+                        /* The best we can do now is to only use what we found
+                         * at cse0.
+                         */ 
+                        mtd_cse = mtd_cse0;
+                        map_destroy(mtd_cse1);
+                }
+        } else {
+                mtd_cse = mtd_cse0? mtd_cse0 : mtd_cse1;
+        }
+
+        return mtd_cse;
+}
+
+/*
+ * Probe the flash chip(s) and, if it succeeds, read the partition-table
+ * and register the partitions with MTD.
+ */
+static int __init init_axis_flash(void)
+{
+        struct mtd_info *mymtd;
+        int err = 0;
+        int pidx = 0;
+        struct partitiontable_head *ptable_head = NULL;
+        struct partitiontable_entry *ptable;
+        int use_default_ptable = 1; /* Until proven otherwise. */
+        const char *pmsg = "  /dev/flash%d at 0x%08x, size 0x%08x\n";
+
+        if (!(mymtd = flash_probe())) {
+                /* There's no reason to use this module if no flash chip can
+                 * be identified. Make sure that's understood.
+                 */
+                printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
+        } else {
+                printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n",
+                       mymtd->name, mymtd->size);
+                axisflash_mtd = mymtd;
+        }
+
+        if (mymtd) {
+                mymtd->owner = THIS_MODULE;
+                ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR +
+                              CONFIG_ETRAX_PTABLE_SECTOR +
+                              PARTITION_TABLE_OFFSET);
+        }
+        pidx++;  /* First partition is always set to the default. */
+
+        if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
+            && (ptable_head->size <
+                (MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
+                PARTITIONTABLE_END_MARKER_SIZE))
+            && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
+                                  ptable_head->size -
+                                  PARTITIONTABLE_END_MARKER_SIZE)
+                == PARTITIONTABLE_END_MARKER)) {
+                /* Looks like a start, sane length and end of a
+                 * partition table, lets check csum etc.
+                 */
+                int ptable_ok = 0;
+                struct partitiontable_entry *max_addr =
+                        (struct partitiontable_entry *)
+                        ((unsigned long)ptable_head + sizeof(*ptable_head) +
+                         ptable_head->size);
+                unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
+                unsigned char *p;
+                unsigned long csum = 0;
+                
+                ptable = (struct partitiontable_entry *)
+                        ((unsigned long)ptable_head + sizeof(*ptable_head));
+
+                /* Lets be PARANOID, and check the checksum. */
+                p = (unsigned char*) ptable;
+
+                while (p <= (unsigned char*)max_addr) {
+                        csum += *p++;
+                        csum += *p++;
+                        csum += *p++;
+                        csum += *p++;
+                }
+                ptable_ok = (csum == ptable_head->checksum);
+
+                /* Read the entries and use/show the info.  */
+                printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n",
+                       (ptable_ok ? " valid" : "n invalid"), ptable_head,
+                       max_addr);
+
+                /* We have found a working bootblock.  Now read the
+                 * partition table.  Scan the table.  It ends when
+                 * there is 0xffffffff, that is, empty flash.
+                 */
+                while (ptable_ok
+                       && ptable->offset != 0xffffffff
+                       && ptable < max_addr
+                       && pidx < MAX_PARTITIONS) {
+
+                        axis_partitions[pidx].offset = offset + ptable->offset;
+                        axis_partitions[pidx].size = ptable->size;
+
+                        printk(pmsg, pidx, axis_partitions[pidx].offset,
+                               axis_partitions[pidx].size);
+                        pidx++;
+                        ptable++;
+                }
+                use_default_ptable = !ptable_ok;
+        }
+
+        if (romfs_in_flash) {
+                /* Add an overlapping device for the root partition (romfs). */
+
+                axis_partitions[pidx].name = "romfs";
+                axis_partitions[pidx].size = romfs_length;
+                axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
+                axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
+
+                printk(KERN_INFO
+                       " Adding readonly flash partition for romfs image:\n");
+                printk(pmsg, pidx, axis_partitions[pidx].offset,
+                       axis_partitions[pidx].size);
+                pidx++;
+        }
+
+        if (mymtd) {
+                if (use_default_ptable) {
+                        printk(KERN_INFO " Using default partition table.\n");
+                        err = add_mtd_partitions(mymtd, axis_default_partitions,
+                                                 NUM_DEFAULT_PARTITIONS);
+                } else {
+                        err = add_mtd_partitions(mymtd, axis_partitions, pidx);
+                }
+
+                if (err) {
+                        panic("axisflashmap could not add MTD partitions!\n");
+                }
+        }
+
+        if (!romfs_in_flash) {
+                /* Create an RAM device for the root partition (romfs). */
+
+#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0)
+                /* No use trying to boot this kernel from RAM. Panic! */
+                printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
+                       "device due to kernel (mis)configuration!\n");
+                panic("This kernel cannot boot from RAM!\n");
+#else
+                struct mtd_info *mtd_ram;
+
+                mtd_ram = (struct mtd_info *)kmalloc(sizeof(struct mtd_info),
+                                                     GFP_KERNEL);
+                if (!mtd_ram) {
+                        panic("axisflashmap couldn't allocate memory for "
+                              "mtd_info!\n");
+                }
+
+                printk(KERN_INFO " Adding RAM partition for romfs image:\n");
+                printk(pmsg, pidx, romfs_start, romfs_length);
+
+                err = mtdram_init_device(mtd_ram, (void*)romfs_start, 
+                                         romfs_length, "romfs");
+                if (err) {
+                        panic("axisflashmap could not initialize MTD RAM "
+                              "device!\n");
+                }
+#endif
+        }
+
+        return err;
+}
+
+/* This adds the above to the kernels init-call chain. */
+module_init(init_axis_flash);
+
+EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c
new file mode 100644
index 000000000000..fba530fcfaeb
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/ds1302.c
@@ -0,0 +1,602 @@
+/*!***************************************************************************
+*!
+*! FILE NAME  : ds1302.c
+*!
+*! DESCRIPTION: Implements an interface for the DS1302 RTC through Etrax I/O
+*!
+*! Functions exported: ds1302_readreg, ds1302_writereg, ds1302_init
+*!
+*! $Log: ds1302.c,v $
+*! Revision 1.14  2004/08/24 06:48:43  starvik
+*! Whitespace cleanup
+*!
+*! Revision 1.13  2004/05/28 09:26:59  starvik
+*! Modified I2C initialization to work in 2.6.
+*!
+*! Revision 1.12  2004/05/14 07:58:03  starvik
+*! Merge of changes from 2.4
+*!
+*! Revision 1.10  2004/02/04 09:25:12  starvik
+*! Merge of Linux 2.6.2
+*!
+*! Revision 1.9  2003/07/04 08:27:37  starvik
+*! Merge of Linux 2.5.74
+*!
+*! Revision 1.8  2003/04/09 05:20:47  starvik
+*! Merge of Linux 2.5.67
+*!
+*! Revision 1.6  2003/01/09 14:42:51  starvik
+*! Merge of Linux 2.5.55
+*!
+*! Revision 1.4  2002/12/11 13:13:57  starvik
+*! Added arch/ to v10 specific includes
+*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
+*!
+*! Revision 1.3  2002/11/20 11:56:10  starvik
+*! Merge of Linux 2.5.48
+*!
+*! Revision 1.2  2002/11/18 13:16:06  starvik
+*! Linux 2.5 port of latest 2.4 drivers
+*!
+*! Revision 1.15  2002/10/11 16:14:33  johana
+*! Added CONFIG_ETRAX_DS1302_TRICKLE_CHARGE and initial setting of the
+*! trcklecharge register.
+*!
+*! Revision 1.14  2002/10/10 12:15:38  magnusmn
+*! Added support for having the RST signal on bit g0
+*!
+*! Revision 1.13  2002/05/29 15:16:08  johana
+*! Removed unused variables.
+*!
+*! Revision 1.12  2002/04/10 15:35:25  johana
+*! Moved probe function closer to init function and marked it __init.
+*!
+*! Revision 1.11  2001/06/14 12:35:52  jonashg
+*! The ATA hack is back. It is unfortunately the only way to set g27 to output.
+*!
+*! Revision 1.9  2001/06/14 10:00:14  jonashg
+*! No need for tempudelay to be inline anymore (had to adjust the usec to
+*! loops conversion because of this to make it slow enough to be a udelay).
+*!
+*! Revision 1.8  2001/06/14 08:06:32  jonashg
+*! Made tempudelay delay usecs (well, just a tad more).
+*!
+*! Revision 1.7  2001/06/13 14:18:11  jonashg
+*! Only allow processes with SYS_TIME capability to set time and charge.
+*!
+*! Revision 1.6  2001/06/12 15:22:07  jonashg
+*! * Made init function __init.
+*! * Parameter to out_byte() is unsigned char.
+*! * The magic number 42 has got a name.
+*! * Removed comment about /proc (nothing is exported there).
+*!
+*! Revision 1.5  2001/06/12 14:35:13  jonashg
+*! Gave the module a name and added it to printk's.
+*!
+*! Revision 1.4  2001/05/31 14:53:40  jonashg
+*! Made tempudelay() inline so that the watchdog doesn't reset (see
+*! function comment).
+*!
+*! Revision 1.3  2001/03/26 16:03:06  bjornw
+*! Needs linux/config.h
+*!
+*! Revision 1.2  2001/03/20 19:42:00  bjornw
+*! Use the ETRAX prefix on the DS1302 options
+*!
+*! Revision 1.1  2001/03/20 09:13:50  magnusmn
+*! Linux 2.4 port
+*!
+*! Revision 1.10  2000/07/05 15:38:23  bjornw
+*! Dont update kernel time when a RTC_SET_TIME is done
+*!
+*! Revision 1.9  2000/03/02 15:42:59  macce
+*! * Hack to make RTC work on all 2100/2400
+*!
+*! Revision 1.8  2000/02/23 16:59:18  torbjore
+*! added setup of R_GEN_CONFIG when RTC is connected to the generic port.
+*!
+*! Revision 1.7  2000/01/17 15:51:43  johana
+*! Added RTC_SET_CHARGE ioctl to enable trickle charger.
+*!
+*! Revision 1.6  1999/10/27 13:19:47  bjornw
+*! Added update_xtime_from_cmos which reads back the updated RTC into the kernel.
+*! /dev/rtc calls it now.
+*!
+*! Revision 1.5  1999/10/27 12:39:37  bjornw
+*! Disabled superuser check. Anyone can now set the time.
+*!
+*! Revision 1.4  1999/09/02 13:27:46  pkj
+*! Added shadow for R_PORT_PB_CONFIG.
+*! Renamed port_g_shadow to port_g_data_shadow.
+*!
+*! Revision 1.3  1999/09/02 08:28:06  pkj
+*! Made it possible to select either port PB or the generic port for the RST
+*! signal line to the DS1302 RTC.
+*! Also make sure the RST bit is configured as output on Port PB (if used).
+*!
+*! Revision 1.2  1999/09/01 14:47:20  bjornw
+*! Added support for /dev/rtc operations with ioctl RD_TIME and SET_TIME to read
+*! and set the date. Register as major 121.
+*!
+*! Revision 1.1  1999/09/01 09:45:29  bjornw
+*! Implemented a DS1302 RTC driver.
+*!
+*!
+*! ---------------------------------------------------------------------------
+*!
+*! (C) Copyright 1999, 2000, 2001  Axis Communications AB, LUND, SWEDEN
+*!
+*! $Id: ds1302.c,v 1.14 2004/08/24 06:48:43 starvik Exp $
+*!
+*!***************************************************************************/
+
+#include <linux/config.h>
+
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+#include <linux/delay.h>
+#include <linux/bcd.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm/rtc.h>
+
+#define RTC_MAJOR_NR 121 /* local major, change later */
+
+static const char ds1302_name[] = "ds1302";
+
+/* The DS1302 might be connected to different bits on different products. 
+ * It has three signals - SDA, SCL and RST. RST and SCL are always outputs,
+ * but SDA can have a selected direction.
+ * For now, only PORT_PB is hardcoded.
+ */
+
+/* The RST bit may be on either the Generic Port or Port PB. */
+#ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
+#define TK_RST_OUT(x) REG_SHADOW_SET(R_PORT_G_DATA,  port_g_data_shadow,  CONFIG_ETRAX_DS1302_RSTBIT, x)
+#define TK_RST_DIR(x)
+#else
+#define TK_RST_OUT(x) REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_DS1302_RSTBIT, x)
+#define TK_RST_DIR(x) REG_SHADOW_SET(R_PORT_PB_DIR,  port_pb_dir_shadow,  CONFIG_ETRAX_DS1302_RSTBIT, x)
+#endif
+
+
+#define TK_SDA_OUT(x) REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_DS1302_SDABIT, x)
+#define TK_SCL_OUT(x) REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_DS1302_SCLBIT, x)
+
+#define TK_SDA_IN()   ((*R_PORT_PB_READ >> CONFIG_ETRAX_DS1302_SDABIT) & 1)
+/* 1 is out, 0 is in */
+#define TK_SDA_DIR(x) REG_SHADOW_SET(R_PORT_PB_DIR,  port_pb_dir_shadow,  CONFIG_ETRAX_DS1302_SDABIT, x)
+#define TK_SCL_DIR(x) REG_SHADOW_SET(R_PORT_PB_DIR,  port_pb_dir_shadow,  CONFIG_ETRAX_DS1302_SCLBIT, x)
+
+
+/*
+ * The reason for tempudelay and not udelay is that loops_per_usec
+ * (used in udelay) is not set when functions here are called from time.c 
+ */
+
+static void tempudelay(int usecs) 
+{
+        volatile int loops;
+
+        for(loops = usecs * 12; loops > 0; loops--)
+                /* nothing */;  
+}
+
+
+/* Send 8 bits. */
+static void
+out_byte(unsigned char x) 
+{
+        int i;
+        TK_SDA_DIR(1);
+        for (i = 8; i--;) {
+                /* The chip latches incoming bits on the rising edge of SCL. */
+                TK_SCL_OUT(0);
+                TK_SDA_OUT(x & 1);
+                tempudelay(1);
+                TK_SCL_OUT(1);
+                tempudelay(1);
+                x >>= 1;
+        }
+        TK_SDA_DIR(0);
+}
+
+static unsigned char
+in_byte(void) 
+{
+        unsigned char x = 0;
+        int i;
+
+        /* Read byte. Bits come LSB first, on the falling edge of SCL.
+         * Assume SDA is in input direction already.
+         */
+        TK_SDA_DIR(0);
+
+        for (i = 8; i--;) {
+                TK_SCL_OUT(0);
+                tempudelay(1);
+                x >>= 1;
+                x |= (TK_SDA_IN() << 7);
+                TK_SCL_OUT(1);
+                tempudelay(1);
+        }
+
+        return x;
+}
+
+/* Prepares for a transaction by de-activating RST (active-low). */
+
+static void
+start(void) 
+{
+        TK_SCL_OUT(0);
+        tempudelay(1);
+        TK_RST_OUT(0);
+        tempudelay(5);
+        TK_RST_OUT(1);  
+}
+
+/* Ends a transaction by taking RST active again. */
+
+static void
+stop(void) 
+{
+        tempudelay(2);
+        TK_RST_OUT(0);
+}
+
+/* Enable writing. */
+
+static void
+ds1302_wenable(void) 
+{
+        start();        
+        out_byte(0x8e); /* Write control register  */
+        out_byte(0x00); /* Disable write protect bit 7 = 0 */
+        stop();
+}
+
+/* Disable writing. */
+
+static void
+ds1302_wdisable(void) 
+{
+        start();
+        out_byte(0x8e); /* Write control register  */
+        out_byte(0x80); /* Disable write protect bit 7 = 0 */
+        stop();
+}
+
+
+
+/* Read a byte from the selected register in the DS1302. */
+
+unsigned char
+ds1302_readreg(int reg) 
+{
+        unsigned char x;
+
+        start();
+        out_byte(0x81 | (reg << 1)); /* read register */
+        x = in_byte();
+        stop();
+
+        return x;
+}
+
+/* Write a byte to the selected register. */
+
+void
+ds1302_writereg(int reg, unsigned char val) 
+{
+#ifndef CONFIG_ETRAX_RTC_READONLY
+        int do_writereg = 1;
+#else
+        int do_writereg = 0;
+
+        if (reg == RTC_TRICKLECHARGER)
+                do_writereg = 1;
+#endif
+
+        if (do_writereg) {
+                ds1302_wenable();
+                start();
+                out_byte(0x80 | (reg << 1)); /* write register */
+                out_byte(val);
+                stop();
+                ds1302_wdisable();
+        }
+}
+
+void
+get_rtc_time(struct rtc_time *rtc_tm) 
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        local_irq_disable();
+
+        rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS);
+        rtc_tm->tm_min = CMOS_READ(RTC_MINUTES);
+        rtc_tm->tm_hour = CMOS_READ(RTC_HOURS);
+        rtc_tm->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
+        rtc_tm->tm_mon = CMOS_READ(RTC_MONTH);
+        rtc_tm->tm_year = CMOS_READ(RTC_YEAR);
+
+        local_irq_restore(flags);
+        
+        BCD_TO_BIN(rtc_tm->tm_sec);
+        BCD_TO_BIN(rtc_tm->tm_min);
+        BCD_TO_BIN(rtc_tm->tm_hour);
+        BCD_TO_BIN(rtc_tm->tm_mday);
+        BCD_TO_BIN(rtc_tm->tm_mon);
+        BCD_TO_BIN(rtc_tm->tm_year);
+
+        /*
+         * Account for differences between how the RTC uses the values
+         * and how they are defined in a struct rtc_time;
+         */
+
+        if (rtc_tm->tm_year <= 69)
+                rtc_tm->tm_year += 100;
+
+        rtc_tm->tm_mon--;
+}
+
+static unsigned char days_in_mo[] = 
+    {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
+
+/* ioctl that supports RTC_RD_TIME and RTC_SET_TIME (read and set time/date). */
+
+static int
+rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+          unsigned long arg) 
+{
+        unsigned long flags;
+
+        switch(cmd) {
+                case RTC_RD_TIME:       /* read the time/date from RTC  */
+                {
+                        struct rtc_time rtc_tm;
+                                                
+                        memset(&rtc_tm, 0, sizeof (struct rtc_time));
+                        get_rtc_time(&rtc_tm);                                          
+                        if (copy_to_user((struct rtc_time*)arg, &rtc_tm, sizeof(struct rtc_time)))
+                                return -EFAULT; 
+                        return 0;
+                }
+
+                case RTC_SET_TIME:      /* set the RTC */
+                {
+                        struct rtc_time rtc_tm;
+                        unsigned char mon, day, hrs, min, sec, leap_yr;
+                        unsigned int yrs;
+
+                        if (!capable(CAP_SYS_TIME))
+                                return -EPERM;
+
+                        if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, sizeof(struct rtc_time)))
+                                return -EFAULT;         
+
+                        yrs = rtc_tm.tm_year + 1900;
+                        mon = rtc_tm.tm_mon + 1;   /* tm_mon starts at zero */
+                        day = rtc_tm.tm_mday;
+                        hrs = rtc_tm.tm_hour;
+                        min = rtc_tm.tm_min;
+                        sec = rtc_tm.tm_sec;
+                        
+                        
+                        if ((yrs < 1970) || (yrs > 2069))
+                                return -EINVAL;
+
+                        leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400));
+
+                        if ((mon > 12) || (day == 0))
+                                return -EINVAL;
+
+                        if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr)))
+                                return -EINVAL;
+                        
+                        if ((hrs >= 24) || (min >= 60) || (sec >= 60))
+                                return -EINVAL;
+
+                        if (yrs >= 2000)
+                                yrs -= 2000;    /* RTC (0, 1, ... 69) */
+                        else
+                                yrs -= 1900;    /* RTC (70, 71, ... 99) */
+
+                        BIN_TO_BCD(sec);
+                        BIN_TO_BCD(min);
+                        BIN_TO_BCD(hrs);
+                        BIN_TO_BCD(day);
+                        BIN_TO_BCD(mon);
+                        BIN_TO_BCD(yrs);
+
+                        local_irq_save(flags);
+                        local_irq_disable();
+                        CMOS_WRITE(yrs, RTC_YEAR);
+                        CMOS_WRITE(mon, RTC_MONTH);
+                        CMOS_WRITE(day, RTC_DAY_OF_MONTH);
+                        CMOS_WRITE(hrs, RTC_HOURS);
+                        CMOS_WRITE(min, RTC_MINUTES);
+                        CMOS_WRITE(sec, RTC_SECONDS);
+                        local_irq_restore(flags);
+
+                        /* Notice that at this point, the RTC is updated but
+                         * the kernel is still running with the old time.
+                         * You need to set that separately with settimeofday
+                         * or adjtimex.
+                         */
+                        return 0;
+                }
+
+                case RTC_SET_CHARGE: /* set the RTC TRICKLE CHARGE register */
+                {
+                        int tcs_val;                        
+
+                        if (!capable(CAP_SYS_TIME))
+                                return -EPERM;
+                        
+                        if(copy_from_user(&tcs_val, (int*)arg, sizeof(int)))
+                                return -EFAULT;
+
+                        tcs_val = RTC_TCR_PATTERN | (tcs_val & 0x0F);
+                        ds1302_writereg(RTC_TRICKLECHARGER, tcs_val);
+                        return 0;
+                }
+                case RTC_VLOW_RD:
+                {
+                        /* TODO:
+                         * Implement voltage low detection support
+                         */
+                        printk(KERN_WARNING "DS1302: RTC Voltage Low detection"
+                               " is not supported\n");
+                        return 0;
+                }
+                case RTC_VLOW_SET:
+                {
+                        /* TODO:
+                         * Nothing to do since Voltage Low detection is not supported
+                         */
+                        return 0;
+                }
+                default:
+                        return -ENOIOCTLCMD;
+        }
+}
+
+static void
+print_rtc_status(void)
+{
+        struct rtc_time tm;
+
+        get_rtc_time(&tm);
+
+        /*
+         * There is no way to tell if the luser has the RTC set for local
+         * time or for Universal Standard Time (GMT). Probably local though.
+         */
+
+        printk(KERN_INFO "rtc_time\t: %02d:%02d:%02d\n",
+               tm.tm_hour, tm.tm_min, tm.tm_sec);
+        printk(KERN_INFO "rtc_date\t: %04d-%02d-%02d\n",
+               tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday);
+}
+
+/* The various file operations we support. */
+
+static struct file_operations rtc_fops = {
+        .owner          = THIS_MODULE,
+        .ioctl          = rtc_ioctl,    
+}; 
+
+/* Probe for the chip by writing something to its RAM and try reading it back. */
+
+#define MAGIC_PATTERN 0x42
+
+static int __init
+ds1302_probe(void) 
+{
+        int retval, res; 
+
+        TK_RST_DIR(1);
+        TK_SCL_DIR(1);
+        TK_SDA_DIR(0);
+        
+        /* Try to talk to timekeeper. */
+
+        ds1302_wenable();  
+        start();
+        out_byte(0xc0); /* write RAM byte 0 */  
+        out_byte(MAGIC_PATTERN); /* write something magic */
+        start();
+        out_byte(0xc1); /* read RAM byte 0 */
+
+        if((res = in_byte()) == MAGIC_PATTERN) {
+                stop();
+                ds1302_wdisable();
+                printk(KERN_INFO "%s: RTC found.\n", ds1302_name);
+                printk(KERN_INFO "%s: SDA, SCL, RST on PB%i, PB%i, %s%i\n",
+                       ds1302_name,
+                       CONFIG_ETRAX_DS1302_SDABIT,
+                       CONFIG_ETRAX_DS1302_SCLBIT,
+#ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
+                       "GENIO",
+#else
+                       "PB",
+#endif
+                       CONFIG_ETRAX_DS1302_RSTBIT);
+                print_rtc_status();
+                retval = 1;
+        } else {
+                stop();
+                retval = 0;
+        }
+
+        return retval;
+}
+
+
+/* Just probe for the RTC and register the device to handle the ioctl needed. */
+
+int __init
+ds1302_init(void) 
+{
+        i2c_init();
+
+        if (!ds1302_probe()) {
+#ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
+#if CONFIG_ETRAX_DS1302_RSTBIT == 27
+                /*
+                 * The only way to set g27 to output is to enable ATA.
+                 *
+                 * Make sure that R_GEN_CONFIG is setup correct.
+                 */
+                genconfig_shadow = ((genconfig_shadow &
+                                     ~IO_MASK(R_GEN_CONFIG, ata)) | 
+                                   (IO_STATE(R_GEN_CONFIG, ata, select)));    
+                *R_GEN_CONFIG = genconfig_shadow;
+#elif CONFIG_ETRAX_DS1302_RSTBIT == 0
+                
+                /* Set the direction of this bit to out. */             
+                genconfig_shadow = ((genconfig_shadow &
+                                     ~IO_MASK(R_GEN_CONFIG, g0dir)) | 
+                                   (IO_STATE(R_GEN_CONFIG, g0dir, out)));    
+                *R_GEN_CONFIG = genconfig_shadow;
+#endif
+                if (!ds1302_probe()) {
+                        printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name);
+                        return -1;
+                }
+#else
+                printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name);
+                return -1;
+#endif
+        }
+        /* Initialise trickle charger */
+        ds1302_writereg(RTC_TRICKLECHARGER,
+                        RTC_TCR_PATTERN |(CONFIG_ETRAX_DS1302_TRICKLE_CHARGE & 0x0F));
+        /* Start clock by resetting CLOCK_HALT */
+        ds1302_writereg(RTC_SECONDS, (ds1302_readreg(RTC_SECONDS) & 0x7F));
+        return 0;
+}
+
+static int __init ds1302_register(void)
+{
+        ds1302_init();
+        if (register_chrdev(RTC_MAJOR_NR, ds1302_name, &rtc_fops)) {
+                printk(KERN_INFO "%s: unable to get major %d for rtc\n", 
+                       ds1302_name, RTC_MAJOR_NR);
+                return -1;
+        }
+        return 0;
+
+}
+
+module_init(ds1302_register);
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
new file mode 100644
index 000000000000..316ca15d6802
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/eeprom.c
@@ -0,0 +1,945 @@
+/*!*****************************************************************************
+*!
+*!  Implements an interface for i2c compatible eeproms to run under linux.
+*!  Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by
+*!  Johan.Adolfsson@axis.com
+*!
+*!  Probing results:
+*!    8k or not is detected (the assumes 2k or 16k)
+*!    2k or 16k detected using test reads and writes.
+*!
+*!------------------------------------------------------------------------
+*!  HISTORY
+*!
+*!  DATE          NAME              CHANGES
+*!  ----          ----              -------
+*!  Aug  28 1999  Edgar Iglesias    Initial Version
+*!  Aug  31 1999  Edgar Iglesias    Allow simultaneous users.
+*!  Sep  03 1999  Edgar Iglesias    Updated probe.
+*!  Sep  03 1999  Edgar Iglesias    Added bail-out stuff if we get interrupted
+*!                                  in the spin-lock.
+*!
+*!  $Log: eeprom.c,v $
+*!  Revision 1.10  2003/09/11 07:29:48  starvik
+*!  Merge of Linux 2.6.0-test5
+*!
+*!  Revision 1.9  2003/07/04 08:27:37  starvik
+*!  Merge of Linux 2.5.74
+*!
+*!  Revision 1.8  2003/04/09 05:20:47  starvik
+*!  Merge of Linux 2.5.67
+*!
+*!  Revision 1.6  2003/02/10 07:19:28  starvik
+*!  Removed misplaced ;
+*!
+*!  Revision 1.5  2002/12/11 13:13:57  starvik
+*!  Added arch/ to v10 specific includes
+*!  Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
+*!
+*!  Revision 1.4  2002/11/20 11:56:10  starvik
+*!  Merge of Linux 2.5.48
+*!
+*!  Revision 1.3  2002/11/18 13:16:06  starvik
+*!  Linux 2.5 port of latest 2.4 drivers
+*!
+*!  Revision 1.8  2001/06/15 13:24:29  jonashg
+*!  * Added verification of pointers from userspace in read and write.
+*!  * Made busy counter volatile.
+*!  * Added define for inital write delay.
+*!  * Removed warnings by using loff_t instead of unsigned long.
+*!
+*!  Revision 1.7  2001/06/14 15:26:54  jonashg
+*!  Removed test because condition is always true.
+*!
+*!  Revision 1.6  2001/06/14 15:18:20  jonashg
+*!  Kb -> kB (makes quite a difference if you don't know if you have 2k or 16k).
+*!
+*!  Revision 1.5  2001/06/14 14:39:51  jonashg
+*!  Forgot to use name when registering the driver.
+*!
+*!  Revision 1.4  2001/06/14 14:35:47  jonashg
+*!  * Gave driver a name and used it in printk's.
+*!  * Cleanup.
+*!
+*!  Revision 1.3  2001/03/19 16:04:46  markusl
+*!  Fixed init of fops struct
+*!
+*!  Revision 1.2  2001/03/19 10:35:07  markusl
+*!  2.4 port of eeprom driver
+*!
+*!  Revision 1.8  2000/05/18 10:42:25  edgar
+*!  Make sure to end write cycle on _every_ write
+*!
+*!  Revision 1.7  2000/01/17 17:41:01  johana
+*!  Adjusted probing and return -ENOSPC when writing outside EEPROM
+*!
+*!  Revision 1.6  2000/01/17 15:50:36  johana
+*!  Added adaptive timing adjustments and fixed autoprobing for 2k and 16k(?)
+*!  EEPROMs
+*!
+*!  Revision 1.5  1999/09/03 15:07:37  edgar
+*!  Added bail-out check to the spinlock
+*!
+*!  Revision 1.4  1999/09/03 12:11:17  bjornw
+*!  Proper atomicity (need to use spinlocks, not if's). users -> busy.
+*!
+*!
+*!        (c) 1999 Axis Communications AB, Lund, Sweden
+*!*****************************************************************************/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <asm/uaccess.h>
+#include "i2c.h"
+
+#define D(x) 
+
+/* If we should use adaptive timing or not: */
+//#define EEPROM_ADAPTIVE_TIMING      
+
+#define EEPROM_MAJOR_NR 122  /* use a LOCAL/EXPERIMENTAL major for now */
+#define EEPROM_MINOR_NR 0
+
+/* Empirical sane initial value of the delay, the value will be adapted to
+ * what the chip needs when using EEPROM_ADAPTIVE_TIMING.
+ */
+#define INITIAL_WRITEDELAY_US 4000
+#define MAX_WRITEDELAY_US 10000 /* 10 ms according to spec for 2KB EEPROM */
+
+/* This one defines how many times to try when eeprom fails. */
+#define EEPROM_RETRIES 10
+
+#define EEPROM_2KB (2 * 1024)
+/*#define EEPROM_4KB (4 * 1024)*/ /* Exists but not used in Axis products */
+#define EEPROM_8KB (8 * 1024 - 1 ) /* Last byte has write protection bit */
+#define EEPROM_16KB (16 * 1024)
+
+#define i2c_delay(x) udelay(x)
+
+/*
+ *  This structure describes the attached eeprom chip.
+ *  The values are probed for.
+ */
+
+struct eeprom_type
+{
+  unsigned long size;
+  unsigned long sequential_write_pagesize;
+  unsigned char select_cmd;
+  unsigned long usec_delay_writecycles; /* Min time between write cycles
+                                           (up to 10ms for some models) */
+  unsigned long usec_delay_step; /* For adaptive algorithm */
+  int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */
+  
+  /* this one is to keep the read/write operations atomic */
+  wait_queue_head_t wait_q;
+  volatile int busy;
+  int retry_cnt_addr; /* Used to keep track of number of retries for
+                         adaptive timing adjustments */
+  int retry_cnt_read;
+};
+
+static int  eeprom_open(struct inode * inode, struct file * file);
+static loff_t  eeprom_lseek(struct file * file, loff_t offset, int orig);
+static ssize_t  eeprom_read(struct file * file, char * buf, size_t count,
+                            loff_t *off);
+static ssize_t  eeprom_write(struct file * file, const char * buf, size_t count,
+                             loff_t *off);
+static int eeprom_close(struct inode * inode, struct file * file);
+
+static int  eeprom_address(unsigned long addr);
+static int  read_from_eeprom(char * buf, int count);
+static int eeprom_write_buf(loff_t addr, const char * buf, int count);
+static int eeprom_read_buf(loff_t addr, char * buf, int count);
+
+static void eeprom_disable_write_protect(void);
+
+
+static const char eeprom_name[] = "eeprom";
+
+/* chip description */
+static struct eeprom_type eeprom;
+
+/* This is the exported file-operations structure for this device. */
+struct file_operations eeprom_fops =
+{
+  .llseek  = eeprom_lseek,
+  .read    = eeprom_read,
+  .write   = eeprom_write,
+  .open    = eeprom_open,
+  .release = eeprom_close
+};
+
+/* eeprom init call. Probes for different eeprom models. */
+
+int __init eeprom_init(void)
+{
+  init_waitqueue_head(&eeprom.wait_q);
+  eeprom.busy = 0;
+
+#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
+#define EETEXT "Found"
+#else
+#define EETEXT "Assuming"
+#endif
+  if (register_chrdev(EEPROM_MAJOR_NR, eeprom_name, &eeprom_fops))
+  {
+    printk(KERN_INFO "%s: unable to get major %d for eeprom device\n",
+           eeprom_name, EEPROM_MAJOR_NR);
+    return -1;
+  }
+  
+  printk("EEPROM char device v0.3, (c) 2000 Axis Communications AB\n");
+
+  /*
+   *  Note: Most of this probing method was taken from the printserver (5470e)
+   *        codebase. It did not contain a way of finding the 16kB chips
+   *        (M24128 or variants). The method used here might not work
+   *        for all models. If you encounter problems the easiest way
+   *        is probably to define your model within #ifdef's, and hard-
+   *        code it.
+   */
+
+  eeprom.size = 0;
+  eeprom.usec_delay_writecycles = INITIAL_WRITEDELAY_US;
+  eeprom.usec_delay_step = 128;
+  eeprom.adapt_state = 0;
+  
+#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
+  i2c_start();
+  i2c_outbyte(0x80);
+  if(!i2c_getack())
+  {
+    /* It's not 8k.. */
+    int success = 0;
+    unsigned char buf_2k_start[16];
+    
+    /* Im not sure this will work... :) */
+    /* assume 2kB, if failure go for 16kB */
+    /* Test with 16kB settings.. */
+    /* If it's a 2kB EEPROM and we address it outside it's range
+     * it will mirror the address space:
+     * 1. We read two locations (that are mirrored), 
+     *    if the content differs * it's a 16kB EEPROM.
+     * 2. if it doesn't differ - write different value to one of the locations,
+     *    check the other - if content still is the same it's a 2k EEPROM,
+     *    restore original data.
+     */
+#define LOC1 8
+#define LOC2 (0x1fb) /*1fb, 3ed, 5df, 7d1 */
+
+   /* 2k settings */  
+    i2c_stop();
+    eeprom.size = EEPROM_2KB;
+    eeprom.select_cmd = 0xA0;   
+    eeprom.sequential_write_pagesize = 16;
+    if( eeprom_read_buf( 0, buf_2k_start, 16 ) == 16 )
+    {
+      D(printk("2k start: '%16.16s'\n", buf_2k_start));
+    }
+    else
+    {
+      printk(KERN_INFO "%s: Failed to read in 2k mode!\n", eeprom_name);  
+    }
+    
+    /* 16k settings */
+    eeprom.size = EEPROM_16KB;
+    eeprom.select_cmd = 0xA0;   
+    eeprom.sequential_write_pagesize = 64;
+
+    {
+      unsigned char loc1[4], loc2[4], tmp[4];
+      if( eeprom_read_buf(LOC2, loc2, 4) == 4)
+      {
+        if( eeprom_read_buf(LOC1, loc1, 4) == 4)
+        {
+          D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", 
+                   LOC1, loc1, LOC2, loc2));
+#if 0
+          if (memcmp(loc1, loc2, 4) != 0 )
+          {
+            /* It's 16k */
+            printk(KERN_INFO "%s: 16k detected in step 1\n", eeprom_name);
+            eeprom.size = EEPROM_16KB;     
+            success = 1;
+          }
+          else
+#endif
+          {
+            /* Do step 2 check */
+            /* Invert value */
+            loc1[0] = ~loc1[0];
+            if (eeprom_write_buf(LOC1, loc1, 1) == 1)
+            {
+              /* If 2k EEPROM this write will actually write 10 bytes
+               * from pos 0
+               */
+              D(printk("1 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", 
+                       LOC1, loc1, LOC2, loc2));
+              if( eeprom_read_buf(LOC1, tmp, 4) == 4)
+              {
+                D(printk("2 loc1: (%i) '%4.4s' tmp '%4.4s'\n", 
+                         LOC1, loc1, tmp));
+                if (memcmp(loc1, tmp, 4) != 0 )
+                {
+                  printk(KERN_INFO "%s: read and write differs! Not 16kB\n",
+                         eeprom_name);
+                  loc1[0] = ~loc1[0];
+                  
+                  if (eeprom_write_buf(LOC1, loc1, 1) == 1)
+                  {
+                    success = 1;
+                  }
+                  else
+                  {
+                    printk(KERN_INFO "%s: Restore 2k failed during probe,"
+                           " EEPROM might be corrupt!\n", eeprom_name);
+                    
+                  }
+                  i2c_stop();
+                  /* Go to 2k mode and write original data */
+                  eeprom.size = EEPROM_2KB;
+                  eeprom.select_cmd = 0xA0;   
+                  eeprom.sequential_write_pagesize = 16;
+                  if( eeprom_write_buf(0, buf_2k_start, 16) == 16)
+                  {
+                  }
+                  else
+                  {
+                    printk(KERN_INFO "%s: Failed to write back 2k start!\n",
+                           eeprom_name);
+                  }
+                  
+                  eeprom.size = EEPROM_2KB;
+                }
+              }
+                
+              if(!success)
+              {
+                if( eeprom_read_buf(LOC2, loc2, 1) == 1)
+                {
+                  D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", 
+                           LOC1, loc1, LOC2, loc2));
+                  if (memcmp(loc1, loc2, 4) == 0 )
+                  {
+                    /* Data the same, must be mirrored -> 2k */
+                    /* Restore data */
+                    printk(KERN_INFO "%s: 2k detected in step 2\n", eeprom_name);
+                    loc1[0] = ~loc1[0];
+                    if (eeprom_write_buf(LOC1, loc1, 1) == 1)
+                    {
+                      success = 1;
+                    }
+                    else
+                    {
+                      printk(KERN_INFO "%s: Restore 2k failed during probe,"
+                             " EEPROM might be corrupt!\n", eeprom_name);
+                      
+                    }
+                    
+                    eeprom.size = EEPROM_2KB;     
+                  }
+                  else
+                  {
+                    printk(KERN_INFO "%s: 16k detected in step 2\n",
+                           eeprom_name);
+                    loc1[0] = ~loc1[0];
+                    /* Data differs, assume 16k */
+                    /* Restore data */
+                    if (eeprom_write_buf(LOC1, loc1, 1) == 1)
+                    {
+                      success = 1;
+                    }
+                    else
+                    {
+                      printk(KERN_INFO "%s: Restore 16k failed during probe,"
+                             " EEPROM might be corrupt!\n", eeprom_name);
+                    }
+                    
+                    eeprom.size = EEPROM_16KB;
+                  }
+                }
+              }
+            }
+          } /* read LOC1 */
+        } /* address LOC1 */
+        if (!success)
+        {
+          printk(KERN_INFO "%s: Probing failed!, using 2KB!\n", eeprom_name);
+          eeprom.size = EEPROM_2KB;               
+        }
+      } /* read */
+    }
+  }
+  else
+  {
+    i2c_outbyte(0x00);
+    if(!i2c_getack())
+    {
+      /* No 8k */
+      eeprom.size = EEPROM_2KB;
+    }
+    else
+    {
+      i2c_start();
+      i2c_outbyte(0x81);
+      if (!i2c_getack())
+      {
+        eeprom.size = EEPROM_2KB;
+      }
+      else
+      {
+        /* It's a 8kB */
+        i2c_inbyte();
+        eeprom.size = EEPROM_8KB;
+      }
+    }
+  }
+  i2c_stop();
+#elif defined(CONFIG_ETRAX_I2C_EEPROM_16KB)
+  eeprom.size = EEPROM_16KB;
+#elif defined(CONFIG_ETRAX_I2C_EEPROM_8KB)
+  eeprom.size = EEPROM_8KB;
+#elif defined(CONFIG_ETRAX_I2C_EEPROM_2KB)
+  eeprom.size = EEPROM_2KB;
+#endif
+
+  switch(eeprom.size)
+  {
+   case (EEPROM_2KB):
+     printk("%s: " EETEXT " i2c compatible 2kB eeprom.\n", eeprom_name);
+     eeprom.sequential_write_pagesize = 16;
+     eeprom.select_cmd = 0xA0;
+     break;
+   case (EEPROM_8KB):
+     printk("%s: " EETEXT " i2c compatible 8kB eeprom.\n", eeprom_name);
+     eeprom.sequential_write_pagesize = 16;
+     eeprom.select_cmd = 0x80;
+     break;
+   case (EEPROM_16KB):
+     printk("%s: " EETEXT " i2c compatible 16kB eeprom.\n", eeprom_name);
+     eeprom.sequential_write_pagesize = 64;
+     eeprom.select_cmd = 0xA0;     
+     break;
+   default:
+     eeprom.size = 0;
+     printk("%s: Did not find a supported eeprom\n", eeprom_name);
+     break;
+  }
+
+  
+
+  eeprom_disable_write_protect();
+
+  return 0;
+}
+
+/* Opens the device. */
+
+static int eeprom_open(struct inode * inode, struct file * file)
+{
+
+  if(MINOR(inode->i_rdev) != EEPROM_MINOR_NR)
+     return -ENXIO;
+  if(MAJOR(inode->i_rdev) != EEPROM_MAJOR_NR)
+     return -ENXIO;
+
+  if( eeprom.size > 0 )
+  {
+    /* OK */
+    return 0;
+  }
+
+  /* No EEprom found */
+  return -EFAULT;
+}
+
+/* Changes the current file position. */
+
+static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig)
+{
+/*
+ *  orig 0: position from begning of eeprom
+ *  orig 1: relative from current position
+ *  orig 2: position from last eeprom address
+ */
+  
+  switch (orig)
+  {
+   case 0:
+     file->f_pos = offset;
+     break;
+   case 1:
+     file->f_pos += offset;
+     break;
+   case 2:
+     file->f_pos = eeprom.size - offset;
+     break;
+   default:
+     return -EINVAL;
+  }
+
+  /* truncate position */
+  if (file->f_pos < 0)
+  {
+    file->f_pos = 0;    
+    return(-EOVERFLOW);
+  }
+  
+  if (file->f_pos >= eeprom.size)
+  {
+    file->f_pos = eeprom.size - 1;
+    return(-EOVERFLOW);
+  }
+
+  return ( file->f_pos );
+}
+
+/* Reads data from eeprom. */
+
+static int eeprom_read_buf(loff_t addr, char * buf, int count)
+{
+  struct file f;
+
+  f.f_pos = addr;
+  return eeprom_read(&f, buf, count, &addr);
+}
+
+
+
+/* Reads data from eeprom. */
+
+static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off)
+{
+  int read=0;
+  unsigned long p = file->f_pos;
+
+  unsigned char page;
+
+  if(p >= eeprom.size)  /* Address i 0 - (size-1) */
+  {
+    return -EFAULT;
+  }
+  
+  while(eeprom.busy)
+  {
+    interruptible_sleep_on(&eeprom.wait_q);
+
+    /* bail out if we get interrupted */
+    if (signal_pending(current))
+      return -EINTR;
+    
+  }
+  eeprom.busy++;
+
+  page = (unsigned char) (p >> 8);
+  
+  if(!eeprom_address(p))
+  {
+    printk(KERN_INFO "%s: Read failed to address the eeprom: "
+           "0x%08X (%i) page: %i\n", eeprom_name, (int)p, (int)p, page);
+    i2c_stop();
+    
+    /* don't forget to wake them up */
+    eeprom.busy--;
+    wake_up_interruptible(&eeprom.wait_q);  
+    return -EFAULT;
+  }
+
+  if( (p + count) > eeprom.size)
+  {
+    /* truncate count */
+    count = eeprom.size - p;
+  }
+
+  /* stop dummy write op and initiate the read op */
+  i2c_start();
+
+  /* special case for small eeproms */
+  if(eeprom.size < EEPROM_16KB)
+  {
+    i2c_outbyte( eeprom.select_cmd | 1 | (page << 1) );
+  }
+
+  /* go on with the actual read */
+  read = read_from_eeprom( buf, count);
+  
+  if(read > 0)
+  {
+    file->f_pos += read;
+  }
+
+  eeprom.busy--;
+  wake_up_interruptible(&eeprom.wait_q);
+  return read;
+}
+
+/* Writes data to eeprom. */
+
+static int eeprom_write_buf(loff_t addr, const char * buf, int count)
+{
+  struct file f;
+
+  f.f_pos = addr;
+  
+  return eeprom_write(&f, buf, count, &addr);
+}
+
+
+/* Writes data to eeprom. */
+
+static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
+                            loff_t *off)
+{
+  int i, written, restart=1;
+  unsigned long p;
+
+  if (!access_ok(VERIFY_READ, buf, count))
+  {
+    return -EFAULT;
+  }
+
+  while(eeprom.busy)
+  {
+    interruptible_sleep_on(&eeprom.wait_q);
+    /* bail out if we get interrupted */
+    if (signal_pending(current))
+      return -EINTR;
+  }
+  eeprom.busy++;
+  for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++)
+  {
+    restart = 0;
+    written = 0;
+    p = file->f_pos;
+   
+    
+    while( (written < count) && (p < eeprom.size))
+    {
+      /* address the eeprom */
+      if(!eeprom_address(p))
+      {
+        printk(KERN_INFO "%s: Write failed to address the eeprom: "
+               "0x%08X (%i) \n", eeprom_name, (int)p, (int)p);
+        i2c_stop();
+        
+        /* don't forget to wake them up */
+        eeprom.busy--;
+        wake_up_interruptible(&eeprom.wait_q);
+        return -EFAULT;
+      }
+#ifdef EEPROM_ADAPTIVE_TIMING      
+      /* Adaptive algorithm to adjust timing */
+      if (eeprom.retry_cnt_addr > 0)
+      {
+        /* To Low now */
+        D(printk(">D=%i d=%i\n",
+               eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
+
+        if (eeprom.usec_delay_step < 4)
+        {
+          eeprom.usec_delay_step++;
+          eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
+        }
+        else
+        {
+
+          if (eeprom.adapt_state > 0)
+          {
+            /* To Low before */
+            eeprom.usec_delay_step *= 2;
+            if (eeprom.usec_delay_step > 2)
+            {
+              eeprom.usec_delay_step--;
+            }
+            eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
+          }
+          else if (eeprom.adapt_state < 0)
+          {
+            /* To High before (toggle dir) */
+            eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
+            if (eeprom.usec_delay_step > 1)
+            {
+              eeprom.usec_delay_step /= 2;
+              eeprom.usec_delay_step--;
+            }
+          }
+        }
+
+        eeprom.adapt_state = 1;
+      }
+      else
+      {
+        /* To High (or good) now */
+        D(printk("<D=%i d=%i\n",
+               eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
+        
+        if (eeprom.adapt_state < 0)
+        {
+          /* To High before */
+          if (eeprom.usec_delay_step > 1)
+          {
+            eeprom.usec_delay_step *= 2;
+            eeprom.usec_delay_step--;
+            
+            if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
+            {
+              eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
+            }
+          }
+        }
+        else if (eeprom.adapt_state > 0)
+        {
+          /* To Low before (toggle dir) */
+          if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
+          {
+            eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
+          }
+          if (eeprom.usec_delay_step > 1)
+          {
+            eeprom.usec_delay_step /= 2;
+            eeprom.usec_delay_step--;
+          }
+          
+          eeprom.adapt_state = -1;
+        }
+
+        if (eeprom.adapt_state > -100)
+        {
+          eeprom.adapt_state--;
+        }
+        else
+        {
+          /* Restart adaption */
+          D(printk("#Restart\n"));
+          eeprom.usec_delay_step++;
+        }
+      }
+#endif /* EEPROM_ADAPTIVE_TIMING */
+      /* write until we hit a page boundary or count */
+      do
+      {
+        i2c_outbyte(buf[written]);        
+        if(!i2c_getack())
+        {
+          restart=1;
+          printk(KERN_INFO "%s: write error, retrying. %d\n", eeprom_name, i);
+          i2c_stop();
+          break;
+        }
+        written++;
+        p++;        
+      } while( written < count && ( p % eeprom.sequential_write_pagesize ));
+
+      /* end write cycle */
+      i2c_stop();
+      i2c_delay(eeprom.usec_delay_writecycles);
+    } /* while */
+  } /* for  */
+
+  eeprom.busy--;
+  wake_up_interruptible(&eeprom.wait_q);
+  if (written == 0 && file->f_pos >= eeprom.size){
+    return -ENOSPC;
+  }
+  file->f_pos += written;
+  return written;
+}
+
+/* Closes the device. */
+
+static int eeprom_close(struct inode * inode, struct file * file)
+{
+  /* do nothing for now */
+  return 0;
+}
+
+/* Sets the current address of the eeprom. */
+
+static int eeprom_address(unsigned long addr)
+{
+  int i;
+  unsigned char page, offset;
+
+  page   = (unsigned char) (addr >> 8);
+  offset = (unsigned char)  addr;
+
+  for(i = 0; i < EEPROM_RETRIES; i++)
+  {
+    /* start a dummy write for addressing */
+    i2c_start();
+
+    if(eeprom.size == EEPROM_16KB)
+    {
+      i2c_outbyte( eeprom.select_cmd ); 
+      i2c_getack();
+      i2c_outbyte(page); 
+    }
+    else
+    {
+      i2c_outbyte( eeprom.select_cmd | (page << 1) ); 
+    }
+    if(!i2c_getack())
+    {
+      /* retry */
+      i2c_stop();
+      /* Must have a delay here.. 500 works, >50, 100->works 5th time*/
+      i2c_delay(MAX_WRITEDELAY_US / EEPROM_RETRIES * i);
+      /* The chip needs up to 10 ms from write stop to next start */
+     
+    }
+    else
+    {
+      i2c_outbyte(offset);
+      
+      if(!i2c_getack())
+      {
+        /* retry */
+        i2c_stop();
+      }
+      else
+        break;
+    }
+  }    
+
+  
+  eeprom.retry_cnt_addr = i;
+  D(printk("%i\n", eeprom.retry_cnt_addr));
+  if(eeprom.retry_cnt_addr == EEPROM_RETRIES)
+  {
+    /* failed */
+    return 0;
+  }
+  return 1;
+}
+
+/* Reads from current address. */
+
+static int read_from_eeprom(char * buf, int count)
+{
+  int i, read=0;
+
+  for(i = 0; i < EEPROM_RETRIES; i++)
+  {    
+    if(eeprom.size == EEPROM_16KB)
+    {
+      i2c_outbyte( eeprom.select_cmd | 1 );
+    }
+
+    if(i2c_getack())
+    {
+      break;
+    }
+  }
+  
+  if(i == EEPROM_RETRIES)
+  {
+    printk(KERN_INFO "%s: failed to read from eeprom\n", eeprom_name);
+    i2c_stop();
+    
+    return -EFAULT;
+  }
+
+  while( (read < count))
+  {    
+    if (put_user(i2c_inbyte(), &buf[read++]))
+    {
+      i2c_stop();
+
+      return -EFAULT;
+    }
+
+    /*
+     *  make sure we don't ack last byte or you will get very strange
+     *  results!
+     */
+    if(read < count)
+    {
+      i2c_sendack();
+    }
+  }
+
+  /* stop the operation */
+  i2c_stop();
+
+  return read;
+}
+
+/* Disables write protection if applicable. */
+
+#define DBP_SAVE(x)
+#define ax_printf printk
+static void eeprom_disable_write_protect(void)
+{
+  /* Disable write protect */
+  if (eeprom.size == EEPROM_8KB)
+  {
+    /* Step 1 Set WEL = 1 (write 00000010 to address 1FFFh */
+    i2c_start();
+    i2c_outbyte(0xbe);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false\n"));
+    }
+    i2c_outbyte(0xFF);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 2\n"));
+    }
+    i2c_outbyte(0x02);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 3\n"));
+    }
+    i2c_stop();
+
+    i2c_delay(1000);
+
+    /* Step 2 Set RWEL = 1 (write 00000110 to address 1FFFh */
+    i2c_start();
+    i2c_outbyte(0xbe);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 55\n"));
+    }
+    i2c_outbyte(0xFF);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 52\n"));
+    }
+    i2c_outbyte(0x06);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 53\n"));
+    }
+    i2c_stop();
+    
+    /* Step 3 Set BP1, BP0, and/or WPEN bits (write 00000110 to address 1FFFh */
+    i2c_start();
+    i2c_outbyte(0xbe);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 56\n"));
+    }
+    i2c_outbyte(0xFF);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 57\n"));
+    }
+    i2c_outbyte(0x06);
+    if(!i2c_getack())
+    {
+      DBP_SAVE(ax_printf("Get ack returns false 58\n"));
+    }
+    i2c_stop();
+    
+    /* Write protect disabled */
+  }
+}
+
+module_init(eeprom_init);
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
new file mode 100644
index 000000000000..c095de82a0da
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/gpio.c
@@ -0,0 +1,944 @@
+/* $Id: gpio.c,v 1.12 2004/08/24 07:19:59 starvik Exp $
+ *
+ * Etrax general port I/O device
+ *
+ * Copyright (c) 1999, 2000, 2001, 2002 Axis Communications AB
+ *
+ * Authors:    Bjorn Wesen      (initial version)
+ *             Ola Knutsson     (LED handling)
+ *             Johan Adolfsson  (read/set directions, write, port G)
+ *
+ * $Log: gpio.c,v $
+ * Revision 1.12  2004/08/24 07:19:59  starvik
+ * Whitespace cleanup
+ *
+ * Revision 1.11  2004/05/14 07:58:03  starvik
+ * Merge of changes from 2.4
+ *
+ * Revision 1.9  2003/09/11 07:29:48  starvik
+ * Merge of Linux 2.6.0-test5
+ *
+ * Revision 1.8  2003/07/04 08:27:37  starvik
+ * Merge of Linux 2.5.74
+ *
+ * Revision 1.7  2003/01/10 07:44:07  starvik
+ * init_ioremap is now called by kernel before drivers are initialized
+ *
+ * Revision 1.6  2002/12/11 13:13:57  starvik
+ * Added arch/ to v10 specific includes
+ * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
+ *
+ * Revision 1.5  2002/11/20 11:56:11  starvik
+ * Merge of Linux 2.5.48
+ *
+ * Revision 1.4  2002/11/18 10:10:05  starvik
+ * Linux 2.5 port of latest gpio.c from Linux 2.4
+ *
+ * Revision 1.20  2002/10/16 21:16:24  johana
+ * Added support for PA high level interrupt.
+ * That gives 2ms response time with iodtest for high levels and 2-12 ms
+ * response time on low levels if the check is not made in
+ * process.c:cpu_idle() as well.
+ *
+ * Revision 1.19  2002/10/14 18:27:33  johana
+ * Implemented alarm handling so select() now works.
+ * Latency is around 6-9 ms with a etrax_gpio_wake_up_check() in
+ * cpu_idle().
+ * Otherwise I get 15-18 ms (same as doing the poll in userspace -
+ * but less overhead).
+ * TODO? Perhaps we should add the check in IMMEDIATE_BH (or whatever it
+ * is in 2.4) as well?
+ * TODO? Perhaps call request_irq()/free_irq() only when needed?
+ * Increased version to 2.5
+ *
+ * Revision 1.18  2002/10/11 15:02:00  johana
+ * Mask inverted 8 bit value in setget_input().
+ *
+ * Revision 1.17  2002/06/17 15:53:01  johana
+ * Added IO_READ_INBITS, IO_READ_OUTBITS, IO_SETGET_INPUT and IO_SETGET_OUTPUT
+ * that take a pointer as argument and thus can handle 32 bit ports (G)
+ * correctly.
+ * These should be used instead of IO_READBITS, IO_SETINPUT and IO_SETOUTPUT.
+ * (especially if Port G bit 31 is used)
+ *
+ * Revision 1.16  2002/06/17 09:59:51  johana
+ * Returning 32 bit values in the ioctl return value doesn't work if bit
+ * 31 is set (could happen for port G), so mask it of with 0x7FFFFFFF.
+ * A new set of ioctl's will be added.
+ *
+ * Revision 1.15  2002/05/06 13:19:13  johana
+ * IO_SETINPUT returns mask with bit set = inputs for PA and PB as well.
+ *
+ * Revision 1.14  2002/04/12 12:01:53  johana
+ * Use global r_port_g_data_shadow.
+ * Moved gpio_init_port_g() closer to gpio_init() and marked it __init.
+ *
+ * Revision 1.13  2002/04/10 12:03:55  johana
+ * Added support for port G /dev/gpiog (minor 3).
+ * Changed indentation on switch cases.
+ * Fixed other spaces to tabs.
+ *
+ * Revision 1.12  2001/11/12 19:42:15  pkj
+ * * Corrected return values from gpio_leds_ioctl().
+ * * Fixed compiler warnings.
+ *
+ * Revision 1.11  2001/10/30 14:39:12  johana
+ * Added D() around gpio_write printk.
+ *
+ * Revision 1.10  2001/10/25 10:24:42  johana
+ * Added IO_CFG_WRITE_MODE ioctl and write method that can do fast
+ * bittoggling in the kernel. (This speeds up programming an FPGA with 450kB
+ * from ~60 seconds to 4 seconds).
+ * Added save_flags/cli/restore_flags in ioctl.
+ *
+ * Revision 1.9  2001/05/04 14:16:07  matsfg
+ * Corrected spelling error
+ *
+ * Revision 1.8  2001/04/27 13:55:26  matsfg
+ * Moved initioremap.
+ * Turns off all LEDS on init.
+ * Added support for shutdown and powerbutton.
+ *
+ * Revision 1.7  2001/04/04 13:30:08  matsfg
+ * Added bitset and bitclear for leds. Calls init_ioremap to set up memmapping
+ *
+ * Revision 1.6  2001/03/26 16:03:06  bjornw
+ * Needs linux/config.h
+ *
+ * Revision 1.5  2001/03/26 14:22:03  bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.4  2001/02/27 13:52:48  bjornw
+ * malloc.h -> slab.h
+ *
+ * Revision 1.3  2001/01/24 15:06:48  bjornw
+ * gpio_wq correct type
+ *
+ * Revision 1.2  2001/01/18 16:07:30  bjornw
+ * 2.4 port
+ *
+ * Revision 1.1  2001/01/18 15:55:16  bjornw
+ * Verbatim copy of etraxgpio.c from elinux 2.0 added
+ *
+ *
+ */
+
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/etraxgpio.h>
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+
+#define GPIO_MAJOR 120  /* experimental MAJOR number */
+
+#define D(x)
+
+#if 0
+static int dp_cnt;
+#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
+#else
+#define DP(x)
+#endif
+        
+static char gpio_name[] = "etrax gpio";
+
+#if 0
+static wait_queue_head_t *gpio_wq;
+#endif
+
+static int gpio_ioctl(struct inode *inode, struct file *file,
+                      unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
+                          loff_t *off);
+static int gpio_open(struct inode *inode, struct file *filp);
+static int gpio_release(struct inode *inode, struct file *filp);
+static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
+
+/* private data per open() of this driver */
+
+struct gpio_private {
+        struct gpio_private *next;
+        /* These fields are for PA and PB only */
+        volatile unsigned char *port, *shadow;
+        volatile unsigned char *dir, *dir_shadow;
+        unsigned char changeable_dir;
+        unsigned char changeable_bits;
+        unsigned char clk_mask;
+        unsigned char data_mask;
+        unsigned char write_msb;
+        unsigned char pad1, pad2, pad3;
+        /* These fields are generic */
+        unsigned long highalarm, lowalarm;
+        wait_queue_head_t alarm_wq;
+        int minor;
+};
+
+/* linked list of alarms to check for */
+
+static struct gpio_private *alarmlist = 0;
+
+static int gpio_some_alarms = 0; /* Set if someone uses alarm */
+static unsigned long gpio_pa_irq_enabled_mask = 0;
+
+/* Port A and B use 8 bit access, but Port G is 32 bit */
+#define NUM_PORTS (GPIO_MINOR_B+1)
+
+static volatile unsigned char *ports[NUM_PORTS] = { 
+        R_PORT_PA_DATA, 
+        R_PORT_PB_DATA,
+};
+static volatile unsigned char *shads[NUM_PORTS] = {
+        &port_pa_data_shadow, 
+        &port_pb_data_shadow
+};
+
+/* What direction bits that are user changeable 1=changeable*/
+#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
+#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
+#endif
+#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
+#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
+#endif
+
+#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
+#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
+#endif
+#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
+#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
+#endif
+
+
+static unsigned char changeable_dir[NUM_PORTS] = { 
+        CONFIG_ETRAX_PA_CHANGEABLE_DIR,
+        CONFIG_ETRAX_PB_CHANGEABLE_DIR 
+};
+static unsigned char changeable_bits[NUM_PORTS] = { 
+        CONFIG_ETRAX_PA_CHANGEABLE_BITS,
+        CONFIG_ETRAX_PB_CHANGEABLE_BITS 
+};
+
+static volatile unsigned char *dir[NUM_PORTS] = { 
+        R_PORT_PA_DIR, 
+        R_PORT_PB_DIR 
+};
+
+static volatile unsigned char *dir_shadow[NUM_PORTS] = {
+        &port_pa_dir_shadow, 
+        &port_pb_dir_shadow 
+};
+
+/* Port G is 32 bit, handle it special, some bits are both inputs 
+   and outputs at the same time, only some of the bits can change direction
+   and some of them in groups of 8 bit. */
+static unsigned long changeable_dir_g;
+static unsigned long dir_g_in_bits;
+static unsigned long dir_g_out_bits;
+static unsigned long dir_g_shadow; /* 1=output */
+
+#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
+
+
+
+static unsigned int 
+gpio_poll(struct file *file,
+          poll_table *wait)
+{
+        unsigned int mask = 0;
+        struct gpio_private *priv = (struct gpio_private *)file->private_data;
+        unsigned long data;
+        poll_wait(file, &priv->alarm_wq, wait);
+        if (priv->minor == GPIO_MINOR_A) {
+                unsigned long flags;
+                unsigned long tmp;
+                data = *R_PORT_PA_DATA;
+                /* PA has support for high level interrupt -
+                 * lets activate for those low and with highalarm set
+                 */
+                tmp = ~data & priv->highalarm & 0xFF;
+                tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
+                save_flags(flags); cli();
+                gpio_pa_irq_enabled_mask |= tmp;
+                *R_IRQ_MASK1_SET = tmp;
+                restore_flags(flags);
+
+        } else if (priv->minor == GPIO_MINOR_B)
+                data = *R_PORT_PB_DATA;
+        else if (priv->minor == GPIO_MINOR_G)
+                data = *R_PORT_G_DATA;
+        else
+                return 0;
+        
+        if ((data & priv->highalarm) ||
+            (~data & priv->lowalarm)) {
+                mask = POLLIN|POLLRDNORM;
+        }
+        
+        DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
+        return mask;
+}
+
+int etrax_gpio_wake_up_check(void)
+{
+        struct gpio_private *priv = alarmlist;
+        unsigned long data = 0;
+        int ret = 0;
+        while (priv) {
+                if (USE_PORTS(priv)) {
+                        data = *priv->port;
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        data = *R_PORT_G_DATA;
+                }
+                if ((data & priv->highalarm) ||
+                    (~data & priv->lowalarm)) {
+                        DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
+                        wake_up_interruptible(&priv->alarm_wq);
+                        ret = 1;
+                }
+                priv = priv->next;
+        }
+        return ret;
+}
+
+static irqreturn_t
+gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        if (gpio_some_alarms) {
+                etrax_gpio_wake_up_check();
+                return IRQ_HANDLED;
+        }
+        return IRQ_NONE;
+}
+
+static irqreturn_t
+gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        unsigned long tmp;
+        /* Find what PA interrupts are active */
+        tmp = (*R_IRQ_READ1);
+
+        /* Find those that we have enabled */
+        tmp &= gpio_pa_irq_enabled_mask;
+
+        /* Clear them.. */
+        *R_IRQ_MASK1_CLR = tmp;
+        gpio_pa_irq_enabled_mask &= ~tmp;
+
+        if (gpio_some_alarms) {
+                return IRQ_RETVAL(etrax_gpio_wake_up_check());
+        }
+        return IRQ_NONE;
+}
+
+
+static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
+                          loff_t *off)
+{
+        struct gpio_private *priv = (struct gpio_private *)file->private_data;
+        unsigned char data, clk_mask, data_mask, write_msb;
+        unsigned long flags;
+        ssize_t retval = count;
+        if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {
+                return -EFAULT;
+        }
+    
+        if (!access_ok(VERIFY_READ, buf, count)) {
+                return -EFAULT;
+        }
+        clk_mask = priv->clk_mask;
+        data_mask = priv->data_mask;
+        /* It must have been configured using the IO_CFG_WRITE_MODE */
+        /* Perhaps a better error code? */
+        if (clk_mask == 0 || data_mask == 0) {
+                return -EPERM;
+        }
+        write_msb = priv->write_msb;
+        D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
+        while (count--) {
+                int i;
+                data = *buf++;
+                if (priv->write_msb) {
+                        for (i = 7; i >= 0;i--) {
+                                local_irq_save(flags); local_irq_disable();
+                                *priv->port = *priv->shadow &= ~clk_mask;
+                                if (data & 1<<i)
+                                        *priv->port = *priv->shadow |= data_mask;
+                                else
+                                        *priv->port = *priv->shadow &= ~data_mask;
+                        /* For FPGA: min 5.0ns (DCC) before CCLK high */
+                                *priv->port = *priv->shadow |= clk_mask;
+                                local_irq_restore(flags);
+                        }
+                } else {
+                        for (i = 0; i <= 7;i++) {
+                                local_irq_save(flags); local_irq_disable();
+                                *priv->port = *priv->shadow &= ~clk_mask;
+                                if (data & 1<<i)
+                                        *priv->port = *priv->shadow |= data_mask;
+                                else
+                                        *priv->port = *priv->shadow &= ~data_mask;
+                        /* For FPGA: min 5.0ns (DCC) before CCLK high */
+                                *priv->port = *priv->shadow |= clk_mask;
+                                local_irq_restore(flags);
+                        }
+                }
+        }
+        return retval;
+}
+
+
+
+static int
+gpio_open(struct inode *inode, struct file *filp)
+{
+        struct gpio_private *priv;
+        int p = MINOR(inode->i_rdev);
+
+        if (p > GPIO_MINOR_LAST)
+                return -EINVAL;
+
+        priv = (struct gpio_private *)kmalloc(sizeof(struct gpio_private), 
+                                              GFP_KERNEL);
+
+        if (!priv)
+                return -ENOMEM;
+
+        priv->minor = p;
+
+        /* initialize the io/alarm struct and link it into our alarmlist */
+
+        priv->next = alarmlist;
+        alarmlist = priv;
+        if (USE_PORTS(priv)) { /* A and B */
+                priv->port = ports[p];
+                priv->shadow = shads[p];
+                priv->dir = dir[p];
+                priv->dir_shadow = dir_shadow[p];
+                priv->changeable_dir = changeable_dir[p];
+                priv->changeable_bits = changeable_bits[p];
+        } else {
+                priv->port = NULL;
+                priv->shadow = NULL;
+                priv->dir = NULL;
+                priv->dir_shadow = NULL;
+                priv->changeable_dir = 0;
+                priv->changeable_bits = 0;
+        }
+
+        priv->highalarm = 0;
+        priv->lowalarm = 0;
+        priv->clk_mask = 0;
+        priv->data_mask = 0;
+        init_waitqueue_head(&priv->alarm_wq);
+
+        filp->private_data = (void *)priv;
+
+        return 0;
+}
+
+static int
+gpio_release(struct inode *inode, struct file *filp)
+{
+        struct gpio_private *p = alarmlist;
+        struct gpio_private *todel = (struct gpio_private *)filp->private_data;
+        
+        /* unlink from alarmlist and free the private structure */
+
+        if (p == todel) {
+                alarmlist = todel->next;
+        } else {
+                while (p->next != todel)
+                        p = p->next;
+                p->next = todel->next;
+        }
+
+        kfree(todel);
+        /* Check if there are still any alarms set */
+        p = alarmlist;
+        while (p) {
+                if (p->highalarm | p->lowalarm) {
+                        gpio_some_alarms = 1;
+                        return 0;
+                }
+                p = p->next;
+        }
+        gpio_some_alarms = 0;
+                
+        return 0;
+}
+
+/* Main device API. ioctl's to read/set/clear bits, as well as to 
+ * set alarms to wait for using a subsequent select().
+ */
+
+unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
+{
+        /* Set direction 0=unchanged 1=input, 
+         * return mask with 1=input 
+         */
+        unsigned long flags;
+        if (USE_PORTS(priv)) {
+                local_irq_save(flags); local_irq_disable();
+                *priv->dir = *priv->dir_shadow &= 
+                ~((unsigned char)arg & priv->changeable_dir);
+                local_irq_restore(flags);
+                return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
+        } else if (priv->minor == GPIO_MINOR_G) {
+                /* We must fiddle with R_GEN_CONFIG to change dir */
+                save_flags(flags); cli();
+                if (((arg & dir_g_in_bits) != arg) && 
+                    (arg & changeable_dir_g)) {
+                        arg &= changeable_dir_g;
+                        /* Clear bits in genconfig to set to input */
+                        if (arg & (1<<0)) {
+                                genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g0dir);
+                                dir_g_in_bits |= (1<<0);
+                                dir_g_out_bits &= ~(1<<0);
+                        }
+                        if ((arg & 0x0000FF00) == 0x0000FF00) {
+                                genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g8_15dir);
+                                dir_g_in_bits |= 0x0000FF00;
+                                dir_g_out_bits &= ~0x0000FF00;
+                        }
+                        if ((arg & 0x00FF0000) == 0x00FF0000) {
+                                genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g16_23dir);
+                                dir_g_in_bits |= 0x00FF0000;
+                                dir_g_out_bits &= ~0x00FF0000;
+                        }
+                        if (arg & (1<<24)) {
+                                genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g24dir);
+                                dir_g_in_bits |= (1<<24);
+                                dir_g_out_bits &= ~(1<<24);
+                        }
+                        D(printk(KERN_INFO "gpio: SETINPUT on port G set "
+                                 "genconfig to 0x%08lX "
+                                 "in_bits: 0x%08lX "
+                                 "out_bits: 0x%08lX\n",
+                                 (unsigned long)genconfig_shadow,
+                                 dir_g_in_bits, dir_g_out_bits));
+                        *R_GEN_CONFIG = genconfig_shadow;
+                        /* Must be a >120 ns delay before writing this again */
+                                
+                }
+                restore_flags(flags);
+                return dir_g_in_bits;
+        }
+        return 0;
+} /* setget_input */
+
+unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
+{
+        unsigned long flags;
+        if (USE_PORTS(priv)) {
+                local_irq_save(flags); local_irq_disable();
+                *priv->dir = *priv->dir_shadow |= 
+                  ((unsigned char)arg & priv->changeable_dir);
+                local_irq_restore(flags);
+                return *priv->dir_shadow;
+        } else if (priv->minor == GPIO_MINOR_G) {
+                /* We must fiddle with R_GEN_CONFIG to change dir */                    
+                save_flags(flags); cli();
+                if (((arg & dir_g_out_bits) != arg) &&
+                    (arg & changeable_dir_g)) {
+                        /* Set bits in genconfig to set to output */
+                        if (arg & (1<<0)) {
+                                genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g0dir);
+                                dir_g_out_bits |= (1<<0);
+                                dir_g_in_bits &= ~(1<<0);
+                        }
+                        if ((arg & 0x0000FF00) == 0x0000FF00) {
+                                genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
+                                dir_g_out_bits |= 0x0000FF00;
+                                dir_g_in_bits &= ~0x0000FF00;
+                        }
+                        if ((arg & 0x00FF0000) == 0x00FF0000) {
+                                genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g16_23dir);
+                                dir_g_out_bits |= 0x00FF0000;
+                                dir_g_in_bits &= ~0x00FF0000;
+                        }
+                        if (arg & (1<<24)) {
+                                genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g24dir);
+                                dir_g_out_bits |= (1<<24);
+                                dir_g_in_bits &= ~(1<<24);
+                        }
+                        D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
+                                 "genconfig to 0x%08lX "
+                                 "in_bits: 0x%08lX "
+                                 "out_bits: 0x%08lX\n",
+                                 (unsigned long)genconfig_shadow,
+                                 dir_g_in_bits, dir_g_out_bits));
+                        *R_GEN_CONFIG = genconfig_shadow;
+                        /* Must be a >120 ns delay before writing this again */
+                }
+                restore_flags(flags);
+                return dir_g_out_bits & 0x7FFFFFFF;
+        }
+        return 0;
+} /* setget_output */
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
+
+static int
+gpio_ioctl(struct inode *inode, struct file *file,
+           unsigned int cmd, unsigned long arg)
+{
+        unsigned long flags;
+        unsigned long val;
+        struct gpio_private *priv = (struct gpio_private *)file->private_data;
+        if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
+                return -EINVAL;
+        }
+
+        switch (_IOC_NR(cmd)) {
+        case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
+                // read the port
+                if (USE_PORTS(priv)) {
+                        return *priv->port;
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        return (*R_PORT_G_DATA) & 0x7FFFFFFF;
+                }
+                break;
+        case IO_SETBITS:
+                local_irq_save(flags); local_irq_disable();
+                // set changeable bits with a 1 in arg
+                if (USE_PORTS(priv)) {
+                        *priv->port = *priv->shadow |= 
+                          ((unsigned char)arg & priv->changeable_bits);
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
+                }
+                local_irq_restore(flags);
+                break;
+        case IO_CLRBITS:
+                local_irq_save(flags); local_irq_disable();
+                // clear changeable bits with a 1 in arg
+                if (USE_PORTS(priv)) {
+                        *priv->port = *priv->shadow &= 
+                         ~((unsigned char)arg & priv->changeable_bits);
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
+                }
+                local_irq_restore(flags);
+                break;
+        case IO_HIGHALARM:
+                // set alarm when bits with 1 in arg go high
+                priv->highalarm |= arg;
+                gpio_some_alarms = 1;
+                break;
+        case IO_LOWALARM:
+                // set alarm when bits with 1 in arg go low
+                priv->lowalarm |= arg;
+                gpio_some_alarms = 1;
+                break;
+        case IO_CLRALARM:
+                // clear alarm for bits with 1 in arg
+                priv->highalarm &= ~arg;
+                priv->lowalarm  &= ~arg;
+                {
+                        /* Must update gpio_some_alarms */
+                        struct gpio_private *p = alarmlist;
+                        int some_alarms;
+                        some_alarms = 0;
+                        while (p) {
+                                if (p->highalarm | p->lowalarm) {
+                                        some_alarms = 1;
+                                        break;
+                                }
+                                p = p->next;
+                        }
+                        gpio_some_alarms = some_alarms;
+                }
+                break;
+        case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
+                /* Read direction 0=input 1=output */
+                if (USE_PORTS(priv)) {
+                        return *priv->dir_shadow;
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        /* Note: Some bits are both in and out,
+                         * Those that are dual is set here as well.
+                         */
+                        return (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
+                }
+        case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
+                /* Set direction 0=unchanged 1=input, 
+                 * return mask with 1=input 
+                 */
+                return setget_input(priv, arg) & 0x7FFFFFFF;
+                break;
+        case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
+                /* Set direction 0=unchanged 1=output, 
+                 * return mask with 1=output 
+                 */
+                return setget_output(priv, arg) & 0x7FFFFFFF;
+
+        case IO_SHUTDOWN:
+                SOFT_SHUTDOWN();
+                break;
+        case IO_GET_PWR_BT:
+#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
+                return (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
+#else
+                return 0;
+#endif
+                break;
+        case IO_CFG_WRITE_MODE:
+                priv->clk_mask = arg & 0xFF;
+                priv->data_mask = (arg >> 8) & 0xFF;
+                priv->write_msb = (arg >> 16) & 0x01;
+                /* Check if we're allowed to change the bits and
+                 * the direction is correct
+                 */
+                if (!((priv->clk_mask & priv->changeable_bits) &&
+                      (priv->data_mask & priv->changeable_bits) &&
+                      (priv->clk_mask & *priv->dir_shadow) &&
+                      (priv->data_mask & *priv->dir_shadow)))
+                {
+                        priv->clk_mask = 0;
+                        priv->data_mask = 0;
+                        return -EPERM;
+                }
+                break;
+        case IO_READ_INBITS: 
+                /* *arg is result of reading the input pins */
+                if (USE_PORTS(priv)) {
+                        val = *priv->port;
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        val = *R_PORT_G_DATA;
+                }
+                if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+                        return -EFAULT;
+                return 0;
+                break;
+        case IO_READ_OUTBITS:
+                 /* *arg is result of reading the output shadow */
+                if (USE_PORTS(priv)) {
+                        val = *priv->shadow;
+                } else if (priv->minor == GPIO_MINOR_G) {
+                        val = port_g_data_shadow;
+                }
+                if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+                        return -EFAULT;
+                break;
+        case IO_SETGET_INPUT: 
+                /* bits set in *arg is set to input,
+                 * *arg updated with current input pins.
+                 */
+                if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+                        return -EFAULT;
+                val = setget_input(priv, val);
+                if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+                        return -EFAULT;
+                break;
+        case IO_SETGET_OUTPUT:
+                /* bits set in *arg is set to output,
+                 * *arg updated with current output pins.
+                 */
+                if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+                        return -EFAULT;
+                val = setget_output(priv, val);
+                if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+                        return -EFAULT;
+                break;
+        default:
+                if (priv->minor == GPIO_MINOR_LEDS)
+                        return gpio_leds_ioctl(cmd, arg);
+                else
+                        return -EINVAL;
+        } /* switch */
+        
+        return 0;
+}
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
+{
+        unsigned char green;
+        unsigned char red;
+
+        switch (_IOC_NR(cmd)) {
+        case IO_LEDACTIVE_SET:
+                green = ((unsigned char) arg) & 1;
+                red   = (((unsigned char) arg) >> 1) & 1;
+                LED_ACTIVE_SET_G(green);
+                LED_ACTIVE_SET_R(red);
+                break;
+
+        case IO_LED_SETBIT:
+                LED_BIT_SET(arg);
+                break;
+
+        case IO_LED_CLRBIT:
+                LED_BIT_CLR(arg);
+                break;
+
+        default:
+                return -EINVAL;
+        } /* switch */
+
+        return 0;
+}
+
+struct file_operations gpio_fops = {
+        .owner       = THIS_MODULE,
+        .poll        = gpio_poll,
+        .ioctl       = gpio_ioctl,
+        .write       = gpio_write,
+        .open        = gpio_open,
+        .release     = gpio_release,
+};
+
+
+static void __init gpio_init_port_g(void)
+{
+#define GROUPA (0x0000FF3F)
+#define GROUPB (1<<6 | 1<<7)
+#define GROUPC (1<<30 | 1<<31)
+#define GROUPD (0x3FFF0000)
+#define GROUPD_LOW (0x00FF0000)
+        unsigned long used_in_bits = 0;
+        unsigned long used_out_bits = 0;
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0, select)){
+                used_in_bits  |= GROUPA | GROUPB | 0 | 0;
+                used_out_bits |= GROUPA | GROUPB | 0 | 0;
+        }
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ata, select)) {
+                used_in_bits  |= GROUPA | GROUPB | GROUPC | (GROUPD & ~(1<<25|1<<26));
+                used_out_bits |= GROUPA | GROUPB | GROUPC | GROUPD;
+        }
+
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par0, select)) {
+                used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
+                used_out_bits |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
+        }
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser2, select)) {
+                used_in_bits  |= 0 | GROUPB | 0 | 0;
+                used_out_bits |= 0 | GROUPB | 0 | 0;
+        }
+        /* mio same as shared RAM ? */
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio, select)) {
+                used_in_bits  |= (GROUPA & ~(1<<0)) | 0 |0 |GROUPD_LOW;
+                used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 |0 |GROUPD_LOW;
+        }
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi1, select)) {
+                used_in_bits  |= 0 | 0 | GROUPC | GROUPD;
+                used_out_bits |= 0 | 0 | GROUPC | GROUPD;
+        }
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0w, select)) {
+                used_in_bits  |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24);
+                used_out_bits |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24 | 1<<25|1<<26);
+        }
+
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par1, select)) {
+                used_in_bits  |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
+                used_out_bits |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
+        }
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser3, select)) {
+                used_in_bits  |= 0 | 0 | GROUPC | 0;
+                used_out_bits |= 0 | 0 | GROUPC | 0;
+        }
+        /* mio same as shared RAM-W? */
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio_w, select)) {
+                used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 |GROUPD_LOW;
+                used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 | 0 |GROUPD_LOW;
+        }
+        /* TODO: USB p2, parw, sync ser3? */
+
+        /* Initialise the dir_g_shadow etc. depending on genconfig */
+        /* 0=input 1=output */
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) 
+                dir_g_shadow |= (1 << 0);
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
+                dir_g_shadow |= 0x0000FF00;
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
+                dir_g_shadow |= 0x00FF0000;
+        if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
+                dir_g_shadow |= (1 << 24);
+
+        dir_g_in_bits = ~used_in_bits;
+        dir_g_out_bits = ~used_out_bits;
+
+        changeable_dir_g = 0x01FFFF01; /* all that can change dir */
+        changeable_dir_g &= dir_g_out_bits;
+        changeable_dir_g &= dir_g_in_bits;
+        /* Correct the bits that can change direction */ 
+        dir_g_out_bits &= ~changeable_dir_g;
+        dir_g_out_bits |= dir_g_shadow;
+        dir_g_in_bits &= ~changeable_dir_g;
+        dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
+
+
+        printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n",
+               dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
+        printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
+               dir_g_shadow, changeable_dir_g);
+}
+
+/* main driver initialization routine, called from mem.c */
+
+static __init int
+gpio_init(void)
+{
+        int res;
+#if defined (CONFIG_ETRAX_CSP0_LEDS)
+        int i;
+#endif
+
+        /* do the formalities */
+
+        res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
+        if (res < 0) {
+                printk(KERN_ERR "gpio: couldn't get a major number.\n");
+                return res;
+        }
+
+        /* Clear all leds */
+#if defined (CONFIG_ETRAX_CSP0_LEDS) ||  defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
+        LED_NETWORK_SET(0);
+        LED_ACTIVE_SET(0);
+        LED_DISK_READ(0);
+        LED_DISK_WRITE(0);
+
+#if defined (CONFIG_ETRAX_CSP0_LEDS)
+        for (i = 0; i < 32; i++) {
+                LED_BIT_SET(i);
+        }
+#endif
+
+#endif
+        gpio_init_port_g();
+        printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002 Axis Communications AB\n");
+        /* We call etrax_gpio_wake_up_check() from timer interrupt and
+         * from cpu_idle() in kernel/process.c
+         * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
+         * in some tests.
+         */  
+        if (request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
+                        SA_SHIRQ | SA_INTERRUPT,"gpio poll", NULL)) {
+                printk(KERN_CRIT "err: timer0 irq for gpio\n");
+        }
+        if (request_irq(PA_IRQ_NBR, gpio_pa_interrupt,
+                        SA_SHIRQ | SA_INTERRUPT,"gpio PA", NULL)) {
+                printk(KERN_CRIT "err: PA irq for gpio\n");
+        }
+        
+
+        return res;
+}
+
+/* this makes sure that gpio_init is called during kernel boot */
+
+module_init(gpio_init);
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
new file mode 100644
index 000000000000..8bbe233ba7b1
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/i2c.c
@@ -0,0 +1,730 @@
+/*!***************************************************************************
+*!
+*! FILE NAME  : i2c.c
+*!
+*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other
+*!              kernel modules (i2c_writereg/readreg) and from userspace using
+*!              ioctl()'s
+*!
+*! Nov 30 1998  Torbjorn Eliasson  Initial version.
+*!              Bjorn Wesen        Elinux kernel version.
+*! Jan 14 2000  Johan Adolfsson    Fixed PB shadow register stuff - 
+*!                                 don't use PB_I2C if DS1302 uses same bits,
+*!                                 use PB.
+*! $Log: i2c.c,v $
+*! Revision 1.9  2004/08/24 06:49:14  starvik
+*! Whitespace cleanup
+*!
+*! Revision 1.8  2004/06/08 08:48:26  starvik
+*! Removed unused code
+*!
+*! Revision 1.7  2004/05/28 09:26:59  starvik
+*! Modified I2C initialization to work in 2.6.
+*!
+*! Revision 1.6  2004/05/14 07:58:03  starvik
+*! Merge of changes from 2.4
+*!
+*! Revision 1.4  2002/12/11 13:13:57  starvik
+*! Added arch/ to v10 specific includes
+*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
+*!
+*! Revision 1.3  2002/11/20 11:56:11  starvik
+*! Merge of Linux 2.5.48
+*!
+*! Revision 1.2  2002/11/18 13:16:06  starvik
+*! Linux 2.5 port of latest 2.4 drivers
+*!
+*! Revision 1.9  2002/10/31 15:32:26  starvik
+*! Update Port B register and shadow even when running with hardware support
+*!   to avoid glitches when reading bits
+*! Never set direction to out in i2c_inbyte
+*! Removed incorrect clock togling at end of i2c_inbyte
+*!
+*! Revision 1.8  2002/08/13 06:31:53  starvik
+*! Made SDA and SCL line configurable
+*! Modified i2c_inbyte to work with PCF8563
+*!
+*! Revision 1.7  2001/04/04 13:11:36  markusl
+*! Updated according to review remarks
+*!
+*! Revision 1.6  2001/03/19 12:43:00  markusl
+*! Made some symbols unstatic (used by the eeprom driver)
+*!
+*! Revision 1.5  2001/02/27 13:52:48  bjornw
+*! malloc.h -> slab.h
+*!
+*! Revision 1.4  2001/02/15 07:17:40  starvik
+*! Corrected usage if port_pb_i2c_shadow
+*!
+*! Revision 1.3  2001/01/26 17:55:13  bjornw
+*! * Made I2C_USES_PB_NOT_PB_I2C a CONFIG option instead of assigning it
+*!   magically. Config.in needs to set it for the options that need it, like
+*!   Dallas 1302 support. Actually, it should be default since it screws up
+*!   the PB bits even if you don't use I2C..
+*! * Include linux/config.h to get the above
+*!
+*! Revision 1.2  2001/01/18 15:49:30  bjornw
+*! 2.4 port of I2C including some cleanups (untested of course)
+*!
+*! Revision 1.1  2001/01/18 15:35:25  bjornw
+*! Verbatim copy of the Etrax i2c driver, 2.0 elinux version
+*!
+*!
+*! ---------------------------------------------------------------------------
+*!
+*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
+*!
+*!***************************************************************************/
+/* $Id: i2c.c,v 1.9 2004/08/24 06:49:14 starvik Exp $ */
+
+/****************** INCLUDE FILES SECTION ***********************************/
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/config.h>
+
+#include <asm/etraxi2c.h>
+
+#include <asm/system.h>
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+
+#include "i2c.h"
+
+/****************** I2C DEFINITION SECTION *************************/
+
+#define D(x)
+
+#define I2C_MAJOR 123  /* LOCAL/EXPERIMENTAL */
+static const char i2c_name[] = "i2c";
+
+#define CLOCK_LOW_TIME            8
+#define CLOCK_HIGH_TIME           8
+#define START_CONDITION_HOLD_TIME 8
+#define STOP_CONDITION_HOLD_TIME  8
+#define ENABLE_OUTPUT 0x01
+#define ENABLE_INPUT 0x00
+#define I2C_CLOCK_HIGH 1
+#define I2C_CLOCK_LOW 0
+#define I2C_DATA_HIGH 1
+#define I2C_DATA_LOW 0
+
+#ifdef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
+/* Use PB and not PB_I2C */
+#ifndef CONFIG_ETRAX_I2C_DATA_PORT
+#define CONFIG_ETRAX_I2C_DATA_PORT 0
+#endif
+#ifndef CONFIG_ETRAX_I2C_CLK_PORT
+#define CONFIG_ETRAX_I2C_CLK_PORT 1
+#endif
+
+#define SDABIT CONFIG_ETRAX_I2C_DATA_PORT
+#define SCLBIT CONFIG_ETRAX_I2C_CLK_PORT
+#define i2c_enable() 
+#define i2c_disable() 
+
+/* enable or disable output-enable, to select output or input on the i2c bus */
+
+#define i2c_dir_out() \
+  REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 1)
+#define i2c_dir_in()  \
+  REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 0)
+
+/* control the i2c clock and data signals */
+
+#define i2c_clk(x) \
+  REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SCLBIT, x)
+#define i2c_data(x) \
+  REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SDABIT, x)
+
+/* read a bit from the i2c interface */
+
+#define i2c_getbit() (((*R_PORT_PB_READ & (1 << SDABIT))) >> SDABIT)
+
+#else
+/* enable or disable the i2c interface */
+
+#define i2c_enable() *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_en))
+#define i2c_disable() *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_en))
+
+/* enable or disable output-enable, to select output or input on the i2c bus */
+
+#define i2c_dir_out() \
+        *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
+        REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 1); 
+#define i2c_dir_in() \
+        *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
+        REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 0);
+
+/* control the i2c clock and data signals */
+
+#define i2c_clk(x) \
+        *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
+       ~IO_MASK(R_PORT_PB_I2C, i2c_clk)) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, (x))); \
+       REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 1, x);
+
+#define i2c_data(x) \
+        *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
+           ~IO_MASK(R_PORT_PB_I2C, i2c_d)) | IO_FIELD(R_PORT_PB_I2C, i2c_d, (x))); \
+        REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 0, x);
+
+/* read a bit from the i2c interface */
+
+#define i2c_getbit() (*R_PORT_PB_READ & 0x1)
+#endif
+
+/* use the kernels delay routine */
+
+#define i2c_delay(usecs) udelay(usecs)
+
+
+/****************** FUNCTION DEFINITION SECTION *************************/
+
+
+/* generate i2c start condition */
+
+void
+i2c_start(void)
+{
+        /*
+         * SCL=1 SDA=1
+         */
+        i2c_dir_out();
+        i2c_delay(CLOCK_HIGH_TIME/6);
+        i2c_data(I2C_DATA_HIGH);
+        i2c_clk(I2C_CLOCK_HIGH);
+        i2c_delay(CLOCK_HIGH_TIME);
+        /*
+         * SCL=1 SDA=0
+         */
+        i2c_data(I2C_DATA_LOW);
+        i2c_delay(START_CONDITION_HOLD_TIME);
+        /*
+         * SCL=0 SDA=0
+         */
+        i2c_clk(I2C_CLOCK_LOW);
+        i2c_delay(CLOCK_LOW_TIME);
+}
+
+/* generate i2c stop condition */
+
+void
+i2c_stop(void)
+{
+        i2c_dir_out();
+
+        /*
+         * SCL=0 SDA=0
+         */
+        i2c_clk(I2C_CLOCK_LOW);
+        i2c_data(I2C_DATA_LOW);
+        i2c_delay(CLOCK_LOW_TIME*2);
+        /*
+         * SCL=1 SDA=0
+         */
+        i2c_clk(I2C_CLOCK_HIGH);
+        i2c_delay(CLOCK_HIGH_TIME*2);
+        /*
+         * SCL=1 SDA=1
+         */
+        i2c_data(I2C_DATA_HIGH);
+        i2c_delay(STOP_CONDITION_HOLD_TIME);
+
+        i2c_dir_in();
+}
+
+/* write a byte to the i2c interface */
+
+void
+i2c_outbyte(unsigned char x)
+{
+        int i;
+
+        i2c_dir_out();
+
+        for (i = 0; i < 8; i++) {
+                if (x & 0x80) {
+                        i2c_data(I2C_DATA_HIGH);
+                } else {
+                        i2c_data(I2C_DATA_LOW);
+                }
+                
+                i2c_delay(CLOCK_LOW_TIME/2);
+                i2c_clk(I2C_CLOCK_HIGH);
+                i2c_delay(CLOCK_HIGH_TIME);
+                i2c_clk(I2C_CLOCK_LOW);
+                i2c_delay(CLOCK_LOW_TIME/2);
+                x <<= 1;
+        }
+        i2c_data(I2C_DATA_LOW);
+        i2c_delay(CLOCK_LOW_TIME/2);
+
+        /*
+         * enable input
+         */
+        i2c_dir_in();
+}
+
+/* read a byte from the i2c interface */
+
+unsigned char
+i2c_inbyte(void)
+{
+        unsigned char aBitByte = 0;
+        int i;
+
+        /* Switch off I2C to get bit */
+        i2c_disable();
+        i2c_dir_in();
+        i2c_delay(CLOCK_HIGH_TIME/2);
+
+        /* Get bit */
+        aBitByte |= i2c_getbit();
+
+        /* Enable I2C */
+        i2c_enable();
+        i2c_delay(CLOCK_LOW_TIME/2);
+
+        for (i = 1; i < 8; i++) {
+                aBitByte <<= 1;
+                /* Clock pulse */
+                i2c_clk(I2C_CLOCK_HIGH);
+                i2c_delay(CLOCK_HIGH_TIME);
+                i2c_clk(I2C_CLOCK_LOW);
+                i2c_delay(CLOCK_LOW_TIME);
+
+                /* Switch off I2C to get bit */
+                i2c_disable();
+                i2c_dir_in();
+                i2c_delay(CLOCK_HIGH_TIME/2);
+
+                /* Get bit */
+                aBitByte |= i2c_getbit();
+
+                /* Enable I2C */
+                i2c_enable();
+                i2c_delay(CLOCK_LOW_TIME/2);
+        }
+        i2c_clk(I2C_CLOCK_HIGH);
+        i2c_delay(CLOCK_HIGH_TIME);
+
+        /*
+         * we leave the clock low, getbyte is usually followed
+         * by sendack/nack, they assume the clock to be low
+         */
+        i2c_clk(I2C_CLOCK_LOW);
+        return aBitByte;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_getack
+*#
+*# DESCRIPTION  : checks if ack was received from ic2
+*#
+*#--------------------------------------------------------------------------*/
+
+int
+i2c_getack(void)
+{
+        int ack = 1;
+        /*
+         * enable output
+         */
+        i2c_dir_out();
+        /*
+         * Release data bus by setting
+         * data high
+         */
+        i2c_data(I2C_DATA_HIGH);
+        /*
+         * enable input
+         */
+        i2c_dir_in();
+        i2c_delay(CLOCK_HIGH_TIME/4);
+        /*
+         * generate ACK clock pulse
+         */
+        i2c_clk(I2C_CLOCK_HIGH);
+        /*
+         * Use PORT PB instead of I2C
+         * for input. (I2C not working)
+         */
+        i2c_clk(1);
+        i2c_data(1);
+        /*
+         * switch off I2C
+         */
+        i2c_data(1);
+        i2c_disable();
+        i2c_dir_in();
+        /*
+         * now wait for ack
+         */
+        i2c_delay(CLOCK_HIGH_TIME/2);
+        /*
+         * check for ack
+         */
+        if(i2c_getbit())
+                ack = 0;
+        i2c_delay(CLOCK_HIGH_TIME/2);
+        if(!ack){
+                if(!i2c_getbit()) /* receiver pulld SDA low */
+                        ack = 1;
+                i2c_delay(CLOCK_HIGH_TIME/2);
+        }
+
+        /*
+         * our clock is high now, make sure data is low
+         * before we enable our output. If we keep data high
+         * and enable output, we would generate a stop condition.
+         */
+        i2c_data(I2C_DATA_LOW);
+
+        /*
+         * end clock pulse
+         */
+        i2c_enable();
+        i2c_dir_out();
+        i2c_clk(I2C_CLOCK_LOW);
+        i2c_delay(CLOCK_HIGH_TIME/4);
+        /*
+         * enable output
+         */
+        i2c_dir_out();
+        /*
+         * remove ACK clock pulse
+         */
+        i2c_data(I2C_DATA_HIGH);
+        i2c_delay(CLOCK_LOW_TIME/2);
+        return ack;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: I2C::sendAck
+*#
+*# DESCRIPTION  : Send ACK on received data
+*#
+*#--------------------------------------------------------------------------*/
+void
+i2c_sendack(void)
+{
+        /*
+         * enable output
+         */
+        i2c_delay(CLOCK_LOW_TIME);
+        i2c_dir_out();
+        /*
+         * set ack pulse high
+         */
+        i2c_data(I2C_DATA_LOW);
+        /*
+         * generate clock pulse
+         */
+        i2c_delay(CLOCK_HIGH_TIME/6);
+        i2c_clk(I2C_CLOCK_HIGH);
+        i2c_delay(CLOCK_HIGH_TIME);
+        i2c_clk(I2C_CLOCK_LOW);
+        i2c_delay(CLOCK_LOW_TIME/6);
+        /*
+         * reset data out
+         */
+        i2c_data(I2C_DATA_HIGH);
+        i2c_delay(CLOCK_LOW_TIME);
+
+        i2c_dir_in();
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_sendnack
+*#
+*# DESCRIPTION  : Sends NACK on received data
+*#
+*#--------------------------------------------------------------------------*/
+void
+i2c_sendnack(void)
+{
+        /*
+         * enable output
+         */
+        i2c_delay(CLOCK_LOW_TIME);
+        i2c_dir_out();
+        /*
+         * set data high
+         */
+        i2c_data(I2C_DATA_HIGH);
+        /*
+         * generate clock pulse
+         */
+        i2c_delay(CLOCK_HIGH_TIME/6);
+        i2c_clk(I2C_CLOCK_HIGH);
+        i2c_delay(CLOCK_HIGH_TIME);
+        i2c_clk(I2C_CLOCK_LOW);
+        i2c_delay(CLOCK_LOW_TIME);
+
+        i2c_dir_in();
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_writereg
+*#
+*# DESCRIPTION  : Writes a value to an I2C device
+*#
+*#--------------------------------------------------------------------------*/
+int
+i2c_writereg(unsigned char theSlave, unsigned char theReg, 
+             unsigned char theValue)
+{
+        int error, cntr = 3;
+        unsigned long flags;
+
+        do {
+                error = 0;
+                /*
+                 * we don't like to be interrupted
+                 */
+                local_irq_save(flags);
+                local_irq_disable();
+
+                i2c_start();
+                /*
+                 * send slave address
+                 */
+                i2c_outbyte((theSlave & 0xfe));
+                /*
+                 * wait for ack
+                 */
+                if(!i2c_getack())
+                        error = 1;
+                /*
+                 * now select register
+                 */
+                i2c_dir_out();
+                i2c_outbyte(theReg);
+                /*
+                 * now it's time to wait for ack
+                 */
+                if(!i2c_getack())
+                        error |= 2;
+                /*
+                 * send register register data
+                 */
+                i2c_outbyte(theValue);
+                /*
+                 * now it's time to wait for ack
+                 */
+                if(!i2c_getack())
+                        error |= 4;
+                /*
+                 * end byte stream
+                 */
+                i2c_stop();
+                /*
+                 * enable interrupt again
+                 */
+                local_irq_restore(flags);
+                
+        } while(error && cntr--);
+
+        i2c_delay(CLOCK_LOW_TIME);
+
+        return -error;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_readreg
+*#
+*# DESCRIPTION  : Reads a value from the decoder registers.
+*#
+*#--------------------------------------------------------------------------*/
+unsigned char
+i2c_readreg(unsigned char theSlave, unsigned char theReg)
+{
+        unsigned char b = 0;
+        int error, cntr = 3;
+        unsigned long flags;
+
+        do {
+                error = 0;
+                /*
+                 * we don't like to be interrupted
+                 */
+                local_irq_save(flags);
+                local_irq_disable();
+                /*
+                 * generate start condition
+                 */
+                i2c_start();
+    
+                /*
+                 * send slave address
+                 */
+                i2c_outbyte((theSlave & 0xfe));
+                /*
+                 * wait for ack
+                 */
+                if(!i2c_getack())
+                        error = 1;
+                /*
+                 * now select register
+                 */
+                i2c_dir_out();
+                i2c_outbyte(theReg);
+                /*
+                 * now it's time to wait for ack
+                 */
+                if(!i2c_getack())
+                        error = 1;
+                /*
+                 * repeat start condition
+                 */
+                i2c_delay(CLOCK_LOW_TIME);
+                i2c_start();
+                /*
+                 * send slave address
+                 */
+                i2c_outbyte(theSlave | 0x01);
+                /*
+                 * wait for ack
+                 */
+                if(!i2c_getack())
+                        error = 1;
+                /*
+                 * fetch register
+                 */
+                b = i2c_inbyte();
+                /*
+                 * last received byte needs to be nacked
+                 * instead of acked
+                 */
+                i2c_sendack();
+                /*
+                 * end sequence
+                 */
+                i2c_stop();
+                /*
+                 * enable interrupt again
+                 */
+                local_irq_restore(flags);
+                
+        } while(error && cntr--);
+
+        return b;
+}
+
+static int
+i2c_open(struct inode *inode, struct file *filp)
+{
+        return 0;
+}
+
+static int
+i2c_release(struct inode *inode, struct file *filp)
+{
+        return 0;
+}
+
+/* Main device API. ioctl's to write or read to/from i2c registers.
+ */
+
+static int
+i2c_ioctl(struct inode *inode, struct file *file,
+          unsigned int cmd, unsigned long arg)
+{
+        if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
+                return -EINVAL;
+        }
+
+        switch (_IOC_NR(cmd)) {
+                case I2C_WRITEREG:
+                        /* write to an i2c slave */
+                        D(printk("i2cw %d %d %d\n", 
+                                 I2C_ARGSLAVE(arg),
+                                 I2C_ARGREG(arg),
+                                 I2C_ARGVALUE(arg)));
+
+                        return i2c_writereg(I2C_ARGSLAVE(arg),
+                                            I2C_ARGREG(arg),
+                                            I2C_ARGVALUE(arg));
+                case I2C_READREG:
+                {
+                        unsigned char val;
+                        /* read from an i2c slave */
+                        D(printk("i2cr %d %d ", 
+                                I2C_ARGSLAVE(arg),
+                                I2C_ARGREG(arg)));
+                        val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
+                        D(printk("= %d\n", val));
+                        return val;
+                }                                           
+                default:
+                        return -EINVAL;
+
+        }
+        
+        return 0;
+}
+
+static struct file_operations i2c_fops = {
+        .owner    = THIS_MODULE,
+        .ioctl    = i2c_ioctl,
+        .open     = i2c_open,
+        .release  = i2c_release,
+};
+
+int __init
+i2c_init(void)
+{
+        /* Setup and enable the Port B I2C interface */
+
+#ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
+        *R_PORT_PB_I2C = port_pb_i2c_shadow |= 
+                IO_STATE(R_PORT_PB_I2C, i2c_en,  on) |
+                IO_FIELD(R_PORT_PB_I2C, i2c_d,   1)  |
+                IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1)  |
+                IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable);
+#endif
+
+        port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0);
+        port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1);
+
+        *R_PORT_PB_DIR = (port_pb_dir_shadow |=
+                          IO_STATE(R_PORT_PB_DIR, dir0, input)  |
+                          IO_STATE(R_PORT_PB_DIR, dir1, output));
+
+        return 0;
+}
+
+static int __init
+i2c_register(void)
+{
+        int res;
+
+        i2c_init();
+        res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
+        if(res < 0) {
+                printk(KERN_ERR "i2c: couldn't get a major number.\n");
+                return res;
+        }
+
+        printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n");
+        
+        return 0;
+}
+
+/* this makes sure that i2c_register is called during boot */
+
+module_init(i2c_register);
+
+/****************** END OF FILE i2c.c ********************************/
diff --git a/arch/cris/arch-v10/drivers/i2c.h b/arch/cris/arch-v10/drivers/i2c.h
new file mode 100644
index 000000000000..4ee91426bd40
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/i2c.h
@@ -0,0 +1,18 @@
+/* $Id: i2c.h,v 1.3 2004/05/28 09:26:59 starvik Exp $ */
+
+int i2c_init(void);
+
+/* High level I2C actions */
+int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
+unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
+
+/* Low level I2C */
+void i2c_start(void);
+void i2c_stop(void);
+void i2c_outbyte(unsigned char x);
+unsigned char i2c_inbyte(void);
+int i2c_getack(void);
+void i2c_sendack(void);
+
+
+
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c
new file mode 100644
index 000000000000..b3dfdf7b8fc5
--- /dev/null
+++ b/arch/cris/arch-v10/drivers/pcf8563.c
@@ -0,0 +1,313 @@
+/*
+ * PCF8563 RTC
+ *
+ * From Phillips' datasheet:
+ *
+ * The PCF8563 is a CMOS real-time clock/calendar optimized for low power
+ * consumption. A programmable clock output, interupt output and voltage
+ * low detector are also provided. All address and data are transferred
+ * serially via two-line bidirectional I2C-bus. Maximum bus speed is
+ * 400 kbits/s. The built-in word address register is incremented
+ * automatically after each written or read bute.
+ *
+ * Copyright (c) 2002, Axis Communications AB
+ * All rights reserved.
+ *
+ * Author: Tobias Anderberg <tobiasa@axis.com>.
+ *
+ * $Id: pcf8563.c,v 1.8 2004/08/24 06:42:51 starvik Exp $
+ */
+
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/ioctl.h>
+#include <linux/delay.h>
+#include <linux/bcd.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/arch/svinto.h>
+#include <asm/rtc.h>
+#include "i2c.h"
+
+#define PCF8563_MAJOR 121               /* Local major number. */
+#define DEVICE_NAME "rtc"               /* Name which is registered in /proc/devices. */
+#define PCF8563_NAME "PCF8563"
+#define DRIVER_VERSION "$Revision: 1.8 $"
+
+/* I2C bus slave registers. */
+#define RTC_I2C_READ            0xa3
+#define RTC_I2C_WRITE           0xa2
+
+/* Two simple wrapper macros, saves a few keystrokes. */
+#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
+#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
+        
+static const unsigned char days_in_month[] =
+        { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+
+static struct file_operations pcf8563_fops = {
+        .owner = THIS_MODULE,
+        .ioctl = pcf8563_ioctl,
+};
+
+unsigned char
+pcf8563_readreg(int reg) 
+{
+        unsigned char res = i2c_readreg(RTC_I2C_READ, reg);
+
+        /* The PCF8563 does not return 0 for unimplemented bits */
+        switch(reg)
+        {
+                case RTC_SECONDS:
+                case RTC_MINUTES:
+                     res &= 0x7f;
+                     break;
+                case RTC_HOURS:
+                case RTC_DAY_OF_MONTH:
+                     res &= 0x3f;
+                     break;
+                case RTC_MONTH:
+                     res = (res & 0x1f) - 1;  /* PCF8563 returns month in range 1-12 */
+                     break;
+        }
+        return res;
+}
+
+void
+pcf8563_writereg(int reg, unsigned char val) 
+{
+#ifdef CONFIG_ETRAX_RTC_READONLY
+        if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR))
+                return;
+#endif
+
+        rtc_write(reg, val);
+}
+
+void
+get_rtc_time(struct rtc_time *tm)
+{
+        tm->tm_sec = rtc_read(RTC_SECONDS);
+        tm->tm_min = rtc_read(RTC_MINUTES);
+        tm->tm_hour = rtc_read(RTC_HOURS);
+        tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH);
+        tm->tm_mon = rtc_read(RTC_MONTH);
+        tm->tm_year = rtc_read(RTC_YEAR);
+
+        if (tm->tm_sec & 0x80)
+                printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME);
+
+        tm->tm_year = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0);
+        tm->tm_sec &= 0x7f;
+        tm->tm_min &= 0x7f;
+        tm->tm_hour &= 0x3f;
+        tm->tm_mday &= 0x3f;
+        tm->tm_mon &= 0x1f;
+
+        BCD_TO_BIN(tm->tm_sec);
+        BCD_TO_BIN(tm->tm_min);
+        BCD_TO_BIN(tm->tm_hour);
+        BCD_TO_BIN(tm->tm_mday);
+        BCD_TO_BIN(tm->tm_mon);
+        tm->tm_mon--; /* Month is 1..12 in RTC but 0..11 in linux */
+}
+
+int __init
+pcf8563_init(void)
+{
+        unsigned char ret;
+
+        i2c_init();
+
+        /*
+         * First of all we need to reset the chip. This is done by
+         * clearing control1, control2 and clk freq, clear the 
+         * Voltage Low bit, and resetting all alarms.
+         */
+        if (rtc_write(RTC_CONTROL1, 0x00) < 0)
+                goto err;
+
+        if (rtc_write(RTC_CONTROL2, 0x00) < 0)
+                goto err;
+
+        if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0)
+                goto err;
+
+        /* Clear the VL bit in the seconds register. */
+        ret = rtc_read(RTC_SECONDS);
+        
+        if (rtc_write(RTC_SECONDS, (ret & 0x7f)) < 0)
+                goto err;
+                
+        /* Reset the alarms. */
+        if (rtc_write(RTC_MINUTE_ALARM, 0x00) < 0)
+                goto err;
+        
+        if (rtc_write(RTC_HOUR_ALARM, 0x00) < 0)
+                goto err;
+        
+        if (rtc_write(RTC_DAY_ALARM, 0x00) < 0)
+                goto err;
+        
+        if (rtc_write(RTC_WEEKDAY_ALARM, 0x00) < 0)
+                goto err;
+        
+        /* Check for low voltage, and warn about it.. */
+        if (rtc_read(RTC_SECONDS) & 0x80)
+                printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME);
+        
+        return 0;
+
+err:
+        printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
+        return -1;
+}
+
+void __exit
+pcf8563_exit(void)
+{
+        if (unregister_chrdev(PCF8563_MAJOR, DEVICE_NAME) < 0) {
+                printk(KERN_INFO "%s: Unable to unregister device.\n", PCF8563_NAME);
+        }
+}
+
+/*
+ * ioctl calls for this driver. Why return -ENOTTY upon error? Because
+ * POSIX says so!
+ */
+int
+pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+        /* Some sanity checks. */
+        if (_IOC_TYPE(cmd) != RTC_MAGIC)
+                return -ENOTTY;
+
+        if (_IOC_NR(cmd) > RTC_MAX_IOCTL)
+                return -ENOTTY;
+
+        switch (cmd) {
+                case RTC_RD_TIME:
+                        {
+                                struct rtc_time tm;
+
+                                get_rtc_time(&tm);
+
+                                if (copy_to_user((struct rtc_time *) arg, &tm, sizeof(struct rtc_time))) {
+                                        return -EFAULT;
+                                }
+
+                                return 0;
+                        }
+                        break;
+                case RTC_SET_TIME:
+                        {
+#ifdef CONFIG_ETRAX_RTC_READONLY
+                                return -EPERM;
+#else
+                                int leap;
+                                int century;
+                                struct rtc_time tm;
+
+                                memset(&tm, 0, sizeof (struct rtc_time));
+                                if (!capable(CAP_SYS_TIME))
+                                        return -EPERM;
+
+                                if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof(struct rtc_time)))
+                                        return -EFAULT;
+
+                                /* Convert from struct tm to struct rtc_time. */
+                                tm.tm_year += 1900;
+                                tm.tm_mon += 1;
+                                
+                                leap = ((tm.tm_mon == 2) && ((tm.tm_year % 4) == 0)) ? 1 : 0;
+
+                                /* Perform some sanity checks. */
+                                if ((tm.tm_year < 1970) ||
+                                    (tm.tm_mon > 12) ||
+                                    (tm.tm_mday == 0) ||
+                                    (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
+                                    (tm.tm_hour >= 24) ||
+                                    (tm.tm_min >= 60) ||
+                                    (tm.tm_sec >= 60))
+                                        return -EINVAL;
+
+                                century = (tm.tm_year >= 2000) ? 0x80 : 0;
+                                tm.tm_year = tm.tm_year % 100;
+
+                                BIN_TO_BCD(tm.tm_year);
+                                BIN_TO_BCD(tm.tm_mday);
+                                BIN_TO_BCD(tm.tm_hour);
+                                BIN_TO_BCD(tm.tm_min);
+                                BIN_TO_BCD(tm.tm_sec);
+                                tm.tm_mon |= century;
+                                
+                                rtc_write(RTC_YEAR, tm.tm_year);
+                                rtc_write(RTC_MONTH, tm.tm_mon);
+                                rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
+                                rtc_write(RTC_HOURS, tm.tm_hour);
+                                rtc_write(RTC_MINUTES, tm.tm_min);
+                                rtc_write(RTC_SECONDS, tm.tm_sec);
+
+                                return 0;
+#endif /* !CONFIG_ETRAX_RTC_READONLY */
+                        }
+
+                case RTC_VLOW_RD:
+                {
+                        int vl_bit = 0;
+
+                        if (rtc_read(RTC_SECONDS) & 0x80) {
+                                vl_bit = 1;
+                                printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
+                                       "date/time information is no longer guaranteed!\n",
+                                       PCF8563_NAME);
+                        }
+                        if (copy_to_user((int *) arg, &vl_bit, sizeof(int)))
+                                return -EFAULT;
+
+                        return 0;
+                }
+
+                case RTC_VLOW_SET:
+                {
+                        /* Clear the VL bit in the seconds register */
+                        int ret = rtc_read(RTC_SECONDS);
+
+                        rtc_write(RTC_SECONDS, (ret & 0x7F));
+
+                        return 0;
+                }
+
+                default:
+                                return -ENOTTY;
+        }
+
+        return 0;
+}
+
+static int __init
+pcf8563_register(void)
+{
+        pcf8563_init();
+        if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
+                printk(KERN_INFO "%s: Unable to get major numer %d for RTC device.\n",
+                       PCF8563_NAME, PCF8563_MAJOR);
+                return -1;
+        }
+
+        printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
+        return 0;
+}
+
+module_init(pcf8563_register);
+module_exit(pcf8563_exit);