aboutsummaryrefslogtreecommitdiffstats
path: root/arch/c6x
diff options
context:
space:
mode:
authorMark Salter <msalter@redhat.com>2011-10-04 12:12:20 -0400
committerMark Salter <msalter@redhat.com>2011-10-06 19:47:33 -0400
commit041cadca7008f08fb4785f2288c8127c16faa529 (patch)
tree19008ae2e32faf489f85e00838a571a5295c79f4 /arch/c6x
parentc1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817 (diff)
C6X: devicetree support
This is the basic devicetree support for C6X. Currently, four boards are supported. Each one uses a different SoC part. Two of the four supported SoCs are multicore. One with 3 cores and the other with 6 cores. There is no coherency between the core-level caches, so SMP is not an option. It is possible to run separate kernel instances on the various cores. There is currently no C6X bootloader support for device trees so we build in the DTB for now. There are some interesting twists to the hardware which are of note for device tree support. Each core has its own interrupt controller which is controlled by special purpose core registers. This core controller provides 12 general purpose prioritized interrupt sources. Each core is contained within a hardware "module" which provides L1 and L2 caches, power control, and another interrupt controller which cascades into the core interrupt controller. These core module functions are controlled by memory mapped registers. The addresses for these registers are the same for each core. That is, when coreN accesses a module-level MMIO register at a given address, it accesses the register for coreN even though other cores would use the same address to access the register in the module containing those cores. Other hardware modules (timers, enet, etc) which are memory mapped can be accessed by all cores. The timers need some further explanation for multicore SoCs. Even though all timer control registers are visible to all cores, interrupt routing or other considerations may make a given timer more suitable for use by a core than some other timer. Because of this and the desire to have the same image run on more than one core, the timer nodes have a "ti,core-mask" property which is used by the driver to scan for a suitable timer to use. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/c6x')
-rw-r--r--arch/c6x/boot/dts/dsk6455.dts62
-rw-r--r--arch/c6x/boot/dts/evmc6457.dts48
-rw-r--r--arch/c6x/boot/dts/evmc6472.dts73
-rw-r--r--arch/c6x/boot/dts/evmc6474.dts58
-rw-r--r--arch/c6x/boot/dts/tms320c6455.dtsi96
-rw-r--r--arch/c6x/boot/dts/tms320c6457.dtsi68
-rw-r--r--arch/c6x/boot/dts/tms320c6472.dtsi134
-rw-r--r--arch/c6x/boot/dts/tms320c6474.dtsi89
-rw-r--r--arch/c6x/boot/linked_dtb.S2
-rw-r--r--arch/c6x/kernel/devicetree.c53
-rw-r--r--arch/c6x/platforms/platform.c17
11 files changed, 700 insertions, 0 deletions
diff --git a/arch/c6x/boot/dts/dsk6455.dts b/arch/c6x/boot/dts/dsk6455.dts
new file mode 100644
index 000000000000..2b71f800618d
--- /dev/null
+++ b/arch/c6x/boot/dts/dsk6455.dts
@@ -0,0 +1,62 @@
1/*
2 * arch/c6x/boot/dts/dsk6455.dts
3 *
4 * DSK6455 Evaluation Platform For TMS320C6455
5 * Copyright (C) 2011 Texas Instruments Incorporated
6 *
7 * Author: Mark Salter <msalter@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 */
15
16/dts-v1/;
17
18/include/ "tms320c6455.dtsi"
19
20/ {
21 model = "Spectrum Digital DSK6455";
22 compatible = "spectrum-digital,dsk6455";
23
24 chosen {
25 bootargs = "root=/dev/nfs ip=dhcp rw";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0xE0000000 0x08000000>;
31 };
32
33 soc {
34 megamod_pic: interrupt-controller@1800000 {
35 interrupts = < 12 13 14 15 >;
36 };
37
38 emifa@70000000 {
39 flash@3,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x3 0x0 0x400000>;
44 bank-width = <1>;
45 device-width = <1>;
46 partition@0 {
47 reg = <0x0 0x400000>;
48 label = "NOR";
49 };
50 };
51 };
52
53 timer1: timer@2980000 {
54 interrupt-parent = <&megamod_pic>;
55 interrupts = < 69 >;
56 };
57
58 clock-controller@029a0000 {
59 clock-frequency = <50000000>;
60 };
61 };
62};
diff --git a/arch/c6x/boot/dts/evmc6457.dts b/arch/c6x/boot/dts/evmc6457.dts
new file mode 100644
index 000000000000..0301eb9a8ff8
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6457.dts
@@ -0,0 +1,48 @@
1/*
2 * arch/c6x/boot/dts/evmc6457.dts
3 *
4 * EVMC6457 Evaluation Platform For TMS320C6457
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6457.dtsi"
20
21/ {
22 model = "eInfochips EVMC6457";
23 compatible = "einfochips,evmc6457";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 67 >;
42 };
43
44 clock-controller@29a0000 {
45 clock-frequency = <60000000>;
46 };
47 };
48};
diff --git a/arch/c6x/boot/dts/evmc6472.dts b/arch/c6x/boot/dts/evmc6472.dts
new file mode 100644
index 000000000000..3e207b449a93
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6472.dts
@@ -0,0 +1,73 @@
1/*
2 * arch/c6x/boot/dts/evmc6472.dts
3 *
4 * EVMC6472 Evaluation Platform For TMS320C6472
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6472.dtsi"
20
21/ {
22 model = "eInfochips EVMC6472";
23 compatible = "einfochips,evmc6472";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@25e0000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 16 >;
42 };
43
44 timer1: timer@25f0000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 16 >;
47 };
48
49 timer2: timer@2600000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 16 >;
52 };
53
54 timer3: timer@2610000 {
55 interrupt-parent = <&megamod_pic>;
56 interrupts = < 16 >;
57 };
58
59 timer4: timer@2620000 {
60 interrupt-parent = <&megamod_pic>;
61 interrupts = < 16 >;
62 };
63
64 timer5: timer@2630000 {
65 interrupt-parent = <&megamod_pic>;
66 interrupts = < 16 >;
67 };
68
69 clock-controller@29a0000 {
70 clock-frequency = <25000000>;
71 };
72 };
73};
diff --git a/arch/c6x/boot/dts/evmc6474.dts b/arch/c6x/boot/dts/evmc6474.dts
new file mode 100644
index 000000000000..4dc291292bc4
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6474.dts
@@ -0,0 +1,58 @@
1/*
2 * arch/c6x/boot/dts/evmc6474.dts
3 *
4 * EVMC6474 Evaluation Platform For TMS320C6474
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6474.dtsi"
20
21/ {
22 model = "Spectrum Digital EVMC6474";
23 compatible = "spectrum-digital,evmc6474";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x08000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer3: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 39 >;
42 };
43
44 timer4: timer@2950000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 41 >;
47 };
48
49 timer5: timer@2960000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 43 >;
52 };
53
54 clock-controller@29a0000 {
55 clock-frequency = <50000000>;
56 };
57 };
58};
diff --git a/arch/c6x/boot/dts/tms320c6455.dtsi b/arch/c6x/boot/dts/tms320c6455.dtsi
new file mode 100644
index 000000000000..a804ec1e018b
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6455.dtsi
@@ -0,0 +1,96 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6455";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 /*
31 * Megamodule interrupt controller
32 */
33 megamod_pic: interrupt-controller@1800000 {
34 compatible = "ti,c64x+megamod-pic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x1800000 0x1000>;
38 interrupt-parent = <&core_pic>;
39 };
40
41 cache-controller@1840000 {
42 compatible = "ti,c64x+cache";
43 reg = <0x01840000 0x8400>;
44 };
45
46 emifa@70000000 {
47 compatible = "ti,c64x+emifa", "simple-bus";
48 #address-cells = <2>;
49 #size-cells = <1>;
50 reg = <0x70000000 0x100>;
51 ranges = <0x2 0x0 0xa0000000 0x00000008
52 0x3 0x0 0xb0000000 0x00400000
53 0x4 0x0 0xc0000000 0x10000000
54 0x5 0x0 0xD0000000 0x10000000>;
55
56 ti,dscr-dev-enable = <13>;
57 ti,emifa-burst-priority = <255>;
58 ti,emifa-ce-config = <0x00240120
59 0x00240120
60 0x00240122
61 0x00240122>;
62 };
63
64 timer1: timer@2980000 {
65 compatible = "ti,c64x+timer64";
66 reg = <0x2980000 0x40>;
67 ti,dscr-dev-enable = <4>;
68 };
69
70 clock-controller@029a0000 {
71 compatible = "ti,c6455-pll", "ti,c64x+pll";
72 reg = <0x029a0000 0x200>;
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
76 };
77
78 device-state-config-regs@2a80000 {
79 compatible = "ti,c64x+dscr";
80 reg = <0x02a80000 0x41000>;
81
82 ti,dscr-devstat = <0>;
83 ti,dscr-silicon-rev = <8 28 0xf>;
84 ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
85
86 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
87 ti,dscr-devstate-ctl-regs =
88 <0 12 0x40008 1 0 0 2
89 12 1 0x40008 3 0 30 2
90 13 2 0x4002c 1 0xffffffff 0 1>;
91 ti,dscr-devstate-stat-regs =
92 <0 10 0x40014 1 0 0 3
93 10 2 0x40018 1 0 0 3>;
94 };
95 };
96};
diff --git a/arch/c6x/boot/dts/tms320c6457.dtsi b/arch/c6x/boot/dts/tms320c6457.dtsi
new file mode 100644
index 000000000000..35f40709a719
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6457.dtsi
@@ -0,0 +1,68 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6457";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 megamod_pic: interrupt-controller@1800000 {
31 compatible = "ti,c64x+megamod-pic";
32 interrupt-controller;
33 #interrupt-cells = <1>;
34 interrupt-parent = <&core_pic>;
35 reg = <0x1800000 0x1000>;
36 };
37
38 cache-controller@1840000 {
39 compatible = "ti,c64x+cache";
40 reg = <0x01840000 0x8400>;
41 };
42
43 device-state-controller@2880800 {
44 compatible = "ti,c64x+dscr";
45 reg = <0x02880800 0x400>;
46
47 ti,dscr-devstat = <0x20>;
48 ti,dscr-silicon-rev = <0x18 28 0xf>;
49 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
50 0x118 0 0 1 2>;
51 ti,dscr-kick-regs = <0x38 0x83E70B13
52 0x3c 0x95A4F1E0>;
53 };
54
55 timer0: timer@2940000 {
56 compatible = "ti,c64x+timer64";
57 reg = <0x2940000 0x40>;
58 };
59
60 clock-controller@29a0000 {
61 compatible = "ti,c6457-pll", "ti,c64x+pll";
62 reg = <0x029a0000 0x200>;
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
66 };
67 };
68};
diff --git a/arch/c6x/boot/dts/tms320c6472.dtsi b/arch/c6x/boot/dts/tms320c6472.dtsi
new file mode 100644
index 000000000000..b488aaec65c0
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6472.dtsi
@@ -0,0 +1,134 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 cpu@3 {
26 device_type = "cpu";
27 reg = <3>;
28 model = "ti,c64x+";
29 };
30 cpu@4 {
31 device_type = "cpu";
32 reg = <4>;
33 model = "ti,c64x+";
34 };
35 cpu@5 {
36 device_type = "cpu";
37 reg = <5>;
38 model = "ti,c64x+";
39 };
40 };
41
42 soc {
43 compatible = "simple-bus";
44 model = "tms320c6472";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 core_pic: interrupt-controller {
50 compatible = "ti,c64x+core-pic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 };
54
55 megamod_pic: interrupt-controller@1800000 {
56 compatible = "ti,c64x+megamod-pic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x1800000 0x1000>;
60 interrupt-parent = <&core_pic>;
61 };
62
63 cache-controller@1840000 {
64 compatible = "ti,c64x+cache";
65 reg = <0x01840000 0x8400>;
66 };
67
68 timer0: timer@25e0000 {
69 compatible = "ti,c64x+timer64";
70 ti,core-mask = < 0x01 >;
71 reg = <0x25e0000 0x40>;
72 };
73
74 timer1: timer@25f0000 {
75 compatible = "ti,c64x+timer64";
76 ti,core-mask = < 0x02 >;
77 reg = <0x25f0000 0x40>;
78 };
79
80 timer2: timer@2600000 {
81 compatible = "ti,c64x+timer64";
82 ti,core-mask = < 0x04 >;
83 reg = <0x2600000 0x40>;
84 };
85
86 timer3: timer@2610000 {
87 compatible = "ti,c64x+timer64";
88 ti,core-mask = < 0x08 >;
89 reg = <0x2610000 0x40>;
90 };
91
92 timer4: timer@2620000 {
93 compatible = "ti,c64x+timer64";
94 ti,core-mask = < 0x10 >;
95 reg = <0x2620000 0x40>;
96 };
97
98 timer5: timer@2630000 {
99 compatible = "ti,c64x+timer64";
100 ti,core-mask = < 0x20 >;
101 reg = <0x2630000 0x40>;
102 };
103
104 clock-controller@29a0000 {
105 compatible = "ti,c6472-pll", "ti,c64x+pll";
106 reg = <0x029a0000 0x200>;
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
110 };
111
112 device-state-controller@2a80000 {
113 compatible = "ti,c64x+dscr";
114 reg = <0x02a80000 0x1000>;
115
116 ti,dscr-devstat = <0>;
117 ti,dscr-silicon-rev = <0x70c 16 0xff>;
118
119 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
120 0x704 5 6 0 0>;
121
122 ti,dscr-rmii-resets = <0x208 1
123 0x20c 1>;
124
125 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
126 0x40c 0x420 0xbea7
127 0x41c 0x420 0xbea7>;
128
129 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
130
131 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
132 };
133 };
134};
diff --git a/arch/c6x/boot/dts/tms320c6474.dtsi b/arch/c6x/boot/dts/tms320c6474.dtsi
new file mode 100644
index 000000000000..cc601bf348a1
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6474.dtsi
@@ -0,0 +1,89 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 };
26
27 soc {
28 compatible = "simple-bus";
29 model = "tms320c6474";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 ranges;
33
34 core_pic: interrupt-controller {
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 compatible = "ti,c64x+core-pic";
38 };
39
40 megamod_pic: interrupt-controller@1800000 {
41 compatible = "ti,c64x+megamod-pic";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 reg = <0x1800000 0x1000>;
45 interrupt-parent = <&core_pic>;
46 };
47
48 cache-controller@1840000 {
49 compatible = "ti,c64x+cache";
50 reg = <0x01840000 0x8400>;
51 };
52
53 timer3: timer@2940000 {
54 compatible = "ti,c64x+timer64";
55 ti,core-mask = < 0x04 >;
56 reg = <0x2940000 0x40>;
57 };
58
59 timer4: timer@2950000 {
60 compatible = "ti,c64x+timer64";
61 ti,core-mask = < 0x02 >;
62 reg = <0x2950000 0x40>;
63 };
64
65 timer5: timer@2960000 {
66 compatible = "ti,c64x+timer64";
67 ti,core-mask = < 0x01 >;
68 reg = <0x2960000 0x40>;
69 };
70
71 device-state-controller@2880800 {
72 compatible = "ti,c64x+dscr";
73 reg = <0x02880800 0x400>;
74
75 ti,dscr-devstat = <0x004>;
76 ti,dscr-silicon-rev = <0x014 28 0xf>;
77 ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
78 0x38 0 0 1 2>;
79 };
80
81 clock-controller@29a0000 {
82 compatible = "ti,c6474-pll", "ti,c64x+pll";
83 reg = <0x029a0000 0x200>;
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
87 };
88 };
89};
diff --git a/arch/c6x/boot/linked_dtb.S b/arch/c6x/boot/linked_dtb.S
new file mode 100644
index 000000000000..57a4454eaec3
--- /dev/null
+++ b/arch/c6x/boot/linked_dtb.S
@@ -0,0 +1,2 @@
1.section __fdt_blob,"a"
2.incbin "arch/c6x/boot/builtin.dtb"
diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c
new file mode 100644
index 000000000000..bdb56f09d0ac
--- /dev/null
+++ b/arch/c6x/kernel/devicetree.c
@@ -0,0 +1,53 @@
1/*
2 * Architecture specific OF callbacks.
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated
5 * Author: Mark Salter <msalter@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/of_fdt.h>
15#include <linux/initrd.h>
16#include <linux/memblock.h>
17
18void __init early_init_devtree(void *params)
19{
20 /* Setup flat device-tree pointer */
21 initial_boot_params = params;
22
23 /* Retrieve various informations from the /chosen node of the
24 * device-tree, including the platform type, initrd location and
25 * size and more ...
26 */
27 of_scan_flat_dt(early_init_dt_scan_chosen, c6x_command_line);
28
29 /* Scan memory nodes and rebuild MEMBLOCKs */
30 of_scan_flat_dt(early_init_dt_scan_root, NULL);
31 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
32}
33
34
35#ifdef CONFIG_BLK_DEV_INITRD
36void __init early_init_dt_setup_initrd_arch(unsigned long start,
37 unsigned long end)
38{
39 initrd_start = (unsigned long)__va(start);
40 initrd_end = (unsigned long)__va(end);
41 initrd_below_start_ok = 1;
42}
43#endif
44
45void __init early_init_dt_add_memory_arch(u64 base, u64 size)
46{
47 c6x_add_memory(base, size);
48}
49
50void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
51{
52 return __va(memblock_alloc(size, align));
53}
diff --git a/arch/c6x/platforms/platform.c b/arch/c6x/platforms/platform.c
new file mode 100644
index 000000000000..26c1a355d600
--- /dev/null
+++ b/arch/c6x/platforms/platform.c
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2011 Texas Instruments Incorporated
3 *
4 * This file is licensed under the terms of the GNU General Public License
5 * version 2. This program is licensed "as is" without any warranty of any
6 * kind, whether express or implied.
7 */
8
9#include <linux/init.h>
10#include <linux/of_platform.h>
11
12static int __init c6x_device_probe(void)
13{
14 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
15 return 0;
16}
17core_initcall(c6x_device_probe);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 13:07:50 -0500