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authorAurelien Jacquiot <a-jacquiot@ti.com>2011-10-04 11:11:35 -0400
committerMark Salter <msalter@redhat.com>2011-10-06 19:48:10 -0400
commit784bdcd0aa1d8ce38025bcfaa321146762738fe0 (patch)
tree1b1bda6b0c573d39aaa6615b6ec2dc9e206378ff /arch/c6x/include/asm
parent81ec98898188639ac53413605681b3e3bb0a2ff1 (diff)
C6X: cache control
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/c6x/include/asm')
-rw-r--r--arch/c6x/include/asm/cache.h90
-rw-r--r--arch/c6x/include/asm/cacheflush.h65
2 files changed, 155 insertions, 0 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
new file mode 100644
index 000000000000..6d521d96d941
--- /dev/null
+++ b/arch/c6x/include/asm/cache.h
@@ -0,0 +1,90 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_CACHE_H
12#define _ASM_C6X_CACHE_H
13
14#include <linux/irqflags.h>
15
16/*
17 * Cache line size
18 */
19#define L1D_CACHE_BYTES 64
20#define L1P_CACHE_BYTES 32
21#define L2_CACHE_BYTES 128
22
23/*
24 * L2 used as cache
25 */
26#define L2MODE_SIZE L2MODE_256K_CACHE
27
28/*
29 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
30 * the L2 line size
31 */
32#define L1_CACHE_BYTES L2_CACHE_BYTES
33
34#define L2_CACHE_ALIGN_LOW(x) \
35 (((x) & ~(L2_CACHE_BYTES - 1)))
36#define L2_CACHE_ALIGN_UP(x) \
37 (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
38#define L2_CACHE_ALIGN_CNT(x) \
39 (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
40
41#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
42#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
43
44/*
45 * This is the granularity of hardware cacheability control.
46 */
47#define CACHEABILITY_ALIGN 0x01000000
48
49/*
50 * Align a physical address to MAR regions
51 */
52#define CACHE_REGION_START(v) \
53 (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
54#define CACHE_REGION_END(v) \
55 (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
56
57extern void __init c6x_cache_init(void);
58
59extern void enable_caching(unsigned long start, unsigned long end);
60extern void disable_caching(unsigned long start, unsigned long end);
61
62extern void L1_cache_off(void);
63extern void L1_cache_on(void);
64
65extern void L1P_cache_global_invalidate(void);
66extern void L1D_cache_global_invalidate(void);
67extern void L1D_cache_global_writeback(void);
68extern void L1D_cache_global_writeback_invalidate(void);
69extern void L2_cache_set_mode(unsigned int mode);
70extern void L2_cache_global_writeback_invalidate(void);
71extern void L2_cache_global_writeback(void);
72
73extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
74extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
75extern void L1D_cache_block_writeback_invalidate(unsigned int start,
76 unsigned int end);
77extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
78extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
79extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
80extern void L2_cache_block_writeback_invalidate(unsigned int start,
81 unsigned int end);
82extern void L2_cache_block_invalidate_nowait(unsigned int start,
83 unsigned int end);
84extern void L2_cache_block_writeback_nowait(unsigned int start,
85 unsigned int end);
86
87extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
88 unsigned int end);
89
90#endif /* _ASM_C6X_CACHE_H */
diff --git a/arch/c6x/include/asm/cacheflush.h b/arch/c6x/include/asm/cacheflush.h
new file mode 100644
index 000000000000..df5db90dbe56
--- /dev/null
+++ b/arch/c6x/include/asm/cacheflush.h
@@ -0,0 +1,65 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_CACHEFLUSH_H
12#define _ASM_C6X_CACHEFLUSH_H
13
14#include <linux/spinlock.h>
15
16#include <asm/setup.h>
17#include <asm/cache.h>
18#include <asm/mman.h>
19#include <asm/page.h>
20#include <asm/string.h>
21
22/*
23 * virtually-indexed cache management (our cache is physically indexed)
24 */
25#define flush_cache_all() do {} while (0)
26#define flush_cache_mm(mm) do {} while (0)
27#define flush_cache_dup_mm(mm) do {} while (0)
28#define flush_cache_range(mm, start, end) do {} while (0)
29#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
30#define flush_cache_vmap(start, end) do {} while (0)
31#define flush_cache_vunmap(start, end) do {} while (0)
32#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
33#define flush_dcache_page(page) do {} while (0)
34#define flush_dcache_mmap_lock(mapping) do {} while (0)
35#define flush_dcache_mmap_unlock(mapping) do {} while (0)
36
37/*
38 * physically-indexed cache management
39 */
40#define flush_icache_range(s, e) \
41do { \
42 L1D_cache_block_writeback((s), (e)); \
43 L1P_cache_block_invalidate((s), (e)); \
44} while (0)
45
46#define flush_icache_page(vma, page) \
47do { \
48 if ((vma)->vm_flags & PROT_EXEC) \
49 L1D_cache_block_writeback_invalidate(page_address(page), \
50 (unsigned long) page_address(page) + PAGE_SIZE)); \
51 L1P_cache_block_invalidate(page_address(page), \
52 (unsigned long) page_address(page) + PAGE_SIZE)); \
53} while (0)
54
55
56#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
57do { \
58 memcpy(dst, src, len); \
59 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
60} while (0)
61
62#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
63 memcpy(dst, src, len)
64
65#endif /* _ASM_C6X_CACHEFLUSH_H */
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