C6X: add basic support for TMS320C6678 SoC

This patch adds support for the TMS320C6678 SoC on an EVMC6678LE
evaluation board. The 6678 is a C66x family CPU which is very similar
to the already supported C64x CPUs with the addition of floating point
instructions.

Signed-off-by: Ken Cox <jkc@redhat.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Aurelien Jacquiot <a-jacquiot@ti.com>
CC: linux-c6x-dev@linux-c6x.org

2 files changed, 229 insertions, 0 deletions

diff --git a/arch/c6x/boot/dts/evmc6678.dts b/arch/c6x/boot/dts/evmc6678.dts
new file mode 100644
index 000000000000..ab686301d321
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6678.dts
@@ -0,0 +1,83 @@
+/*
+ * arch/c6x/boot/dts/evmc6678.dts
+ *
+ * EVMC6678 Evaluation Platform For TMS320C6678
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated
+ *
+ * Author: Ken Cox <jkc@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6678.dtsi"
+
+/ {
+        model = "Advantech EVMC6678";
+        compatible = "advantech,evmc6678";
+
+        chosen {
+                bootargs = "root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                       interrupts = < 12 13 14 15 >;
+                };
+
+                timer8: timer@2280000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 66 >;
+                };
+
+                timer9: timer@2290000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 68 >;
+                };
+
+                timer10: timer@22A0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 70 >;
+                };
+
+                timer11: timer@22B0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 72 >;
+                };
+
+                timer12: timer@22C0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 74 >;
+                };
+
+                timer13: timer@22D0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 76 >;
+                };
+
+                timer14: timer@22E0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 78 >;
+                };
+
+                timer15: timer@22F0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 80 >;
+                };
+
+                clock-controller@2310000 {
+                        clock-frequency = <100000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6678.dtsi b/arch/c6x/boot/dts/tms320c6678.dtsi
new file mode 100644
index 000000000000..386196e5eae7
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6678.dtsi
@@ -0,0 +1,146 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        model = "ti,c66x";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        model = "ti,c66x";
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        model = "ti,c66x";
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        model = "ti,c66x";
+                };
+                cpu@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        model = "ti,c66x";
+                };
+                cpu@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        model = "ti,c66x";
+                };
+                cpu@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        model = "ti,c66x";
+                };
+                cpu@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        model = "ti,c66x";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6678";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                        compatible = "ti,c64x+core-pic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                megamod_pic: interrupt-controller@1800000 {
+                       compatible = "ti,c64x+megamod-pic";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x1800000 0x1000>;
+                       interrupt-parent = <&core_pic>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                timer8: timer@2280000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x01 >;
+                        reg = <0x2280000 0x40>;
+                };
+
+                timer9: timer@2290000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x02 >;
+                        reg = <0x2290000 0x40>;
+                };
+
+                timer10: timer@22A0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x04 >;
+                        reg = <0x22A0000 0x40>;
+                };
+
+                timer11: timer@22B0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x08 >;
+                        reg = <0x22B0000 0x40>;
+                };
+
+                timer12: timer@22C0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x10 >;
+                        reg = <0x22C0000 0x40>;
+                };
+
+                timer13: timer@22D0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x20 >;
+                        reg = <0x22D0000 0x40>;
+                };
+
+                timer14: timer@22E0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x40 >;
+                        reg = <0x22E0000 0x40>;
+                };
+
+                timer15: timer@22F0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x80 >;
+                        reg = <0x22F0000 0x40>;
+                };
+
+                clock-controller@2310000 {
+                        compatible = "ti,c6678-pll", "ti,c64x+pll";
+                        reg = <0x02310000 0x200>;
+                        ti,c64x+pll-bypass-delay = <200>;
+                        ti,c64x+pll-reset-delay = <12000>;
+                        ti,c64x+pll-lock-delay = <80000>;
+                };
+
+                device-state-controller@2620000 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02620000 0x1000>;
+
+                        ti,dscr-devstat = <0x20>;
+                        ti,dscr-silicon-rev = <0x18 28 0xf>;
+
+                        ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
+                                                 0x114 5 6 0 0>;
+
+                };
+        };
+};