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authorMichael Hennerich <michael.hennerich@analog.com>2008-02-25 00:50:20 -0500
committerBryan Wu <cooloney@kernel.org>2008-02-25 00:50:20 -0500
commit464abc5de6ea8f4af1c1246e0d1ea7b07362db43 (patch)
tree240ad94cba9a8482756fd0b4059497afc353e1a2 /arch/blackfin
parentce3b7bb61c120e1e4e70e892ec281ef2bb81d6fa (diff)
[Blackfin] arch: Cleanup abd Simplify:
- Simplify init_arch_irq - Make code more readable - Remove useless SSYNCs - Fix comments Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-common/ints-priority.c157
1 files changed, 51 insertions, 106 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 22bcdef00e0a..225ef14af75e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -74,7 +74,7 @@ unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74#endif 74#endif
75 75
76struct ivgx { 76struct ivgx {
77 /* irq number for request_irq, available in mach-bf533/irq.h */ 77 /* irq number for request_irq, available in mach-bf5xx/irq.h */
78 unsigned int irqno; 78 unsigned int irqno;
79 /* corresponding bit in the SIC_ISR register */ 79 /* corresponding bit in the SIC_ISR register */
80 unsigned int isrflag; 80 unsigned int isrflag;
@@ -86,7 +86,6 @@ struct ivg_slice {
86 struct ivgx *istop; 86 struct ivgx *istop;
87} ivg7_13[IVG13 - IVG7 + 1]; 87} ivg7_13[IVG13 - IVG7 + 1];
88 88
89static void search_IAR(void);
90 89
91/* 90/*
92 * Search SIC_IAR and fill tables with the irqvalues 91 * Search SIC_IAR and fill tables with the irqvalues
@@ -120,10 +119,10 @@ static void __init search_IAR(void)
120} 119}
121 120
122/* 121/*
123 * This is for BF533 internal IRQs 122 * This is for core internal IRQs
124 */ 123 */
125 124
126static void ack_noop(unsigned int irq) 125static void bfin_ack_noop(unsigned int irq)
127{ 126{
128 /* Dummy function. */ 127 /* Dummy function. */
129} 128}
@@ -156,11 +155,11 @@ static void bfin_internal_mask_irq(unsigned int irq)
156{ 155{
157#ifdef CONFIG_BF53x 156#ifdef CONFIG_BF53x
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << (irq - (IRQ_CORETMR + 1)))); 158 ~(1 << SIC_SYSIRQ(irq)));
160#else 159#else
161 unsigned mask_bank, mask_bit; 160 unsigned mask_bank, mask_bit;
162 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 161 mask_bank = SIC_SYSIRQ(irq) / 32;
163 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; 162 mask_bit = SIC_SYSIRQ(irq) % 32;
164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 163 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit)); 164 ~(1 << mask_bit));
166#endif 165#endif
@@ -171,11 +170,11 @@ static void bfin_internal_unmask_irq(unsigned int irq)
171{ 170{
172#ifdef CONFIG_BF53x 171#ifdef CONFIG_BF53x
173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << (irq - (IRQ_CORETMR + 1)))); 173 (1 << SIC_SYSIRQ(irq)));
175#else 174#else
176 unsigned mask_bank, mask_bit; 175 unsigned mask_bank, mask_bit;
177 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 176 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; 177 mask_bit = SIC_SYSIRQ(irq) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | 178 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit)); 179 (1 << mask_bit));
181#endif 180#endif
@@ -187,8 +186,8 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{ 186{
188 unsigned bank, bit; 187 unsigned bank, bit;
189 unsigned long flags; 188 unsigned long flags;
190 bank = (irq - (IRQ_CORETMR + 1)) / 32; 189 bank = SIC_SYSIRQ(irq) / 32;
191 bit = (irq - (IRQ_CORETMR + 1)) % 32; 190 bit = SIC_SYSIRQ(irq) % 32;
192 191
193 local_irq_save(flags); 192 local_irq_save(flags);
194 193
@@ -204,13 +203,13 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
204#endif 203#endif
205 204
206static struct irq_chip bfin_core_irqchip = { 205static struct irq_chip bfin_core_irqchip = {
207 .ack = ack_noop, 206 .ack = bfin_ack_noop,
208 .mask = bfin_core_mask_irq, 207 .mask = bfin_core_mask_irq,
209 .unmask = bfin_core_unmask_irq, 208 .unmask = bfin_core_unmask_irq,
210}; 209};
211 210
212static struct irq_chip bfin_internal_irqchip = { 211static struct irq_chip bfin_internal_irqchip = {
213 .ack = ack_noop, 212 .ack = bfin_ack_noop,
214 .mask = bfin_internal_mask_irq, 213 .mask = bfin_internal_mask_irq,
215 .unmask = bfin_internal_unmask_irq, 214 .unmask = bfin_internal_unmask_irq,
216 .mask_ack = bfin_internal_mask_irq, 215 .mask_ack = bfin_internal_mask_irq,
@@ -224,38 +223,23 @@ static struct irq_chip bfin_internal_irqchip = {
224#ifdef BF537_GENERIC_ERROR_INT_DEMUX 223#ifdef BF537_GENERIC_ERROR_INT_DEMUX
225static int error_int_mask; 224static int error_int_mask;
226 225
227static void bfin_generic_error_ack_irq(unsigned int irq)
228{
229
230}
231
232static void bfin_generic_error_mask_irq(unsigned int irq) 226static void bfin_generic_error_mask_irq(unsigned int irq)
233{ 227{
234 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); 228 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
235 229
236 if (!error_int_mask) { 230 if (!error_int_mask)
237 local_irq_disable(); 231 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
238 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
239 ~(1 << (IRQ_GENERIC_ERROR -
240 (IRQ_CORETMR + 1))));
241 SSYNC();
242 local_irq_enable();
243 }
244} 232}
245 233
246static void bfin_generic_error_unmask_irq(unsigned int irq) 234static void bfin_generic_error_unmask_irq(unsigned int irq)
247{ 235{
248 local_irq_disable(); 236 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
249 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
250 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
251 SSYNC();
252 local_irq_enable();
253
254 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); 237 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
255} 238}
256 239
257static struct irq_chip bfin_generic_error_irqchip = { 240static struct irq_chip bfin_generic_error_irqchip = {
258 .ack = bfin_generic_error_ack_irq, 241 .ack = bfin_ack_noop,
242 .mask_ack = bfin_generic_error_mask_irq,
259 .mask = bfin_generic_error_mask_irq, 243 .mask = bfin_generic_error_mask_irq,
260 .unmask = bfin_generic_error_unmask_irq, 244 .unmask = bfin_generic_error_unmask_irq,
261}; 245};
@@ -611,7 +595,7 @@ static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
611 (struct pin_int_t *)PINT3_MASK_SET, 595 (struct pin_int_t *)PINT3_MASK_SET,
612}; 596};
613 597
614unsigned short get_irq_base(u8 bank, u8 bmap) 598inline unsigned short get_irq_base(u8 bank, u8 bmap)
615{ 599{
616 600
617 u16 irq_base; 601 u16 irq_base;
@@ -978,7 +962,6 @@ int __init init_arch_irq(void)
978#else 962#else
979 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 963 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
980#endif 964#endif
981 SSYNC();
982 965
983 local_irq_disable(); 966 local_irq_disable();
984 967
@@ -1000,90 +983,53 @@ int __init init_arch_irq(void)
1000 set_irq_chip(irq, &bfin_core_irqchip); 983 set_irq_chip(irq, &bfin_core_irqchip);
1001 else 984 else
1002 set_irq_chip(irq, &bfin_internal_irqchip); 985 set_irq_chip(irq, &bfin_internal_irqchip);
1003#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1004 if (irq != IRQ_GENERIC_ERROR) {
1005#endif
1006 986
1007 switch (irq) { 987 switch (irq) {
1008#if defined(CONFIG_BF53x) 988#if defined(CONFIG_BF53x)
1009 case IRQ_PROG_INTA: 989 case IRQ_PROG_INTA:
1010 set_irq_chained_handler(irq,
1011 bfin_demux_gpio_irq);
1012 break;
1013# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 990# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1014 case IRQ_MAC_RX: 991 case IRQ_MAC_RX:
1015 set_irq_chained_handler(irq,
1016 bfin_demux_gpio_irq);
1017 break;
1018# endif 992# endif
1019#elif defined(CONFIG_BF54x) 993#elif defined(CONFIG_BF54x)
1020 case IRQ_PINT0: 994 case IRQ_PINT0:
1021 set_irq_chained_handler(irq, 995 case IRQ_PINT1:
1022 bfin_demux_gpio_irq); 996 case IRQ_PINT2:
1023 break; 997 case IRQ_PINT3:
1024 case IRQ_PINT1:
1025 set_irq_chained_handler(irq,
1026 bfin_demux_gpio_irq);
1027 break;
1028 case IRQ_PINT2:
1029 set_irq_chained_handler(irq,
1030 bfin_demux_gpio_irq);
1031 break;
1032 case IRQ_PINT3:
1033 set_irq_chained_handler(irq,
1034 bfin_demux_gpio_irq);
1035 break;
1036#elif defined(CONFIG_BF52x) 998#elif defined(CONFIG_BF52x)
1037 case IRQ_PORTF_INTA: 999 case IRQ_PORTF_INTA:
1038 set_irq_chained_handler(irq, 1000 case IRQ_PORTG_INTA:
1039 bfin_demux_gpio_irq); 1001 case IRQ_PORTH_INTA:
1040 break;
1041 case IRQ_PORTG_INTA:
1042 set_irq_chained_handler(irq,
1043 bfin_demux_gpio_irq);
1044 break;
1045 case IRQ_PORTH_INTA:
1046 set_irq_chained_handler(irq,
1047 bfin_demux_gpio_irq);
1048 break;
1049#elif defined(CONFIG_BF561) 1002#elif defined(CONFIG_BF561)
1050 case IRQ_PROG0_INTA: 1003 case IRQ_PROG0_INTA:
1051 set_irq_chained_handler(irq, 1004 case IRQ_PROG1_INTA:
1052 bfin_demux_gpio_irq); 1005 case IRQ_PROG2_INTA:
1053 break;
1054 case IRQ_PROG1_INTA:
1055 set_irq_chained_handler(irq,
1056 bfin_demux_gpio_irq);
1057 break;
1058 case IRQ_PROG2_INTA:
1059 set_irq_chained_handler(irq,
1060 bfin_demux_gpio_irq);
1061 break;
1062#endif 1006#endif
1063 default: 1007 set_irq_chained_handler(irq,
1064 set_irq_handler(irq, handle_simple_irq); 1008 bfin_demux_gpio_irq);
1065 break; 1009 break;
1066 }
1067
1068#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1010#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1069 } else { 1011 case IRQ_GENERIC_ERROR:
1070 set_irq_handler(irq, bfin_demux_error_irq); 1012 set_irq_handler(irq, bfin_demux_error_irq);
1071 } 1013
1014 break;
1072#endif 1015#endif
1016 default:
1017 set_irq_handler(irq, handle_simple_irq);
1018 break;
1019 }
1073 } 1020 }
1021
1074#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1022#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1075 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) { 1023 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1076 set_irq_chip(irq, &bfin_generic_error_irqchip); 1024 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1077 set_irq_handler(irq, handle_level_irq); 1025 handle_level_irq);
1078 }
1079#endif 1026#endif
1080 1027
1081 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) { 1028 /* if configured as edge, then will be changed to do_edge_IRQ */
1029 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1030 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1031 handle_level_irq);
1082 1032
1083 set_irq_chip(irq, &bfin_gpio_irqchip);
1084 /* if configured as edge, then will be changed to do_edge_IRQ */
1085 set_irq_handler(irq, handle_level_irq);
1086 }
1087 1033
1088 bfin_write_IMASK(0); 1034 bfin_write_IMASK(0);
1089 CSYNC(); 1035 CSYNC();
@@ -1131,7 +1077,6 @@ void do_irq(int vec, struct pt_regs *fp)
1131#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1077#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1132 unsigned long sic_status[3]; 1078 unsigned long sic_status[3];
1133 1079
1134 SSYNC();
1135 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1080 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1136 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); 1081 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1137#ifdef CONFIG_BF54x 1082#ifdef CONFIG_BF54x
@@ -1147,7 +1092,7 @@ void do_irq(int vec, struct pt_regs *fp)
1147 } 1092 }
1148#else 1093#else
1149 unsigned long sic_status; 1094 unsigned long sic_status;
1150 SSYNC(); 1095
1151 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 1096 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1152 1097
1153 for (;; ivg++) { 1098 for (;; ivg++) {