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authorMike Frysinger <vapier.adi@gmail.com>2008-08-14 02:29:57 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-14 02:29:57 -0400
commit0e06b50dda5965e0f8a15b0be14b759ead54fd2a (patch)
tree3b0bf1ba71ba8799e55a7670d8572615443c0ba5 /arch/blackfin
parent55546ac45dfb4087437bedaed43400630c96680e (diff)
Blackfin arch: cleanup cache lock code
- remove cheesy read_iloc() function - move invalidate_entire_icache function to lock.S - export proper prototypes for functions in lock.S - only build lock.S when BFIN_ICACHE_LOCK is enabled Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/setup.c2
-rw-r--r--arch/blackfin/mach-common/Makefile3
-rw-r--r--arch/blackfin/mach-common/lock.S45
3 files changed, 34 insertions, 16 deletions
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 936c06d820de..2ae84fea89eb 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1059,7 +1059,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1059 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, 1059 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1060 BFIN_DLINES); 1060 BFIN_DLINES);
1061#ifdef CONFIG_BFIN_ICACHE_LOCK 1061#ifdef CONFIG_BFIN_ICACHE_LOCK
1062 switch (read_iloc()) { 1062 switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) {
1063 case WAY0_L: 1063 case WAY0_L:
1064 seq_printf(m, "Way0 Locked-Down\n"); 1064 seq_printf(m, "Way0 Locked-Down\n");
1065 break; 1065 break;
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 862cd73c9504..e6ed57c56d4b 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,8 +4,9 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o entry.o head.o \ 6 cache.o entry.o head.o \
7 interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o 7 interrupt.o irqpanic.o arch_checks.o ints-priority.o
8 8
9obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
9obj-$(CONFIG_PM) += pm.o dpmc_modes.o 10obj-$(CONFIG_PM) += pm.o dpmc_modes.o
10obj-$(CONFIG_CPU_FREQ) += cpufreq.o 11obj-$(CONFIG_CPU_FREQ) += cpufreq.o
11obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o 12obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 30b887e67dd6..9daf01201e9f 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -28,13 +28,10 @@
28 */ 28 */
29 29
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <asm/cplb.h>
32#include <asm/blackfin.h> 31#include <asm/blackfin.h>
33 32
34.text 33.text
35 34
36#ifdef CONFIG_BFIN_ICACHE_LOCK
37
38/* When you come here, it is assumed that 35/* When you come here, it is assumed that
39 * R0 - Which way to be locked 36 * R0 - Which way to be locked
40 */ 37 */
@@ -189,18 +186,38 @@ ENTRY(_cache_lock)
189 RTS; 186 RTS;
190ENDPROC(_cache_lock) 187ENDPROC(_cache_lock)
191 188
192#endif /* BFIN_ICACHE_LOCK */ 189/* Invalidate the Entire Instruction cache by
193 190 * disabling IMC bit
194/* Return the ILOC bits of IMEM_CONTROL
195 */ 191 */
192ENTRY(_invalidate_entire_icache)
193 [--SP] = ( R7:5);
196 194
197ENTRY(_read_iloc) 195 P0.L = LO(IMEM_CONTROL);
198 P1.H = HI(IMEM_CONTROL); 196 P0.H = HI(IMEM_CONTROL);
199 P1.L = LO(IMEM_CONTROL); 197 R7 = [P0];
200 R1 = 0xF; 198
201 R0 = [P1]; 199 /* Clear the IMC bit , All valid bits in the instruction
202 R0 = R0 >> 3; 200 * cache are set to the invalid state
203 R0 = R0 & R1; 201 */
202 BITCLR(R7,IMC_P);
203 CLI R6;
204 SSYNC; /* SSYNC required before invalidating cache. */
205 .align 8;
206 [P0] = R7;
207 SSYNC;
208 STI R6;
209
210 /* Configures the instruction cache agian */
211 R6 = (IMC | ENICPLB);
212 R7 = R7 | R6;
213
214 CLI R6;
215 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
216 .align 8;
217 [P0] = R7;
218 SSYNC;
219 STI R6;
204 220
221 ( R7:5) = [SP++];
205 RTS; 222 RTS;
206ENDPROC(_read_iloc) 223ENDPROC(_invalidate_entire_icache)