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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-09 11:45:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-09 11:45:40 -0400
commit39de65aa2c3eee901db020a4f1396998e09602a3 (patch)
tree0582450ec0b5b6b9778275b431207145d5fedfc8 /arch/blackfin
parent97e18dc007546fce8e99098480b921a02ebb3037 (diff)
parent1fbeab0b8fd5e655ffef8a793b869eb7dffe0337 (diff)
Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: "Here is the pull request from the i2c subsystem. It got a little delayed because I needed to wait for a dependency to be included (commit b424080a9e08: "reset: Add optional resets and stubs"). Plus, I had some email problems. All done now, the highlights are: - drivers can now deprecate their use of i2c classes. That shouldn't be used on embedded platforms anyhow and was often blindly copy&pasted. This mechanism gives users time to switch away and ultimately boot faster once the use of classes for those drivers is gone for good. - new drivers for QUP, Cadence, efm32 - tracepoint support for I2C and SMBus - bigger cleanups for the mv64xxx, nomadik, and designware drivers And the usual bugfixes, cleanups, feature additions. Most stuff has been in linux-next for a while. Just some hot fixes and new drivers were added a bit more recently." * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (63 commits) i2c: cadence: fix Kconfig dependency i2c: Add driver for Cadence I2C controller i2c: cadence: Document device tree bindings Documentation: i2c: improve section about flags mangling the protocol i2c: qup: use proper type fro clk_freq i2c: qup: off by ones in qup_i2c_probe() i2c: efm32: fix binding doc MAINTAINERS: update I2C web resources i2c: qup: New bus driver for the Qualcomm QUP I2C controller i2c: qup: Add device tree bindings information i2c: i2c-xiic: deprecate class based instantiation i2c: i2c-sirf: deprecate class based instantiation i2c: i2c-mv64xxx: deprecate class based instantiation i2c: i2c-designware-platdrv: deprecate class based instantiation i2c: i2c-davinci: deprecate class based instantiation i2c: i2c-bcm2835: deprecate class based instantiation i2c: mv64xxx: Fix reset controller handling i2c: omap: fix usage of IS_ERR_VALUE with pm_runtime_get_sync i2c: efm32: new bus driver i2c: exynos5: remove unnecessary cast of void pointer ...
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h143
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c1
2 files changed, 20 insertions, 124 deletions
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index 90c3c006557d..aaa0834d34aa 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -9,60 +9,7 @@
9#ifndef __ASM_BFIN_TWI_H__ 9#ifndef __ASM_BFIN_TWI_H__
10#define __ASM_BFIN_TWI_H__ 10#define __ASM_BFIN_TWI_H__
11 11
12#include <linux/types.h> 12#include <asm/blackfin.h>
13#include <linux/i2c.h>
14
15/*
16 * All Blackfin system MMRs are padded to 32bits even if the register
17 * itself is only 16bits. So use a helper macro to streamline this.
18 */
19#define __BFP(m) u16 m; u16 __pad_##m
20
21/*
22 * bfin twi registers layout
23 */
24struct bfin_twi_regs {
25 __BFP(clkdiv);
26 __BFP(control);
27 __BFP(slave_ctl);
28 __BFP(slave_stat);
29 __BFP(slave_addr);
30 __BFP(master_ctl);
31 __BFP(master_stat);
32 __BFP(master_addr);
33 __BFP(int_stat);
34 __BFP(int_mask);
35 __BFP(fifo_ctl);
36 __BFP(fifo_stat);
37 u32 __pad[20];
38 __BFP(xmt_data8);
39 __BFP(xmt_data16);
40 __BFP(rcv_data8);
41 __BFP(rcv_data16);
42};
43
44#undef __BFP
45
46struct bfin_twi_iface {
47 int irq;
48 spinlock_t lock;
49 char read_write;
50 u8 command;
51 u8 *transPtr;
52 int readNum;
53 int writeNum;
54 int cur_mode;
55 int manual_stop;
56 int result;
57 struct i2c_adapter adap;
58 struct completion complete;
59 struct i2c_msg *pmsg;
60 int msg_num;
61 int cur_msg;
62 u16 saved_clkdiv;
63 u16 saved_control;
64 struct bfin_twi_regs __iomem *regs_base;
65};
66 13
67#define DEFINE_TWI_REG(reg_name, reg) \ 14#define DEFINE_TWI_REG(reg_name, reg) \
68static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ 15static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
@@ -71,7 +18,6 @@ static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
71 { bfin_write16(&iface->regs_base->reg, v); } 18 { bfin_write16(&iface->regs_base->reg, v); }
72 19
73DEFINE_TWI_REG(CLKDIV, clkdiv) 20DEFINE_TWI_REG(CLKDIV, clkdiv)
74DEFINE_TWI_REG(CONTROL, control)
75DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) 21DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
76DEFINE_TWI_REG(SLAVE_STAT, slave_stat) 22DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
77DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) 23DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
@@ -80,7 +26,6 @@ DEFINE_TWI_REG(MASTER_STAT, master_stat)
80DEFINE_TWI_REG(MASTER_ADDR, master_addr) 26DEFINE_TWI_REG(MASTER_ADDR, master_addr)
81DEFINE_TWI_REG(INT_STAT, int_stat) 27DEFINE_TWI_REG(INT_STAT, int_stat)
82DEFINE_TWI_REG(INT_MASK, int_mask) 28DEFINE_TWI_REG(INT_MASK, int_mask)
83DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
84DEFINE_TWI_REG(FIFO_STAT, fifo_stat) 29DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
85DEFINE_TWI_REG(XMT_DATA8, xmt_data8) 30DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
86DEFINE_TWI_REG(XMT_DATA16, xmt_data16) 31DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
@@ -113,75 +58,25 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
113} 58}
114#endif 59#endif
115 60
61static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
62{
63 return bfin_read16(&iface->regs_base->fifo_ctl);
64}
116 65
117/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ 66static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
118/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 67{
119#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 68 bfin_write16(&iface->regs_base->fifo_ctl, v);
120#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 69 SSYNC();
121 70}
122/* TWI_PRESCALE Masks */
123#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
124#define TWI_ENA 0x0080 /* TWI Enable */
125#define SCCB 0x0200 /* SCCB Compatibility Enable */
126
127/* TWI_SLAVE_CTL Masks */
128#define SEN 0x0001 /* Slave Enable */
129#define SADD_LEN 0x0002 /* Slave Address Length */
130#define STDVAL 0x0004 /* Slave Transmit Data Valid */
131#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
132#define GEN 0x0010 /* General Call Address Matching Enabled */
133
134/* TWI_SLAVE_STAT Masks */
135#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
136#define GCALL 0x0002 /* General Call Indicator */
137
138/* TWI_MASTER_CTL Masks */
139#define MEN 0x0001 /* Master Mode Enable */
140#define MADD_LEN 0x0002 /* Master Address Length */
141#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
142#define FAST 0x0008 /* Use Fast Mode Timing Specs */
143#define STOP 0x0010 /* Issue Stop Condition */
144#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
145#define DCNT 0x3FC0 /* Data Bytes To Transfer */
146#define SDAOVR 0x4000 /* Serial Data Override */
147#define SCLOVR 0x8000 /* Serial Clock Override */
148
149/* TWI_MASTER_STAT Masks */
150#define MPROG 0x0001 /* Master Transfer In Progress */
151#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
152#define ANAK 0x0004 /* Address Not Acknowledged */
153#define DNAK 0x0008 /* Data Not Acknowledged */
154#define BUFRDERR 0x0010 /* Buffer Read Error */
155#define BUFWRERR 0x0020 /* Buffer Write Error */
156#define SDASEN 0x0040 /* Serial Data Sense */
157#define SCLSEN 0x0080 /* Serial Clock Sense */
158#define BUSBUSY 0x0100 /* Bus Busy Indicator */
159
160/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
161#define SINIT 0x0001 /* Slave Transfer Initiated */
162#define SCOMP 0x0002 /* Slave Transfer Complete */
163#define SERR 0x0004 /* Slave Transfer Error */
164#define SOVF 0x0008 /* Slave Overflow */
165#define MCOMP 0x0010 /* Master Transfer Complete */
166#define MERR 0x0020 /* Master Transfer Error */
167#define XMTSERV 0x0040 /* Transmit FIFO Service */
168#define RCVSERV 0x0080 /* Receive FIFO Service */
169
170/* TWI_FIFO_CTRL Masks */
171#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
172#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
173#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
174#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
175
176/* TWI_FIFO_STAT Masks */
177#define XMTSTAT 0x0003 /* Transmit FIFO Status */
178#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
179#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
180#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
181 71
182#define RCVSTAT 0x000C /* Receive FIFO Status */ 72static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
183#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 73{
184#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 74 return bfin_read16(&iface->regs_base->control);
185#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 75}
186 76
77static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
78{
79 SSYNC();
80 bfin_write16(&iface->regs_base->control, v);
81}
187#endif 82#endif
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index 01232a13470d..947ad0832338 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -10,6 +10,7 @@
10#include <linux/fs.h> 10#include <linux/fs.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/i2c/bfin_twi.h>
13 14
14#include <asm/blackfin.h> 15#include <asm/blackfin.h>
15#include <asm/gpio.h> 16#include <asm/gpio.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 21:34:55 -0500