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authorMike Frysinger <vapier@gentoo.org>2011-06-26 23:11:19 -0400
committerMike Frysinger <vapier@gentoo.org>2011-07-23 01:18:29 -0400
commiteed7b8365807549c67613ea7d9a451262050ba3e (patch)
tree784d91e216a393904d5bb74bfcb00a878c159d10 /arch/blackfin
parentd7228e7eb9bd9d65ddb5338fc9574f34ea6d53e1 (diff)
Blackfin: dpmc: optimize hibernate/resume path
The current save logic used in hibernation is to do a MMR load (base + offset) into a register, and then push that onto the stack. Then when restoring, pop off the stack into a register followed by a MMR store (base + offset). These use plenty of 32bit insns rather than 16bit, are pretty long winded, and full of pipeline bubbles. So, by taking advantage of MMRs that are contiguous, the multi-register push/pop insn, and register abuse, we can shrink this code considerably. When saving, the new logic does a lot of loads into the data and pointer registers before executing a single multi-register push insn. Then when restoring, we do a single multi-register pop insn followed by a lot of stores. Overall, this allows us to cut the insn count by ~30%, the code size by ~45%, and drastically reduce the register hazards that trigger bubbles in the pipeline. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/include/asm/dpmc.h1
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S1010
2 files changed, 572 insertions, 439 deletions
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index d1ba87793e9b..c4ec959dad78 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -117,7 +117,6 @@
117#ifndef __ASSEMBLY__ 117#ifndef __ASSEMBLY__
118 118
119void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 119void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
120void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
121void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 120void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
122void do_hibernate(int wakeup); 121void do_hibernate(int wakeup);
123void set_dram_srfs(void); 122void set_dram_srfs(void);
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index d814bf571231..1a1c09287222 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -50,11 +50,21 @@ ENTRY(_sleep_mode)
50 RTS; 50 RTS;
51ENDPROC(_sleep_mode) 51ENDPROC(_sleep_mode)
52 52
53/*
54 * This func never returns as it puts the part into hibernate, and
55 * is only called from do_hibernate, so we don't bother saving or
56 * restoring any of the normal C runtime state. When we wake up,
57 * the entry point will be in do_hibernate and not here.
58 *
59 * We accept just one argument -- the value to write to VR_CTL.
60 */
53ENTRY(_hibernate_mode) 61ENTRY(_hibernate_mode)
54 [--SP] = ( R7:0, P5:0 ); 62 /* Save/setup the regs we need early for minor pipeline optimization */
55 [--SP] = RETS; 63 R4 = R0;
64 P3.H = hi(VR_CTL);
65 P3.L = lo(VR_CTL);
56 66
57 R3 = R0; 67 /* Disable all wakeup sources */
58 R0 = IWR_DISABLE_ALL; 68 R0 = IWR_DISABLE_ALL;
59 R1 = IWR_DISABLE_ALL; 69 R1 = IWR_DISABLE_ALL;
60 R2 = IWR_DISABLE_ALL; 70 R2 = IWR_DISABLE_ALL;
@@ -62,10 +72,8 @@ ENTRY(_hibernate_mode)
62 call _set_dram_srfs; 72 call _set_dram_srfs;
63 SSYNC; 73 SSYNC;
64 74
65 P0.H = hi(VR_CTL); 75 /* Finally, we climb into our cave to hibernate */
66 P0.L = lo(VR_CTL); 76 W[P3] = R4.L;
67
68 W[P0] = R3.L;
69 CLI R2; 77 CLI R2;
70 IDLE; 78 IDLE;
71.Lforever: 79.Lforever:
@@ -268,227 +276,55 @@ ENDPROC(_test_pll_locked)
268 276
269.section .text 277.section .text
270 278
271#define PM_PUSH(x) \ 279#define PM_REG0 R7
272 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\ 280#define PM_REG1 R6
273 [--SP] = R0;\ 281#define PM_REG2 R5
274 282#define PM_REG3 R4
275#define PM_POP(x) \ 283#define PM_REG4 R3
276 R0 = [SP++];\ 284#define PM_REG5 R2
277 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\ 285#define PM_REG6 R1
278 286#define PM_REG7 R0
279#define PM_SYS_PUSH(x) \ 287#define PM_REG8 P5
280 R0 = [P0 + (x - PLL_CTL)];\ 288#define PM_REG9 P4
281 [--SP] = R0;\ 289#define PM_REG10 P3
282 290#define PM_REG11 P2
283#define PM_SYS_POP(x) \ 291#define PM_REG12 P1
284 R0 = [SP++];\ 292#define PM_REG13 P0
285 [P0 + (x - PLL_CTL)] = R0;\ 293
286 294#define PM_REGSET0 R7:7
287#define PM_SYS_PUSH16(x) \ 295#define PM_REGSET1 R7:6
288 R0 = w[P0 + (x - PLL_CTL)];\ 296#define PM_REGSET2 R7:5
289 [--SP] = R0;\ 297#define PM_REGSET3 R7:4
290 298#define PM_REGSET4 R7:3
291#define PM_SYS_POP16(x) \ 299#define PM_REGSET5 R7:2
292 R0 = [SP++];\ 300#define PM_REGSET6 R7:1
293 w[P0 + (x - PLL_CTL)] = R0;\ 301#define PM_REGSET7 R7:0
302#define PM_REGSET8 R7:0, P5:5
303#define PM_REGSET9 R7:0, P5:4
304#define PM_REGSET10 R7:0, P5:3
305#define PM_REGSET11 R7:0, P5:2
306#define PM_REGSET12 R7:0, P5:1
307#define PM_REGSET13 R7:0, P5:0
308
309#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
310#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
311#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
312#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
313#define PM_PUSH(n, x) PM_REG##n = [FP++];
314#define PM_POP(n, x) [FP--] = PM_REG##n;
315#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
316#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
317#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
318#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
319#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
320#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
294 321
295ENTRY(_do_hibernate) 322ENTRY(_do_hibernate)
296 [--SP] = ( R7:0, P5:0 ); 323 /*
297 [--SP] = RETS; 324 * Save the core regs early so we can blow them away when
298 /* Save System MMRs */ 325 * saving/restoring MMR states
299 R2 = R0; 326 */
300 P0.H = hi(PLL_CTL); 327 [--sp] = (R7:0, P5:0);
301 P0.L = lo(PLL_CTL);
302
303#ifdef SIC_IMASK0
304 PM_SYS_PUSH(SIC_IMASK0)
305#endif
306#ifdef SIC_IMASK1
307 PM_SYS_PUSH(SIC_IMASK1)
308#endif
309#ifdef SIC_IMASK2
310 PM_SYS_PUSH(SIC_IMASK2)
311#endif
312#ifdef SIC_IMASK
313 PM_SYS_PUSH(SIC_IMASK)
314#endif
315#ifdef SIC_IAR0
316 PM_SYS_PUSH(SIC_IAR0)
317 PM_SYS_PUSH(SIC_IAR1)
318 PM_SYS_PUSH(SIC_IAR2)
319#endif
320#ifdef SIC_IAR3
321 PM_SYS_PUSH(SIC_IAR3)
322#endif
323#ifdef SIC_IAR4
324 PM_SYS_PUSH(SIC_IAR4)
325 PM_SYS_PUSH(SIC_IAR5)
326 PM_SYS_PUSH(SIC_IAR6)
327#endif
328#ifdef SIC_IAR7
329 PM_SYS_PUSH(SIC_IAR7)
330#endif
331#ifdef SIC_IAR8
332 PM_SYS_PUSH(SIC_IAR8)
333 PM_SYS_PUSH(SIC_IAR9)
334 PM_SYS_PUSH(SIC_IAR10)
335 PM_SYS_PUSH(SIC_IAR11)
336#endif
337
338#ifdef SIC_IWR
339 PM_SYS_PUSH(SIC_IWR)
340#endif
341#ifdef SIC_IWR0
342 PM_SYS_PUSH(SIC_IWR0)
343#endif
344#ifdef SIC_IWR1
345 PM_SYS_PUSH(SIC_IWR1)
346#endif
347#ifdef SIC_IWR2
348 PM_SYS_PUSH(SIC_IWR2)
349#endif
350
351#ifdef PINT0_ASSIGN
352 PM_SYS_PUSH(PINT0_MASK_SET)
353 PM_SYS_PUSH(PINT1_MASK_SET)
354 PM_SYS_PUSH(PINT2_MASK_SET)
355 PM_SYS_PUSH(PINT3_MASK_SET)
356 PM_SYS_PUSH(PINT0_ASSIGN)
357 PM_SYS_PUSH(PINT1_ASSIGN)
358 PM_SYS_PUSH(PINT2_ASSIGN)
359 PM_SYS_PUSH(PINT3_ASSIGN)
360 PM_SYS_PUSH(PINT0_INVERT_SET)
361 PM_SYS_PUSH(PINT1_INVERT_SET)
362 PM_SYS_PUSH(PINT2_INVERT_SET)
363 PM_SYS_PUSH(PINT3_INVERT_SET)
364 PM_SYS_PUSH(PINT0_EDGE_SET)
365 PM_SYS_PUSH(PINT1_EDGE_SET)
366 PM_SYS_PUSH(PINT2_EDGE_SET)
367 PM_SYS_PUSH(PINT3_EDGE_SET)
368#endif
369
370 PM_SYS_PUSH(EBIU_AMBCTL0)
371 PM_SYS_PUSH(EBIU_AMBCTL1)
372 PM_SYS_PUSH16(EBIU_AMGCTL)
373
374#ifdef EBIU_FCTL
375 PM_SYS_PUSH(EBIU_MBSCTL)
376 PM_SYS_PUSH(EBIU_MODE)
377 PM_SYS_PUSH(EBIU_FCTL)
378#endif
379
380#ifdef PORTCIO_FER
381 PM_SYS_PUSH16(PORTCIO_DIR)
382 PM_SYS_PUSH16(PORTCIO_INEN)
383 PM_SYS_PUSH16(PORTCIO)
384 PM_SYS_PUSH16(PORTCIO_FER)
385 PM_SYS_PUSH16(PORTDIO_DIR)
386 PM_SYS_PUSH16(PORTDIO_INEN)
387 PM_SYS_PUSH16(PORTDIO)
388 PM_SYS_PUSH16(PORTDIO_FER)
389 PM_SYS_PUSH16(PORTEIO_DIR)
390 PM_SYS_PUSH16(PORTEIO_INEN)
391 PM_SYS_PUSH16(PORTEIO)
392 PM_SYS_PUSH16(PORTEIO_FER)
393#endif
394
395 PM_SYS_PUSH16(SYSCR)
396
397 /* Save Core MMRs */
398 P0.H = hi(SRAM_BASE_ADDRESS);
399 P0.L = lo(SRAM_BASE_ADDRESS);
400
401 PM_PUSH(DMEM_CONTROL)
402 PM_PUSH(DCPLB_ADDR0)
403 PM_PUSH(DCPLB_ADDR1)
404 PM_PUSH(DCPLB_ADDR2)
405 PM_PUSH(DCPLB_ADDR3)
406 PM_PUSH(DCPLB_ADDR4)
407 PM_PUSH(DCPLB_ADDR5)
408 PM_PUSH(DCPLB_ADDR6)
409 PM_PUSH(DCPLB_ADDR7)
410 PM_PUSH(DCPLB_ADDR8)
411 PM_PUSH(DCPLB_ADDR9)
412 PM_PUSH(DCPLB_ADDR10)
413 PM_PUSH(DCPLB_ADDR11)
414 PM_PUSH(DCPLB_ADDR12)
415 PM_PUSH(DCPLB_ADDR13)
416 PM_PUSH(DCPLB_ADDR14)
417 PM_PUSH(DCPLB_ADDR15)
418 PM_PUSH(DCPLB_DATA0)
419 PM_PUSH(DCPLB_DATA1)
420 PM_PUSH(DCPLB_DATA2)
421 PM_PUSH(DCPLB_DATA3)
422 PM_PUSH(DCPLB_DATA4)
423 PM_PUSH(DCPLB_DATA5)
424 PM_PUSH(DCPLB_DATA6)
425 PM_PUSH(DCPLB_DATA7)
426 PM_PUSH(DCPLB_DATA8)
427 PM_PUSH(DCPLB_DATA9)
428 PM_PUSH(DCPLB_DATA10)
429 PM_PUSH(DCPLB_DATA11)
430 PM_PUSH(DCPLB_DATA12)
431 PM_PUSH(DCPLB_DATA13)
432 PM_PUSH(DCPLB_DATA14)
433 PM_PUSH(DCPLB_DATA15)
434 PM_PUSH(IMEM_CONTROL)
435 PM_PUSH(ICPLB_ADDR0)
436 PM_PUSH(ICPLB_ADDR1)
437 PM_PUSH(ICPLB_ADDR2)
438 PM_PUSH(ICPLB_ADDR3)
439 PM_PUSH(ICPLB_ADDR4)
440 PM_PUSH(ICPLB_ADDR5)
441 PM_PUSH(ICPLB_ADDR6)
442 PM_PUSH(ICPLB_ADDR7)
443 PM_PUSH(ICPLB_ADDR8)
444 PM_PUSH(ICPLB_ADDR9)
445 PM_PUSH(ICPLB_ADDR10)
446 PM_PUSH(ICPLB_ADDR11)
447 PM_PUSH(ICPLB_ADDR12)
448 PM_PUSH(ICPLB_ADDR13)
449 PM_PUSH(ICPLB_ADDR14)
450 PM_PUSH(ICPLB_ADDR15)
451 PM_PUSH(ICPLB_DATA0)
452 PM_PUSH(ICPLB_DATA1)
453 PM_PUSH(ICPLB_DATA2)
454 PM_PUSH(ICPLB_DATA3)
455 PM_PUSH(ICPLB_DATA4)
456 PM_PUSH(ICPLB_DATA5)
457 PM_PUSH(ICPLB_DATA6)
458 PM_PUSH(ICPLB_DATA7)
459 PM_PUSH(ICPLB_DATA8)
460 PM_PUSH(ICPLB_DATA9)
461 PM_PUSH(ICPLB_DATA10)
462 PM_PUSH(ICPLB_DATA11)
463 PM_PUSH(ICPLB_DATA12)
464 PM_PUSH(ICPLB_DATA13)
465 PM_PUSH(ICPLB_DATA14)
466 PM_PUSH(ICPLB_DATA15)
467 PM_PUSH(EVT2)
468 PM_PUSH(EVT3)
469 PM_PUSH(EVT5)
470 PM_PUSH(EVT6)
471 PM_PUSH(EVT7)
472 PM_PUSH(EVT8)
473 PM_PUSH(EVT9)
474 PM_PUSH(EVT10)
475 PM_PUSH(EVT11)
476 PM_PUSH(EVT12)
477 PM_PUSH(EVT13)
478 PM_PUSH(EVT14)
479 PM_PUSH(EVT15)
480 PM_PUSH(IMASK)
481 PM_PUSH(ILAT)
482 PM_PUSH(IPRIO)
483 PM_PUSH(TCNTL)
484 PM_PUSH(TPERIOD)
485 PM_PUSH(TSCALE)
486 PM_PUSH(TCOUNT)
487 PM_PUSH(TBUFCTL)
488
489 /* Save Core Registers */
490 [--sp] = SYSCFG;
491 [--sp] = ( R7:0, P5:0 );
492 [--sp] = fp; 328 [--sp] = fp;
493 [--sp] = usp; 329 [--sp] = usp;
494 330
@@ -523,43 +359,532 @@ ENTRY(_do_hibernate)
523 [--sp] = LB0; 359 [--sp] = LB0;
524 [--sp] = LB1; 360 [--sp] = LB1;
525 361
362 /* We can't push RETI directly as that'll change IPEND[4] */
363 r7 = RETI;
364 [--sp] = RETS;
526 [--sp] = ASTAT; 365 [--sp] = ASTAT;
527 [--sp] = CYCLES; 366 [--sp] = CYCLES;
528 [--sp] = CYCLES2; 367 [--sp] = CYCLES2;
529 368 [--sp] = SYSCFG;
530 [--sp] = RETS;
531 r0 = RETI;
532 [--sp] = r0;
533 [--sp] = RETX; 369 [--sp] = RETX;
534 [--sp] = SEQSTAT; 370 [--sp] = SEQSTAT;
371 [--sp] = r7;
372
373 /* Save first func arg in M3 */
374 M3 = R0;
375
376 /* Save system MMRs */
377 FP.H = hi(SYSMMR_BASE);
378 FP.L = lo(SYSMMR_BASE);
379
380#ifdef SIC_IMASK0
381 PM_SYS_PUSH(0, SIC_IMASK0)
382 PM_SYS_PUSH(1, SIC_IMASK1)
383# ifdef SIC_IMASK2
384 PM_SYS_PUSH(2, SIC_IMASK2)
385# endif
386#else
387 PM_SYS_PUSH(0, SIC_IMASK)
388#endif
389#ifdef SIC_IAR0
390 PM_SYS_PUSH(3, SIC_IAR0)
391 PM_SYS_PUSH(4, SIC_IAR1)
392 PM_SYS_PUSH(5, SIC_IAR2)
393#endif
394#ifdef SIC_IAR3
395 PM_SYS_PUSH(6, SIC_IAR3)
396#endif
397#ifdef SIC_IAR4
398 PM_SYS_PUSH(7, SIC_IAR4)
399 PM_SYS_PUSH(8, SIC_IAR5)
400 PM_SYS_PUSH(9, SIC_IAR6)
401#endif
402#ifdef SIC_IAR7
403 PM_SYS_PUSH(10, SIC_IAR7)
404#endif
405#ifdef SIC_IAR8
406 PM_SYS_PUSH(11, SIC_IAR8)
407 PM_SYS_PUSH(12, SIC_IAR9)
408 PM_SYS_PUSH(13, SIC_IAR10)
409#endif
410 PM_PUSH_SYNC(13)
411#ifdef SIC_IAR11
412 PM_SYS_PUSH(0, SIC_IAR11)
413#endif
414
415#ifdef SIC_IWR
416 PM_SYS_PUSH(1, SIC_IWR)
417#endif
418#ifdef SIC_IWR0
419 PM_SYS_PUSH(1, SIC_IWR0)
420#endif
421#ifdef SIC_IWR1
422 PM_SYS_PUSH(2, SIC_IWR1)
423#endif
424#ifdef SIC_IWR2
425 PM_SYS_PUSH(3, SIC_IWR2)
426#endif
427
428#ifdef PINT0_ASSIGN
429 PM_SYS_PUSH(4, PINT0_MASK_SET)
430 PM_SYS_PUSH(5, PINT1_MASK_SET)
431 PM_SYS_PUSH(6, PINT2_MASK_SET)
432 PM_SYS_PUSH(7, PINT3_MASK_SET)
433 PM_SYS_PUSH(8, PINT0_ASSIGN)
434 PM_SYS_PUSH(9, PINT1_ASSIGN)
435 PM_SYS_PUSH(10, PINT2_ASSIGN)
436 PM_SYS_PUSH(11, PINT3_ASSIGN)
437 PM_SYS_PUSH(12, PINT0_INVERT_SET)
438 PM_SYS_PUSH(13, PINT1_INVERT_SET)
439 PM_PUSH_SYNC(13)
440 PM_SYS_PUSH(0, PINT2_INVERT_SET)
441 PM_SYS_PUSH(1, PINT3_INVERT_SET)
442 PM_SYS_PUSH(2, PINT0_EDGE_SET)
443 PM_SYS_PUSH(3, PINT1_EDGE_SET)
444 PM_SYS_PUSH(4, PINT2_EDGE_SET)
445 PM_SYS_PUSH(5, PINT3_EDGE_SET)
446#endif
447
448 PM_SYS_PUSH16(6, SYSCR)
449
450 PM_SYS_PUSH16(7, EBIU_AMGCTL)
451 PM_SYS_PUSH(8, EBIU_AMBCTL0)
452 PM_SYS_PUSH(9, EBIU_AMBCTL1)
453#ifdef EBIU_FCTL
454 PM_SYS_PUSH(10, EBIU_MBSCTL)
455 PM_SYS_PUSH(11, EBIU_MODE)
456 PM_SYS_PUSH(12, EBIU_FCTL)
457 PM_PUSH_SYNC(12)
458#else
459 PM_PUSH_SYNC(9)
460#endif
461
462#ifdef PORTCIO_FER
463 /* 16bit loads can only be done with dregs */
464 PM_SYS_PUSH16(0, PORTCIO_DIR)
465 PM_SYS_PUSH16(1, PORTCIO_INEN)
466 PM_SYS_PUSH16(2, PORTCIO)
467 PM_SYS_PUSH16(3, PORTCIO_FER)
468 PM_SYS_PUSH16(4, PORTDIO_DIR)
469 PM_SYS_PUSH16(5, PORTDIO_INEN)
470 PM_SYS_PUSH16(6, PORTDIO)
471 PM_SYS_PUSH16(7, PORTDIO_FER)
472 PM_PUSH_SYNC(7)
473 PM_SYS_PUSH16(0, PORTEIO_DIR)
474 PM_SYS_PUSH16(1, PORTEIO_INEN)
475 PM_SYS_PUSH16(2, PORTEIO)
476 PM_SYS_PUSH16(3, PORTEIO_FER)
477 PM_PUSH_SYNC(3)
478#endif
479
480 /* Save Core MMRs */
481 I0.H = hi(COREMMR_BASE);
482 I0.L = lo(COREMMR_BASE);
483 I1 = I0;
484 I2 = I0;
485 I3 = I0;
486 B0 = I0;
487 B1 = I0;
488 B2 = I0;
489 B3 = I0;
490 I1.L = lo(DCPLB_ADDR0);
491 I2.L = lo(DCPLB_DATA0);
492 I3.L = lo(ICPLB_ADDR0);
493 B0.L = lo(ICPLB_DATA0);
494 B1.L = lo(EVT2);
495 B2.L = lo(IMASK);
496 B3.L = lo(TCNTL);
497
498 /* DCPLB Addr */
499 FP = I1;
500 PM_PUSH(0, DCPLB_ADDR0)
501 PM_PUSH(1, DCPLB_ADDR1)
502 PM_PUSH(2, DCPLB_ADDR2)
503 PM_PUSH(3, DCPLB_ADDR3)
504 PM_PUSH(4, DCPLB_ADDR4)
505 PM_PUSH(5, DCPLB_ADDR5)
506 PM_PUSH(6, DCPLB_ADDR6)
507 PM_PUSH(7, DCPLB_ADDR7)
508 PM_PUSH(8, DCPLB_ADDR8)
509 PM_PUSH(9, DCPLB_ADDR9)
510 PM_PUSH(10, DCPLB_ADDR10)
511 PM_PUSH(11, DCPLB_ADDR11)
512 PM_PUSH(12, DCPLB_ADDR12)
513 PM_PUSH(13, DCPLB_ADDR13)
514 PM_PUSH_SYNC(13)
515 PM_PUSH(0, DCPLB_ADDR14)
516 PM_PUSH(1, DCPLB_ADDR15)
517
518 /* DCPLB Data */
519 FP = I2;
520 PM_PUSH(2, DCPLB_DATA0)
521 PM_PUSH(3, DCPLB_DATA1)
522 PM_PUSH(4, DCPLB_DATA2)
523 PM_PUSH(5, DCPLB_DATA3)
524 PM_PUSH(6, DCPLB_DATA4)
525 PM_PUSH(7, DCPLB_DATA5)
526 PM_PUSH(8, DCPLB_DATA6)
527 PM_PUSH(9, DCPLB_DATA7)
528 PM_PUSH(10, DCPLB_DATA8)
529 PM_PUSH(11, DCPLB_DATA9)
530 PM_PUSH(12, DCPLB_DATA10)
531 PM_PUSH(13, DCPLB_DATA11)
532 PM_PUSH_SYNC(13)
533 PM_PUSH(0, DCPLB_DATA12)
534 PM_PUSH(1, DCPLB_DATA13)
535 PM_PUSH(2, DCPLB_DATA14)
536 PM_PUSH(3, DCPLB_DATA15)
537
538 /* ICPLB Addr */
539 FP = I3;
540 PM_PUSH(4, ICPLB_ADDR0)
541 PM_PUSH(5, ICPLB_ADDR1)
542 PM_PUSH(6, ICPLB_ADDR2)
543 PM_PUSH(7, ICPLB_ADDR3)
544 PM_PUSH(8, ICPLB_ADDR4)
545 PM_PUSH(9, ICPLB_ADDR5)
546 PM_PUSH(10, ICPLB_ADDR6)
547 PM_PUSH(11, ICPLB_ADDR7)
548 PM_PUSH(12, ICPLB_ADDR8)
549 PM_PUSH(13, ICPLB_ADDR9)
550 PM_PUSH_SYNC(13)
551 PM_PUSH(0, ICPLB_ADDR10)
552 PM_PUSH(1, ICPLB_ADDR11)
553 PM_PUSH(2, ICPLB_ADDR12)
554 PM_PUSH(3, ICPLB_ADDR13)
555 PM_PUSH(4, ICPLB_ADDR14)
556 PM_PUSH(5, ICPLB_ADDR15)
557
558 /* ICPLB Data */
559 FP = B0;
560 PM_PUSH(6, ICPLB_DATA0)
561 PM_PUSH(7, ICPLB_DATA1)
562 PM_PUSH(8, ICPLB_DATA2)
563 PM_PUSH(9, ICPLB_DATA3)
564 PM_PUSH(10, ICPLB_DATA4)
565 PM_PUSH(11, ICPLB_DATA5)
566 PM_PUSH(12, ICPLB_DATA6)
567 PM_PUSH(13, ICPLB_DATA7)
568 PM_PUSH_SYNC(13)
569 PM_PUSH(0, ICPLB_DATA8)
570 PM_PUSH(1, ICPLB_DATA9)
571 PM_PUSH(2, ICPLB_DATA10)
572 PM_PUSH(3, ICPLB_DATA11)
573 PM_PUSH(4, ICPLB_DATA12)
574 PM_PUSH(5, ICPLB_DATA13)
575 PM_PUSH(6, ICPLB_DATA14)
576 PM_PUSH(7, ICPLB_DATA15)
577
578 /* Event Vectors */
579 FP = B1;
580 PM_PUSH(8, EVT2)
581 PM_PUSH(9, EVT3)
582 FP += 4; /* EVT4 */
583 PM_PUSH(10, EVT5)
584 PM_PUSH(11, EVT6)
585 PM_PUSH(12, EVT7)
586 PM_PUSH(13, EVT8)
587 PM_PUSH_SYNC(13)
588 PM_PUSH(0, EVT9)
589 PM_PUSH(1, EVT10)
590 PM_PUSH(2, EVT11)
591 PM_PUSH(3, EVT12)
592 PM_PUSH(4, EVT13)
593 PM_PUSH(5, EVT14)
594 PM_PUSH(6, EVT15)
595
596 /* CEC */
597 FP = B2;
598 PM_PUSH(7, IMASK)
599 FP += 4; /* IPEND */
600 PM_PUSH(8, ILAT)
601 PM_PUSH(9, IPRIO)
602
603 /* Core Timer */
604 FP = B3;
605 PM_PUSH(10, TCNTL)
606 PM_PUSH(11, TPERIOD)
607 PM_PUSH(12, TSCALE)
608 PM_PUSH(13, TCOUNT)
609 PM_PUSH_SYNC(13)
610
611 /* Misc non-contiguous registers */
612 FP = I0;
613 PM_CORE_PUSH(0, DMEM_CONTROL);
614 PM_CORE_PUSH(1, IMEM_CONTROL);
615 PM_CORE_PUSH(2, TBUFCTL);
616 PM_PUSH_SYNC(2)
617
618 /* Setup args to hibernate mode early for pipeline optimization */
619 R0 = M3;
620 P1.H = _hibernate_mode;
621 P1.L = _hibernate_mode;
535 622
536 /* Save Magic, return address and Stack Pointer */ 623 /* Save Magic, return address and Stack Pointer */
537 P0.H = 0; 624 P0 = 0;
538 P0.L = 0; 625 R1.H = 0xDEAD; /* Hibernate Magic */
539 R0.H = 0xDEAD; /* Hibernate Magic */ 626 R1.L = 0xBEEF;
540 R0.L = 0xBEEF; 627 R2.H = .Lpm_resume_here;
541 [P0++] = R0; /* Store Hibernate Magic */ 628 R2.L = .Lpm_resume_here;
542 R0.H = .Lpm_resume_here; 629 [P0++] = R1; /* Store Hibernate Magic */
543 R0.L = .Lpm_resume_here; 630 [P0++] = R2; /* Save Return Address */
544 [P0++] = R0; /* Save Return Address */
545 [P0++] = SP; /* Save Stack Pointer */ 631 [P0++] = SP; /* Save Stack Pointer */
546 P0.H = _hibernate_mode; 632
547 P0.L = _hibernate_mode; 633 /* Must use an indirect call as we need to jump to L1 */
548 R0 = R2; 634 call (P1); /* Goodbye */
549 call (P0); /* Goodbye */
550 635
551.Lpm_resume_here: 636.Lpm_resume_here:
552 637
638 /* Restore Core MMRs */
639 I0.H = hi(COREMMR_BASE);
640 I0.L = lo(COREMMR_BASE);
641 I1 = I0;
642 I2 = I0;
643 I3 = I0;
644 B0 = I0;
645 B1 = I0;
646 B2 = I0;
647 B3 = I0;
648 I1.L = lo(DCPLB_ADDR15);
649 I2.L = lo(DCPLB_DATA15);
650 I3.L = lo(ICPLB_ADDR15);
651 B0.L = lo(ICPLB_DATA15);
652 B1.L = lo(EVT15);
653 B2.L = lo(IPRIO);
654 B3.L = lo(TCOUNT);
655
656 /* Misc non-contiguous registers */
657 FP = I0;
658 PM_POP_SYNC(2)
659 PM_CORE_POP(2, TBUFCTL)
660 PM_CORE_POP(1, IMEM_CONTROL)
661 PM_CORE_POP(0, DMEM_CONTROL)
662
663 /* Core Timer */
664 PM_POP_SYNC(13)
665 FP = B3;
666 PM_POP(13, TCOUNT)
667 PM_POP(12, TSCALE)
668 PM_POP(11, TPERIOD)
669 PM_POP(10, TCNTL)
670
671 /* CEC */
672 FP = B2;
673 PM_POP(9, IPRIO)
674 PM_POP(8, ILAT)
675 FP += -4; /* IPEND */
676 PM_POP(7, IMASK)
677
678 /* Event Vectors */
679 FP = B1;
680 PM_POP(6, EVT15)
681 PM_POP(5, EVT14)
682 PM_POP(4, EVT13)
683 PM_POP(3, EVT12)
684 PM_POP(2, EVT11)
685 PM_POP(1, EVT10)
686 PM_POP(0, EVT9)
687 PM_POP_SYNC(13)
688 PM_POP(13, EVT8)
689 PM_POP(12, EVT7)
690 PM_POP(11, EVT6)
691 PM_POP(10, EVT5)
692 FP += -4; /* EVT4 */
693 PM_POP(9, EVT3)
694 PM_POP(8, EVT2)
695
696 /* ICPLB Data */
697 FP = B0;
698 PM_POP(7, ICPLB_DATA15)
699 PM_POP(6, ICPLB_DATA14)
700 PM_POP(5, ICPLB_DATA13)
701 PM_POP(4, ICPLB_DATA12)
702 PM_POP(3, ICPLB_DATA11)
703 PM_POP(2, ICPLB_DATA10)
704 PM_POP(1, ICPLB_DATA9)
705 PM_POP(0, ICPLB_DATA8)
706 PM_POP_SYNC(13)
707 PM_POP(13, ICPLB_DATA7)
708 PM_POP(12, ICPLB_DATA6)
709 PM_POP(11, ICPLB_DATA5)
710 PM_POP(10, ICPLB_DATA4)
711 PM_POP(9, ICPLB_DATA3)
712 PM_POP(8, ICPLB_DATA2)
713 PM_POP(7, ICPLB_DATA1)
714 PM_POP(6, ICPLB_DATA0)
715
716 /* ICPLB Addr */
717 FP = I3;
718 PM_POP(5, ICPLB_ADDR15)
719 PM_POP(4, ICPLB_ADDR14)
720 PM_POP(3, ICPLB_ADDR13)
721 PM_POP(2, ICPLB_ADDR12)
722 PM_POP(1, ICPLB_ADDR11)
723 PM_POP(0, ICPLB_ADDR10)
724 PM_POP_SYNC(13)
725 PM_POP(13, ICPLB_ADDR9)
726 PM_POP(12, ICPLB_ADDR8)
727 PM_POP(11, ICPLB_ADDR7)
728 PM_POP(10, ICPLB_ADDR6)
729 PM_POP(9, ICPLB_ADDR5)
730 PM_POP(8, ICPLB_ADDR4)
731 PM_POP(7, ICPLB_ADDR3)
732 PM_POP(6, ICPLB_ADDR2)
733 PM_POP(5, ICPLB_ADDR1)
734 PM_POP(4, ICPLB_ADDR0)
735
736 /* DCPLB Data */
737 FP = I2;
738 PM_POP(3, DCPLB_DATA15)
739 PM_POP(2, DCPLB_DATA14)
740 PM_POP(1, DCPLB_DATA13)
741 PM_POP(0, DCPLB_DATA12)
742 PM_POP_SYNC(13)
743 PM_POP(13, DCPLB_DATA11)
744 PM_POP(12, DCPLB_DATA10)
745 PM_POP(11, DCPLB_DATA9)
746 PM_POP(10, DCPLB_DATA8)
747 PM_POP(9, DCPLB_DATA7)
748 PM_POP(8, DCPLB_DATA6)
749 PM_POP(7, DCPLB_DATA5)
750 PM_POP(6, DCPLB_DATA4)
751 PM_POP(5, DCPLB_DATA3)
752 PM_POP(4, DCPLB_DATA2)
753 PM_POP(3, DCPLB_DATA1)
754 PM_POP(2, DCPLB_DATA0)
755
756 /* DCPLB Addr */
757 FP = I1;
758 PM_POP(1, DCPLB_ADDR15)
759 PM_POP(0, DCPLB_ADDR14)
760 PM_POP_SYNC(13)
761 PM_POP(13, DCPLB_ADDR13)
762 PM_POP(12, DCPLB_ADDR12)
763 PM_POP(11, DCPLB_ADDR11)
764 PM_POP(10, DCPLB_ADDR10)
765 PM_POP(9, DCPLB_ADDR9)
766 PM_POP(8, DCPLB_ADDR8)
767 PM_POP(7, DCPLB_ADDR7)
768 PM_POP(6, DCPLB_ADDR6)
769 PM_POP(5, DCPLB_ADDR5)
770 PM_POP(4, DCPLB_ADDR4)
771 PM_POP(3, DCPLB_ADDR3)
772 PM_POP(2, DCPLB_ADDR2)
773 PM_POP(1, DCPLB_ADDR1)
774 PM_POP(0, DCPLB_ADDR0)
775
776 /* Restore System MMRs */
777 FP.H = hi(SYSMMR_BASE);
778 FP.L = lo(SYSMMR_BASE);
779
780#ifdef PORTCIO_FER
781 PM_POP_SYNC(3)
782 PM_SYS_POP16(3, PORTEIO_FER)
783 PM_SYS_POP16(2, PORTEIO)
784 PM_SYS_POP16(1, PORTEIO_INEN)
785 PM_SYS_POP16(0, PORTEIO_DIR)
786 PM_POP_SYNC(7)
787 PM_SYS_POP16(7, PORTDIO_FER)
788 PM_SYS_POP16(6, PORTDIO)
789 PM_SYS_POP16(5, PORTDIO_INEN)
790 PM_SYS_POP16(4, PORTDIO_DIR)
791 PM_SYS_POP16(3, PORTCIO_FER)
792 PM_SYS_POP16(2, PORTCIO)
793 PM_SYS_POP16(1, PORTCIO_INEN)
794 PM_SYS_POP16(0, PORTCIO_DIR)
795#endif
796
797#ifdef EBIU_FCTL
798 PM_POP_SYNC(12)
799 PM_SYS_POP(12, EBIU_FCTL)
800 PM_SYS_POP(11, EBIU_MODE)
801 PM_SYS_POP(10, EBIU_MBSCTL)
802#else
803 PM_POP_SYNC(9)
804#endif
805 PM_SYS_POP(9, EBIU_AMBCTL1)
806 PM_SYS_POP(8, EBIU_AMBCTL0)
807 PM_SYS_POP16(7, EBIU_AMGCTL)
808
809 PM_SYS_POP16(6, SYSCR)
810
811#ifdef PINT0_ASSIGN
812 PM_SYS_POP(5, PINT3_EDGE_SET)
813 PM_SYS_POP(4, PINT2_EDGE_SET)
814 PM_SYS_POP(3, PINT1_EDGE_SET)
815 PM_SYS_POP(2, PINT0_EDGE_SET)
816 PM_SYS_POP(1, PINT3_INVERT_SET)
817 PM_SYS_POP(0, PINT2_INVERT_SET)
818 PM_POP_SYNC(13)
819 PM_SYS_POP(13, PINT1_INVERT_SET)
820 PM_SYS_POP(12, PINT0_INVERT_SET)
821 PM_SYS_POP(11, PINT3_ASSIGN)
822 PM_SYS_POP(10, PINT2_ASSIGN)
823 PM_SYS_POP(9, PINT1_ASSIGN)
824 PM_SYS_POP(8, PINT0_ASSIGN)
825 PM_SYS_POP(7, PINT3_MASK_SET)
826 PM_SYS_POP(6, PINT2_MASK_SET)
827 PM_SYS_POP(5, PINT1_MASK_SET)
828 PM_SYS_POP(4, PINT0_MASK_SET)
829#endif
830
831#ifdef SIC_IWR2
832 PM_SYS_POP(3, SIC_IWR2)
833#endif
834#ifdef SIC_IWR1
835 PM_SYS_POP(2, SIC_IWR1)
836#endif
837#ifdef SIC_IWR0
838 PM_SYS_POP(1, SIC_IWR0)
839#endif
840#ifdef SIC_IWR
841 PM_SYS_POP(1, SIC_IWR)
842#endif
843
844#ifdef SIC_IAR11
845 PM_SYS_POP(0, SIC_IAR11)
846#endif
847 PM_POP_SYNC(13)
848#ifdef SIC_IAR8
849 PM_SYS_POP(13, SIC_IAR10)
850 PM_SYS_POP(12, SIC_IAR9)
851 PM_SYS_POP(11, SIC_IAR8)
852#endif
853#ifdef SIC_IAR7
854 PM_SYS_POP(10, SIC_IAR7)
855#endif
856#ifdef SIC_IAR6
857 PM_SYS_POP(9, SIC_IAR6)
858 PM_SYS_POP(8, SIC_IAR5)
859 PM_SYS_POP(7, SIC_IAR4)
860#endif
861#ifdef SIC_IAR3
862 PM_SYS_POP(6, SIC_IAR3)
863#endif
864#ifdef SIC_IAR0
865 PM_SYS_POP(5, SIC_IAR2)
866 PM_SYS_POP(4, SIC_IAR1)
867 PM_SYS_POP(3, SIC_IAR0)
868#endif
869#ifdef SIC_IMASK0
870# ifdef SIC_IMASK2
871 PM_SYS_POP(2, SIC_IMASK2)
872# endif
873 PM_SYS_POP(1, SIC_IMASK1)
874 PM_SYS_POP(0, SIC_IMASK0)
875#else
876 PM_SYS_POP(0, SIC_IMASK)
877#endif
878
553 /* Restore Core Registers */ 879 /* Restore Core Registers */
880 RETI = [sp++];
554 SEQSTAT = [sp++]; 881 SEQSTAT = [sp++];
555 RETX = [sp++]; 882 RETX = [sp++];
556 r0 = [sp++]; 883 SYSCFG = [sp++];
557 RETI = r0;
558 RETS = [sp++];
559
560 CYCLES2 = [sp++]; 884 CYCLES2 = [sp++];
561 CYCLES = [sp++]; 885 CYCLES = [sp++];
562 ASTAT = [sp++]; 886 ASTAT = [sp++];
887 RETS = [sp++];
563 888
564 LB1 = [sp++]; 889 LB1 = [sp++];
565 LB0 = [sp++]; 890 LB0 = [sp++];
@@ -594,201 +919,10 @@ ENTRY(_do_hibernate)
594 919
595 usp = [sp++]; 920 usp = [sp++];
596 fp = [sp++]; 921 fp = [sp++];
597 922 (R7:0, P5:0) = [sp++];
598 ( R7 : 0, P5 : 0) = [ SP ++ ];
599 SYSCFG = [sp++];
600
601 /* Restore Core MMRs */
602
603 PM_POP(TBUFCTL)
604 PM_POP(TCOUNT)
605 PM_POP(TSCALE)
606 PM_POP(TPERIOD)
607 PM_POP(TCNTL)
608 PM_POP(IPRIO)
609 PM_POP(ILAT)
610 PM_POP(IMASK)
611 PM_POP(EVT15)
612 PM_POP(EVT14)
613 PM_POP(EVT13)
614 PM_POP(EVT12)
615 PM_POP(EVT11)
616 PM_POP(EVT10)
617 PM_POP(EVT9)
618 PM_POP(EVT8)
619 PM_POP(EVT7)
620 PM_POP(EVT6)
621 PM_POP(EVT5)
622 PM_POP(EVT3)
623 PM_POP(EVT2)
624 PM_POP(ICPLB_DATA15)
625 PM_POP(ICPLB_DATA14)
626 PM_POP(ICPLB_DATA13)
627 PM_POP(ICPLB_DATA12)
628 PM_POP(ICPLB_DATA11)
629 PM_POP(ICPLB_DATA10)
630 PM_POP(ICPLB_DATA9)
631 PM_POP(ICPLB_DATA8)
632 PM_POP(ICPLB_DATA7)
633 PM_POP(ICPLB_DATA6)
634 PM_POP(ICPLB_DATA5)
635 PM_POP(ICPLB_DATA4)
636 PM_POP(ICPLB_DATA3)
637 PM_POP(ICPLB_DATA2)
638 PM_POP(ICPLB_DATA1)
639 PM_POP(ICPLB_DATA0)
640 PM_POP(ICPLB_ADDR15)
641 PM_POP(ICPLB_ADDR14)
642 PM_POP(ICPLB_ADDR13)
643 PM_POP(ICPLB_ADDR12)
644 PM_POP(ICPLB_ADDR11)
645 PM_POP(ICPLB_ADDR10)
646 PM_POP(ICPLB_ADDR9)
647 PM_POP(ICPLB_ADDR8)
648 PM_POP(ICPLB_ADDR7)
649 PM_POP(ICPLB_ADDR6)
650 PM_POP(ICPLB_ADDR5)
651 PM_POP(ICPLB_ADDR4)
652 PM_POP(ICPLB_ADDR3)
653 PM_POP(ICPLB_ADDR2)
654 PM_POP(ICPLB_ADDR1)
655 PM_POP(ICPLB_ADDR0)
656 PM_POP(IMEM_CONTROL)
657 PM_POP(DCPLB_DATA15)
658 PM_POP(DCPLB_DATA14)
659 PM_POP(DCPLB_DATA13)
660 PM_POP(DCPLB_DATA12)
661 PM_POP(DCPLB_DATA11)
662 PM_POP(DCPLB_DATA10)
663 PM_POP(DCPLB_DATA9)
664 PM_POP(DCPLB_DATA8)
665 PM_POP(DCPLB_DATA7)
666 PM_POP(DCPLB_DATA6)
667 PM_POP(DCPLB_DATA5)
668 PM_POP(DCPLB_DATA4)
669 PM_POP(DCPLB_DATA3)
670 PM_POP(DCPLB_DATA2)
671 PM_POP(DCPLB_DATA1)
672 PM_POP(DCPLB_DATA0)
673 PM_POP(DCPLB_ADDR15)
674 PM_POP(DCPLB_ADDR14)
675 PM_POP(DCPLB_ADDR13)
676 PM_POP(DCPLB_ADDR12)
677 PM_POP(DCPLB_ADDR11)
678 PM_POP(DCPLB_ADDR10)
679 PM_POP(DCPLB_ADDR9)
680 PM_POP(DCPLB_ADDR8)
681 PM_POP(DCPLB_ADDR7)
682 PM_POP(DCPLB_ADDR6)
683 PM_POP(DCPLB_ADDR5)
684 PM_POP(DCPLB_ADDR4)
685 PM_POP(DCPLB_ADDR3)
686 PM_POP(DCPLB_ADDR2)
687 PM_POP(DCPLB_ADDR1)
688 PM_POP(DCPLB_ADDR0)
689 PM_POP(DMEM_CONTROL)
690
691 /* Restore System MMRs */
692
693 P0.H = hi(PLL_CTL);
694 P0.L = lo(PLL_CTL);
695 PM_SYS_POP16(SYSCR)
696
697#ifdef PORTCIO_FER
698 PM_SYS_POP16(PORTEIO_FER)
699 PM_SYS_POP16(PORTEIO)
700 PM_SYS_POP16(PORTEIO_INEN)
701 PM_SYS_POP16(PORTEIO_DIR)
702 PM_SYS_POP16(PORTDIO_FER)
703 PM_SYS_POP16(PORTDIO)
704 PM_SYS_POP16(PORTDIO_INEN)
705 PM_SYS_POP16(PORTDIO_DIR)
706 PM_SYS_POP16(PORTCIO_FER)
707 PM_SYS_POP16(PORTCIO)
708 PM_SYS_POP16(PORTCIO_INEN)
709 PM_SYS_POP16(PORTCIO_DIR)
710#endif
711
712#ifdef EBIU_FCTL
713 PM_SYS_POP(EBIU_FCTL)
714 PM_SYS_POP(EBIU_MODE)
715 PM_SYS_POP(EBIU_MBSCTL)
716#endif
717 PM_SYS_POP16(EBIU_AMGCTL)
718 PM_SYS_POP(EBIU_AMBCTL1)
719 PM_SYS_POP(EBIU_AMBCTL0)
720
721#ifdef PINT0_ASSIGN
722 PM_SYS_POP(PINT3_EDGE_SET)
723 PM_SYS_POP(PINT2_EDGE_SET)
724 PM_SYS_POP(PINT1_EDGE_SET)
725 PM_SYS_POP(PINT0_EDGE_SET)
726 PM_SYS_POP(PINT3_INVERT_SET)
727 PM_SYS_POP(PINT2_INVERT_SET)
728 PM_SYS_POP(PINT1_INVERT_SET)
729 PM_SYS_POP(PINT0_INVERT_SET)
730 PM_SYS_POP(PINT3_ASSIGN)
731 PM_SYS_POP(PINT2_ASSIGN)
732 PM_SYS_POP(PINT1_ASSIGN)
733 PM_SYS_POP(PINT0_ASSIGN)
734 PM_SYS_POP(PINT3_MASK_SET)
735 PM_SYS_POP(PINT2_MASK_SET)
736 PM_SYS_POP(PINT1_MASK_SET)
737 PM_SYS_POP(PINT0_MASK_SET)
738#endif
739
740#ifdef SIC_IWR2
741 PM_SYS_POP(SIC_IWR2)
742#endif
743#ifdef SIC_IWR1
744 PM_SYS_POP(SIC_IWR1)
745#endif
746#ifdef SIC_IWR0
747 PM_SYS_POP(SIC_IWR0)
748#endif
749#ifdef SIC_IWR
750 PM_SYS_POP(SIC_IWR)
751#endif
752
753#ifdef SIC_IAR8
754 PM_SYS_POP(SIC_IAR11)
755 PM_SYS_POP(SIC_IAR10)
756 PM_SYS_POP(SIC_IAR9)
757 PM_SYS_POP(SIC_IAR8)
758#endif
759#ifdef SIC_IAR7
760 PM_SYS_POP(SIC_IAR7)
761#endif
762#ifdef SIC_IAR6
763 PM_SYS_POP(SIC_IAR6)
764 PM_SYS_POP(SIC_IAR5)
765 PM_SYS_POP(SIC_IAR4)
766#endif
767#ifdef SIC_IAR3
768 PM_SYS_POP(SIC_IAR3)
769#endif
770#ifdef SIC_IAR0
771 PM_SYS_POP(SIC_IAR2)
772 PM_SYS_POP(SIC_IAR1)
773 PM_SYS_POP(SIC_IAR0)
774#endif
775#ifdef SIC_IMASK
776 PM_SYS_POP(SIC_IMASK)
777#endif
778#ifdef SIC_IMASK2
779 PM_SYS_POP(SIC_IMASK2)
780#endif
781#ifdef SIC_IMASK1
782 PM_SYS_POP(SIC_IMASK1)
783#endif
784#ifdef SIC_IMASK0
785 PM_SYS_POP(SIC_IMASK0)
786#endif
787 923
788 [--sp] = RETI; /* Clear Global Interrupt Disable */ 924 [--sp] = RETI; /* Clear Global Interrupt Disable */
789 SP += 4; 925 SP += 4;
790 926
791 RETS = [SP++];
792 ( R7:0, P5:0 ) = [SP++];
793 RTS; 927 RTS;
794ENDPROC(_do_hibernate) 928ENDPROC(_do_hibernate)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 16:33:34 -0500