Blackfin arch: issue reset via SWRST so we dont clobber the watchdog state

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
author: Mike Frysinger <michael.frysinger@analog.com> 2007-05-21 06:09:26 -0400
committer: Linus Torvalds <torvalds@woody.linux-foundation.org> 2007-05-21 12:50:22 -0400
commit: ef9256d2831df0896566c3823cd2bdf0e55df984 (patch)
tree: 5a04be14dfc6c213f5ed27e7f7bfd71476ad61d1 /arch/blackfin
parent: c0fc525dcc407a516132fc11af82375319ebdadb (diff)
3 files changed, 48 insertions, 160 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7cb8258841d4..1a54ff5f061d 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -481,66 +481,30 @@ ENTRY(_bfin_reset)
        [p0] = r0;
        SSYNC;
-        /* Disable the WDOG TIMER */
+        /* make sure SYSCR is set to use BMODE */
-        p0.h = hi(WDOG_CTL);
+        P0.h = hi(SYSCR);
-        p0.l = lo(WDOG_CTL);
+        P0.l = lo(SYSCR);
-        r0.l = 0xAD6;
+        R0.l = 0x0;
-        w[p0] = r0.l;
+        W[P0] = R0.l;
-        SSYNC;
-        /* Clear the sticky bit incase it is already set */
-        p0.h = hi(WDOG_CTL);
-        p0.l = lo(WDOG_CTL);
-        r0.l = 0x8AD6;
-        w[p0] = r0.l;
        SSYNC;
-        /* Program the count value */
+        /* issue a system soft reset */
-        R0.l = 0x100;
+        P1.h = hi(SWRST);
-        R0.h = 0x0;
+        P1.l = lo(SWRST);
-        P0.h = hi(WDOG_CNT);
+        R1.l = 0x0007;
-        P0.l = lo(WDOG_CNT);
+        W[P1] = R1;
-        [P0] = R0;
        SSYNC;
-        /* Program WDOG_STAT if necessary */
+        /* clear system soft reset */
-        P0.h = hi(WDOG_CTL);
+        R0.l = 0x0000;
-        P0.l = lo(WDOG_CTL);
+        W[P0] = R0;
-        R0 = W[P0](Z);
-        CC = BITTST(R0,1);
-        if !CC JUMP .LWRITESTAT;
-        CC = BITTST(R0,2);
-        if !CC JUMP .LWRITESTAT;
-        JUMP .LSKIP_WRITE;
-.LWRITESTAT:
-        /* When watch dog timer is enabled, a write to STAT will load the contents of CNT to STAT */
-        R0 = 0x0000(z);
-        P0.h = hi(WDOG_STAT);
-        P0.l = lo(WDOG_STAT)
-        [P0] = R0;
-        SSYNC;
-.LSKIP_WRITE:
-        /* Enable the reset event */
-        P0.h = hi(WDOG_CTL);
-        P0.l = lo(WDOG_CTL);
-        R0 = W[P0](Z);
-        BITCLR(R0,1);
-        BITCLR(R0,2);
-        W[P0] = R0.L;
-        SSYNC;
-        NOP;
-        /* Enable the wdog counter */
-        R0 = W[P0](Z);
-        BITCLR(R0,4);
-        W[P0] = R0.L;
        SSYNC;
-        IDLE;
+        /* issue core reset */
+        raise 1;
        RTS;
+ENDPROC(_bfin_reset)
 #if CONFIG_DEBUG_KERNEL_START
 debug_kernel_start_trap:
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index de78e4281aef..aafc686749ed 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -517,68 +517,30 @@ _delay_lab1_end:
        [p0] = r0;
        SSYNC;
-        /* Disable the WDOG TIMER */
+        /* make sure SYSCR is set to use BMODE */
-        p0.h = hi(WDOG_CTL);
+        P0.h = hi(SYSCR);
-        p0.l = lo(WDOG_CTL);
+        P0.l = lo(SYSCR);
-        r0.l = 0xAD6;
+        R0.l = 0x0;
-        w[p0] = r0.l;
+        W[P0] = R0.l;
        SSYNC;
-        /* Clear the sticky bit incase it is already set */
+        /* issue a system soft reset */
-        p0.h = hi(WDOG_CTL);
+        P1.h = hi(SWRST);
-        p0.l = lo(WDOG_CTL);
+        P1.l = lo(SWRST);
-        r0.l = 0x8AD6;
+        R1.l = 0x0007;
-        w[p0] = r0.l;
+        W[P1] = R1;
        SSYNC;
-        /* Program the count value */
+        /* clear system soft reset */
-        R0.l = 0x100;
+        R0.l = 0x0000;
-        R0.h = 0x0;
+        W[P0] = R0;
-        P0.h = hi(WDOG_CNT);
-        P0.l = lo(WDOG_CNT);
-        [P0] = R0;
-        SSYNC;
-        /* Program WDOG_STAT if necessary */
-        P0.h = hi(WDOG_CTL);
-        P0.l = lo(WDOG_CTL);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,1);
-        if !CC JUMP .LWRITESTAT;
-        CC = BITTST(R0,2);
-        if !CC JUMP .LWRITESTAT;
-        JUMP .LSKIP_WRITE;
-.LWRITESTAT:
-        /* When watch dog timer is enabled,
-         * a write to STAT will load the contents of CNT to STAT
-         */
-        R0 = 0x0000(z);
-        P0.h = hi(WDOG_STAT);
-        P0.l = lo(WDOG_STAT)
-        [P0] = R0;
-        SSYNC;
-.LSKIP_WRITE:
-        /* Enable the reset event */
-        P0.h = hi(WDOG_CTL);
-        P0.l = lo(WDOG_CTL);
-        R0 = W[P0](Z);
-        BITCLR(R0,1);
-        BITCLR(R0,2);
-        W[P0] = R0.L;
-        SSYNC;
-        NOP;
-        /* Enable the wdog counter */
-        R0 = W[P0](Z);
-        BITCLR(R0,4);
-        W[P0] = R0.L;
        SSYNC;
-        IDLE;
+        /* issue core reset */
+        raise 1;
        RTS;
+ENDPROC(_bfin_reset)
 .data
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 462c39ed8ec5..04f3ac33ab0e 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -427,68 +427,30 @@ ENTRY(_bfin_reset)
        [p0] = r0;
        SSYNC;
-        /* Disable the WDOG TIMER */
+        /* make sure SYSCR is set to use BMODE */
-        p0.h = hi(WDOGA_CTL);
+        P0.h = hi(SICA_SYSCR);
-        p0.l = lo(WDOGA_CTL);
+        P0.l = lo(SICA_SYSCR);
-        r0.l = 0xAD6;
+        R0.l = 0x0;
-        w[p0] = r0.l;
+        W[P0] = R0.l;
        SSYNC;
-        /* Clear the sticky bit incase it is already set */
+        /* issue a system soft reset */
-        p0.h = hi(WDOGA_CTL);
+        P1.h = hi(SICA_SWRST);
-        p0.l = lo(WDOGA_CTL);
+        P1.l = lo(SICA_SWRST);
-        r0.l = 0x8AD6;
+        R1.l = 0x0007;
-        w[p0] = r0.l;
+        W[P1] = R1;
-        SSYNC;
-        /* Program the count value */
-        R0.l = 0x100;
-        R0.h = 0x0;
-        P0.h = hi(WDOGA_CNT);
-        P0.l = lo(WDOGA_CNT);
-        [P0] = R0;
        SSYNC;
-        /* Program WDOG_STAT if necessary */
+        /* clear system soft reset */
-        P0.h = hi(WDOGA_CTL);
+        R0.l = 0x0000;
-        P0.l = lo(WDOGA_CTL);
+        W[P0] = R0;
-        R0 = W[P0](Z);
-        CC = BITTST(R0,1);
-        if !CC JUMP .LWRITESTAT;
-        CC = BITTST(R0,2);
-        if !CC JUMP .LWRITESTAT;
-        JUMP .LSKIP_WRITE;
-.LWRITESTAT:
-        /* When watch dog timer is enabled,
-         * a write to STAT will load the contents of CNT to STAT
-         */
-        R0 = 0x0000(z);
-        P0.h = hi(WDOGA_STAT);
-        P0.l = lo(WDOGA_STAT)
-        [P0] = R0;
-        SSYNC;
-.LSKIP_WRITE:
-        /* Enable the reset event */
-        P0.h = hi(WDOGA_CTL);
-        P0.l = lo(WDOGA_CTL);
-        R0 = W[P0](Z);
-        BITCLR(R0,1);
-        BITCLR(R0,2);
-        W[P0] = R0.L;
-        SSYNC;
-        NOP;
-        /* Enable the wdog counter */
-        R0 = W[P0](Z);
-        BITCLR(R0,4);
-        W[P0] = R0.L;
        SSYNC;
-        IDLE;
+        /* issue core reset */
+        raise 1;
        RTS;
+ENDPROC(_bfin_reset)
 .data
author	Mike Frysinger <michael.frysinger@analog.com>	2007-05-21 06:09:26 -0400
committer	Linus Torvalds <torvalds@woody.linux-foundation.org>	2007-05-21 12:50:22 -0400
commit	ef9256d2831df0896566c3823cd2bdf0e55df984 (patch)
tree	5a04be14dfc6c213f5ed27e7f7bfd71476ad61d1 /arch/blackfin
parent	c0fc525dcc407a516132fc11af82375319ebdadb (diff)

diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 7cb8258841d4..1a54ff5f061d 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S
@@ -481,66 +481,30 @@ ENTRY(_bfin_reset)
481	[p0] = r0;	481	[p0] = r0;
482	SSYNC;	482	SSYNC;
483		483
484	/* Disable the WDOG TIMER */	484	/* make sure SYSCR is set to use BMODE */
485	p0.h = hi(WDOG_CTL);	485	P0.h = hi(SYSCR);
486	p0.l = lo(WDOG_CTL);	486	P0.l = lo(SYSCR);
487	r0.l = 0xAD6;	487	R0.l = 0x0;
488	w[p0] = r0.l;	488	W[P0] = R0.l;
489	SSYNC;
490
491	/* Clear the sticky bit incase it is already set */
492	p0.h = hi(WDOG_CTL);
493	p0.l = lo(WDOG_CTL);
494	r0.l = 0x8AD6;
495	w[p0] = r0.l;
496	SSYNC;	489	SSYNC;
497		490
498	/* Program the count value */	491	/* issue a system soft reset */
499	R0.l = 0x100;	492	P1.h = hi(SWRST);
500	R0.h = 0x0;	493	P1.l = lo(SWRST);
501	P0.h = hi(WDOG_CNT);	494	R1.l = 0x0007;
502	P0.l = lo(WDOG_CNT);	495	W[P1] = R1;
503	[P0] = R0;
504	SSYNC;	496	SSYNC;
505		497
506	/* Program WDOG_STAT if necessary */	498	/* clear system soft reset */
507	P0.h = hi(WDOG_CTL);	499	R0.l = 0x0000;
508	P0.l = lo(WDOG_CTL);	500	W[P0] = R0;
509	R0 = W[P0](Z);
510	CC = BITTST(R0,1);
511	if !CC JUMP .LWRITESTAT;
512	CC = BITTST(R0,2);
513	if !CC JUMP .LWRITESTAT;
514	JUMP .LSKIP_WRITE;
515
516	.LWRITESTAT:
517	/* When watch dog timer is enabled, a write to STAT will load the contents of CNT to STAT */
518	R0 = 0x0000(z);
519	P0.h = hi(WDOG_STAT);
520	P0.l = lo(WDOG_STAT)
521	[P0] = R0;
522	SSYNC;
523
524	.LSKIP_WRITE:
525	/* Enable the reset event */
526	P0.h = hi(WDOG_CTL);
527	P0.l = lo(WDOG_CTL);
528	R0 = W[P0](Z);
529	BITCLR(R0,1);
530	BITCLR(R0,2);
531	W[P0] = R0.L;
532	SSYNC;
533	NOP;
534
535	/* Enable the wdog counter */
536	R0 = W[P0](Z);
537	BITCLR(R0,4);
538	W[P0] = R0.L;
539	SSYNC;	501	SSYNC;
540		502
541	IDLE;	503	/* issue core reset */
		504	raise 1;
542		505
543	RTS;	506	RTS;
		507	ENDPROC(_bfin_reset)
544		508
545	#if CONFIG_DEBUG_KERNEL_START	509	#if CONFIG_DEBUG_KERNEL_START
546	debug_kernel_start_trap:	510	debug_kernel_start_trap:


diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index de78e4281aef..aafc686749ed 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S
@@ -517,68 +517,30 @@ _delay_lab1_end:
517	[p0] = r0;	517	[p0] = r0;
518	SSYNC;	518	SSYNC;
519		519
520	/* Disable the WDOG TIMER */	520	/* make sure SYSCR is set to use BMODE */
521	p0.h = hi(WDOG_CTL);	521	P0.h = hi(SYSCR);
522	p0.l = lo(WDOG_CTL);	522	P0.l = lo(SYSCR);
523	r0.l = 0xAD6;	523	R0.l = 0x0;
524	w[p0] = r0.l;	524	W[P0] = R0.l;
525	SSYNC;	525	SSYNC;
526		526
527	/* Clear the sticky bit incase it is already set */	527	/* issue a system soft reset */
528	p0.h = hi(WDOG_CTL);	528	P1.h = hi(SWRST);
529	p0.l = lo(WDOG_CTL);	529	P1.l = lo(SWRST);
530	r0.l = 0x8AD6;	530	R1.l = 0x0007;
531	w[p0] = r0.l;	531	W[P1] = R1;
532	SSYNC;	532	SSYNC;
533		533
534	/* Program the count value */	534	/* clear system soft reset */
535	R0.l = 0x100;	535	R0.l = 0x0000;
536	R0.h = 0x0;	536	W[P0] = R0;
537	P0.h = hi(WDOG_CNT);
538	P0.l = lo(WDOG_CNT);
539	[P0] = R0;
540	SSYNC;
541
542	/* Program WDOG_STAT if necessary */
543	P0.h = hi(WDOG_CTL);
544	P0.l = lo(WDOG_CTL);
545	R0 = W[P0](Z);
546	CC = BITTST(R0,1);
547	if !CC JUMP .LWRITESTAT;
548	CC = BITTST(R0,2);
549	if !CC JUMP .LWRITESTAT;
550	JUMP .LSKIP_WRITE;
551
552	.LWRITESTAT:
553	/* When watch dog timer is enabled,
554	* a write to STAT will load the contents of CNT to STAT
555	*/
556	R0 = 0x0000(z);
557	P0.h = hi(WDOG_STAT);
558	P0.l = lo(WDOG_STAT)
559	[P0] = R0;
560	SSYNC;
561
562	.LSKIP_WRITE:
563	/* Enable the reset event */
564	P0.h = hi(WDOG_CTL);
565	P0.l = lo(WDOG_CTL);
566	R0 = W[P0](Z);
567	BITCLR(R0,1);
568	BITCLR(R0,2);
569	W[P0] = R0.L;
570	SSYNC;
571	NOP;
572
573	/* Enable the wdog counter */
574	R0 = W[P0](Z);
575	BITCLR(R0,4);
576	W[P0] = R0.L;
577	SSYNC;	537	SSYNC;
578		538
579	IDLE;	539	/* issue core reset */
		540	raise 1;
580		541
581	RTS;	542	RTS;
		543	ENDPROC(_bfin_reset)
582		544
583	.data	545	.data
584		546


diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 462c39ed8ec5..04f3ac33ab0e 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S
@@ -427,68 +427,30 @@ ENTRY(_bfin_reset)
427	[p0] = r0;	427	[p0] = r0;
428	SSYNC;	428	SSYNC;
429		429
430	/* Disable the WDOG TIMER */	430	/* make sure SYSCR is set to use BMODE */
431	p0.h = hi(WDOGA_CTL);	431	P0.h = hi(SICA_SYSCR);
432	p0.l = lo(WDOGA_CTL);	432	P0.l = lo(SICA_SYSCR);
433	r0.l = 0xAD6;	433	R0.l = 0x0;
434	w[p0] = r0.l;	434	W[P0] = R0.l;
435	SSYNC;	435	SSYNC;
436		436
437	/* Clear the sticky bit incase it is already set */	437	/* issue a system soft reset */
438	p0.h = hi(WDOGA_CTL);	438	P1.h = hi(SICA_SWRST);
439	p0.l = lo(WDOGA_CTL);	439	P1.l = lo(SICA_SWRST);
440	r0.l = 0x8AD6;	440	R1.l = 0x0007;
441	w[p0] = r0.l;	441	W[P1] = R1;
442	SSYNC;
443
444	/* Program the count value */
445	R0.l = 0x100;
446	R0.h = 0x0;
447	P0.h = hi(WDOGA_CNT);
448	P0.l = lo(WDOGA_CNT);
449	[P0] = R0;
450	SSYNC;	442	SSYNC;
451		443
452	/* Program WDOG_STAT if necessary */	444	/* clear system soft reset */
453	P0.h = hi(WDOGA_CTL);	445	R0.l = 0x0000;
454	P0.l = lo(WDOGA_CTL);	446	W[P0] = R0;
455	R0 = W[P0](Z);
456	CC = BITTST(R0,1);
457	if !CC JUMP .LWRITESTAT;
458	CC = BITTST(R0,2);
459	if !CC JUMP .LWRITESTAT;
460	JUMP .LSKIP_WRITE;
461
462	.LWRITESTAT:
463	/* When watch dog timer is enabled,
464	* a write to STAT will load the contents of CNT to STAT
465	*/
466	R0 = 0x0000(z);
467	P0.h = hi(WDOGA_STAT);
468	P0.l = lo(WDOGA_STAT)
469	[P0] = R0;
470	SSYNC;
471
472	.LSKIP_WRITE:
473	/* Enable the reset event */
474	P0.h = hi(WDOGA_CTL);
475	P0.l = lo(WDOGA_CTL);
476	R0 = W[P0](Z);
477	BITCLR(R0,1);
478	BITCLR(R0,2);
479	W[P0] = R0.L;
480	SSYNC;
481	NOP;
482
483	/* Enable the wdog counter */
484	R0 = W[P0](Z);
485	BITCLR(R0,4);
486	W[P0] = R0.L;
487	SSYNC;	447	SSYNC;
488		448
489	IDLE;	449	/* issue core reset */
		450	raise 1;
490		451
491	RTS;	452	RTS;
		453	ENDPROC(_bfin_reset)
492		454
493	.data	455	.data
494		456