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authorBarry Song <barry.song@analog.com>2009-12-01 21:50:43 -0500
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:15:54 -0500
commite187837b6f23c99c219ffc1d42aa18567f6e299d (patch)
treeebf6dad4112689aca936221027115328fdf4456d /arch/blackfin
parentd45e8db1b20c510a189d769d877af2e8e9df985f (diff)
Blackfin: MPU: support XIP in async flash memory
The NOMPU code already supported executing in the async banks, so this brings the MPU code in line. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 69e0e530d70f..930c01c06813 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu)
113 addr = L2_START; 113 addr = L2_START;
114 d_data = L2_DMEMORY; 114 d_data = L2_DMEMORY;
115 } else if (addr >= physical_mem_end) { 115 } else if (addr >= physical_mem_end) {
116 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE 116 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
117 && (status & FAULT_USERSUPV)) { 117 addr &= ~(4 * 1024 * 1024 - 1);
118 addr &= ~0x3fffff;
119 d_data &= ~PAGE_SIZE_4KB; 118 d_data &= ~PAGE_SIZE_4KB;
120 d_data |= PAGE_SIZE_4MB; 119 d_data |= PAGE_SIZE_4MB;
120 d_data |= CPLB_USER_RD | CPLB_USER_WR;
121 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH 121 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
122 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { 122 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
123 addr &= ~(1 * 1024 * 1024 - 1); 123 addr &= ~(1 * 1024 * 1024 - 1);
@@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu)
203 addr = L2_START; 203 addr = L2_START;
204 i_data = L2_IMEMORY; 204 i_data = L2_IMEMORY;
205 } else if (addr >= physical_mem_end) { 205 } else if (addr >= physical_mem_end) {
206 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH 206 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
207 addr &= ~(4 * 1024 * 1024 - 1);
208 i_data &= ~PAGE_SIZE_4KB;
209 i_data |= PAGE_SIZE_4MB;
210 i_data |= CPLB_USER_RD;
211 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
207 && (status & FAULT_USERSUPV)) { 212 && (status & FAULT_USERSUPV)) {
208 addr &= ~(1 * 1024 * 1024 - 1); 213 addr &= ~(1 * 1024 * 1024 - 1);
209 i_data &= ~PAGE_SIZE_4KB; 214 i_data &= ~PAGE_SIZE_4KB;