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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-23 00:12:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-23 00:12:27 -0400
commit7f3883962870dd28b5f2322ac44a9d03640ef448 (patch)
tree01f7dd2ac2b7c61e5e6726c4fec4484aaca6e7b7 /arch/blackfin
parent10f2a2b0f68abf39c06cf519cbc1740fa50f900b (diff)
parentb9ac41e314f0b43641bc01bd553fd2e0458ed832 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (47 commits) Blackfin: bfin_spi.h: add MMR peripheral layout Blackfin: bfin_ppi.h: start a common PPI/EPPI header Blackfin: bfin_can.h: add missing VERSION/VERSION2 MMRs Blackfin: bf538: add missing SIC_RVECT define Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx Blackfin: bf54x: add missing SIC_RVECT definition Blackfin: H8606: move 8250 irqflags to platform resources Blackfin: glue XIP/ROM kernel kconfigs Blackfin: update sparse flags for latest upstream changes Blackfin: coreb: update ioctl numbers Blackfin: coreb: add gpl module license Blackfin: bf518-ezkit: add ssm2603 codec resources Blackfin: bf51x/bf52x: fix 16/32bit SPORT MMR helpers Blackfin: tll6527m: new board port Blackfin: bf526-ezbrd/bf527-ezkit: add NAND partition for u-boot Blackfin: merge kernel init memory back into main memory region Blackfin: gpio: add peripheral group check Blackfin: dma: bf54x: add missing break for SPORT1 TX IRQ Blackfin: add new cacheflush syscall Blackfin: bf548-ezkit: increase u-boot partition size ...
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/Kconfig12
-rw-r--r--arch/blackfin/Makefile3
-rw-r--r--arch/blackfin/configs/BF527-AD7160-EVAL_defconfig105
-rw-r--r--arch/blackfin/configs/BF527-TLL6527M_defconfig180
-rw-r--r--arch/blackfin/include/asm/Kbuild1
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h19
-rw-r--r--arch/blackfin/include/asm/bfin_can.h9
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h51
-rw-r--r--arch/blackfin/include/asm/cachectl.h20
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h9
-rw-r--r--arch/blackfin/include/asm/ptrace.h3
-rw-r--r--arch/blackfin/include/asm/serial.h1
-rw-r--r--arch/blackfin/include/asm/unistd.h3
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c185
-rw-r--r--arch/blackfin/kernel/process.c5
-rw-r--r--arch/blackfin/kernel/ptrace.c12
-rw-r--r--arch/blackfin/kernel/sys_bfin.c15
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c21
-rw-r--r--arch/blackfin/mach-bf518/boards/tcm-bf518.c2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h32
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h45
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig10
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile2
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c870
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c12
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c6
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c23
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c986
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h32
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h45
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c10
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c4
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c10
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c12
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c2
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c19
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h70
-rw-r--r--arch/blackfin/mach-bf537/Kconfig4
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c10
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c10
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c597
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c10
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h44
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c4
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h73
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c47
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c31
-rw-r--r--arch/blackfin/mach-bf548/dma.c1
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h51
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c2
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c10
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c68
-rw-r--r--arch/blackfin/mach-bf561/coreb.c11
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h33
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h76
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h94
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf561/smp.c24
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S50
-rw-r--r--arch/blackfin/mach-common/entry.S113
-rw-r--r--arch/blackfin/mach-common/interrupt.S17
-rw-r--r--arch/blackfin/mach-common/ints-priority.c11
-rw-r--r--arch/blackfin/mm/init.c3
65 files changed, 3431 insertions, 839 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 5a3152b75cdb..d9a1cb7ec30a 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -300,7 +300,7 @@ config BF_REV_0_1
300 300
301config BF_REV_0_2 301config BF_REV_0_2
302 bool "0.2" 302 bool "0.2"
303 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 303 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
304 304
305config BF_REV_0_3 305config BF_REV_0_3
306 bool "0.3" 306 bool "0.3"
@@ -356,7 +356,7 @@ config MEM_MT48LC8M32B2B5_7
356 356
357config MEM_MT48LC32M16A2TG_75 357config MEM_MT48LC32M16A2TG_75
358 bool 358 bool
359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) 359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
360 default y 360 default y
361 361
362config MEM_MT48H32M16LFCJ_75 362config MEM_MT48H32M16LFCJ_75
@@ -426,6 +426,7 @@ config CLKIN_HZ
426 default "25000000" # most people use this 426 default "25000000" # most people use this
427 default "27000000" if BFIN533_EZKIT 427 default "27000000" if BFIN533_EZKIT
428 default "30000000" if BFIN561_EZKIT 428 default "30000000" if BFIN561_EZKIT
429 default "24000000" if BFIN527_AD7160EVAL
429 help 430 help
430 The frequency of CLKIN crystal oscillator on the board in Hz. 431 The frequency of CLKIN crystal oscillator on the board in Hz.
431 Warning: This value should match the crystal on the board. Otherwise, 432 Warning: This value should match the crystal on the board. Otherwise,
@@ -463,6 +464,7 @@ config VCO_MULT
463 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 464 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
464 default "20" if BFIN561_EZKIT 465 default "20" if BFIN561_EZKIT
465 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 466 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
467 default "25" if BFIN527_AD7160EVAL
466 help 468 help
467 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 469 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
468 PLL Frequency = (Crystal Frequency) * (this setting) 470 PLL Frequency = (Crystal Frequency) * (this setting)
@@ -926,6 +928,12 @@ config ROMKERNEL
926 928
927endchoice 929endchoice
928 930
931# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
932config XIP_KERNEL
933 bool
934 default y
935 depends on ROMKERNEL
936
929source "mm/Kconfig" 937source "mm/Kconfig"
930 938
931config BFIN_GPTIMERS 939config BFIN_GPTIMERS
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 3e65b0ffe084..46738d49b7c8 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -101,9 +101,8 @@ KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
101KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) 101KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
102 102
103# - we utilize the silicon rev from the toolchain, so move it over to the checkflags 103# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
104# - the l1_text attribute is Blackfin specific, so fake it out as used to kill warnings
105CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') 104CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
106CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__ 105CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
107 106
108head-y := arch/$(ARCH)/kernel/init_task.o 107head-y := arch/$(ARCH)/kernel/init_task.o
109 108
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
new file mode 100644
index 000000000000..08c55f6b8b7a
--- /dev/null
+++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
@@ -0,0 +1,105 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y
9# CONFIG_ELF_CORE is not set
10# CONFIG_AIO is not set
11CONFIG_SLAB=y
12CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set
16CONFIG_PREEMPT=y
17CONFIG_BF527=y
18CONFIG_BF_REV_0_2=y
19CONFIG_IRQ_TWI=7
20CONFIG_IRQ_PORTH_INTA=7
21CONFIG_IRQ_PORTH_INTB=7
22CONFIG_BFIN527_AD7160EVAL=y
23CONFIG_BF527_SPORT0_PORTF=y
24CONFIG_BF527_UART1_PORTG=y
25CONFIG_IRQ_USB_INT0=11
26CONFIG_IRQ_USB_INT1=11
27CONFIG_IRQ_USB_INT2=11
28CONFIG_IRQ_USB_DMA=11
29CONFIG_CMDLINE_BOOL=y
30CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
31CONFIG_CLKIN_HZ=24000000
32CONFIG_HZ_300=y
33# CONFIG_CYCLES_CLOCKSOURCE is not set
34CONFIG_IP_CHECKSUM_L1=y
35CONFIG_SYSCALL_TAB_L1=y
36CONFIG_CPLB_SWITCH_TAB_L1=y
37CONFIG_BFIN_GPTIMERS=y
38CONFIG_C_CDPRIO=y
39CONFIG_BANK_1=0x5554
40CONFIG_BANK_3=0xFFC0
41CONFIG_BINFMT_FLAT=y
42CONFIG_BINFMT_ZFLAT=y
43CONFIG_NET=y
44CONFIG_UNIX=y
45# CONFIG_WIRELESS is not set
46CONFIG_BLK_DEV_LOOP=y
47CONFIG_BLK_DEV_RAM=y
48# CONFIG_MISC_DEVICES is not set
49# CONFIG_INPUT_MOUSEDEV is not set
50CONFIG_INPUT_EVDEV=y
51# CONFIG_INPUT_KEYBOARD is not set
52# CONFIG_INPUT_MOUSE is not set
53CONFIG_INPUT_TOUCHSCREEN=y
54CONFIG_TOUCHSCREEN_AD7160=y
55CONFIG_TOUCHSCREEN_AD7160_FW=y
56# CONFIG_SERIO is not set
57# CONFIG_BFIN_DMA_INTERFACE is not set
58# CONFIG_DEVKMEM is not set
59CONFIG_SERIAL_BFIN=y
60CONFIG_SERIAL_BFIN_CONSOLE=y
61CONFIG_SERIAL_BFIN_UART0=y
62# CONFIG_LEGACY_PTYS is not set
63# CONFIG_BFIN_OTP is not set
64# CONFIG_HW_RANDOM is not set
65CONFIG_I2C=y
66# CONFIG_I2C_HELPER_AUTO is not set
67CONFIG_I2C_ALGOBIT=y
68CONFIG_I2C_BLACKFIN_TWI=y
69CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
70CONFIG_SPI=y
71CONFIG_SPI_BFIN=y
72CONFIG_GPIOLIB=y
73CONFIG_GPIO_SYSFS=y
74# CONFIG_HWMON is not set
75CONFIG_FB=y
76CONFIG_FRAMEBUFFER_CONSOLE=y
77CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
78CONFIG_LOGO=y
79# CONFIG_LOGO_LINUX_MONO is not set
80# CONFIG_LOGO_LINUX_VGA16 is not set
81# CONFIG_LOGO_LINUX_CLUT224 is not set
82# CONFIG_LOGO_BLACKFIN_VGA16 is not set
83# CONFIG_HID_SUPPORT is not set
84CONFIG_USB_MUSB_HDRC=y
85CONFIG_USB_GADGET_MUSB_HDRC=y
86CONFIG_USB_GADGET=y
87CONFIG_USB_GADGET_VBUS_DRAW=500
88CONFIG_USB_G_SERIAL=y
89CONFIG_MMC=y
90CONFIG_MMC_SPI=y
91CONFIG_EXT2_FS=y
92# CONFIG_DNOTIFY is not set
93CONFIG_MSDOS_FS=y
94CONFIG_VFAT_FS=y
95CONFIG_NLS_CODEPAGE_437=y
96CONFIG_NLS_ISO8859_1=y
97CONFIG_DEBUG_KERNEL=y
98CONFIG_DETECT_HUNG_TASK=y
99# CONFIG_SCHED_DEBUG is not set
100# CONFIG_DEBUG_BUGVERBOSE is not set
101# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
102CONFIG_EARLY_PRINTK=y
103CONFIG_CPLB_INFO=y
104CONFIG_SECURITY=y
105CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig
new file mode 100644
index 000000000000..92ded5edc86c
--- /dev/null
+++ b/arch/blackfin/configs/BF527-TLL6527M_defconfig
@@ -0,0 +1,180 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="DEV_0-1_pre2010"
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_BLK_DEV_INITRD=y
8# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
9CONFIG_EMBEDDED=y
10# CONFIG_SYSCTL_SYSCALL is not set
11# CONFIG_ELF_CORE is not set
12# CONFIG_FUTEX is not set
13# CONFIG_SIGNALFD is not set
14# CONFIG_TIMERFD is not set
15# CONFIG_EVENTFD is not set
16# CONFIG_AIO is not set
17CONFIG_SLAB=y
18CONFIG_MMAP_ALLOW_UNINITIALIZED=y
19CONFIG_MODULES=y
20CONFIG_MODULE_UNLOAD=y
21# CONFIG_LBDAF is not set
22# CONFIG_BLK_DEV_BSG is not set
23# CONFIG_IOSCHED_DEADLINE is not set
24CONFIG_PREEMPT_VOLUNTARY=y
25CONFIG_BF527=y
26CONFIG_BF_REV_0_2=y
27CONFIG_BFIN527_TLL6527M=y
28CONFIG_BF527_UART1_PORTG=y
29CONFIG_IRQ_USB_INT0=11
30CONFIG_IRQ_USB_INT1=11
31CONFIG_IRQ_USB_INT2=11
32CONFIG_IRQ_USB_DMA=11
33CONFIG_BOOT_LOAD=0x400000
34# CONFIG_CYCLES_CLOCKSOURCE is not set
35# CONFIG_SCHEDULE_L1 is not set
36# CONFIG_MEMSET_L1 is not set
37# CONFIG_MEMCPY_L1 is not set
38# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
39CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
40CONFIG_BFIN_GPTIMERS=y
41CONFIG_DMA_UNCACHED_2M=y
42CONFIG_C_CDPRIO=y
43CONFIG_BANK_0=0xFFC2
44CONFIG_BANK_1=0xFFC2
45CONFIG_BANK_2=0xFFC2
46CONFIG_BANK_3=0xFFC2
47CONFIG_BINFMT_FLAT=y
48CONFIG_BINFMT_ZFLAT=y
49CONFIG_NET=y
50CONFIG_PACKET=y
51CONFIG_UNIX=y
52CONFIG_INET=y
53CONFIG_IP_PNP=y
54# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
55# CONFIG_INET_XFRM_MODE_TUNNEL is not set
56# CONFIG_INET_XFRM_MODE_BEET is not set
57# CONFIG_INET_LRO is not set
58# CONFIG_INET_DIAG is not set
59# CONFIG_IPV6 is not set
60CONFIG_IRDA=m
61CONFIG_IRLAN=m
62CONFIG_IRCOMM=m
63CONFIG_IRTTY_SIR=m
64CONFIG_BFIN_SIR=m
65CONFIG_BFIN_SIR0=y
66# CONFIG_WIRELESS is not set
67CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
68# CONFIG_FW_LOADER is not set
69CONFIG_MTD=y
70CONFIG_MTD_CHAR=y
71CONFIG_MTD_BLOCK=y
72CONFIG_MTD_CFI=y
73CONFIG_MTD_CFI_INTELEXT=y
74CONFIG_MTD_RAM=y
75CONFIG_MTD_ROM=y
76CONFIG_MTD_COMPLEX_MAPPINGS=y
77CONFIG_MTD_GPIO_ADDR=y
78CONFIG_BLK_DEV_RAM=y
79CONFIG_SCSI=y
80# CONFIG_SCSI_PROC_FS is not set
81CONFIG_BLK_DEV_SD=y
82CONFIG_BLK_DEV_SR=m
83# CONFIG_SCSI_LOWLEVEL is not set
84CONFIG_NETDEVICES=y
85CONFIG_NET_ETHERNET=y
86CONFIG_BFIN_MAC=y
87# CONFIG_NETDEV_1000 is not set
88# CONFIG_NETDEV_10000 is not set
89# CONFIG_WLAN is not set
90# CONFIG_INPUT_MOUSEDEV is not set
91CONFIG_INPUT_EVDEV=y
92# CONFIG_INPUT_KEYBOARD is not set
93# CONFIG_INPUT_MOUSE is not set
94CONFIG_INPUT_TOUCHSCREEN=y
95CONFIG_TOUCHSCREEN_AD7879=m
96CONFIG_INPUT_MISC=y
97CONFIG_INPUT_AD714X=y
98CONFIG_INPUT_ADXL34X=y
99# CONFIG_SERIO is not set
100CONFIG_BFIN_PPI=m
101CONFIG_BFIN_SIMPLE_TIMER=m
102CONFIG_BFIN_SPORT=m
103# CONFIG_CONSOLE_TRANSLATIONS is not set
104# CONFIG_DEVKMEM is not set
105CONFIG_BFIN_JTAG_COMM=m
106CONFIG_SERIAL_BFIN=y
107CONFIG_SERIAL_BFIN_CONSOLE=y
108CONFIG_SERIAL_BFIN_UART1=y
109# CONFIG_LEGACY_PTYS is not set
110# CONFIG_HW_RANDOM is not set
111CONFIG_I2C_CHARDEV=y
112# CONFIG_I2C_HELPER_AUTO is not set
113CONFIG_I2C_SMBUS=y
114CONFIG_I2C_BLACKFIN_TWI=y
115CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
116CONFIG_GPIOLIB=y
117CONFIG_GPIO_SYSFS=y
118# CONFIG_HWMON is not set
119CONFIG_WATCHDOG=y
120CONFIG_BFIN_WDT=y
121CONFIG_MEDIA_SUPPORT=y
122CONFIG_VIDEO_DEV=y
123# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
124CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
125CONFIG_VIDEO_BLACKFIN_CAM=m
126CONFIG_OV9655=y
127CONFIG_FB=y
128CONFIG_BACKLIGHT_LCD_SUPPORT=y
129CONFIG_FRAMEBUFFER_CONSOLE=y
130CONFIG_FONTS=y
131CONFIG_FONT_6x11=y
132CONFIG_LOGO=y
133# CONFIG_LOGO_LINUX_MONO is not set
134# CONFIG_LOGO_LINUX_VGA16 is not set
135# CONFIG_LOGO_LINUX_CLUT224 is not set
136# CONFIG_LOGO_BLACKFIN_VGA16 is not set
137CONFIG_SOUND=y
138CONFIG_SND=y
139CONFIG_SND_MIXER_OSS=y
140CONFIG_SND_PCM_OSS=y
141CONFIG_SND_SOC=y
142CONFIG_SND_BF5XX_I2S=y
143CONFIG_SND_BF5XX_SOC_SSM2602=y
144# CONFIG_HID_SUPPORT is not set
145# CONFIG_USB_SUPPORT is not set
146CONFIG_MMC=m
147CONFIG_RTC_CLASS=y
148CONFIG_RTC_DRV_BFIN=y
149CONFIG_EXT2_FS=y
150# CONFIG_DNOTIFY is not set
151CONFIG_ISO9660_FS=m
152CONFIG_JOLIET=y
153CONFIG_UDF_FS=m
154CONFIG_MSDOS_FS=y
155CONFIG_VFAT_FS=y
156CONFIG_JFFS2_FS=y
157CONFIG_NFS_FS=m
158CONFIG_NFS_V3=y
159# CONFIG_RPCSEC_GSS_KRB5 is not set
160CONFIG_NLS_CODEPAGE_437=m
161CONFIG_NLS_CODEPAGE_936=m
162CONFIG_NLS_ISO8859_1=m
163CONFIG_NLS_UTF8=m
164CONFIG_DEBUG_KERNEL=y
165CONFIG_DEBUG_SHIRQ=y
166CONFIG_DETECT_HUNG_TASK=y
167CONFIG_DEBUG_INFO=y
168# CONFIG_RCU_CPU_STALL_DETECTOR is not set
169# CONFIG_FTRACE is not set
170CONFIG_DEBUG_MMRS=y
171CONFIG_DEBUG_HWERR=y
172CONFIG_EXACT_HWERR=y
173CONFIG_DEBUG_DOUBLEFAULT=y
174CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
175CONFIG_EARLY_PRINTK=y
176CONFIG_CPLB_INFO=y
177CONFIG_SECURITY=y
178CONFIG_CRYPTO=y
179# CONFIG_CRYPTO_ANSI_CPRNG is not set
180CONFIG_CRC7=m
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index d9eb29e2555c..9e7c5379d3ff 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,4 +1,5 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += bfin_sport.h 3header-y += bfin_sport.h
4header-y += cachectl.h
4header-y += fixed_code.h 5header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index 4223cf08ce83..0b5136e334b5 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -41,6 +41,25 @@
41#define BIT_STU_SENDOVER 0x0001 41#define BIT_STU_SENDOVER 0x0001
42#define BIT_STU_RECVFULL 0x0020 42#define BIT_STU_RECVFULL 0x0020
43 43
44/*
45 * All Blackfin system MMRs are padded to 32bits even if the register
46 * itself is only 16bits. So use a helper macro to streamline this.
47 */
48#define __BFP(m) u16 m; u16 __pad_##m
49
50/*
51 * bfin spi registers layout
52 */
53struct bfin_spi_regs {
54 __BFP(ctl);
55 __BFP(flg);
56 __BFP(stat);
57 __BFP(tdbr);
58 __BFP(rdbr);
59 __BFP(baud);
60 __BFP(shadow);
61};
62
44#define MAX_CTRL_CS 8 /* cs in spi controller */ 63#define MAX_CTRL_CS 8 /* cs in spi controller */
45 64
46/* device.platform_data for SSP controller devices */ 65/* device.platform_data for SSP controller devices */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
index eec0076a385b..b1492e0bcabb 100644
--- a/arch/blackfin/include/asm/bfin_can.h
+++ b/arch/blackfin/include/asm/bfin_can.h
@@ -34,6 +34,7 @@ struct bfin_can_mask_regs {
34}; 34};
35 35
36struct bfin_can_channel_regs { 36struct bfin_can_channel_regs {
37 /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
37 u16 data[8]; 38 u16 data[8];
38 __BFP(dlc); 39 __BFP(dlc);
39 __BFP(tsv); 40 __BFP(tsv);
@@ -83,16 +84,18 @@ struct bfin_can_regs {
83 __BFP(gif); /* offset 0x9c */ 84 __BFP(gif); /* offset 0x9c */
84 __BFP(control); /* offset 0xa0 */ 85 __BFP(control); /* offset 0xa0 */
85 __BFP(intr); /* offset 0xa4 */ 86 __BFP(intr); /* offset 0xa4 */
86 u32 __pad3[1]; 87 __BFP(version); /* offset 0xa8 */
87 __BFP(mbtd); /* offset 0xac */ 88 __BFP(mbtd); /* offset 0xac */
88 __BFP(ewr); /* offset 0xb0 */ 89 __BFP(ewr); /* offset 0xb0 */
89 __BFP(esr); /* offset 0xb4 */ 90 __BFP(esr); /* offset 0xb4 */
90 u32 __pad4[2]; 91 u32 __pad3[2];
91 __BFP(ucreg); /* offset 0xc0 */ 92 __BFP(ucreg); /* offset 0xc0 */
92 __BFP(uccnt); /* offset 0xc4 */ 93 __BFP(uccnt); /* offset 0xc4 */
93 __BFP(ucrc); /* offset 0xc8 */ 94 __BFP(ucrc); /* offset 0xc8 */
94 __BFP(uccnf); /* offset 0xcc */ 95 __BFP(uccnf); /* offset 0xcc */
95 u32 __pad5[12]; 96 u32 __pad4[1];
97 __BFP(version2); /* offset 0xd4 */
98 u32 __pad5[10];
96 99
97 /* 100 /*
98 * channel(mailbox) mask and message registers 101 * channel(mailbox) mask and message registers
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
new file mode 100644
index 000000000000..003900886f97
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -0,0 +1,51 @@
1/*
2 * bfin_ppi.h - interface to Blackfin PPIs
3 *
4 * Copyright 2005-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_PPI_H__
10#define __ASM_BFIN_PPI_H__
11
12#include <linux/types.h>
13
14/*
15 * All Blackfin system MMRs are padded to 32bits even if the register
16 * itself is only 16bits. So use a helper macro to streamline this.
17 */
18#define __BFP(m) u16 m; u16 __pad_##m
19
20/*
21 * bfin ppi registers layout
22 */
23struct bfin_ppi_regs {
24 __BFP(control);
25 __BFP(status);
26 __BFP(count);
27 __BFP(delay);
28 __BFP(frame);
29};
30
31/*
32 * bfin eppi registers layout
33 */
34struct bfin_eppi_regs {
35 __BFP(status);
36 __BFP(hcount);
37 __BFP(hdelay);
38 __BFP(vcount);
39 __BFP(vdelay);
40 __BFP(frame);
41 __BFP(line);
42 __BFP(clkdiv);
43 u32 control;
44 u32 fs1w_hbl;
45 u32 fs1p_avpl;
46 u32 fs2w_lvb;
47 u32 fs2p_lavf;
48 u32 clip;
49};
50
51#endif
diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h
new file mode 100644
index 000000000000..03255df6c1ea
--- /dev/null
+++ b/arch/blackfin/include/asm/cachectl.h
@@ -0,0 +1,20 @@
1/*
2 * based on the mips/cachectl.h
3 *
4 * Copyright 2010 Analog Devices Inc.
5 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#ifndef _ASM_CACHECTL
11#define _ASM_CACHECTL
12
13/*
14 * Options for cacheflush system call
15 */
16#define ICACHE (1<<0) /* flush instruction cache */
17#define DCACHE (1<<1) /* writeback and flush data cache */
18#define BCACHE (ICACHE|DCACHE) /* flush both caches */
19
20#endif /* _ASM_CACHECTL */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 6c39d94b44d0..a1f6817687e8 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -172,16 +172,19 @@
172#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) 172#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
173#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) 173#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
174#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) 174#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
175#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
176#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) 175#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
177#if 0 176#if 0
178#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ 177#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
179#endif 178#endif
180#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
181#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) 179#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
182#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
183#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) 180#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
184 181
182#if ANOMALY_05000481
183#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
184#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
185#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
186#endif
187
185/* Event/Interrupt Registers*/ 188/* Event/Interrupt Registers*/
186 189
187#define bfin_read_EVT0() bfin_read32(EVT0) 190#define bfin_read_EVT0() bfin_read32(EVT0)
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index aaa1c6c2bc19..832d7c009a2c 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child);
113/* common code demands this function */ 113/* common code demands this function */
114#define ptrace_disable(child) user_disable_single_step(child) 114#define ptrace_disable(child) user_disable_single_step(child)
115 115
116extern int is_user_addr_valid(struct task_struct *child,
117 unsigned long start, unsigned long len);
118
116/* 119/*
117 * Get the address of the live pt_regs for the specified task. 120 * Get the address of the live pt_regs for the specified task.
118 * These are saved onto the top kernel stack when the process 121 * These are saved onto the top kernel stack when the process
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
index 94a4a12e3bf2..a0cb0caff152 100644
--- a/arch/blackfin/include/asm/serial.h
+++ b/arch/blackfin/include/asm/serial.h
@@ -1,2 +1 @@
1#include <asm-generic/serial.h> #include <asm-generic/serial.h>
2#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 14fcd254b185..928ae975b87e 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -392,8 +392,9 @@
392#define __NR_fanotify_init 371 392#define __NR_fanotify_init 371
393#define __NR_fanotify_mark 372 393#define __NR_fanotify_mark 372
394#define __NR_prlimit64 373 394#define __NR_prlimit64 373
395#define __NR_cacheflush 374
395 396
396#define __NR_syscall 374 397#define __NR_syscall 375
397#define NR_syscalls __NR_syscall 398#define NR_syscalls __NR_syscall
398 399
399/* Old optional stuff no one actually uses */ 400/* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index ca1c1f9debd6..170cf90735ba 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GPIO Abstraction Layer 2 * GPIO Abstraction Layer
3 * 3 *
4 * Copyright 2006-2009 Analog Devices Inc. 4 * Copyright 2006-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later 6 * Licensed under the GPL-2 or later
7 */ 7 */
@@ -215,82 +215,91 @@ static void port_setup(unsigned gpio, unsigned short usage)
215} 215}
216 216
217#ifdef BF537_FAMILY 217#ifdef BF537_FAMILY
218static struct { 218static const s8 port_mux[] = {
219 unsigned short res; 219 [GPIO_PF0] = 3,
220 unsigned short offset; 220 [GPIO_PF1] = 3,
221} port_mux_lut[] = { 221 [GPIO_PF2] = 4,
222 {.res = P_PPI0_D13, .offset = 11}, 222 [GPIO_PF3] = 4,
223 {.res = P_PPI0_D14, .offset = 11}, 223 [GPIO_PF4] = 5,
224 {.res = P_PPI0_D15, .offset = 11}, 224 [GPIO_PF5] = 6,
225 {.res = P_SPORT1_TFS, .offset = 11}, 225 [GPIO_PF6] = 7,
226 {.res = P_SPORT1_TSCLK, .offset = 11}, 226 [GPIO_PF7] = 8,
227 {.res = P_SPORT1_DTPRI, .offset = 11}, 227 [GPIO_PF8 ... GPIO_PF15] = -1,
228 {.res = P_PPI0_D10, .offset = 10}, 228 [GPIO_PG0 ... GPIO_PG7] = -1,
229 {.res = P_PPI0_D11, .offset = 10}, 229 [GPIO_PG8] = 9,
230 {.res = P_PPI0_D12, .offset = 10}, 230 [GPIO_PG9] = 9,
231 {.res = P_SPORT1_RSCLK, .offset = 10}, 231 [GPIO_PG10] = 10,
232 {.res = P_SPORT1_RFS, .offset = 10}, 232 [GPIO_PG11] = 10,
233 {.res = P_SPORT1_DRPRI, .offset = 10}, 233 [GPIO_PG12] = 10,
234 {.res = P_PPI0_D8, .offset = 9}, 234 [GPIO_PG13] = 11,
235 {.res = P_PPI0_D9, .offset = 9}, 235 [GPIO_PG14] = 11,
236 {.res = P_SPORT1_DRSEC, .offset = 9}, 236 [GPIO_PG15] = 11,
237 {.res = P_SPORT1_DTSEC, .offset = 9}, 237 [GPIO_PH0 ... GPIO_PH15] = -1,
238 {.res = P_TMR2, .offset = 8}, 238 [PORT_PJ0 ... PORT_PJ3] = -1,
239 {.res = P_PPI0_FS3, .offset = 8}, 239 [PORT_PJ4] = 1,
240 {.res = P_TMR3, .offset = 7}, 240 [PORT_PJ5] = 1,
241 {.res = P_SPI0_SSEL4, .offset = 7}, 241 [PORT_PJ6 ... PORT_PJ9] = -1,
242 {.res = P_TMR4, .offset = 6}, 242 [PORT_PJ10] = 0,
243 {.res = P_SPI0_SSEL5, .offset = 6}, 243 [PORT_PJ11] = 0,
244 {.res = P_TMR5, .offset = 5},
245 {.res = P_SPI0_SSEL6, .offset = 5},
246 {.res = P_UART1_RX, .offset = 4},
247 {.res = P_UART1_TX, .offset = 4},
248 {.res = P_TMR6, .offset = 4},
249 {.res = P_TMR7, .offset = 4},
250 {.res = P_UART0_RX, .offset = 3},
251 {.res = P_UART0_TX, .offset = 3},
252 {.res = P_DMAR0, .offset = 3},
253 {.res = P_DMAR1, .offset = 3},
254 {.res = P_SPORT0_DTSEC, .offset = 1},
255 {.res = P_SPORT0_DRSEC, .offset = 1},
256 {.res = P_CAN0_RX, .offset = 1},
257 {.res = P_CAN0_TX, .offset = 1},
258 {.res = P_SPI0_SSEL7, .offset = 1},
259 {.res = P_SPORT0_TFS, .offset = 0},
260 {.res = P_SPORT0_DTPRI, .offset = 0},
261 {.res = P_SPI0_SSEL2, .offset = 0},
262 {.res = P_SPI0_SSEL3, .offset = 0},
263}; 244};
264 245
265static void portmux_setup(unsigned short per) 246static int portmux_group_check(unsigned short per)
266{ 247{
267 u16 y, offset, muxreg; 248 u16 ident = P_IDENT(per);
268 u16 function = P_FUNCT2MUX(per); 249 u16 function = P_FUNCT2MUX(per);
250 s8 offset = port_mux[ident];
251 u16 m, pmux, pfunc;
269 252
270 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { 253 if (offset < 0)
271 if (port_mux_lut[y].res == per) { 254 return 0;
272
273 /* SET PORTMUX REG */
274
275 offset = port_mux_lut[y].offset;
276 muxreg = bfin_read_PORT_MUX();
277 255
278 if (offset != 1) 256 pmux = bfin_read_PORT_MUX();
279 muxreg &= ~(1 << offset); 257 for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
280 else 258 if (m == ident)
281 muxreg &= ~(3 << 1); 259 continue;
260 if (port_mux[m] != offset)
261 continue;
262 if (!is_reserved(peri, m, 1))
263 continue;
282 264
283 muxreg |= (function << offset); 265 if (offset == 1)
284 bfin_write_PORT_MUX(muxreg); 266 pfunc = (pmux >> offset) & 3;
267 else
268 pfunc = (pmux >> offset) & 1;
269 if (pfunc != function) {
270 pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
271 ident, function, m, pfunc);
272 return -EINVAL;
285 } 273 }
286 } 274 }
275
276 return 0;
277}
278
279static void portmux_setup(unsigned short per)
280{
281 u16 ident = P_IDENT(per);
282 u16 function = P_FUNCT2MUX(per);
283 s8 offset = port_mux[ident];
284 u16 pmux;
285
286 if (offset == -1)
287 return;
288
289 pmux = bfin_read_PORT_MUX();
290 if (offset != 1)
291 pmux &= ~(1 << offset);
292 else
293 pmux &= ~(3 << 1);
294 pmux |= (function << offset);
295 bfin_write_PORT_MUX(pmux);
287} 296}
288#elif defined(CONFIG_BF54x) 297#elif defined(CONFIG_BF54x)
289inline void portmux_setup(unsigned short per) 298inline void portmux_setup(unsigned short per)
290{ 299{
291 u32 pmux;
292 u16 ident = P_IDENT(per); 300 u16 ident = P_IDENT(per);
293 u16 function = P_FUNCT2MUX(per); 301 u16 function = P_FUNCT2MUX(per);
302 u32 pmux;
294 303
295 pmux = gpio_array[gpio_bank(ident)]->port_mux; 304 pmux = gpio_array[gpio_bank(ident)]->port_mux;
296 305
@@ -302,20 +311,54 @@ inline void portmux_setup(unsigned short per)
302 311
303inline u16 get_portmux(unsigned short per) 312inline u16 get_portmux(unsigned short per)
304{ 313{
305 u32 pmux;
306 u16 ident = P_IDENT(per); 314 u16 ident = P_IDENT(per);
307 315 u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
308 pmux = gpio_array[gpio_bank(ident)]->port_mux;
309
310 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); 316 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
311} 317}
318static int portmux_group_check(unsigned short per)
319{
320 return 0;
321}
312#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) 322#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
323static int portmux_group_check(unsigned short per)
324{
325 u16 ident = P_IDENT(per);
326 u16 function = P_FUNCT2MUX(per);
327 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
328 u16 pin, gpiopin, pfunc;
329
330 for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
331 if (offset != pmux_offset[gpio_bank(ident)][pin])
332 continue;
333
334 gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
335 if (gpiopin == ident)
336 continue;
337 if (!is_reserved(peri, gpiopin, 1))
338 continue;
339
340 pfunc = *port_mux[gpio_bank(ident)];
341 pfunc = (pfunc >> offset) & 3;
342 if (pfunc != function) {
343 pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
344 ident, function, gpiopin, pfunc);
345 return -EINVAL;
346 }
347 }
348
349 return 0;
350}
351
313inline void portmux_setup(unsigned short per) 352inline void portmux_setup(unsigned short per)
314{ 353{
315 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); 354 u16 ident = P_IDENT(per);
355 u16 function = P_FUNCT2MUX(per);
316 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; 356 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
357 u16 pmux;
317 358
318 pmux = *port_mux[gpio_bank(ident)]; 359 pmux = *port_mux[gpio_bank(ident)];
360 if (((pmux >> offset) & 3) == function)
361 return;
319 pmux &= ~(3 << offset); 362 pmux &= ~(3 << offset);
320 pmux |= (function & 3) << offset; 363 pmux |= (function & 3) << offset;
321 *port_mux[gpio_bank(ident)] = pmux; 364 *port_mux[gpio_bank(ident)] = pmux;
@@ -323,6 +366,10 @@ inline void portmux_setup(unsigned short per)
323} 366}
324#else 367#else
325# define portmux_setup(...) do { } while (0) 368# define portmux_setup(...) do { } while (0)
369static int portmux_group_check(unsigned short per)
370{
371 return 0;
372}
326#endif 373#endif
327 374
328#ifndef CONFIG_BF54x 375#ifndef CONFIG_BF54x
@@ -735,6 +782,10 @@ int peripheral_request(unsigned short per, const char *label)
735 } 782 }
736 } 783 }
737 784
785 if (unlikely(portmux_group_check(per))) {
786 hard_local_irq_restore(flags);
787 return -EBUSY;
788 }
738 anyway: 789 anyway:
739 reserve(peri, ident); 790 reserve(peri, ident);
740 791
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index c86a3ed5f48f..cd0c090ebc54 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -493,6 +493,11 @@ int _access_ok(unsigned long addr, unsigned long size)
493 return 1; 493 return 1;
494#endif 494#endif
495 495
496#ifndef CONFIG_EXCEPTION_L1_SCRATCH
497 if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
498 return 1;
499#endif
500
496 aret = in_async(addr, size); 501 aret = in_async(addr, size);
497 if (aret < 2) 502 if (aret < 2)
498 return aret; 503 return aret;
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 6ec77685df52..b35839354130 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -27,6 +27,7 @@
27#include <asm/fixed_code.h> 27#include <asm/fixed_code.h>
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29#include <asm/mem_map.h> 29#include <asm/mem_map.h>
30#include <asm/mmu_context.h>
30 31
31/* 32/*
32 * does not yet catch signals sent when the child dies. 33 * does not yet catch signals sent when the child dies.
@@ -113,8 +114,8 @@ put_reg(struct task_struct *task, long regno, unsigned long data)
113/* 114/*
114 * check that an address falls within the bounds of the target process's memory mappings 115 * check that an address falls within the bounds of the target process's memory mappings
115 */ 116 */
116static inline int is_user_addr_valid(struct task_struct *child, 117int
117 unsigned long start, unsigned long len) 118is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
118{ 119{
119 struct vm_area_struct *vma; 120 struct vm_area_struct *vma;
120 struct sram_list_struct *sraml; 121 struct sram_list_struct *sraml;
@@ -135,6 +136,13 @@ static inline int is_user_addr_valid(struct task_struct *child,
135 if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END) 136 if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
136 return 0; 137 return 0;
137 138
139#ifdef CONFIG_APP_STACK_L1
140 if (child->mm->context.l1_stack_save)
141 if (start >= (unsigned long)l1_stack_base &&
142 start + len < (unsigned long)l1_stack_base + l1_stack_len)
143 return 0;
144#endif
145
138 return -EIO; 146 return -EIO;
139} 147}
140 148
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index bdc1e2f0da32..89448ed7065d 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -21,6 +21,8 @@
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/dma.h> 23#include <asm/dma.h>
24#include <asm/cachectl.h>
25#include <asm/ptrace.h>
24 26
25asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) 27asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
26{ 28{
@@ -70,3 +72,16 @@ asmlinkage int sys_bfin_spinlock(int *p)
70 72
71 return ret; 73 return ret;
72} 74}
75
76SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
77{
78 if (is_user_addr_valid(current, addr, len) != 0)
79 return -EINVAL;
80
81 if (op & DCACHE)
82 blackfin_dcache_flush_range(addr, addr + len);
83 if (op & ICACHE)
84 blackfin_icache_flush_range(addr, addr + len);
85
86 return 0;
87}
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 44d6d5299022..f95e6096719b 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -312,7 +312,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
312#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 312#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
313/* SPI (0) */ 313/* SPI (0) */
314static struct bfin5xx_spi_master bfin_spi0_info = { 314static struct bfin5xx_spi_master bfin_spi0_info = {
315 .num_chipselect = 5, 315 .num_chipselect = 6,
316 .enable_dma = 1, /* master has the ability to do dma transfer */ 316 .enable_dma = 1, /* master has the ability to do dma transfer */
317 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 317 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
318}; 318};
@@ -347,7 +347,7 @@ static struct platform_device bfin_spi0_device = {
347 347
348/* SPI (1) */ 348/* SPI (1) */
349static struct bfin5xx_spi_master bfin_spi1_info = { 349static struct bfin5xx_spi_master bfin_spi1_info = {
350 .num_chipselect = 5, 350 .num_chipselect = 6,
351 .enable_dma = 1, /* master has the ability to do dma transfer */ 351 .enable_dma = 1, /* master has the ability to do dma transfer */
352 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 352 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
353}; 353};
@@ -525,6 +525,14 @@ static struct platform_device bfin_sir1_device = {
525#endif 525#endif
526#endif 526#endif
527 527
528#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
529static struct platform_device bfin_i2s = {
530 .name = "bfin-i2s",
531 .id = CONFIG_SND_BF5XX_SPORT_NUM,
532 /* TODO: add platform data here */
533};
534#endif
535
528#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 536#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
529static struct resource bfin_twi0_resource[] = { 537static struct resource bfin_twi0_resource[] = {
530 [0] = { 538 [0] = {
@@ -559,6 +567,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
559 .irq = IRQ_PF8, 567 .irq = IRQ_PF8,
560 }, 568 },
561#endif 569#endif
570#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
571 {
572 I2C_BOARD_INFO("ssm2602", 0x1b),
573 },
574#endif
562}; 575};
563 576
564#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 577#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -736,6 +749,10 @@ static struct platform_device *stamp_devices[] __initdata = {
736 &i2c_bfin_twi_device, 749 &i2c_bfin_twi_device,
737#endif 750#endif
738 751
752#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
753 &bfin_i2s,
754#endif
755
739#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 756#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
740#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 757#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
741 &bfin_sport0_uart_device, 758 &bfin_sport0_uart_device,
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 9b72e5cb21fe..bead810a6546 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -291,7 +291,7 @@ static struct platform_device bfin_spi0_device = {
291 291
292/* SPI (1) */ 292/* SPI (1) */
293static struct bfin5xx_spi_master bfin_spi1_info = { 293static struct bfin5xx_spi_master bfin_spi1_info = {
294 .num_chipselect = 5, 294 .num_chipselect = 6,
295 .enable_dma = 1, /* master has the ability to do dma transfer */ 295 .enable_dma = 1, /* master has the ability to do dma transfer */
296 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 296 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
297}; 297};
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 29498e59e71f..e16969f24ffd 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -262,14 +262,14 @@
262#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 262#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
263#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 263#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
264#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 264#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
265#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) 265#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
266#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) 266#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
267#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) 267#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
268#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) 268#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
269#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) 269#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
270#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) 270#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
271#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) 271#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
272#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) 272#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
273#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 273#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
274#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 274#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
275#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 275#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
@@ -317,14 +317,14 @@
317#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 317#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
318#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 318#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
319#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 319#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
320#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) 320#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
321#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) 321#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
322#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) 322#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
323#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) 323#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
324#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) 324#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
325#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) 325#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
326#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) 326#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
327#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) 327#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
328#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 328#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
329#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 329#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
330#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 330#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 037a51fd8e93..5f84913dcd91 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -748,51 +748,6 @@
748#define FFE 0x20 /* Force Framing Error On Transmit */ 748#define FFE 0x20 /* Force Framing Error On Transmit */
749 749
750 750
751/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
752/* SPI_CTL Masks */
753#define TIMOD 0x0003 /* Transfer Initiate Mode */
754#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
755#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
756#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
757#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
758#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
759#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
760#define PSSE 0x0010 /* Slave-Select Input Enable */
761#define EMISO 0x0020 /* Enable MISO As Output */
762#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
763#define LSBF 0x0200 /* LSB First */
764#define CPHA 0x0400 /* Clock Phase */
765#define CPOL 0x0800 /* Clock Polarity */
766#define MSTR 0x1000 /* Master/Slave* */
767#define WOM 0x2000 /* Write Open Drain Master */
768#define SPE 0x4000 /* SPI Enable */
769
770/* SPI_FLG Masks */
771#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
772#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
773#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
774#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
775#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
776#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
777#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
778#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
779#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
780#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
781#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
782#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
783#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
784#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
785
786/* SPI_STAT Masks */
787#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
788#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
789#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
790#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
791#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
792#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
793#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
794
795
796/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 751/* **************** GENERAL PURPOSE TIMER MASKS **********************/
797/* TIMER_ENABLE Masks */ 752/* TIMER_ENABLE Masks */
798#define TIMEN0 0x0001 /* Enable Timer 0 */ 753#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
index b14c28810a44..1cc2667c10f1 100644
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ b/arch/blackfin/mach-bf527/boards/Kconfig
@@ -24,4 +24,14 @@ config BFIN526_EZBRD
24 help 24 help
25 BF526-EZBRD/EZKIT Lite board support. 25 BF526-EZBRD/EZKIT Lite board support.
26 26
27config BFIN527_AD7160EVAL
28 bool "BF527-AD7160-EVAL"
29 help
30 BF527-AD7160-EVAL board support.
31
32config BFIN527_TLL6527M
33 bool "The Learning Labs TLL6527M"
34 help
35 TLL6527M V1.0 platform support
36
27endchoice 37endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
index 51a5817c4a90..1d67da9f05ac 100644
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o 6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o 7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o 8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
9obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
10obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
new file mode 100644
index 000000000000..fc767ac76381
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -0,0 +1,870 @@
1/*
2 * Copyright 2004-20010 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/i2c.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <linux/leds.h>
21#include <linux/input.h>
22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },
51 [2] = { /* DMA IRQ */
52 .start = IRQ_USB_DMA,
53 .end = IRQ_USB_DMA,
54 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
55 },
56};
57
58static struct musb_hdrc_config musb_config = {
59 .multipoint = 0,
60 .dyn_fifo = 0,
61 .soft_con = 1,
62 .dma = 1,
63 .num_eps = 8,
64 .dma_channels = 8,
65 .gpio_vrsel = GPIO_PG13,
66 /* Some custom boards need to be active low, just set it to "0"
67 * if it is the case.
68 */
69 .gpio_vrsel_active = 1,
70};
71
72static struct musb_hdrc_platform_data musb_plat = {
73#if defined(CONFIG_USB_MUSB_OTG)
74 .mode = MUSB_OTG,
75#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
76 .mode = MUSB_HOST,
77#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
78 .mode = MUSB_PERIPHERAL,
79#endif
80 .config = &musb_config,
81};
82
83static u64 musb_dmamask = ~(u32)0;
84
85static struct platform_device musb_device = {
86 .name = "musb_hdrc",
87 .id = 0,
88 .dev = {
89 .dma_mask = &musb_dmamask,
90 .coherent_dma_mask = 0xffffffff,
91 .platform_data = &musb_plat,
92 },
93 .num_resources = ARRAY_SIZE(musb_resources),
94 .resource = musb_resources,
95};
96#endif
97
98#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
99static struct resource bf52x_ra158z_resources[] = {
100 {
101 .start = IRQ_PPI_ERROR,
102 .end = IRQ_PPI_ERROR,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device bf52x_ra158z_device = {
108 .name = "bfin-ra158z",
109 .id = -1,
110 .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
111 .resource = bf52x_ra158z_resources,
112};
113#endif
114
115#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
116static struct mtd_partition ad7160eval_partitions[] = {
117 {
118 .name = "bootloader(nor)",
119 .size = 0x40000,
120 .offset = 0,
121 }, {
122 .name = "linux kernel(nor)",
123 .size = 0x1C0000,
124 .offset = MTDPART_OFS_APPEND,
125 }, {
126 .name = "file system(nor)",
127 .size = MTDPART_SIZ_FULL,
128 .offset = MTDPART_OFS_APPEND,
129 }
130};
131
132static struct physmap_flash_data ad7160eval_flash_data = {
133 .width = 2,
134 .parts = ad7160eval_partitions,
135 .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
136};
137
138static struct resource ad7160eval_flash_resource = {
139 .start = 0x20000000,
140 .end = 0x203fffff,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct platform_device ad7160eval_flash_device = {
145 .name = "physmap-flash",
146 .id = 0,
147 .dev = {
148 .platform_data = &ad7160eval_flash_data,
149 },
150 .num_resources = 1,
151 .resource = &ad7160eval_flash_resource,
152};
153#endif
154
155#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
156static struct mtd_partition partition_info[] = {
157 {
158 .name = "linux kernel(nand)",
159 .offset = 0,
160 .size = 4 * 1024 * 1024,
161 },
162 {
163 .name = "file system(nand)",
164 .offset = MTDPART_OFS_APPEND,
165 .size = MTDPART_SIZ_FULL,
166 },
167};
168
169static struct bf5xx_nand_platform bf5xx_nand_platform = {
170 .data_width = NFC_NWIDTH_8,
171 .partitions = partition_info,
172 .nr_partitions = ARRAY_SIZE(partition_info),
173 .rd_dly = 3,
174 .wr_dly = 3,
175};
176
177static struct resource bf5xx_nand_resources[] = {
178 {
179 .start = NFC_CTL,
180 .end = NFC_DATA_RD + 2,
181 .flags = IORESOURCE_MEM,
182 },
183 {
184 .start = CH_NFC,
185 .end = CH_NFC,
186 .flags = IORESOURCE_IRQ,
187 },
188};
189
190static struct platform_device bf5xx_nand_device = {
191 .name = "bf5xx-nand",
192 .id = 0,
193 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
194 .resource = bf5xx_nand_resources,
195 .dev = {
196 .platform_data = &bf5xx_nand_platform,
197 },
198};
199#endif
200
201#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
208#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
209#include <linux/bfin_mac.h>
210static const unsigned short bfin_mac_peripherals[] = P_RMII0;
211
212static struct bfin_phydev_platform_data bfin_phydev_data[] = {
213 {
214 .addr = 1,
215 .irq = IRQ_MAC_PHYINT,
216 },
217};
218
219static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
220 .phydev_number = 1,
221 .phydev_data = bfin_phydev_data,
222 .phy_mode = PHY_INTERFACE_MODE_RMII,
223 .mac_peripherals = bfin_mac_peripherals,
224};
225
226static struct platform_device bfin_mii_bus = {
227 .name = "bfin_mii_bus",
228 .dev = {
229 .platform_data = &bfin_mii_bus_data,
230 }
231};
232
233static struct platform_device bfin_mac_device = {
234 .name = "bfin_mac",
235 .dev = {
236 .platform_data = &bfin_mii_bus,
237 }
238};
239#endif
240
241
242#if defined(CONFIG_MTD_M25P80) \
243 || defined(CONFIG_MTD_M25P80_MODULE)
244static struct mtd_partition bfin_spi_flash_partitions[] = {
245 {
246 .name = "bootloader(spi)",
247 .size = 0x00040000,
248 .offset = 0,
249 .mask_flags = MTD_CAP_ROM
250 }, {
251 .name = "linux kernel(spi)",
252 .size = MTDPART_SIZ_FULL,
253 .offset = MTDPART_OFS_APPEND,
254 }
255};
256
257static struct flash_platform_data bfin_spi_flash_data = {
258 .name = "m25p80",
259 .parts = bfin_spi_flash_partitions,
260 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
261 .type = "m25p16",
262};
263
264/* SPI flash chip (m25p64) */
265static struct bfin5xx_spi_chip spi_flash_chip_info = {
266 .enable_dma = 0, /* use dma transfer with this chip*/
267 .bits_per_word = 8,
268};
269#endif
270
271#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
272 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
273static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
274 .enable_dma = 0,
275 .bits_per_word = 16,
276};
277#endif
278
279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
280static struct bfin5xx_spi_chip mmc_spi_chip_info = {
281 .enable_dma = 0,
282 .bits_per_word = 8,
283};
284#endif
285
286#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
287static struct bfin5xx_spi_chip spidev_chip_info = {
288 .enable_dma = 0,
289 .bits_per_word = 8,
290};
291#endif
292
293#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
294static struct platform_device bfin_i2s = {
295 .name = "bfin-i2s",
296 .id = CONFIG_SND_BF5XX_SPORT_NUM,
297 /* TODO: add platform data here */
298};
299#endif
300
301#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
302static struct platform_device bfin_tdm = {
303 .name = "bfin-tdm",
304 .id = CONFIG_SND_BF5XX_SPORT_NUM,
305 /* TODO: add platform data here */
306};
307#endif
308
309static struct spi_board_info bfin_spi_board_info[] __initdata = {
310#if defined(CONFIG_MTD_M25P80) \
311 || defined(CONFIG_MTD_M25P80_MODULE)
312 {
313 /* the modalias must be the same as spi device driver name */
314 .modalias = "m25p80", /* Name of spi_driver for this device */
315 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
316 .bus_num = 0, /* Framework bus number */
317 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
318 .platform_data = &bfin_spi_flash_data,
319 .controller_data = &spi_flash_chip_info,
320 .mode = SPI_MODE_3,
321 },
322#endif
323#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
324 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
325 {
326 .modalias = "ad183x",
327 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
328 .bus_num = 0,
329 .chip_select = 4,
330 .controller_data = &ad1836_spi_chip_info,
331 },
332#endif
333#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
334 {
335 .modalias = "mmc_spi",
336 .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
337 .bus_num = 0,
338 .chip_select = GPIO_PH3 + MAX_CTRL_CS,
339 .controller_data = &mmc_spi_chip_info,
340 .mode = SPI_MODE_3,
341 },
342#endif
343#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
344 {
345 .modalias = "spidev",
346 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
347 .bus_num = 0,
348 .chip_select = 1,
349 .controller_data = &spidev_chip_info,
350 },
351#endif
352};
353
354#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
355/* SPI controller data */
356static struct bfin5xx_spi_master bfin_spi0_info = {
357 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
358 .enable_dma = 1, /* master has the ability to do dma transfer */
359 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
360};
361
362/* SPI (0) */
363static struct resource bfin_spi0_resource[] = {
364 [0] = {
365 .start = SPI0_REGBASE,
366 .end = SPI0_REGBASE + 0xFF,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = CH_SPI,
371 .end = CH_SPI,
372 .flags = IORESOURCE_DMA,
373 },
374 [2] = {
375 .start = IRQ_SPI,
376 .end = IRQ_SPI,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device bfin_spi0_device = {
382 .name = "bfin-spi",
383 .id = 0, /* Bus number */
384 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
385 .resource = bfin_spi0_resource,
386 .dev = {
387 .platform_data = &bfin_spi0_info, /* Passed to driver */
388 },
389};
390#endif /* spi master and devices */
391
392#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
393#ifdef CONFIG_SERIAL_BFIN_UART0
394static struct resource bfin_uart0_resources[] = {
395 {
396 .start = UART0_THR,
397 .end = UART0_GCTL+2,
398 .flags = IORESOURCE_MEM,
399 },
400 {
401 .start = IRQ_UART0_RX,
402 .end = IRQ_UART0_RX+1,
403 .flags = IORESOURCE_IRQ,
404 },
405 {
406 .start = IRQ_UART0_ERROR,
407 .end = IRQ_UART0_ERROR,
408 .flags = IORESOURCE_IRQ,
409 },
410 {
411 .start = CH_UART0_TX,
412 .end = CH_UART0_TX,
413 .flags = IORESOURCE_DMA,
414 },
415 {
416 .start = CH_UART0_RX,
417 .end = CH_UART0_RX,
418 .flags = IORESOURCE_DMA,
419 },
420};
421
422unsigned short bfin_uart0_peripherals[] = {
423 P_UART0_TX, P_UART0_RX, 0
424};
425
426static struct platform_device bfin_uart0_device = {
427 .name = "bfin-uart",
428 .id = 0,
429 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
430 .resource = bfin_uart0_resources,
431 .dev = {
432 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
433 },
434};
435#endif
436#ifdef CONFIG_SERIAL_BFIN_UART1
437static struct resource bfin_uart1_resources[] = {
438 {
439 .start = UART1_THR,
440 .end = UART1_GCTL+2,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .start = IRQ_UART1_RX,
445 .end = IRQ_UART1_RX+1,
446 .flags = IORESOURCE_IRQ,
447 },
448 {
449 .start = IRQ_UART1_ERROR,
450 .end = IRQ_UART1_ERROR,
451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 .start = CH_UART1_TX,
455 .end = CH_UART1_TX,
456 .flags = IORESOURCE_DMA,
457 },
458 {
459 .start = CH_UART1_RX,
460 .end = CH_UART1_RX,
461 .flags = IORESOURCE_DMA,
462 },
463#ifdef CONFIG_BFIN_UART1_CTSRTS
464 { /* CTS pin */
465 .start = GPIO_PF9,
466 .end = GPIO_PF9,
467 .flags = IORESOURCE_IO,
468 },
469 { /* RTS pin */
470 .start = GPIO_PF10,
471 .end = GPIO_PF10,
472 .flags = IORESOURCE_IO,
473 },
474#endif
475};
476
477unsigned short bfin_uart1_peripherals[] = {
478 P_UART1_TX, P_UART1_RX, 0
479};
480
481static struct platform_device bfin_uart1_device = {
482 .name = "bfin-uart",
483 .id = 1,
484 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
485 .resource = bfin_uart1_resources,
486 .dev = {
487 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
488 },
489};
490#endif
491#endif
492
493#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
494#ifdef CONFIG_BFIN_SIR0
495static struct resource bfin_sir0_resources[] = {
496 {
497 .start = 0xFFC00400,
498 .end = 0xFFC004FF,
499 .flags = IORESOURCE_MEM,
500 },
501 {
502 .start = IRQ_UART0_RX,
503 .end = IRQ_UART0_RX+1,
504 .flags = IORESOURCE_IRQ,
505 },
506 {
507 .start = CH_UART0_RX,
508 .end = CH_UART0_RX+1,
509 .flags = IORESOURCE_DMA,
510 },
511};
512
513static struct platform_device bfin_sir0_device = {
514 .name = "bfin_sir",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
517 .resource = bfin_sir0_resources,
518};
519#endif
520#ifdef CONFIG_BFIN_SIR1
521static struct resource bfin_sir1_resources[] = {
522 {
523 .start = 0xFFC02000,
524 .end = 0xFFC020FF,
525 .flags = IORESOURCE_MEM,
526 },
527 {
528 .start = IRQ_UART1_RX,
529 .end = IRQ_UART1_RX+1,
530 .flags = IORESOURCE_IRQ,
531 },
532 {
533 .start = CH_UART1_RX,
534 .end = CH_UART1_RX+1,
535 .flags = IORESOURCE_DMA,
536 },
537};
538
539static struct platform_device bfin_sir1_device = {
540 .name = "bfin_sir",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
543 .resource = bfin_sir1_resources,
544};
545#endif
546#endif
547
548#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
549#include <linux/input/ad7160.h>
550static const struct ad7160_platform_data bfin_ad7160_ts_info = {
551 .sensor_x_res = 854,
552 .sensor_y_res = 480,
553 .pressure = 100,
554 .filter_coef = 3,
555 .coord_pref = AD7160_ORIG_TOP_LEFT,
556 .first_touch_window = 5,
557 .move_window = 3,
558 .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
559 AD7160_EMIT_ABS_MT_PRESSURE |
560 AD7160_TRACKING_ID_ASCENDING,
561 .finger_act_ctrl = 0x64,
562 .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
563 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
564 AD7160_HAPTIC_SLOT_B(60) |
565 AD7160_HAPTIC_SLOT_B_LVL_LOW,
566
567 .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
568 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
569 AD7160_HAPTIC_SLOT_B(80) |
570 AD7160_HAPTIC_SLOT_B_LVL_LOW |
571 AD7160_HAPTIC_SLOT_C(120) |
572 AD7160_HAPTIC_SLOT_C_LVL_HIGH |
573 AD7160_HAPTIC_SLOT_D(30) |
574 AD7160_HAPTIC_SLOT_D_LVL_LOW,
575};
576#endif
577
578#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
579static struct resource bfin_twi0_resource[] = {
580 [0] = {
581 .start = TWI0_REGBASE,
582 .end = TWI0_REGBASE,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 .start = IRQ_TWI,
587 .end = IRQ_TWI,
588 .flags = IORESOURCE_IRQ,
589 },
590};
591
592static struct platform_device i2c_bfin_twi_device = {
593 .name = "i2c-bfin-twi",
594 .id = 0,
595 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
596 .resource = bfin_twi0_resource,
597};
598#endif
599
600static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
601#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
602 {
603 I2C_BOARD_INFO("ad7160", 0x33),
604 .irq = IRQ_PH1,
605 .platform_data = (void *)&bfin_ad7160_ts_info,
606 },
607#endif
608};
609
610#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
611#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
612static struct resource bfin_sport0_uart_resources[] = {
613 {
614 .start = SPORT0_TCR1,
615 .end = SPORT0_MRCS3+4,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .start = IRQ_SPORT0_RX,
620 .end = IRQ_SPORT0_RX+1,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = IRQ_SPORT0_ERROR,
625 .end = IRQ_SPORT0_ERROR,
626 .flags = IORESOURCE_IRQ,
627 },
628};
629
630unsigned short bfin_sport0_peripherals[] = {
631 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
632 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
633};
634
635static struct platform_device bfin_sport0_uart_device = {
636 .name = "bfin-sport-uart",
637 .id = 0,
638 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
639 .resource = bfin_sport0_uart_resources,
640 .dev = {
641 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
642 },
643};
644#endif
645#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
646static struct resource bfin_sport1_uart_resources[] = {
647 {
648 .start = SPORT1_TCR1,
649 .end = SPORT1_MRCS3+4,
650 .flags = IORESOURCE_MEM,
651 },
652 {
653 .start = IRQ_SPORT1_RX,
654 .end = IRQ_SPORT1_RX+1,
655 .flags = IORESOURCE_IRQ,
656 },
657 {
658 .start = IRQ_SPORT1_ERROR,
659 .end = IRQ_SPORT1_ERROR,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664unsigned short bfin_sport1_peripherals[] = {
665 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
666 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
667};
668
669static struct platform_device bfin_sport1_uart_device = {
670 .name = "bfin-sport-uart",
671 .id = 1,
672 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
673 .resource = bfin_sport1_uart_resources,
674 .dev = {
675 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
676 },
677};
678#endif
679#endif
680
681#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
682#include <asm/bfin_rotary.h>
683
684static struct bfin_rotary_platform_data bfin_rotary_data = {
685 /*.rotary_up_key = KEY_UP,*/
686 /*.rotary_down_key = KEY_DOWN,*/
687 .rotary_rel_code = REL_WHEEL,
688 .rotary_button_key = KEY_ENTER,
689 .debounce = 10, /* 0..17 */
690 .mode = ROT_QUAD_ENC | ROT_DEBE,
691};
692
693static struct resource bfin_rotary_resources[] = {
694 {
695 .start = IRQ_CNT,
696 .end = IRQ_CNT,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device bfin_rotary_device = {
702 .name = "bfin-rotary",
703 .id = -1,
704 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
705 .resource = bfin_rotary_resources,
706 .dev = {
707 .platform_data = &bfin_rotary_data,
708 },
709};
710#endif
711
712static const unsigned int cclk_vlev_datasheet[] = {
713 VRPAIR(VLEV_100, 400000000),
714 VRPAIR(VLEV_105, 426000000),
715 VRPAIR(VLEV_110, 500000000),
716 VRPAIR(VLEV_115, 533000000),
717 VRPAIR(VLEV_120, 600000000),
718};
719
720static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
721 .tuple_tab = cclk_vlev_datasheet,
722 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
723 .vr_settling_time = 25 /* us */,
724};
725
726static struct platform_device bfin_dpmc = {
727 .name = "bfin dpmc",
728 .dev = {
729 .platform_data = &bfin_dmpc_vreg_data,
730 },
731};
732
733static struct platform_device *stamp_devices[] __initdata = {
734
735 &bfin_dpmc,
736
737#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
738 &bf5xx_nand_device,
739#endif
740
741#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
742 &rtc_device,
743#endif
744
745#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
746 &musb_device,
747#endif
748
749#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
750 &bfin_mii_bus,
751 &bfin_mac_device,
752#endif
753
754#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
755 &bfin_spi0_device,
756#endif
757
758#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
759#ifdef CONFIG_SERIAL_BFIN_UART0
760 &bfin_uart0_device,
761#endif
762#ifdef CONFIG_SERIAL_BFIN_UART1
763 &bfin_uart1_device,
764#endif
765#endif
766
767#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
768 &bf52x_ra158z_device,
769#endif
770
771#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
772#ifdef CONFIG_BFIN_SIR0
773 &bfin_sir0_device,
774#endif
775#ifdef CONFIG_BFIN_SIR1
776 &bfin_sir1_device,
777#endif
778#endif
779
780#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
781 &i2c_bfin_twi_device,
782#endif
783
784#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
785#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
786 &bfin_sport0_uart_device,
787#endif
788#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
789 &bfin_sport1_uart_device,
790#endif
791#endif
792
793#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
794 &bfin_rotary_device,
795#endif
796
797#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
798 &ad7160eval_flash_device,
799#endif
800
801#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
802 &bfin_i2s,
803#endif
804
805#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
806 &bfin_tdm,
807#endif
808};
809
810static int __init ad7160eval_init(void)
811{
812 printk(KERN_INFO "%s(): registering device resources\n", __func__);
813 i2c_register_board_info(0, bfin_i2c_board_info,
814 ARRAY_SIZE(bfin_i2c_board_info));
815 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
816 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
817 return 0;
818}
819
820arch_initcall(ad7160eval_init);
821
822static struct platform_device *ad7160eval_early_devices[] __initdata = {
823#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
824#ifdef CONFIG_SERIAL_BFIN_UART0
825 &bfin_uart0_device,
826#endif
827#ifdef CONFIG_SERIAL_BFIN_UART1
828 &bfin_uart1_device,
829#endif
830#endif
831
832#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
833#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
834 &bfin_sport0_uart_device,
835#endif
836#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
837 &bfin_sport1_uart_device,
838#endif
839#endif
840};
841
842void __init native_machine_early_platform_add_devices(void)
843{
844 printk(KERN_INFO "register early platform devices\n");
845 early_platform_add_devices(ad7160eval_early_devices,
846 ARRAY_SIZE(ad7160eval_early_devices));
847}
848
849void native_machine_restart(char *cmd)
850{
851 /* workaround reboot hang when booting from SPI */
852 if ((bfin_read_SYSCR() & 0x7) == 0x3)
853 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
854}
855
856void bfin_get_ether_addr(char *addr)
857{
858 /* the MAC is stored in OTP memory page 0xDF */
859 u32 ret;
860 u64 otp_mac;
861 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
862
863 ret = otp_read(0xDF, 0x00, &otp_mac);
864 if (!(ret & 0x1)) {
865 char *otp_mac_p = (char *)&otp_mac;
866 for (ret = 0; ret < 6; ++ret)
867 addr[ret] = otp_mac_p[5 - ret];
868 }
869}
870EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 645ba5c8077b..38037c7e125a 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -342,8 +342,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
342}; 342};
343#endif 343#endif
344 344
345#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 345#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
346 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 346 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 347static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0, 348 .enable_dma = 0,
349 .bits_per_word = 16, 349 .bits_per_word = 16,
@@ -420,13 +420,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
420 }, 420 },
421#endif 421#endif
422 422
423#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 423#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
424 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 424 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
425 { 425 {
426 .modalias = "ad1836", 426 .modalias = "ad183x",
427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
428 .bus_num = 0, 428 .bus_num = 0,
429 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 429 .chip_select = 4,
430 .controller_data = &ad1836_spi_chip_info, 430 .controller_data = &ad1836_spi_chip_info,
431 }, 431 },
432#endif 432#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index c975fe88eba3..6cc64a1e78b9 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -137,8 +137,12 @@ static struct platform_device ezbrd_flash_device = {
137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
138static struct mtd_partition partition_info[] = { 138static struct mtd_partition partition_info[] = {
139 { 139 {
140 .name = "linux kernel(nand)", 140 .name = "bootloader(nand)",
141 .offset = 0, 141 .offset = 0,
142 .size = 0x40000,
143 }, {
144 .name = "linux kernel(nand)",
145 .offset = MTDPART_OFS_APPEND,
142 .size = 4 * 1024 * 1024, 146 .size = 4 * 1024 * 1024,
143 }, 147 },
144 { 148 {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 87b41e994ba3..07c132dc4125 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -222,8 +222,12 @@ static struct platform_device ezkit_flash_device = {
222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
223static struct mtd_partition partition_info[] = { 223static struct mtd_partition partition_info[] = {
224 { 224 {
225 .name = "linux kernel(nand)", 225 .name = "bootloader(nand)",
226 .offset = 0, 226 .offset = 0,
227 .size = 0x40000,
228 }, {
229 .name = "linux kernel(nand)",
230 .offset = MTDPART_OFS_APPEND,
227 .size = 4 * 1024 * 1024, 231 .size = 4 * 1024 * 1024,
228 }, 232 },
229 { 233 {
@@ -431,8 +435,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
431}; 435};
432#endif 436#endif
433 437
434#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 438#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
435 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 439 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
436static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 440static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
437 .enable_dma = 0, 441 .enable_dma = 0,
438 .bits_per_word = 16, 442 .bits_per_word = 16,
@@ -547,13 +551,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
547 }, 551 },
548#endif 552#endif
549 553
550#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 554#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
551 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 555 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
552 { 556 {
553 .modalias = "ad1836", 557 .modalias = "ad183x",
554 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 558 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
555 .bus_num = 0, 559 .bus_num = 0,
556 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 560 .chip_select = 4,
557 .controller_data = &ad1836_spi_chip_info, 561 .controller_data = &ad1836_spi_chip_info,
558 }, 562 },
559#endif 563#endif
@@ -929,6 +933,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
929 I2C_BOARD_INFO("ssm2602", 0x1b), 933 I2C_BOARD_INFO("ssm2602", 0x1b),
930 }, 934 },
931#endif 935#endif
936#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
937 {
938 I2C_BOARD_INFO("ad5252", 0x2f),
939 },
940#endif
932}; 941};
933 942
934#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 943#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
new file mode 100644
index 000000000000..ae4130e97c01
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -0,0 +1,986 @@
1/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
2 * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Author: Ashish Gupta
4 *
5 * Copyright: 2010 - The Learning Labs Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/usb/musb.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29
30#if defined(CONFIG_TOUCHSCREEN_AD7879) \
31 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
32#include <linux/spi/ad7879.h>
33#define LCD_BACKLIGHT_GPIO 0x40
34/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
35 * LCD Backlight Enable
36 */
37#endif
38
39/*
40 * Name the Board for the /proc/cpuinfo
41 */
42const char bfin_board_name[] = "TLL6527M";
43/*
44 * Driver needs to know address, irq and flag pin.
45 */
46
47#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
48static struct resource musb_resources[] = {
49 [0] = {
50 .start = 0xffc03800,
51 .end = 0xffc03cff,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = { /* general IRQ */
55 .start = IRQ_USB_INT0,
56 .end = IRQ_USB_INT0,
57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
58 },
59 [2] = { /* DMA IRQ */
60 .start = IRQ_USB_DMA,
61 .end = IRQ_USB_DMA,
62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
63 },
64};
65
66static struct musb_hdrc_config musb_config = {
67 .multipoint = 0,
68 .dyn_fifo = 0,
69 .soft_con = 1,
70 .dma = 1,
71 .num_eps = 8,
72 .dma_channels = 8,
73 /*.gpio_vrsel = GPIO_PG13,*/
74 /* Some custom boards need to be active low, just set it to "0"
75 * if it is the case.
76 */
77 .gpio_vrsel_active = 1,
78};
79
80static struct musb_hdrc_platform_data musb_plat = {
81#if defined(CONFIG_USB_MUSB_OTG)
82 .mode = MUSB_OTG,
83#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
84 .mode = MUSB_HOST,
85#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
86 .mode = MUSB_PERIPHERAL,
87#endif
88 .config = &musb_config,
89};
90
91static u64 musb_dmamask = ~(u32)0;
92
93static struct platform_device musb_device = {
94 .name = "musb_hdrc",
95 .id = 0,
96 .dev = {
97 .dma_mask = &musb_dmamask,
98 .coherent_dma_mask = 0xffffffff,
99 .platform_data = &musb_plat,
100 },
101 .num_resources = ARRAY_SIZE(musb_resources),
102 .resource = musb_resources,
103};
104#endif
105
106#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
107#include <asm/bfin-lq035q1.h>
108
109static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
110 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
111 .ppi_mode = USE_RGB565_16_BIT_PPI,
112 .use_bl = 1,
113 .gpio_bl = LCD_BACKLIGHT_GPIO,
114};
115
116static struct resource bfin_lq035q1_resources[] = {
117 {
118 .start = IRQ_PPI_ERROR,
119 .end = IRQ_PPI_ERROR,
120 .flags = IORESOURCE_IRQ,
121 },
122};
123
124static struct platform_device bfin_lq035q1_device = {
125 .name = "bfin-lq035q1",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
128 .resource = bfin_lq035q1_resources,
129 .dev = {
130 .platform_data = &bfin_lq035q1_data,
131 },
132};
133#endif
134
135#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
136static struct mtd_partition tll6527m_partitions[] = {
137 {
138 .name = "bootloader(nor)",
139 .size = 0xA0000,
140 .offset = 0,
141 }, {
142 .name = "linux kernel(nor)",
143 .size = 0xD00000,
144 .offset = MTDPART_OFS_APPEND,
145 }, {
146 .name = "file system(nor)",
147 .size = MTDPART_SIZ_FULL,
148 .offset = MTDPART_OFS_APPEND,
149 }
150};
151
152static struct physmap_flash_data tll6527m_flash_data = {
153 .width = 2,
154 .parts = tll6527m_partitions,
155 .nr_parts = ARRAY_SIZE(tll6527m_partitions),
156};
157
158static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
159
160static struct resource tll6527m_flash_resource[] = {
161 {
162 .name = "cfi_probe",
163 .start = 0x20000000,
164 .end = 0x201fffff,
165 .flags = IORESOURCE_MEM,
166 }, {
167 .start = (unsigned long)tll6527m_flash_gpios,
168 .end = ARRAY_SIZE(tll6527m_flash_gpios),
169 .flags = IORESOURCE_IRQ,
170 }
171};
172
173static struct platform_device tll6527m_flash_device = {
174 .name = "gpio-addr-flash",
175 .id = 0,
176 .dev = {
177 .platform_data = &tll6527m_flash_data,
178 },
179 .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
180 .resource = tll6527m_flash_resource,
181};
182#endif
183
184#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
185/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
187 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
189 */
190#include <linux/gpio-decoder.h>
191#define EXP_GPIO_SPISEL_BASE 0x64
192static unsigned gpio_addr_inputs[] = {
193 GPIO_PG1, GPIO_PH9, GPIO_PH10
194};
195
196static struct gpio_decoder_platfrom_data spi_decoded_cs = {
197 .base = EXP_GPIO_SPISEL_BASE,
198 .input_addrs = gpio_addr_inputs,
199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
200 .default_output = 0,
201/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
202};
203
204static struct platform_device spi_decoded_gpio = {
205 .name = "gpio-decoder",
206 .id = 0,
207 .dev = {
208 .platform_data = &spi_decoded_cs,
209 },
210};
211
212#else
213#define EXP_GPIO_SPISEL_BASE 0x0
214
215#endif
216
217#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
218#include <linux/input/adxl34x.h>
219static const struct adxl34x_platform_data adxl345_info = {
220 .x_axis_offset = 0,
221 .y_axis_offset = 0,
222 .z_axis_offset = 0,
223 .tap_threshold = 0x31,
224 .tap_duration = 0x10,
225 .tap_latency = 0x60,
226 .tap_window = 0xF0,
227 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
228 .act_axis_control = 0xFF,
229 .activity_threshold = 5,
230 .inactivity_threshold = 2,
231 .inactivity_time = 2,
232 .free_fall_threshold = 0x7,
233 .free_fall_time = 0x20,
234 .data_rate = 0x8,
235 .data_range = ADXL_FULL_RES,
236
237 .ev_type = EV_ABS,
238 .ev_code_x = ABS_X, /* EV_REL */
239 .ev_code_y = ABS_Y, /* EV_REL */
240 .ev_code_z = ABS_Z, /* EV_REL */
241
242 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
243
244/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
245 .ev_code_act_inactivity = KEY_A, /* EV_KEY */
246 .use_int2 = 1,
247 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
248 .fifo_mode = ADXL_FIFO_STREAM,
249};
250#endif
251
252#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
253static struct platform_device rtc_device = {
254 .name = "rtc-bfin",
255 .id = -1,
256};
257#endif
258
259#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
260static struct platform_device bfin_mii_bus = {
261 .name = "bfin_mii_bus",
262};
263
264static struct platform_device bfin_mac_device = {
265 .name = "bfin_mac",
266 .dev.platform_data = &bfin_mii_bus,
267};
268#endif
269
270#if defined(CONFIG_MTD_M25P80) \
271 || defined(CONFIG_MTD_M25P80_MODULE)
272static struct mtd_partition bfin_spi_flash_partitions[] = {
273 {
274 .name = "bootloader(spi)",
275 .size = 0x00040000,
276 .offset = 0,
277 .mask_flags = MTD_CAP_ROM
278 }, {
279 .name = "linux kernel(spi)",
280 .size = MTDPART_SIZ_FULL,
281 .offset = MTDPART_OFS_APPEND,
282 }
283};
284
285static struct flash_platform_data bfin_spi_flash_data = {
286 .name = "m25p80",
287 .parts = bfin_spi_flash_partitions,
288 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
289 .type = "m25p16",
290};
291
292/* SPI flash chip (m25p64) */
293static struct bfin5xx_spi_chip spi_flash_chip_info = {
294 .enable_dma = 0, /* use dma transfer with this chip*/
295 .bits_per_word = 8,
296};
297#endif
298
299#if defined(CONFIG_BFIN_SPI_ADC) \
300 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
301/* SPI ADC chip */
302static struct bfin5xx_spi_chip spi_adc_chip_info = {
303 .enable_dma = 0, /* use dma transfer with this chip*/
304/*
305 * tll6527m V1.0 does not support native spi slave selects
306 * hence DMA mode will not be useful since the ADC needs
307 * CS to toggle for each sample and cs_change_per_word
308 * seems to be removed from spi_bfin5xx.c
309 */
310 .bits_per_word = 16,
311};
312#endif
313
314#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
315static struct bfin5xx_spi_chip mmc_spi_chip_info = {
316 .enable_dma = 0,
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_TOUCHSCREEN_AD7879) \
322 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
323static const struct ad7879_platform_data bfin_ad7879_ts_info = {
324 .model = 7879, /* Model = AD7879 */
325 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
326 .pressure_max = 10000,
327 .pressure_min = 0,
328 .first_conversion_delay = 3,
329 /* wait 512us before do a first conversion */
330 .acquisition_time = 1, /* 4us acquisition time per sample */
331 .median = 2, /* do 8 measurements */
332 .averaging = 1,
333 /* take the average of 4 middle samples */
334 .pen_down_acc_interval = 255, /* 9.4 ms */
335 .gpio_export = 1, /* configure AUX as GPIO output*/
336 .gpio_base = LCD_BACKLIGHT_GPIO,
337};
338#endif
339
340#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
341 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
342static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
343 .enable_dma = 0,
344 .bits_per_word = 16,
345};
346#endif
347
348#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
349static struct bfin5xx_spi_chip spidev_chip_info = {
350 .enable_dma = 0,
351 .bits_per_word = 8,
352};
353#endif
354
355#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
356static struct platform_device bfin_i2s = {
357 .name = "bfin-i2s",
358 .id = CONFIG_SND_BF5XX_SPORT_NUM,
359 /* TODO: add platform data here */
360};
361#endif
362
363#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
364static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 8,
367};
368#endif
369
370#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
371static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375
376static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
377 .enable_dma = 0,
378 .bits_per_word = 8,
379};
380
381#include <linux/spi/mcp23s08.h>
382static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
383 .chip[0].is_present = true,
384 .base = 0x30,
385};
386static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
387 .chip[2].is_present = true,
388 .base = 0x38,
389};
390#endif
391
392static struct spi_board_info bfin_spi_board_info[] __initdata = {
393#if defined(CONFIG_MTD_M25P80) \
394 || defined(CONFIG_MTD_M25P80_MODULE)
395 {
396 /* the modalias must be the same as spi device driver name */
397 .modalias = "m25p80", /* Name of spi_driver for this device */
398 .max_speed_hz = 25000000,
399 /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
402 /* Can be connected to TLL6527M GPIO connector */
403 /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
404 .platform_data = &bfin_spi_flash_data,
405 .controller_data = &spi_flash_chip_info,
406 .mode = SPI_MODE_3,
407 },
408#endif
409
410#if defined(CONFIG_BFIN_SPI_ADC)
411 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
412 {
413 .modalias = "bfin_spi_adc",
414 /* Name of spi_driver for this device */
415 .max_speed_hz = 10000000,
416 /* max spi clock (SCK) speed in HZ */
417 .bus_num = 0, /* Framework bus number */
418 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
419 /* Framework chip select. */
420 .platform_data = NULL, /* No spi_driver specific config */
421 .controller_data = &spi_adc_chip_info,
422 .mode = SPI_MODE_0,
423 },
424#endif
425
426#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
427 {
428 .modalias = "mmc_spi",
429/*
430 * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
431 * SPI buffer limitations
432 */
433 .max_speed_hz = 10000000,
434 /* max spi clock (SCK) speed in HZ */
435 .bus_num = 0,
436 .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
437 .controller_data = &mmc_spi_chip_info,
438 .mode = SPI_MODE_0,
439 },
440#endif
441#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
442 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
443 {
444 .modalias = "ad7879",
445 .platform_data = &bfin_ad7879_ts_info,
446 .irq = IRQ_PH14,
447 .max_speed_hz = 5000000,
448 /* max spi clock (SCK) speed in HZ */
449 .bus_num = 0,
450 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
451 .controller_data = &spi_ad7879_chip_info,
452 .mode = SPI_CPHA | SPI_CPOL,
453 },
454#endif
455#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
456 {
457 .modalias = "spidev",
458 .max_speed_hz = 10000000,
459 /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
460 .bus_num = 0,
461 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
462 .mode = SPI_CPHA | SPI_CPOL,
463 .controller_data = &spidev_chip_info,
464 },
465#endif
466#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
467 {
468 .modalias = "bfin-lq035q1-spi",
469 .max_speed_hz = 20000000,
470 .bus_num = 0,
471 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
472 .controller_data = &lq035q1_spi_chip_info,
473 .mode = SPI_CPHA | SPI_CPOL,
474 },
475#endif
476#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
477 {
478 .modalias = "mcp23s08",
479 .platform_data = &bfin_mcp23s08_sys_gpio_info,
480 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
481 .bus_num = 0,
482 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
483 .controller_data = &spi_mcp23s08_sys_chip_info,
484 .mode = SPI_CPHA | SPI_CPOL,
485 },
486 {
487 .modalias = "mcp23s08",
488 .platform_data = &bfin_mcp23s08_usr_gpio_info,
489 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
490 .bus_num = 0,
491 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
492 .controller_data = &spi_mcp23s08_usr_chip_info,
493 .mode = SPI_CPHA | SPI_CPOL,
494 },
495#endif
496};
497
498#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
499/* SPI controller data */
500static struct bfin5xx_spi_master bfin_spi0_info = {
501 .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
502 /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
503 .enable_dma = 1, /* master has the ability to do dma transfer */
504 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
505};
506
507/* SPI (0) */
508static struct resource bfin_spi0_resource[] = {
509 [0] = {
510 .start = SPI0_REGBASE,
511 .end = SPI0_REGBASE + 0xFF,
512 .flags = IORESOURCE_MEM,
513 },
514 [1] = {
515 .start = CH_SPI,
516 .end = CH_SPI,
517 .flags = IORESOURCE_DMA,
518 },
519 [2] = {
520 .start = IRQ_SPI,
521 .end = IRQ_SPI,
522 .flags = IORESOURCE_IRQ,
523 },
524};
525
526static struct platform_device bfin_spi0_device = {
527 .name = "bfin-spi",
528 .id = 0, /* Bus number */
529 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
530 .resource = bfin_spi0_resource,
531 .dev = {
532 .platform_data = &bfin_spi0_info, /* Passed to driver */
533 },
534};
535#endif /* spi master and devices */
536
537#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
538#ifdef CONFIG_SERIAL_BFIN_UART0
539static struct resource bfin_uart0_resources[] = {
540 {
541 .start = UART0_THR,
542 .end = UART0_GCTL+2,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 .start = IRQ_UART0_RX,
547 .end = IRQ_UART0_RX+1,
548 .flags = IORESOURCE_IRQ,
549 },
550 {
551 .start = IRQ_UART0_ERROR,
552 .end = IRQ_UART0_ERROR,
553 .flags = IORESOURCE_IRQ,
554 },
555 {
556 .start = CH_UART0_TX,
557 .end = CH_UART0_TX,
558 .flags = IORESOURCE_DMA,
559 },
560 {
561 .start = CH_UART0_RX,
562 .end = CH_UART0_RX,
563 .flags = IORESOURCE_DMA,
564 },
565};
566
567unsigned short bfin_uart0_peripherals[] = {
568 P_UART0_TX, P_UART0_RX, 0
569};
570
571static struct platform_device bfin_uart0_device = {
572 .name = "bfin-uart",
573 .id = 0,
574 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
575 .resource = bfin_uart0_resources,
576 .dev = {
577 .platform_data = &bfin_uart0_peripherals,
578 /* Passed to driver */
579 },
580};
581#endif
582#ifdef CONFIG_SERIAL_BFIN_UART1
583static struct resource bfin_uart1_resources[] = {
584 {
585 .start = UART1_THR,
586 .end = UART1_GCTL+2,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_UART1_RX,
591 .end = IRQ_UART1_RX+1,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_UART1_ERROR,
596 .end = IRQ_UART1_ERROR,
597 .flags = IORESOURCE_IRQ,
598 },
599 {
600 .start = CH_UART1_TX,
601 .end = CH_UART1_TX,
602 .flags = IORESOURCE_DMA,
603 },
604 {
605 .start = CH_UART1_RX,
606 .end = CH_UART1_RX,
607 .flags = IORESOURCE_DMA,
608 },
609#ifdef CONFIG_BFIN_UART1_CTSRTS
610 { /* CTS pin */
611 .start = GPIO_PF9,
612 .end = GPIO_PF9,
613 .flags = IORESOURCE_IO,
614 },
615 { /* RTS pin */
616 .start = GPIO_PF10,
617 .end = GPIO_PF10,
618 .flags = IORESOURCE_IO,
619 },
620#endif
621};
622
623unsigned short bfin_uart1_peripherals[] = {
624 P_UART1_TX, P_UART1_RX, 0
625};
626
627static struct platform_device bfin_uart1_device = {
628 .name = "bfin-uart",
629 .id = 1,
630 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
631 .resource = bfin_uart1_resources,
632 .dev = {
633 .platform_data = &bfin_uart1_peripherals,
634 /* Passed to driver */
635 },
636};
637#endif
638#endif
639
640#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
641#ifdef CONFIG_BFIN_SIR0
642static struct resource bfin_sir0_resources[] = {
643 {
644 .start = 0xFFC00400,
645 .end = 0xFFC004FF,
646 .flags = IORESOURCE_MEM,
647 },
648 {
649 .start = IRQ_UART0_RX,
650 .end = IRQ_UART0_RX+1,
651 .flags = IORESOURCE_IRQ,
652 },
653 {
654 .start = CH_UART0_RX,
655 .end = CH_UART0_RX+1,
656 .flags = IORESOURCE_DMA,
657 },
658};
659
660static struct platform_device bfin_sir0_device = {
661 .name = "bfin_sir",
662 .id = 0,
663 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
664 .resource = bfin_sir0_resources,
665};
666#endif
667#ifdef CONFIG_BFIN_SIR1
668static struct resource bfin_sir1_resources[] = {
669 {
670 .start = 0xFFC02000,
671 .end = 0xFFC020FF,
672 .flags = IORESOURCE_MEM,
673 },
674 {
675 .start = IRQ_UART1_RX,
676 .end = IRQ_UART1_RX+1,
677 .flags = IORESOURCE_IRQ,
678 },
679 {
680 .start = CH_UART1_RX,
681 .end = CH_UART1_RX+1,
682 .flags = IORESOURCE_DMA,
683 },
684};
685
686static struct platform_device bfin_sir1_device = {
687 .name = "bfin_sir",
688 .id = 1,
689 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
690 .resource = bfin_sir1_resources,
691};
692#endif
693#endif
694
695#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
696static struct resource bfin_twi0_resource[] = {
697 [0] = {
698 .start = TWI0_REGBASE,
699 .end = TWI0_REGBASE,
700 .flags = IORESOURCE_MEM,
701 },
702 [1] = {
703 .start = IRQ_TWI,
704 .end = IRQ_TWI,
705 .flags = IORESOURCE_IRQ,
706 },
707};
708
709static struct platform_device i2c_bfin_twi_device = {
710 .name = "i2c-bfin-twi",
711 .id = 0,
712 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
713 .resource = bfin_twi0_resource,
714};
715#endif
716
717static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
718#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
719 {
720 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
721 },
722#endif
723
724#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
725 {
726 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
727 },
728#endif
729#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
730 || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
731 {
732 I2C_BOARD_INFO("ad7879", 0x2C),
733 .irq = IRQ_PH14,
734 .platform_data = (void *)&bfin_ad7879_ts_info,
735 },
736#endif
737#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
738 {
739 I2C_BOARD_INFO("ssm2602", 0x1b),
740 },
741#endif
742 {
743 I2C_BOARD_INFO("adm1192", 0x2e),
744 },
745
746 {
747 I2C_BOARD_INFO("ltc3576", 0x09),
748 },
749#if defined(CONFIG_INPUT_ADXL34X_I2C) \
750 || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
751 {
752 I2C_BOARD_INFO("adxl34x", 0x53),
753 .irq = IRQ_PH13,
754 .platform_data = (void *)&adxl345_info,
755 },
756#endif
757};
758
759#if defined(CONFIG_SERIAL_BFIN_SPORT) \
760 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
761#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
762static struct resource bfin_sport0_uart_resources[] = {
763 {
764 .start = SPORT0_TCR1,
765 .end = SPORT0_MRCS3+4,
766 .flags = IORESOURCE_MEM,
767 },
768 {
769 .start = IRQ_SPORT0_RX,
770 .end = IRQ_SPORT0_RX+1,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .start = IRQ_SPORT0_ERROR,
775 .end = IRQ_SPORT0_ERROR,
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780unsigned short bfin_sport0_peripherals[] = {
781 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
782 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
783};
784
785static struct platform_device bfin_sport0_uart_device = {
786 .name = "bfin-sport-uart",
787 .id = 0,
788 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
789 .resource = bfin_sport0_uart_resources,
790 .dev = {
791 .platform_data = &bfin_sport0_peripherals,
792 /* Passed to driver */
793 },
794};
795#endif
796#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
797static struct resource bfin_sport1_uart_resources[] = {
798 {
799 .start = SPORT1_TCR1,
800 .end = SPORT1_MRCS3+4,
801 .flags = IORESOURCE_MEM,
802 },
803 {
804 .start = IRQ_SPORT1_RX,
805 .end = IRQ_SPORT1_RX+1,
806 .flags = IORESOURCE_IRQ,
807 },
808 {
809 .start = IRQ_SPORT1_ERROR,
810 .end = IRQ_SPORT1_ERROR,
811 .flags = IORESOURCE_IRQ,
812 },
813};
814
815unsigned short bfin_sport1_peripherals[] = {
816 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
817 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
818};
819
820static struct platform_device bfin_sport1_uart_device = {
821 .name = "bfin-sport-uart",
822 .id = 1,
823 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
824 .resource = bfin_sport1_uart_resources,
825 .dev = {
826 .platform_data = &bfin_sport1_peripherals,
827 /* Passed to driver */
828 },
829};
830#endif
831#endif
832
833static const unsigned int cclk_vlev_datasheet[] = {
834 VRPAIR(VLEV_100, 400000000),
835 VRPAIR(VLEV_105, 426000000),
836 VRPAIR(VLEV_110, 500000000),
837 VRPAIR(VLEV_115, 533000000),
838 VRPAIR(VLEV_120, 600000000),
839};
840
841static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
842 .tuple_tab = cclk_vlev_datasheet,
843 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
844 .vr_settling_time = 25 /* us */,
845};
846
847static struct platform_device bfin_dpmc = {
848 .name = "bfin dpmc",
849 .dev = {
850 .platform_data = &bfin_dmpc_vreg_data,
851 },
852};
853
854static struct platform_device *tll6527m_devices[] __initdata = {
855
856 &bfin_dpmc,
857
858#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
859 &rtc_device,
860#endif
861
862#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
863 &musb_device,
864#endif
865
866#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
867 &bfin_mii_bus,
868 &bfin_mac_device,
869#endif
870
871#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
872 &bfin_spi0_device,
873#endif
874
875#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
876 &bfin_lq035q1_device,
877#endif
878
879#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
880#ifdef CONFIG_SERIAL_BFIN_UART0
881 &bfin_uart0_device,
882#endif
883#ifdef CONFIG_SERIAL_BFIN_UART1
884 &bfin_uart1_device,
885#endif
886#endif
887
888#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
889#ifdef CONFIG_BFIN_SIR0
890 &bfin_sir0_device,
891#endif
892#ifdef CONFIG_BFIN_SIR1
893 &bfin_sir1_device,
894#endif
895#endif
896
897#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
898 &i2c_bfin_twi_device,
899#endif
900
901#if defined(CONFIG_SERIAL_BFIN_SPORT) \
902 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
903#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
904 &bfin_sport0_uart_device,
905#endif
906#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
907 &bfin_sport1_uart_device,
908#endif
909#endif
910
911#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
912 &tll6527m_flash_device,
913#endif
914
915#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
916 &bfin_i2s,
917#endif
918
919#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
920 &spi_decoded_gpio,
921#endif
922};
923
924static int __init tll6527m_init(void)
925{
926 printk(KERN_INFO "%s(): registering device resources\n", __func__);
927 i2c_register_board_info(0, bfin_i2c_board_info,
928 ARRAY_SIZE(bfin_i2c_board_info));
929 platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
930 spi_register_board_info(bfin_spi_board_info,
931 ARRAY_SIZE(bfin_spi_board_info));
932 return 0;
933}
934
935arch_initcall(tll6527m_init);
936
937static struct platform_device *tll6527m_early_devices[] __initdata = {
938#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
939#ifdef CONFIG_SERIAL_BFIN_UART0
940 &bfin_uart0_device,
941#endif
942#ifdef CONFIG_SERIAL_BFIN_UART1
943 &bfin_uart1_device,
944#endif
945#endif
946
947#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
948#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
949 &bfin_sport0_uart_device,
950#endif
951#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
952 &bfin_sport1_uart_device,
953#endif
954#endif
955};
956
957void __init native_machine_early_platform_add_devices(void)
958{
959 printk(KERN_INFO "register early platform devices\n");
960 early_platform_add_devices(tll6527m_early_devices,
961 ARRAY_SIZE(tll6527m_early_devices));
962}
963
964void native_machine_restart(char *cmd)
965{
966 /* workaround reboot hang when booting from SPI */
967 if ((bfin_read_SYSCR() & 0x7) == 0x3)
968 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
969}
970
971void bfin_get_ether_addr(char *addr)
972{
973 /* the MAC is stored in OTP memory page 0xDF */
974 u32 ret;
975 u64 otp_mac;
976 u32 (*otp_read)(u32 page, u32 flags,
977 u64 *page_content) = (void *)0xEF00001A;
978
979 ret = otp_read(0xDF, 0x00, &otp_mac);
980 if (!(ret & 0x1)) {
981 char *otp_mac_p = (char *)&otp_mac;
982 for (ret = 0; ret < 6; ++ret)
983 addr[ret] = otp_mac_p[5 - ret];
984 }
985}
986EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 11fb27bc427d..3048b52bf46a 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -279,14 +279,14 @@
279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 279#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 280#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 281#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) 282#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) 283#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) 284#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) 285#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) 286#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) 287#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) 288#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) 289#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 290#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 291#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 292#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
@@ -334,14 +334,14 @@
334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 334#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 335#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 336#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) 337#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) 338#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) 339#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) 340#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) 341#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) 342#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) 343#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) 344#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 345#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 346#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 347#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 3e000756aacd..09475034c6a1 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -749,51 +749,6 @@
749#define FFE 0x20 /* Force Framing Error On Transmit */ 749#define FFE 0x20 /* Force Framing Error On Transmit */
750 750
751 751
752/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
753/* SPI_CTL Masks */
754#define TIMOD 0x0003 /* Transfer Initiate Mode */
755#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
756#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
757#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
758#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
759#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
760#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
761#define PSSE 0x0010 /* Slave-Select Input Enable */
762#define EMISO 0x0020 /* Enable MISO As Output */
763#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
764#define LSBF 0x0200 /* LSB First */
765#define CPHA 0x0400 /* Clock Phase */
766#define CPOL 0x0800 /* Clock Polarity */
767#define MSTR 0x1000 /* Master/Slave* */
768#define WOM 0x2000 /* Write Open Drain Master */
769#define SPE 0x4000 /* SPI Enable */
770
771/* SPI_FLG Masks */
772#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
773#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
774#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
775#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
776#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
777#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
778#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
779#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
780#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
781#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
782#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
783#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
784#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
785#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
786
787/* SPI_STAT Masks */
788#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
789#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
790#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
791#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
792#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
793#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
794#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
795
796
797/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 752/* **************** GENERAL PURPOSE TIMER MASKS **********************/
798/* TIMER_ENABLE Masks */ 753/* TIMER_ENABLE Masks */
799#define TIMEN0 0x0001 /* Enable Timer 0 */ 754#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 175371af0692..2ce7b16faee1 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -171,7 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
171}; 171};
172#endif 172#endif
173 173
174#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 174#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
175static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 175static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
176 .enable_dma = 0, 176 .enable_dma = 0,
177 .bits_per_word = 16, 177 .bits_per_word = 16,
@@ -206,12 +206,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
206 }, 206 },
207#endif 207#endif
208 208
209#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 209#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
210 { 210 {
211 .modalias = "ad1836", 211 .modalias = "ad183x",
212 .max_speed_hz = 16, 212 .max_speed_hz = 16,
213 .bus_num = 1, 213 .bus_num = 1,
214 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 214 .chip_select = 4,
215 .controller_data = &ad1836_spi_chip_info, 215 .controller_data = &ad1836_spi_chip_info,
216 }, 216 },
217#endif 217#endif
@@ -347,6 +347,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
347 .membase = (void *)0x20200000, 347 .membase = (void *)0x20200000,
348 .mapbase = 0x20200000, 348 .mapbase = 0x20200000,
349 .irq = IRQ_PF8, 349 .irq = IRQ_PF8,
350 .irqflags = IRQF_TRIGGER_HIGH,
350 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, 351 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
351 .iotype = UPIO_MEM, 352 .iotype = UPIO_MEM,
352 .regshift = 1, 353 .regshift = 1,
@@ -355,6 +356,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
355 .membase = (void *)0x20200010, 356 .membase = (void *)0x20200010,
356 .mapbase = 0x20200010, 357 .mapbase = 0x20200010,
357 .irq = IRQ_PF8, 358 .irq = IRQ_PF8,
359 .irqflags = IRQF_TRIGGER_HIGH,
358 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, 360 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
359 .iotype = UPIO_MEM, 361 .iotype = UPIO_MEM,
360 .regshift = 1, 362 .regshift = 1,
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 84a06f677dff..20c102285bef 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -368,8 +368,8 @@ static struct platform_device bfin_device_gpiokeys = {
368#include <linux/i2c-gpio.h> 368#include <linux/i2c-gpio.h>
369 369
370static struct i2c_gpio_platform_data i2c_gpio_data = { 370static struct i2c_gpio_platform_data i2c_gpio_data = {
371 .sda_pin = 8, 371 .sda_pin = GPIO_PF8,
372 .scl_pin = 9, 372 .scl_pin = GPIO_PF9,
373 .sda_is_open_drain = 0, 373 .sda_is_open_drain = 0,
374 .scl_is_open_drain = 0, 374 .scl_is_open_drain = 0,
375 .udelay = 40, 375 .udelay = 40,
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index fdcde61906dc..adbe62a81e25 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -71,7 +71,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
71}; 71};
72#endif 72#endif
73 73
74#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 74#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
75static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 75static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
76 .enable_dma = 0, 76 .enable_dma = 0,
77 .bits_per_word = 16, 77 .bits_per_word = 16,
@@ -110,12 +110,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
110 }, 110 },
111#endif 111#endif
112 112
113#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 113#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
114 { 114 {
115 .modalias = "ad1836", 115 .modalias = "ad183x",
116 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 116 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
117 .bus_num = 0, 117 .bus_num = 0,
118 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 118 .chip_select = 4,
119 .controller_data = &ad1836_spi_chip_info, 119 .controller_data = &ad1836_spi_chip_info,
120 }, 120 },
121#endif 121#endif
@@ -400,7 +400,7 @@ static struct resource isp1362_hcd_resources[] = {
400 }, { 400 }, {
401 .start = IRQ_PF4, 401 .start = IRQ_PF4,
402 .end = IRQ_PF4, 402 .end = IRQ_PF4,
403 .flags = IORESOURCE_IRQ, 403 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
404 }, 404 },
405}; 405};
406 406
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 739773cb7fc6..a1cb8e7c1010 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -222,7 +222,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
222}; 222};
223#endif 223#endif
224 224
225#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 225#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
226static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 226static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
227 .enable_dma = 0, 227 .enable_dma = 0,
228 .bits_per_word = 16, 228 .bits_per_word = 16,
@@ -261,12 +261,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
261 }, 261 },
262#endif 262#endif
263 263
264#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 264#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
265 { 265 {
266 .modalias = "ad1836", 266 .modalias = "ad183x",
267 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 267 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
268 .bus_num = 0, 268 .bus_num = 0,
269 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 269 .chip_select = 4,
270 .controller_data = &ad1836_spi_chip_info, 270 .controller_data = &ad1836_spi_chip_info,
271 }, 271 },
272#endif 272#endif
@@ -422,8 +422,8 @@ static struct platform_device bfin_device_gpiokeys = {
422#include <linux/i2c-gpio.h> 422#include <linux/i2c-gpio.h>
423 423
424static struct i2c_gpio_platform_data i2c_gpio_data = { 424static struct i2c_gpio_platform_data i2c_gpio_data = {
425 .sda_pin = 1, 425 .sda_pin = GPIO_PF1,
426 .scl_pin = 0, 426 .scl_pin = GPIO_PF0,
427 .sda_is_open_drain = 0, 427 .sda_is_open_drain = 0,
428 .scl_is_open_drain = 0, 428 .scl_is_open_drain = 0,
429 .udelay = 40, 429 .udelay = 40,
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index b8474cac6b03..5ba4b02a12eb 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -232,7 +232,7 @@ static struct resource isp1362_hcd_resources[] = {
232 },{ 232 },{
233 .start = IRQ_PF11, 233 .start = IRQ_PF11,
234 .end = IRQ_PF11, 234 .end = IRQ_PF11,
235 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 235 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
236 }, 236 },
237}; 237};
238 238
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 29c219eff2ff..b3b1cdea2703 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -185,7 +185,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
185}; 185};
186#endif 186#endif
187 187
188#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 188#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
189static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 189static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
190 .enable_dma = 0, 190 .enable_dma = 0,
191 .bits_per_word = 16, 191 .bits_per_word = 16,
@@ -252,13 +252,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
252 }, 252 },
253#endif 253#endif
254 254
255#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 255#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
256 { 256 {
257 .modalias = "ad1836", 257 .modalias = "ad183x",
258 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 258 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
259 .bus_num = 0, 259 .bus_num = 0,
260 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 260 .chip_select = 4,
261 .platform_data = "ad1836", /* only includes chip name for the moment */
261 .controller_data = &ad1836_spi_chip_info, 262 .controller_data = &ad1836_spi_chip_info,
263 .mode = SPI_MODE_3,
262 }, 264 },
263#endif 265#endif
264 266
@@ -495,8 +497,8 @@ static struct platform_device bfin_device_gpiokeys = {
495#include <linux/i2c-gpio.h> 497#include <linux/i2c-gpio.h>
496 498
497static struct i2c_gpio_platform_data i2c_gpio_data = { 499static struct i2c_gpio_platform_data i2c_gpio_data = {
498 .sda_pin = 2, 500 .sda_pin = GPIO_PF2,
499 .scl_pin = 3, 501 .scl_pin = GPIO_PF3,
500 .sda_is_open_drain = 0, 502 .sda_is_open_drain = 0,
501 .scl_is_open_drain = 0, 503 .scl_is_open_drain = 0,
502 .udelay = 40, 504 .udelay = 40,
@@ -534,6 +536,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
534 I2C_BOARD_INFO("bfin-adv7393", 0x2B), 536 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
535 }, 537 },
536#endif 538#endif
539#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
540 {
541 I2C_BOARD_INFO("ad5252", 0x2f),
542 },
543#endif
537}; 544};
538 545
539static const unsigned int cclk_vlev_datasheet[] = 546static const unsigned int cclk_vlev_datasheet[] =
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 04acf1ed10f9..3adb0b44e597 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -681,76 +681,6 @@
681#define PF14_P 14 681#define PF14_P 14
682#define PF15_P 15 682#define PF15_P 15
683 683
684/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
685
686/* SPI_CTL Masks */
687#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
688#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
689#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
690#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
691#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
692#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
693#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
694#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
695#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
696#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
697#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
698#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
699#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
700#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
701#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
702#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
703
704/* SPI_FLG Masks */
705#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
706#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
707#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
708#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
709#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
710#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
711#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
712#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
713#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
714#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
715#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
716#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
717#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
718#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
719
720/* SPI_FLG Bit Positions */
721#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
722#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
723#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
724#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
725#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
726#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
727#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
728#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
729#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
730#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
731#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
732#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
733#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
734#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
735
736/* SPI_STAT Masks */
737#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
738#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
739#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
740#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
741#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
742#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
743#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
744
745/* SPIx_FLG Masks */
746#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
747#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
748#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
749#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
750#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
751#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
752#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
753
754/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 684/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
755 685
756/* AMGCTL Masks */ 686/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index d81224f9d723..08b2b343ccec 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -14,8 +14,8 @@ config IRQ_DMA_ERROR
14 int "IRQ_DMA_ERROR Generic" 14 int "IRQ_DMA_ERROR Generic"
15 default 7 15 default 7
16config IRQ_ERROR 16config IRQ_ERROR
17 int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" 17 int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
18 default 7 18 default 11
19config IRQ_RTC 19config IRQ_RTC
20 int "IRQ_RTC" 20 int "IRQ_RTC"
21 default 8 21 default 8
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index d35fc5fe4c2b..e2e7be40ef44 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -73,7 +73,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
73}; 73};
74#endif 74#endif
75 75
76#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 76#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
77static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 77static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
78 .enable_dma = 0, 78 .enable_dma = 0,
79 .bits_per_word = 16, 79 .bits_per_word = 16,
@@ -112,12 +112,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
112 }, 112 },
113#endif 113#endif
114 114
115#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 115#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
116 { 116 {
117 .modalias = "ad1836", 117 .modalias = "ad183x",
118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
119 .bus_num = 0, 119 .bus_num = 0,
120 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 120 .chip_select = 4,
121 .controller_data = &ad1836_spi_chip_info, 121 .controller_data = &ad1836_spi_chip_info,
122 }, 122 },
123#endif 123#endif
@@ -229,7 +229,7 @@ static struct resource isp1362_hcd_resources[] = {
229 }, { 229 }, {
230 .start = IRQ_PG15, 230 .start = IRQ_PG15,
231 .end = IRQ_PG15, 231 .end = IRQ_PG15,
232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
233 }, 233 },
234}; 234};
235 235
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index d464ad5b72b2..752c833f7ca8 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
74}; 74};
75#endif 75#endif
76 76
77#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0, 79 .enable_dma = 0,
80 .bits_per_word = 16, 80 .bits_per_word = 16,
@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
113 }, 113 },
114#endif 114#endif
115 115
116#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 117 {
118 .modalias = "ad1836", 118 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 120 .bus_num = 0,
121 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 121 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info, 122 .controller_data = &ad1836_spi_chip_info,
123 }, 123 },
124#endif 124#endif
@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
230 }, { 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
234 }, 234 },
235}; 235};
236 236
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 812e8f991601..6b03808800a6 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -175,8 +175,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
175}; 175};
176#endif 176#endif
177 177
178#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 178#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
179 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 179 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
180static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 180static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
181 .enable_dma = 0, 181 .enable_dma = 0,
182 .bits_per_word = 16, 182 .bits_per_word = 16,
@@ -238,13 +238,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
238 }, 238 },
239#endif 239#endif
240 240
241#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 241#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
242 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 242 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
243 { 243 {
244 .modalias = "ad1836", 244 .modalias = "ad183x",
245 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 245 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
246 .bus_num = 0, 246 .bus_num = 0,
247 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 247 .chip_select = 4,
248 .controller_data = &ad1836_spi_chip_info, 248 .controller_data = &ad1836_spi_chip_info,
249 }, 249 },
250#endif 250#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 68a27bccc7d4..c9e0e85629bf 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -35,12 +35,10 @@
35#include <asm/reboot.h> 35#include <asm/reboot.h>
36#include <asm/portmux.h> 36#include <asm/portmux.h>
37#include <asm/dpmc.h> 37#include <asm/dpmc.h>
38#ifdef CONFIG_REGULATOR_ADP_SWITCH 38#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
39#include <linux/regulator/adp_switch.h> 39#include <linux/regulator/fixed.h>
40#endif
41#ifdef CONFIG_REGULATOR_AD5398
42#include <linux/regulator/ad5398.h>
43#endif 40#endif
41#include <linux/regulator/machine.h>
44#include <linux/regulator/consumer.h> 42#include <linux/regulator/consumer.h>
45#include <linux/regulator/userspace-consumer.h> 43#include <linux/regulator/userspace-consumer.h>
46 44
@@ -264,7 +262,7 @@ static struct resource isp1362_hcd_resources[] = {
264 }, { 262 }, {
265 .start = IRQ_PF3, 263 .start = IRQ_PF3,
266 .end = IRQ_PF3, 264 .end = IRQ_PF3,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 265 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
268 }, 266 },
269}; 267};
270 268
@@ -418,7 +416,7 @@ static struct platform_nand_data bfin_plat_nand_data = {
418static struct resource bfin_plat_nand_resources = { 416static struct resource bfin_plat_nand_resources = {
419 .start = 0x20212000, 417 .start = 0x20212000,
420 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), 418 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
421 .flags = IORESOURCE_IO, 419 .flags = IORESOURCE_MEM,
422}; 420};
423 421
424static struct platform_device bfin_async_nand_device = { 422static struct platform_device bfin_async_nand_device = {
@@ -545,6 +543,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
545}; 543};
546#endif 544#endif
547 545
546#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
547 || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
548static struct bfin5xx_spi_chip adav801_spi_chip_info = {
549 .enable_dma = 0,
550 .bits_per_word = 8,
551};
552#endif
553
548#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) 554#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
549#include <linux/input/ad714x.h> 555#include <linux/input/ad714x.h>
550static struct bfin5xx_spi_chip ad7147_spi_chip_info = { 556static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
@@ -693,6 +699,65 @@ static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
693}; 699};
694#endif 700#endif
695 701
702#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
703static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
704 .enable_dma = 0,
705 .bits_per_word = 16,
706};
707#endif
708
709#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
710static unsigned short ad7816_platform_data[] = {
711 GPIO_PF4, /* rdwr_pin */
712 GPIO_PF5, /* convert_pin */
713 GPIO_PF7, /* busy_pin */
714 0,
715};
716
717static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
718 .enable_dma = 0,
719 .bits_per_word = 8,
720};
721#endif
722
723#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
724static unsigned long adt7310_platform_data[3] = {
725/* INT bound temperature alarm event. line 1 */
726 IRQ_PG4, IRQF_TRIGGER_LOW,
727/* CT bound temperature alarm event irq_flags. line 0 */
728 IRQF_TRIGGER_LOW,
729};
730
731static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
732 .enable_dma = 0,
733 .bits_per_word = 8,
734};
735#endif
736
737#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
738static unsigned short ad7298_platform_data[] = {
739 GPIO_PF7, /* busy_pin */
740 0,
741};
742
743static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
744 .enable_dma = 0,
745 .bits_per_word = 16,
746};
747#endif
748
749#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
750static unsigned long adt7316_spi_data[2] = {
751 IRQF_TRIGGER_LOW, /* interrupt flags */
752 GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
753};
754
755static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
756 .enable_dma = 0,
757 .bits_per_word = 8,
758};
759#endif
760
696#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 761#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
697#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 762#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
698 763
@@ -824,14 +889,12 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
824static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { 889static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
825 .enable_dma = 1, 890 .enable_dma = 1,
826 .bits_per_word = 8, 891 .bits_per_word = 8,
827 .cs_gpio = GPIO_PF10,
828}; 892};
829#endif 893#endif
830 894
831#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) 895#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
832static struct bfin5xx_spi_chip adf7021_spi_chip_info = { 896static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
833 .bits_per_word = 16, 897 .bits_per_word = 16,
834 .cs_gpio = GPIO_PF10,
835}; 898};
836 899
837#include <linux/spi/adf702x.h> 900#include <linux/spi/adf702x.h>
@@ -938,6 +1001,13 @@ static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
938}; 1001};
939#endif 1002#endif
940 1003
1004#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
1005static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
1006 .enable_dma = 0, /* use dma transfer with this chip*/
1007 .bits_per_word = 8,
1008};
1009#endif
1010
941static struct spi_board_info bfin_spi_board_info[] __initdata = { 1011static struct spi_board_info bfin_spi_board_info[] __initdata = {
942#if defined(CONFIG_MTD_M25P80) \ 1012#if defined(CONFIG_MTD_M25P80) \
943 || defined(CONFIG_MTD_M25P80_MODULE) 1013 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -982,7 +1052,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
982 .modalias = "ad183x", 1052 .modalias = "ad183x",
983 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1053 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
984 .bus_num = 0, 1054 .bus_num = 0,
985 .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ 1055 .chip_select = 4,
986 .platform_data = "ad1836", /* only includes chip name for the moment */ 1056 .platform_data = "ad1836", /* only includes chip name for the moment */
987 .controller_data = &ad1836_spi_chip_info, 1057 .controller_data = &ad1836_spi_chip_info,
988 .mode = SPI_MODE_3, 1058 .mode = SPI_MODE_3,
@@ -1000,6 +1070,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1000 }, 1070 },
1001#endif 1071#endif
1002 1072
1073#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
1074 {
1075 .modalias = "adav80x",
1076 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1077 .bus_num = 0,
1078 .chip_select = 1,
1079 .controller_data = &adav801_spi_chip_info,
1080 .mode = SPI_MODE_3,
1081 },
1082#endif
1083
1003#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) 1084#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
1004 { 1085 {
1005 .modalias = "ad714x_captouch", 1086 .modalias = "ad714x_captouch",
@@ -1018,6 +1099,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1018 .modalias = "ad2s90", 1099 .modalias = "ad2s90",
1019 .bus_num = 0, 1100 .bus_num = 0,
1020 .chip_select = 3, /* change it for your board */ 1101 .chip_select = 3, /* change it for your board */
1102 .mode = SPI_MODE_3,
1021 .platform_data = NULL, 1103 .platform_data = NULL,
1022 .controller_data = &ad2s90_spi_chip_info, 1104 .controller_data = &ad2s90_spi_chip_info,
1023 }, 1105 },
@@ -1044,6 +1126,67 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1044 }, 1126 },
1045#endif 1127#endif
1046 1128
1129#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
1130 {
1131 .modalias = "ad7314",
1132 .max_speed_hz = 1000000,
1133 .bus_num = 0,
1134 .chip_select = 4, /* CS, change it for your board */
1135 .controller_data = &ad7314_spi_chip_info,
1136 .mode = SPI_MODE_1,
1137 },
1138#endif
1139
1140#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
1141 {
1142 .modalias = "ad7818",
1143 .max_speed_hz = 1000000,
1144 .bus_num = 0,
1145 .chip_select = 4, /* CS, change it for your board */
1146 .platform_data = ad7816_platform_data,
1147 .controller_data = &ad7816_spi_chip_info,
1148 .mode = SPI_MODE_3,
1149 },
1150#endif
1151
1152#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
1153 {
1154 .modalias = "adt7310",
1155 .max_speed_hz = 1000000,
1156 .irq = IRQ_PG5, /* CT alarm event. Line 0 */
1157 .bus_num = 0,
1158 .chip_select = 4, /* CS, change it for your board */
1159 .platform_data = adt7310_platform_data,
1160 .controller_data = &adt7310_spi_chip_info,
1161 .mode = SPI_MODE_3,
1162 },
1163#endif
1164
1165#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
1166 {
1167 .modalias = "ad7298",
1168 .max_speed_hz = 1000000,
1169 .bus_num = 0,
1170 .chip_select = 4, /* CS, change it for your board */
1171 .platform_data = ad7298_platform_data,
1172 .controller_data = &ad7298_spi_chip_info,
1173 .mode = SPI_MODE_3,
1174 },
1175#endif
1176
1177#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
1178 {
1179 .modalias = "adt7316",
1180 .max_speed_hz = 1000000,
1181 .irq = IRQ_PG5, /* interrupt line */
1182 .bus_num = 0,
1183 .chip_select = 4, /* CS, change it for your board */
1184 .platform_data = adt7316_spi_data,
1185 .controller_data = &adt7316_spi_chip_info,
1186 .mode = SPI_MODE_3,
1187 },
1188#endif
1189
1047#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 1190#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1048 { 1191 {
1049 .modalias = "mmc_spi", 1192 .modalias = "mmc_spi",
@@ -1103,7 +1246,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1103 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 1246 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1104 .irq = IRQ_PF6, 1247 .irq = IRQ_PF6,
1105 .bus_num = 0, 1248 .bus_num = 0,
1106 .chip_select = 0, /* GPIO controlled SSEL */ 1249 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1107 .controller_data = &enc28j60_spi_chip_info, 1250 .controller_data = &enc28j60_spi_chip_info,
1108 .mode = SPI_MODE_0, 1251 .mode = SPI_MODE_0,
1109 }, 1252 },
@@ -1125,7 +1268,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1125 .modalias = "adf702x", 1268 .modalias = "adf702x",
1126 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ 1269 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1127 .bus_num = 0, 1270 .bus_num = 0,
1128 .chip_select = 0, /* GPIO controlled SSEL */ 1271 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1129 .controller_data = &adf7021_spi_chip_info, 1272 .controller_data = &adf7021_spi_chip_info,
1130 .platform_data = &adf7021_platform_data, 1273 .platform_data = &adf7021_platform_data,
1131 .mode = SPI_MODE_0, 1274 .mode = SPI_MODE_0,
@@ -1143,12 +1286,239 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1143 .mode = SPI_MODE_0, 1286 .mode = SPI_MODE_0,
1144 }, 1287 },
1145#endif 1288#endif
1289#if defined(CONFIG_AD7476) \
1290 || defined(CONFIG_AD7476_MODULE)
1291 {
1292 .modalias = "ad7476", /* Name of spi_driver for this device */
1293 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
1294 .bus_num = 0, /* Framework bus number */
1295 .chip_select = 1, /* Framework chip select. */
1296 .platform_data = NULL, /* No spi_driver specific config */
1297 .controller_data = &spi_ad7476_chip_info,
1298 .mode = SPI_MODE_3,
1299 },
1300#endif
1301#if defined(CONFIG_ADE7753) \
1302 || defined(CONFIG_ADE7753_MODULE)
1303 {
1304 .modalias = "ade7753",
1305 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1306 .bus_num = 0,
1307 .chip_select = 1, /* CS, change it for your board */
1308 .platform_data = NULL, /* No spi_driver specific config */
1309 .mode = SPI_MODE_1,
1310 },
1311#endif
1312#if defined(CONFIG_ADE7754) \
1313 || defined(CONFIG_ADE7754_MODULE)
1314 {
1315 .modalias = "ade7754",
1316 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1317 .bus_num = 0,
1318 .chip_select = 1, /* CS, change it for your board */
1319 .platform_data = NULL, /* No spi_driver specific config */
1320 .mode = SPI_MODE_1,
1321 },
1322#endif
1323#if defined(CONFIG_ADE7758) \
1324 || defined(CONFIG_ADE7758_MODULE)
1325 {
1326 .modalias = "ade7758",
1327 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1328 .bus_num = 0,
1329 .chip_select = 1, /* CS, change it for your board */
1330 .platform_data = NULL, /* No spi_driver specific config */
1331 .mode = SPI_MODE_1,
1332 },
1333#endif
1334#if defined(CONFIG_ADE7759) \
1335 || defined(CONFIG_ADE7759_MODULE)
1336 {
1337 .modalias = "ade7759",
1338 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1339 .bus_num = 0,
1340 .chip_select = 1, /* CS, change it for your board */
1341 .platform_data = NULL, /* No spi_driver specific config */
1342 .mode = SPI_MODE_1,
1343 },
1344#endif
1345#if defined(CONFIG_ADE7854_SPI) \
1346 || defined(CONFIG_ADE7854_SPI_MODULE)
1347 {
1348 .modalias = "ade7854",
1349 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1350 .bus_num = 0,
1351 .chip_select = 1, /* CS, change it for your board */
1352 .platform_data = NULL, /* No spi_driver specific config */
1353 .mode = SPI_MODE_3,
1354 },
1355#endif
1356#if defined(CONFIG_ADIS16060) \
1357 || defined(CONFIG_ADIS16060_MODULE)
1358 {
1359 .modalias = "adis16060_r",
1360 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1361 .bus_num = 0,
1362 .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
1363 .platform_data = NULL, /* No spi_driver specific config */
1364 .mode = SPI_MODE_0,
1365 },
1366 {
1367 .modalias = "adis16060_w",
1368 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1369 .bus_num = 0,
1370 .chip_select = 2, /* CS for write, change it for your board */
1371 .platform_data = NULL, /* No spi_driver specific config */
1372 .mode = SPI_MODE_1,
1373 },
1374#endif
1375#if defined(CONFIG_ADIS16130) \
1376 || defined(CONFIG_ADIS16130_MODULE)
1377 {
1378 .modalias = "adis16130",
1379 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1380 .bus_num = 0,
1381 .chip_select = 1, /* CS for read, change it for your board */
1382 .platform_data = NULL, /* No spi_driver specific config */
1383 .mode = SPI_MODE_3,
1384 },
1385#endif
1386#if defined(CONFIG_ADIS16201) \
1387 || defined(CONFIG_ADIS16201_MODULE)
1388 {
1389 .modalias = "adis16201",
1390 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1391 .bus_num = 0,
1392 .chip_select = 5, /* CS, change it for your board */
1393 .platform_data = NULL, /* No spi_driver specific config */
1394 .mode = SPI_MODE_3,
1395 .irq = IRQ_PF4,
1396 },
1397#endif
1398#if defined(CONFIG_ADIS16203) \
1399 || defined(CONFIG_ADIS16203_MODULE)
1400 {
1401 .modalias = "adis16203",
1402 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1403 .bus_num = 0,
1404 .chip_select = 5, /* CS, change it for your board */
1405 .platform_data = NULL, /* No spi_driver specific config */
1406 .mode = SPI_MODE_3,
1407 .irq = IRQ_PF4,
1408 },
1409#endif
1410#if defined(CONFIG_ADIS16204) \
1411 || defined(CONFIG_ADIS16204_MODULE)
1412 {
1413 .modalias = "adis16204",
1414 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1415 .bus_num = 0,
1416 .chip_select = 5, /* CS, change it for your board */
1417 .platform_data = NULL, /* No spi_driver specific config */
1418 .mode = SPI_MODE_3,
1419 .irq = IRQ_PF4,
1420 },
1421#endif
1422#if defined(CONFIG_ADIS16209) \
1423 || defined(CONFIG_ADIS16209_MODULE)
1424 {
1425 .modalias = "adis16209",
1426 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1427 .bus_num = 0,
1428 .chip_select = 5, /* CS, change it for your board */
1429 .platform_data = NULL, /* No spi_driver specific config */
1430 .mode = SPI_MODE_3,
1431 .irq = IRQ_PF4,
1432 },
1433#endif
1434#if defined(CONFIG_ADIS16220) \
1435 || defined(CONFIG_ADIS16220_MODULE)
1436 {
1437 .modalias = "adis16220",
1438 .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
1439 .bus_num = 0,
1440 .chip_select = 5, /* CS, change it for your board */
1441 .platform_data = NULL, /* No spi_driver specific config */
1442 .mode = SPI_MODE_3,
1443 .irq = IRQ_PF4,
1444 },
1445#endif
1446#if defined(CONFIG_ADIS16240) \
1447 || defined(CONFIG_ADIS16240_MODULE)
1448 {
1449 .modalias = "adis16240",
1450 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1451 .bus_num = 0,
1452 .chip_select = 5, /* CS, change it for your board */
1453 .platform_data = NULL, /* No spi_driver specific config */
1454 .mode = SPI_MODE_3,
1455 .irq = IRQ_PF4,
1456 },
1457#endif
1458#if defined(CONFIG_ADIS16260) \
1459 || defined(CONFIG_ADIS16260_MODULE)
1460 {
1461 .modalias = "adis16260",
1462 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1463 .bus_num = 0,
1464 .chip_select = 5, /* CS, change it for your board */
1465 .platform_data = NULL, /* No spi_driver specific config */
1466 .mode = SPI_MODE_3,
1467 .irq = IRQ_PF4,
1468 },
1469#endif
1470#if defined(CONFIG_ADIS16261) \
1471 || defined(CONFIG_ADIS16261_MODULE)
1472 {
1473 .modalias = "adis16261",
1474 .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
1475 .bus_num = 0,
1476 .chip_select = 1, /* CS, change it for your board */
1477 .platform_data = NULL, /* No spi_driver specific config */
1478 .mode = SPI_MODE_3,
1479 },
1480#endif
1481#if defined(CONFIG_ADIS16300) \
1482 || defined(CONFIG_ADIS16300_MODULE)
1483 {
1484 .modalias = "adis16300",
1485 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1486 .bus_num = 0,
1487 .chip_select = 5, /* CS, change it for your board */
1488 .platform_data = NULL, /* No spi_driver specific config */
1489 .mode = SPI_MODE_3,
1490 .irq = IRQ_PF4,
1491 },
1492#endif
1493#if defined(CONFIG_ADIS16350) \
1494 || defined(CONFIG_ADIS16350_MODULE)
1495 {
1496 .modalias = "adis16364",
1497 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1498 .bus_num = 0,
1499 .chip_select = 5, /* CS, change it for your board */
1500 .platform_data = NULL, /* No spi_driver specific config */
1501 .mode = SPI_MODE_3,
1502 .irq = IRQ_PF4,
1503 },
1504#endif
1505#if defined(CONFIG_ADIS16400) \
1506 || defined(CONFIG_ADIS16400_MODULE)
1507 {
1508 .modalias = "adis16400",
1509 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1510 .bus_num = 0,
1511 .chip_select = 1, /* CS, change it for your board */
1512 .platform_data = NULL, /* No spi_driver specific config */
1513 .mode = SPI_MODE_3,
1514 },
1515#endif
1146}; 1516};
1147 1517
1148#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 1518#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1149/* SPI controller data */ 1519/* SPI controller data */
1150static struct bfin5xx_spi_master bfin_spi0_info = { 1520static struct bfin5xx_spi_master bfin_spi0_info = {
1151 .num_chipselect = 8, 1521 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1152 .enable_dma = 1, /* master has the ability to do dma transfer */ 1522 .enable_dma = 1, /* master has the ability to do dma transfer */
1153 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1523 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1154}; 1524};
@@ -1773,12 +2143,6 @@ static struct regulator_init_data ad5398_regulator_data = {
1773 .consumer_supplies = &ad5398_consumer, 2143 .consumer_supplies = &ad5398_consumer,
1774}; 2144};
1775 2145
1776static struct ad5398_platform_data ad5398_i2c_platform_data = {
1777 .current_bits = 10,
1778 .current_offset = 4,
1779 .regulator_data = &ad5398_regulator_data,
1780};
1781
1782#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ 2146#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
1783 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) 2147 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
1784static struct platform_device ad5398_virt_consumer_device = { 2148static struct platform_device ad5398_virt_consumer_device = {
@@ -1811,7 +2175,34 @@ static struct platform_device ad5398_userspace_consumer_device = {
1811#endif 2175#endif
1812#endif 2176#endif
1813 2177
2178#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2179/* INT bound temperature alarm event. line 1 */
2180static unsigned long adt7410_platform_data[2] = {
2181 IRQ_PG4, IRQF_TRIGGER_LOW,
2182};
2183#endif
2184
2185#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2186/* INT bound temperature alarm event. line 1 */
2187static unsigned long adt7316_i2c_data[2] = {
2188 IRQF_TRIGGER_LOW, /* interrupt flags */
2189 GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
2190};
2191#endif
2192
1814static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 2193static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
2194#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
2195 {
2196 I2C_BOARD_INFO("ad1937", 0x04),
2197 },
2198#endif
2199
2200#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
2201 {
2202 I2C_BOARD_INFO("adav803", 0x10),
2203 },
2204#endif
2205
1815#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) 2206#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
1816 { 2207 {
1817 I2C_BOARD_INFO("ad7142_captouch", 0x2C), 2208 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
@@ -1843,12 +2234,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1843 { 2234 {
1844 I2C_BOARD_INFO("ad7414", 0x9), 2235 I2C_BOARD_INFO("ad7414", 0x9),
1845 .irq = IRQ_PG5, 2236 .irq = IRQ_PG5,
1846 /* 2237 .irq_flags = IRQF_TRIGGER_LOW,
1847 * platform_data pointer is borrwoed by the driver to
1848 * store custimer defined IRQ ALART level mode.
1849 * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid.
1850 */
1851 .platform_data = (void *)IRQF_TRIGGER_LOW,
1852 }, 2238 },
1853#endif 2239#endif
1854 2240
@@ -1856,12 +2242,56 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1856 { 2242 {
1857 I2C_BOARD_INFO("ad7417", 0xb), 2243 I2C_BOARD_INFO("ad7417", 0xb),
1858 .irq = IRQ_PG5, 2244 .irq = IRQ_PG5,
1859 /* 2245 .irq_flags = IRQF_TRIGGER_LOW,
1860 * platform_data pointer is borrwoed by the driver to 2246 .platform_data = (void *)GPIO_PF4,
1861 * store custimer defined IRQ ALART level mode. 2247 },
1862 * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. 2248#endif
1863 */ 2249
1864 .platform_data = (void *)IRQF_TRIGGER_LOW, 2250#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE)
2251 {
2252 I2C_BOARD_INFO("ade7854", 0x38),
2253 },
2254#endif
2255
2256#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE)
2257 {
2258 I2C_BOARD_INFO("adt75", 0x9),
2259 .irq = IRQ_PG5,
2260 .irq_flags = IRQF_TRIGGER_LOW,
2261 },
2262#endif
2263
2264#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE)
2265 {
2266 I2C_BOARD_INFO("adt7408", 0x18),
2267 .irq = IRQ_PG5,
2268 .irq_flags = IRQF_TRIGGER_LOW,
2269 },
2270#endif
2271
2272#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2273 {
2274 I2C_BOARD_INFO("adt7410", 0x48),
2275 /* CT critical temperature event. line 0 */
2276 .irq = IRQ_PG5,
2277 .irq_flags = IRQF_TRIGGER_LOW,
2278 .platform_data = (void *)&adt7410_platform_data,
2279 },
2280#endif
2281
2282#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE)
2283 {
2284 I2C_BOARD_INFO("ad7291", 0x20),
2285 .irq = IRQ_PG5,
2286 .irq_flags = IRQF_TRIGGER_LOW,
2287 },
2288#endif
2289
2290#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2291 {
2292 I2C_BOARD_INFO("adt7316", 0x48),
2293 .irq = IRQ_PG6,
2294 .platform_data = (void *)&adt7316_i2c_data,
1865 }, 2295 },
1866#endif 2296#endif
1867 2297
@@ -1917,7 +2347,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1917#endif 2347#endif
1918#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) 2348#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1919 { 2349 {
1920 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), 2350 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
1921 }, 2351 },
1922#endif 2352#endif
1923#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) 2353#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
@@ -1954,7 +2384,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1954#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) 2384#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
1955 { 2385 {
1956 I2C_BOARD_INFO("ad5398", 0xC), 2386 I2C_BOARD_INFO("ad5398", 0xC),
1957 .platform_data = (void *)&ad5398_i2c_platform_data, 2387 .platform_data = (void *)&ad5398_regulator_data,
1958 }, 2388 },
1959#endif 2389#endif
1960#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE) 2390#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
@@ -1963,6 +2393,16 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1963 .platform_data = (void *)&adp8860_pdata, 2393 .platform_data = (void *)&adp8860_pdata,
1964 }, 2394 },
1965#endif 2395#endif
2396#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
2397 {
2398 I2C_BOARD_INFO("adau1373", 0x1A),
2399 },
2400#endif
2401#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
2402 {
2403 I2C_BOARD_INFO("ad5252", 0x2e),
2404 },
2405#endif
1966}; 2406};
1967 2407
1968#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 2408#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -2147,50 +2587,38 @@ static struct platform_device bfin_ac97 = {
2147}; 2587};
2148#endif 2588#endif
2149 2589
2150#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) 2590#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
2151#define REGULATOR_ADP122 "adp122" 2591#define REGULATOR_ADP122 "adp122"
2152#define REGULATOR_ADP150 "adp150" 2592#define REGULATOR_ADP122_UV 2500000
2153 2593
2154static struct regulator_consumer_supply adp122_consumers = { 2594static struct regulator_consumer_supply adp122_consumers = {
2155 .supply = REGULATOR_ADP122, 2595 .supply = REGULATOR_ADP122,
2156}; 2596};
2157 2597
2158static struct regulator_consumer_supply adp150_consumers = { 2598static struct regulator_init_data adp_switch_regulator_data = {
2159 .supply = REGULATOR_ADP150, 2599 .constraints = {
2160}; 2600 .name = REGULATOR_ADP122,
2161 2601 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2162static struct regulator_init_data adp_switch_regulator_data[] = { 2602 .min_uV = REGULATOR_ADP122_UV,
2163 { 2603 .max_uV = REGULATOR_ADP122_UV,
2164 .constraints = { 2604 .min_uA = 0,
2165 .name = REGULATOR_ADP122, 2605 .max_uA = 300000,
2166 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2167 .min_uA = 0,
2168 .max_uA = 300000,
2169 },
2170 .num_consumer_supplies = 1, /* only 1 */
2171 .consumer_supplies = &adp122_consumers,
2172 .driver_data = (void *)GPIO_PF2, /* gpio port only */
2173 },
2174 {
2175 .constraints = {
2176 .name = REGULATOR_ADP150,
2177 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2178 .min_uA = 0,
2179 .max_uA = 150000,
2180 },
2181 .num_consumer_supplies = 1, /* only 1 */
2182 .consumer_supplies = &adp150_consumers,
2183 .driver_data = (void *)GPIO_PF3, /* gpio port only */
2184 }, 2606 },
2607 .num_consumer_supplies = 1, /* only 1 */
2608 .consumer_supplies = &adp122_consumers,
2185}; 2609};
2186 2610
2187static struct adp_switch_platform_data adp_switch_pdata = { 2611static struct fixed_voltage_config adp_switch_pdata = {
2188 .regulator_num = ARRAY_SIZE(adp_switch_regulator_data), 2612 .supply_name = REGULATOR_ADP122,
2189 .regulator_data = adp_switch_regulator_data, 2613 .microvolts = REGULATOR_ADP122_UV,
2614 .gpio = GPIO_PF2,
2615 .enable_high = 1,
2616 .enabled_at_boot = 0,
2617 .init_data = &adp_switch_regulator_data,
2190}; 2618};
2191 2619
2192static struct platform_device adp_switch_device = { 2620static struct platform_device adp_switch_device = {
2193 .name = "adp_switch", 2621 .name = "reg-fixed-voltage",
2194 .id = 0, 2622 .id = 0,
2195 .dev = { 2623 .dev = {
2196 .platform_data = &adp_switch_pdata, 2624 .platform_data = &adp_switch_pdata,
@@ -2216,27 +2644,26 @@ static struct platform_device adp122_userspace_consumer_device = {
2216 .platform_data = &adp122_userspace_comsumer_data, 2644 .platform_data = &adp122_userspace_comsumer_data,
2217 }, 2645 },
2218}; 2646};
2647#endif
2648#endif
2219 2649
2220static struct regulator_bulk_data adp150_bulk_data = { 2650#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2221 .supply = REGULATOR_ADP150, 2651 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2222};
2223 2652
2224static struct regulator_userspace_consumer_data adp150_userspace_comsumer_data = { 2653static struct resource iio_gpio_trigger_resources[] = {
2225 .name = REGULATOR_ADP150, 2654 [0] = {
2226 .num_supplies = 1, 2655 .start = IRQ_PF5,
2227 .supplies = &adp150_bulk_data, 2656 .end = IRQ_PF5,
2657 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
2658 },
2228}; 2659};
2229 2660
2230static struct platform_device adp150_userspace_consumer_device = { 2661static struct platform_device iio_gpio_trigger = {
2231 .name = "reg-userspace-consumer", 2662 .name = "iio_gpio_trigger",
2232 .id = 1, 2663 .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
2233 .dev = { 2664 .resource = iio_gpio_trigger_resources,
2234 .platform_data = &adp150_userspace_comsumer_data,
2235 },
2236}; 2665};
2237#endif 2666#endif
2238#endif
2239
2240 2667
2241static struct platform_device *stamp_devices[] __initdata = { 2668static struct platform_device *stamp_devices[] __initdata = {
2242 2669
@@ -2369,14 +2796,18 @@ static struct platform_device *stamp_devices[] __initdata = {
2369#endif 2796#endif
2370#endif 2797#endif
2371 2798
2372#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) 2799#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
2373 &adp_switch_device, 2800 &adp_switch_device,
2374#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \ 2801#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2375 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE) 2802 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2376 &adp122_userspace_consumer_device, 2803 &adp122_userspace_consumer_device,
2377 &adp150_userspace_consumer_device,
2378#endif 2804#endif
2379#endif 2805#endif
2806
2807#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2808 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2809 &iio_gpio_trigger,
2810#endif
2380}; 2811};
2381 2812
2382static int __init stamp_init(void) 2813static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 4f0a2e72ce4c..a4d62b5fc7ba 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
74}; 74};
75#endif 75#endif
76 76
77#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0, 79 .enable_dma = 0,
80 .bits_per_word = 16, 80 .bits_per_word = 16,
@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
113 }, 113 },
114#endif 114#endif
115 115
116#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 117 {
118 .modalias = "ad1836", 118 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 120 .bus_num = 0,
121 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 121 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info, 122 .controller_data = &ad1836_spi_chip_info,
123 }, 123 },
124#endif 124#endif
@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
230 }, { 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
234 }, 234 },
235}; 235};
236 236
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 6f56907a18c0..0323e6bacdae 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1071,50 +1071,6 @@
1071#define FPE 0x10 /* Force Parity Error On Transmit */ 1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */ 1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073 1073
1074/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1075/* SPI_CTL Masks */
1076#define TIMOD 0x0003 /* Transfer Initiate Mode */
1077#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1078#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1079#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1080#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1081#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1082#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1083#define PSSE 0x0010 /* Slave-Select Input Enable */
1084#define EMISO 0x0020 /* Enable MISO As Output */
1085#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1086#define LSBF 0x0200 /* LSB First */
1087#define CPHA 0x0400 /* Clock Phase */
1088#define CPOL 0x0800 /* Clock Polarity */
1089#define MSTR 0x1000 /* Master/Slave* */
1090#define WOM 0x2000 /* Write Open Drain Master */
1091#define SPE 0x4000 /* SPI Enable */
1092
1093/* SPI_FLG Masks */
1094#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1095#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1096#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1097#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1098#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1099#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1100#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1101#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1102#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1103#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1104#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1105#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1106#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1107#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1108
1109/* SPI_STAT Masks */
1110#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1111#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1112#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1113#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1114#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1115#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1116#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1117
1118/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1119/* TIMER_ENABLE Masks */ 1075/* TIMER_ENABLE Masks */
1120#define TIMEN0 0x0001 /* Enable Timer 0 */ 1076#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 1a1f65855b03..c6fb0a52f849 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -695,7 +695,7 @@ static struct platform_device bf538_spi_master0 = {
695}; 695};
696 696
697static struct bfin5xx_spi_master bf538_spi_master_info1 = { 697static struct bfin5xx_spi_master bf538_spi_master_info1 = {
698 .num_chipselect = 8, 698 .num_chipselect = 2,
699 .enable_dma = 1, /* master has the ability to do dma transfer */ 699 .enable_dma = 1, /* master has the ability to do dma transfer */
700 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 700 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
701}; 701};
@@ -711,7 +711,7 @@ static struct platform_device bf538_spi_master1 = {
711}; 711};
712 712
713static struct bfin5xx_spi_master bf538_spi_master_info2 = { 713static struct bfin5xx_spi_master bf538_spi_master_info2 = {
714 .num_chipselect = 8, 714 .num_chipselect = 2,
715 .enable_dma = 1, /* master has the ability to do dma transfer */ 715 .enable_dma = 1, /* master has the ability to do dma transfer */
716 .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, 716 .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
717}; 717};
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index fe43062b4975..7a8ac5f44204 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -32,6 +32,7 @@
32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ 33#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
34#define SYSCR 0xFFC00104 /* System Configuration registe */ 34#define SYSCR 0xFFC00104 /* System Configuration registe */
35#define SIC_RVECT 0xFFC00108
35#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ 36#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
36#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 37#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
37#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 38#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
@@ -1894,78 +1895,6 @@
1894#define PE14_P 0xE 1895#define PE14_P 0xE
1895#define PE15_P 0xF 1896#define PE15_P 0xF
1896 1897
1897
1898/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1899/* SPIx_CTL Masks */
1900#define TIMOD 0x0003 /* Transfer Initiate Mode */
1901#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1902#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1903#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1904#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1905#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1906#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1907#define PSSE 0x0010 /* Slave-Select Input Enable */
1908#define EMISO 0x0020 /* Enable MISO As Output */
1909#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1910#define LSBF 0x0200 /* LSB First */
1911#define CPHA 0x0400 /* Clock Phase */
1912#define CPOL 0x0800 /* Clock Polarity */
1913#define MSTR 0x1000 /* Master/Slave* */
1914#define WOM 0x2000 /* Write Open Drain Master */
1915#define SPE 0x4000 /* SPI Enable */
1916
1917/* SPIx_FLG Masks */
1918#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1919#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1920#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1921#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1922#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1923#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1924#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1925
1926#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1927#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1928#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1929#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1930#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1931#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1932#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1933
1934/* SPIx_FLG Bit Positions */
1935#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1936#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1937#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1938#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1939#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1940#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1941#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1942#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1943#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1944#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1945#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1946#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1947#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1948#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1949
1950/* SPIx_STAT Masks */
1951#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
1952#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
1953#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1954#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1955#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
1956#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1957#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
1958
1959/* SPIx_FLG Masks */
1960#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
1961#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
1962#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
1963#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
1964#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
1965#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
1966#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
1967
1968
1969/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1898/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1970/* EBIU_AMGCTL Masks */ 1899/* EBIU_AMGCTL Masks */
1971#define AMCKEN 0x0001 /* Enable CLKOUT */ 1900#define AMCKEN 0x0001 /* Enable CLKOUT */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 0c38eec9ade1..f0c0eef95ba8 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -753,6 +753,44 @@ static struct platform_device bf54x_sdh_device = {
753}; 753};
754#endif 754#endif
755 755
756#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
757unsigned short bfin_can_peripherals[] = {
758 P_CAN0_RX, P_CAN0_TX, 0
759};
760
761static struct resource bfin_can_resources[] = {
762 {
763 .start = 0xFFC02A00,
764 .end = 0xFFC02FFF,
765 .flags = IORESOURCE_MEM,
766 },
767 {
768 .start = IRQ_CAN0_RX,
769 .end = IRQ_CAN0_RX,
770 .flags = IORESOURCE_IRQ,
771 },
772 {
773 .start = IRQ_CAN0_TX,
774 .end = IRQ_CAN0_TX,
775 .flags = IORESOURCE_IRQ,
776 },
777 {
778 .start = IRQ_CAN0_ERROR,
779 .end = IRQ_CAN0_ERROR,
780 .flags = IORESOURCE_IRQ,
781 },
782};
783
784static struct platform_device bfin_can_device = {
785 .name = "bfin_can",
786 .num_resources = ARRAY_SIZE(bfin_can_resources),
787 .resource = bfin_can_resources,
788 .dev = {
789 .platform_data = &bfin_can_peripherals, /* Passed to driver */
790 },
791};
792#endif
793
756#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 794#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
757static struct mtd_partition para_partitions[] = { 795static struct mtd_partition para_partitions[] = {
758 { 796 {
@@ -928,7 +966,7 @@ static struct resource bfin_spi1_resource[] = {
928 966
929/* SPI controller data */ 967/* SPI controller data */
930static struct bfin5xx_spi_master bf54x_spi_master_info0 = { 968static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
931 .num_chipselect = 3, 969 .num_chipselect = 4,
932 .enable_dma = 1, /* master has the ability to do dma transfer */ 970 .enable_dma = 1, /* master has the ability to do dma transfer */
933 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 971 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
934}; 972};
@@ -944,7 +982,7 @@ static struct platform_device bf54x_spi_master0 = {
944}; 982};
945 983
946static struct bfin5xx_spi_master bf54x_spi_master_info1 = { 984static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
947 .num_chipselect = 3, 985 .num_chipselect = 4,
948 .enable_dma = 1, /* master has the ability to do dma transfer */ 986 .enable_dma = 1, /* master has the ability to do dma transfer */
949 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 987 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
950}; 988};
@@ -1152,6 +1190,11 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
1152#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 1190#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1153 &para_flash_device, 1191 &para_flash_device,
1154#endif 1192#endif
1193
1194#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1195 &bfin_can_device,
1196#endif
1197
1155}; 1198};
1156 1199
1157static int __init cm_bf548_init(void) 1200static int __init cm_bf548_init(void)
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 56682a36e42d..216e26999af9 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -837,8 +837,12 @@ static struct platform_device bfin_atapi_device = {
837#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 837#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
838static struct mtd_partition partition_info[] = { 838static struct mtd_partition partition_info[] = {
839 { 839 {
840 .name = "linux kernel(nand)", 840 .name = "bootloader(nand)",
841 .offset = 0, 841 .offset = 0,
842 .size = 0x80000,
843 }, {
844 .name = "linux kernel(nand)",
845 .offset = MTDPART_OFS_APPEND,
842 .size = 4 * 1024 * 1024, 846 .size = 4 * 1024 * 1024,
843 }, 847 },
844 { 848 {
@@ -901,7 +905,7 @@ static struct platform_device bf54x_sdh_device = {
901static struct mtd_partition ezkit_partitions[] = { 905static struct mtd_partition ezkit_partitions[] = {
902 { 906 {
903 .name = "bootloader(nor)", 907 .name = "bootloader(nor)",
904 .size = 0x40000, 908 .size = 0x80000,
905 .offset = 0, 909 .offset = 0,
906 }, { 910 }, {
907 .name = "linux kernel(nor)", 911 .name = "linux kernel(nor)",
@@ -943,7 +947,7 @@ static struct platform_device ezkit_flash_device = {
943static struct mtd_partition bfin_spi_flash_partitions[] = { 947static struct mtd_partition bfin_spi_flash_partitions[] = {
944 { 948 {
945 .name = "bootloader(spi)", 949 .name = "bootloader(spi)",
946 .size = 0x00040000, 950 .size = 0x00080000,
947 .offset = 0, 951 .offset = 0,
948 .mask_flags = MTD_CAP_ROM 952 .mask_flags = MTD_CAP_ROM
949 }, { 953 }, {
@@ -966,8 +970,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
966}; 970};
967#endif 971#endif
968 972
969#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 973#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
970 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 974 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
971static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 975static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
972 .enable_dma = 0, 976 .enable_dma = 0,
973 .bits_per_word = 16, 977 .bits_per_word = 16,
@@ -1023,13 +1027,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1023 .mode = SPI_MODE_3, 1027 .mode = SPI_MODE_3,
1024 }, 1028 },
1025#endif 1029#endif
1026#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 1030#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1027 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 1031 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1028 { 1032 {
1029 .modalias = "ad1836", 1033 .modalias = "ad183x",
1030 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1034 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1031 .bus_num = 1, 1035 .bus_num = 1,
1032 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 1036 .chip_select = 4,
1033 .controller_data = &ad1836_spi_chip_info, 1037 .controller_data = &ad1836_spi_chip_info,
1034 }, 1038 },
1035#endif 1039#endif
@@ -1107,7 +1111,7 @@ static struct resource bfin_spi1_resource[] = {
1107 1111
1108/* SPI controller data */ 1112/* SPI controller data */
1109static struct bfin5xx_spi_master bf54x_spi_master_info0 = { 1113static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
1110 .num_chipselect = 3, 1114 .num_chipselect = 4,
1111 .enable_dma = 1, /* master has the ability to do dma transfer */ 1115 .enable_dma = 1, /* master has the ability to do dma transfer */
1112 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1116 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1113}; 1117};
@@ -1123,7 +1127,7 @@ static struct platform_device bf54x_spi_master0 = {
1123}; 1127};
1124 1128
1125static struct bfin5xx_spi_master bf54x_spi_master_info1 = { 1129static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
1126 .num_chipselect = 3, 1130 .num_chipselect = 4,
1127 .enable_dma = 1, /* master has the ability to do dma transfer */ 1131 .enable_dma = 1, /* master has the ability to do dma transfer */
1128 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 1132 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1129}; 1133};
@@ -1206,6 +1210,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1206 .platform_data = (void *)&adxl34x_info, 1210 .platform_data = (void *)&adxl34x_info,
1207 }, 1211 },
1208#endif 1212#endif
1213#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
1214 {
1215 I2C_BOARD_INFO("ad5252", 0x2f),
1216 },
1217#endif
1209}; 1218};
1210#endif 1219#endif
1211 1220
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 039a6d9d38f3..888b9cc0b822 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -63,6 +63,7 @@ int channel2irq(unsigned int channel)
63 break; 63 break;
64 case CH_SPORT1_TX: 64 case CH_SPORT1_TX:
65 ret_irq = IRQ_SPORT1_TX; 65 ret_irq = IRQ_SPORT1_TX;
66 break;
66 case CH_SPI0: 67 case CH_SPI0:
67 ret_irq = IRQ_SPI0; 68 ret_irq = IRQ_SPI0;
68 break; 69 break;
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 0c16067df4f3..deaf5d6542d5 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -40,6 +40,8 @@
40 40
41/* SIC Registers */ 41/* SIC Registers */
42 42
43#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
44#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
43#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) 45#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
44#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) 46#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
45#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) 47#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 7866197f5485..78f91103f175 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -35,6 +35,7 @@
35 35
36/* SIC Registers */ 36/* SIC Registers */
37 37
38#define SIC_RVECT 0xffc00108
38#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ 39#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
39#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ 40#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
40#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ 41#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
@@ -2061,56 +2062,6 @@
2061#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ 2062#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
2062#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ 2063#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
2063 2064
2064/* Bit masks for SPIx_BAUD */
2065
2066#define SPI_BAUD 0xffff /* Baud Rate */
2067
2068/* Bit masks for SPIx_CTL */
2069
2070#define SPE 0x4000 /* SPI Enable */
2071#define WOM 0x2000 /* Write Open Drain Master */
2072#define MSTR 0x1000 /* Master Mode */
2073#define CPOL 0x800 /* Clock Polarity */
2074#define CPHA 0x400 /* Clock Phase */
2075#define LSBF 0x200 /* LSB First */
2076#define SIZE 0x100 /* Size of Words */
2077#define EMISO 0x20 /* Enable MISO Output */
2078#define PSSE 0x10 /* Slave-Select Enable */
2079#define GM 0x8 /* Get More Data */
2080#define SZ 0x4 /* Send Zero */
2081#define TIMOD 0x3 /* Transfer Initiation Mode */
2082
2083/* Bit masks for SPIx_FLG */
2084
2085#define FLS1 0x2 /* Slave Select Enable 1 */
2086#define FLS2 0x4 /* Slave Select Enable 2 */
2087#define FLS3 0x8 /* Slave Select Enable 3 */
2088#define FLG1 0x200 /* Slave Select Value 1 */
2089#define FLG2 0x400 /* Slave Select Value 2 */
2090#define FLG3 0x800 /* Slave Select Value 3 */
2091
2092/* Bit masks for SPIx_STAT */
2093
2094#define TXCOL 0x40 /* Transmit Collision Error */
2095#define RXS 0x20 /* RDBR Data Buffer Status */
2096#define RBSY 0x10 /* Receive Error */
2097#define TXS 0x8 /* TDBR Data Buffer Status */
2098#define TXE 0x4 /* Transmission Error */
2099#define MODF 0x2 /* Mode Fault Error */
2100#define SPIF 0x1 /* SPI Finished */
2101
2102/* Bit masks for SPIx_TDBR */
2103
2104#define TDBR 0xffff /* Transmit Data Buffer */
2105
2106/* Bit masks for SPIx_RDBR */
2107
2108#define RDBR 0xffff /* Receive Data Buffer */
2109
2110/* Bit masks for SPIx_SHADOW */
2111
2112#define SHADOW 0xffff /* RDBR Shadow */
2113
2114/* ************************************************ */ 2065/* ************************************************ */
2115/* The TWI bit masks fields are from the ADSP-BF538 */ 2066/* The TWI bit masks fields are from the ADSP-BF538 */
2116/* and they have not been verified as the final */ 2067/* and they have not been verified as the final */
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 35b6d124c1e3..0b1c20f14fe0 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -302,7 +302,7 @@ static struct platform_nand_data bfin_plat_nand_data = {
302static struct resource bfin_plat_nand_resources = { 302static struct resource bfin_plat_nand_resources = {
303 .start = 0x24000000, 303 .start = 0x24000000,
304 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), 304 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
305 .flags = IORESOURCE_IO, 305 .flags = IORESOURCE_MEM,
306}; 306};
307 307
308static struct platform_device bfin_async_nand_device = { 308static struct platform_device bfin_async_nand_device = {
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index e127aedc1d7f..087b6b05cc73 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
72}; 72};
73#endif 73#endif
74 74
75#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 75#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
76static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 76static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
77 .enable_dma = 0, 77 .enable_dma = 0,
78 .bits_per_word = 16, 78 .bits_per_word = 16,
@@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
111 }, 111 },
112#endif 112#endif
113 113
114#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 114#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
115 { 115 {
116 .modalias = "ad1836", 116 .modalias = "ad183x",
117 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 117 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
118 .bus_num = 0, 118 .bus_num = 0,
119 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 119 .chip_select = 4,
120 .controller_data = &ad1836_spi_chip_info, 120 .controller_data = &ad1836_spi_chip_info,
121 }, 121 },
122#endif 122#endif
@@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = {
278 }, { 278 }, {
279 .start = IRQ_PF47, 279 .start = IRQ_PF47,
280 .end = IRQ_PF47, 280 .end = IRQ_PF47,
281 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 281 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
282 }, 282 },
283}; 283};
284 284
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9b93e2f95791..ab7a487975fd 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -14,6 +14,7 @@
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/delay.h>
17#include <asm/dma.h> 18#include <asm/dma.h>
18#include <asm/bfin5xx_spi.h> 19#include <asm/bfin5xx_spi.h>
19#include <asm/portmux.h> 20#include <asm/portmux.h>
@@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = {
74 }, { 75 }, {
75 .start = IRQ_PF8, 76 .start = IRQ_PF8,
76 .end = IRQ_PF8, 77 .end = IRQ_PF8,
77 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
78 }, 79 },
79}; 80};
80 81
@@ -274,8 +275,8 @@ static struct platform_device ezkit_flash_device = {
274}; 275};
275#endif 276#endif
276 277
277#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 278#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
278 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 279 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
279static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 280static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
280 .enable_dma = 0, 281 .enable_dma = 0,
281 .bits_per_word = 16, 282 .bits_per_word = 16,
@@ -328,14 +329,16 @@ static struct platform_device bfin_spi0_device = {
328#endif 329#endif
329 330
330static struct spi_board_info bfin_spi_board_info[] __initdata = { 331static struct spi_board_info bfin_spi_board_info[] __initdata = {
331#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 332#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
332 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 333 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
333 { 334 {
334 .modalias = "ad1836", 335 .modalias = "ad183x",
335 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 336 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
336 .bus_num = 0, 337 .bus_num = 0,
337 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 338 .chip_select = 4,
339 .platform_data = "ad1836", /* only includes chip name for the moment */
338 .controller_data = &ad1836_spi_chip_info, 340 .controller_data = &ad1836_spi_chip_info,
341 .mode = SPI_MODE_3,
339 }, 342 },
340#endif 343#endif
341#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 344#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -377,8 +380,8 @@ static struct platform_device bfin_device_gpiokeys = {
377#include <linux/i2c-gpio.h> 380#include <linux/i2c-gpio.h>
378 381
379static struct i2c_gpio_platform_data i2c_gpio_data = { 382static struct i2c_gpio_platform_data i2c_gpio_data = {
380 .sda_pin = 1, 383 .sda_pin = GPIO_PF1,
381 .scl_pin = 0, 384 .scl_pin = GPIO_PF0,
382 .sda_is_open_drain = 0, 385 .sda_is_open_drain = 0,
383 .scl_is_open_drain = 0, 386 .scl_is_open_drain = 0,
384 .udelay = 40, 387 .udelay = 40,
@@ -420,6 +423,30 @@ static struct platform_device bfin_dpmc = {
420 }, 423 },
421}; 424};
422 425
426#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
427static struct platform_device bfin_i2s = {
428 .name = "bfin-i2s",
429 .id = CONFIG_SND_BF5XX_SPORT_NUM,
430 /* TODO: add platform data here */
431};
432#endif
433
434#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
435static struct platform_device bfin_tdm = {
436 .name = "bfin-tdm",
437 .id = CONFIG_SND_BF5XX_SPORT_NUM,
438 /* TODO: add platform data here */
439};
440#endif
441
442#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
443static struct platform_device bfin_ac97 = {
444 .name = "bfin-ac97",
445 .id = CONFIG_SND_BF5XX_SPORT_NUM,
446 /* TODO: add platform data here */
447};
448#endif
449
423static struct platform_device *ezkit_devices[] __initdata = { 450static struct platform_device *ezkit_devices[] __initdata = {
424 451
425 &bfin_dpmc, 452 &bfin_dpmc,
@@ -467,6 +494,18 @@ static struct platform_device *ezkit_devices[] __initdata = {
467#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 494#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
468 &ezkit_flash_device, 495 &ezkit_flash_device,
469#endif 496#endif
497
498#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
499 &bfin_i2s,
500#endif
501
502#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
503 &bfin_tdm,
504#endif
505
506#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
507 &bfin_ac97,
508#endif
470}; 509};
471 510
472static int __init ezkit_init(void) 511static int __init ezkit_init(void)
@@ -484,6 +523,17 @@ static int __init ezkit_init(void)
484 SSYNC(); 523 SSYNC();
485#endif 524#endif
486 525
526#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
527 bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
528 bfin_write_FIO0_FLAG_S(1 << 15);
529 SSYNC();
530 /*
531 * This initialization lasts for approximately 4500 MCLKs.
532 * MCLK = 12.288MHz
533 */
534 udelay(400);
535#endif
536
487 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 537 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
488 return 0; 538 return 0;
489} 539}
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index c6a4c8f2d37b..78ecb50bafc8 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -18,9 +18,9 @@
18#include <linux/miscdevice.h> 18#include <linux/miscdevice.h>
19#include <linux/module.h> 19#include <linux/module.h>
20 20
21#define CMD_COREB_START 2 21#define CMD_COREB_START _IO('b', 0)
22#define CMD_COREB_STOP 3 22#define CMD_COREB_STOP _IO('b', 1)
23#define CMD_COREB_RESET 4 23#define CMD_COREB_RESET _IO('b', 2)
24 24
25static long 25static long
26coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 26coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
@@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
29 29
30 switch (cmd) { 30 switch (cmd) {
31 case CMD_COREB_START: 31 case CMD_COREB_START:
32 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); 32 bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
33 break; 33 break;
34 case CMD_COREB_STOP: 34 case CMD_COREB_STOP:
35 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); 35 bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); 36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
37 break; 37 break;
38 case CMD_COREB_RESET: 38 case CMD_COREB_RESET:
@@ -74,3 +74,4 @@ module_exit(bf561_coreb_exit);
74 74
75MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); 75MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
76MODULE_DESCRIPTION("BF561 Core B Support"); 76MODULE_DESCRIPTION("BF561 Core B Support");
77MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 67d6bdcd3fa8..6c7dc58c018c 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -24,29 +24,16 @@
24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
26 26
27#define SIC_IWR0 SICA_IWR0 27/* Weird muxer funcs which pick SIC regs from IMASK base */
28#define SIC_IWR1 SICA_IWR1 28#define __SIC_MUX(base, x) ((base) + ((x) << 2))
29#define SIC_IAR0 SICA_IAR0 29#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
30#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 30#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
31#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 31#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
32#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 32#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
33#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 33#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
34 34#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
35#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
38#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
39#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
40#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
41
42#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
44#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
46#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
47#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
48#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
49#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
50 37
51#define BFIN_UART_NR_PORTS 1 38#define BFIN_UART_NR_PORTS 1
52 39
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index cc0416a5fa02..2bab99152495 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -30,49 +30,41 @@
30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
31#define bfin_read_CHIPID() bfin_read32(CHIPID) 31#define bfin_read_CHIPID() bfin_read32(CHIPID)
32 32
33/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
34#define bfin_read_SWRST() bfin_read_SICA_SWRST()
35#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
36#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
37#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
38
39/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 33/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
40#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 34#define bfin_read_SWRST() bfin_read16(SWRST)
41#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 35#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
42#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) 36#define bfin_read_SYSCR() bfin_read16(SYSCR)
43#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) 37#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
44#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) 38#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
45#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) 39#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
46#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) 40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
47#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) 41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
48#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) 42#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
49#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) 43#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
50#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) 44#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
51#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) 45#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
52#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) 46#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
53#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) 47#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
54#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) 48#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
55#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) 49#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
56#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) 50#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
57#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) 51#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
58#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) 52#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
59#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) 53#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
60#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) 54#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
61#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) 55#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
62#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) 56#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
63#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) 57#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
64#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) 58#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
65#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) 59#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
66#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) 60#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
67#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) 61#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
68#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) 62#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
69#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) 63#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
70#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) 64#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
71#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) 65#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
72#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) 66#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
73#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) 67#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
74#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
75#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
76 68
77/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 69/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
78#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) 70#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 2674f0097576..79e048d452e0 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -28,32 +28,29 @@
28#define CHIPID 0xFFC00014 /* Chip ID Register */ 28#define CHIPID 0xFFC00014 /* Chip ID Register */
29 29
30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
31#define SWRST SICA_SWRST
32#define SYSCR SICA_SYSCR
33#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) 31#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
34#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) 32#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
35#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) 33#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
36#define RESET_SOFTWARE (SWRST_OCCURRED) 34#define RESET_SOFTWARE (SWRST_OCCURRED)
37 35
38/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 36/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
39#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 37#define SWRST 0xFFC00100 /* Software Reset register */
40#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 38#define SYSCR 0xFFC00104 /* System Reset Configuration register */
41#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ 39#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
42#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ 40#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
43#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ 41#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
44#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ 42#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
45#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ 43#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
46#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ 44#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
47#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ 45#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
48#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ 46#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
49#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ 47#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
50#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ 48#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
51#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ 49#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
52#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ 50#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
53#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ 51#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
54#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ 52#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
55#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ 53#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
56#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
57 54
58/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 55/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
59#define SICB_SWRST 0xFFC01100 /* reserved */ 56#define SICB_SWRST 0xFFC01100 /* reserved */
@@ -1271,63 +1268,6 @@
1271#define PF14_P 14 1268#define PF14_P 14
1272#define PF15_P 15 1269#define PF15_P 15
1273 1270
1274/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1275
1276/* SPI_CTL Masks */
1277#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1278#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1279#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1280#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1281#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1282#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1283#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1284#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1285#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1286#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1287#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1288#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1289
1290/* SPI_FLG Masks */
1291#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1292#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1293#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1294#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1295#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1296#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1297#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1298#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1299#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1300#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1301#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1302#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1303#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1304#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1305
1306/* SPI_FLG Bit Positions */
1307#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1308#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1309#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1310#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1311#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1312#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1313#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1314#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1315#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1316#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1317#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1318#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1319#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1320#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1321
1322/* SPI_STAT Masks */
1323#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1324#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1325#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1326#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1327#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1328#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1329#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1330
1331/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1271/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1332 1272
1333/* AMGCTL Masks */ 1273/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index b4424172ad9e..7ee9262fe132 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -13,7 +13,7 @@
13void __init program_IAR(void) 13void __init program_IAR(void)
14{ 14{
15 /* Program the IAR0 Register with the configured priority */ 15 /* Program the IAR0 Register with the configured priority */
16 bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | 16 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | 17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | 18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | 19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
@@ -22,7 +22,7 @@ void __init program_IAR(void)
22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | 22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); 23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
24 24
25 bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | 25 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | 26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | 27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | 28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
@@ -31,7 +31,7 @@ void __init program_IAR(void)
31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | 31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); 32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
33 33
34 bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | 34 bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | 35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | 36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | 37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
@@ -40,7 +40,7 @@ void __init program_IAR(void)
40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | 40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); 41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
42 42
43 bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | 43 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | 44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | 45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | 46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
@@ -49,7 +49,7 @@ void __init program_IAR(void)
49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | 49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); 50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
51 51
52 bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | 52 bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | 53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | 54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | 55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
@@ -58,7 +58,7 @@ void __init program_IAR(void)
58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | 58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); 59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
60 60
61 bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | 61 bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | 62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | 63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | 64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
@@ -67,7 +67,7 @@ void __init program_IAR(void)
67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | 67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); 68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
69 69
70 bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | 70 bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | 71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | 72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | 73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
@@ -76,7 +76,7 @@ void __init program_IAR(void)
76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | 76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); 77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
78 78
79 bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | 79 bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | 80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | 81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | 82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 3b9a4bf7dacc..f540ed1257d6 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
52void __cpuinit platform_secondary_init(unsigned int cpu) 52void __cpuinit platform_secondary_init(unsigned int cpu)
53{ 53{
54 /* Clone setup for peripheral interrupt sources from CoreA. */ 54 /* Clone setup for peripheral interrupt sources from CoreA. */
55 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); 55 bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
56 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); 56 bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
57 SSYNC(); 57 SSYNC();
58 58
59 /* Clone setup for IARs from CoreA. */ 59 /* Clone setup for IARs from CoreA. */
60 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); 60 bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
61 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); 61 bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
62 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); 62 bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
63 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); 63 bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
64 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); 64 bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
65 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); 65 bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
66 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); 66 bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
67 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); 67 bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
68 bfin_write_SICB_IWR0(IWR_DISABLE_ALL); 68 bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL); 69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
70 SSYNC(); 70 SSYNC();
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
86 86
87 spin_lock(&boot_lock); 87 spin_lock(&boot_lock);
88 88
89 if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { 89 if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
90 /* CoreB already running, sending ipi to wakeup it */ 90 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else { 92 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ 93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); 94 bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
95 SSYNC(); 95 SSYNC();
96 } 96 }
97 97
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 5969d86836a5..9cfdd49a3127 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -292,13 +292,7 @@ ENTRY(_do_hibernate)
292#ifdef SIC_IMASK 292#ifdef SIC_IMASK
293 PM_SYS_PUSH(SIC_IMASK) 293 PM_SYS_PUSH(SIC_IMASK)
294#endif 294#endif
295#ifdef SICA_IMASK0 295#ifdef SIC_IAR0
296 PM_SYS_PUSH(SICA_IMASK0)
297#endif
298#ifdef SICA_IMASK1
299 PM_SYS_PUSH(SICA_IMASK1)
300#endif
301#ifdef SIC_IAR2
302 PM_SYS_PUSH(SIC_IAR0) 296 PM_SYS_PUSH(SIC_IAR0)
303 PM_SYS_PUSH(SIC_IAR1) 297 PM_SYS_PUSH(SIC_IAR1)
304 PM_SYS_PUSH(SIC_IAR2) 298 PM_SYS_PUSH(SIC_IAR2)
@@ -321,17 +315,6 @@ ENTRY(_do_hibernate)
321 PM_SYS_PUSH(SIC_IAR11) 315 PM_SYS_PUSH(SIC_IAR11)
322#endif 316#endif
323 317
324#ifdef SICA_IAR0
325 PM_SYS_PUSH(SICA_IAR0)
326 PM_SYS_PUSH(SICA_IAR1)
327 PM_SYS_PUSH(SICA_IAR2)
328 PM_SYS_PUSH(SICA_IAR3)
329 PM_SYS_PUSH(SICA_IAR4)
330 PM_SYS_PUSH(SICA_IAR5)
331 PM_SYS_PUSH(SICA_IAR6)
332 PM_SYS_PUSH(SICA_IAR7)
333#endif
334
335#ifdef SIC_IWR 318#ifdef SIC_IWR
336 PM_SYS_PUSH(SIC_IWR) 319 PM_SYS_PUSH(SIC_IWR)
337#endif 320#endif
@@ -344,12 +327,6 @@ ENTRY(_do_hibernate)
344#ifdef SIC_IWR2 327#ifdef SIC_IWR2
345 PM_SYS_PUSH(SIC_IWR2) 328 PM_SYS_PUSH(SIC_IWR2)
346#endif 329#endif
347#ifdef SICA_IWR0
348 PM_SYS_PUSH(SICA_IWR0)
349#endif
350#ifdef SICA_IWR1
351 PM_SYS_PUSH(SICA_IWR1)
352#endif
353 330
354#ifdef PINT0_ASSIGN 331#ifdef PINT0_ASSIGN
355 PM_SYS_PUSH(PINT0_MASK_SET) 332 PM_SYS_PUSH(PINT0_MASK_SET)
@@ -750,12 +727,6 @@ ENTRY(_do_hibernate)
750 PM_SYS_POP(PINT0_MASK_SET) 727 PM_SYS_POP(PINT0_MASK_SET)
751#endif 728#endif
752 729
753#ifdef SICA_IWR1
754 PM_SYS_POP(SICA_IWR1)
755#endif
756#ifdef SICA_IWR0
757 PM_SYS_POP(SICA_IWR0)
758#endif
759#ifdef SIC_IWR2 730#ifdef SIC_IWR2
760 PM_SYS_POP(SIC_IWR2) 731 PM_SYS_POP(SIC_IWR2)
761#endif 732#endif
@@ -769,17 +740,6 @@ ENTRY(_do_hibernate)
769 PM_SYS_POP(SIC_IWR) 740 PM_SYS_POP(SIC_IWR)
770#endif 741#endif
771 742
772#ifdef SICA_IAR0
773 PM_SYS_POP(SICA_IAR7)
774 PM_SYS_POP(SICA_IAR6)
775 PM_SYS_POP(SICA_IAR5)
776 PM_SYS_POP(SICA_IAR4)
777 PM_SYS_POP(SICA_IAR3)
778 PM_SYS_POP(SICA_IAR2)
779 PM_SYS_POP(SICA_IAR1)
780 PM_SYS_POP(SICA_IAR0)
781#endif
782
783#ifdef SIC_IAR8 743#ifdef SIC_IAR8
784 PM_SYS_POP(SIC_IAR11) 744 PM_SYS_POP(SIC_IAR11)
785 PM_SYS_POP(SIC_IAR10) 745 PM_SYS_POP(SIC_IAR10)
@@ -797,17 +757,11 @@ ENTRY(_do_hibernate)
797#ifdef SIC_IAR3 757#ifdef SIC_IAR3
798 PM_SYS_POP(SIC_IAR3) 758 PM_SYS_POP(SIC_IAR3)
799#endif 759#endif
800#ifdef SIC_IAR2 760#ifdef SIC_IAR0
801 PM_SYS_POP(SIC_IAR2) 761 PM_SYS_POP(SIC_IAR2)
802 PM_SYS_POP(SIC_IAR1) 762 PM_SYS_POP(SIC_IAR1)
803 PM_SYS_POP(SIC_IAR0) 763 PM_SYS_POP(SIC_IAR0)
804#endif 764#endif
805#ifdef SICA_IMASK1
806 PM_SYS_POP(SICA_IMASK1)
807#endif
808#ifdef SICA_IMASK0
809 PM_SYS_POP(SICA_IMASK0)
810#endif
811#ifdef SIC_IMASK 765#ifdef SIC_IMASK
812 PM_SYS_POP(SIC_IMASK) 766 PM_SYS_POP(SIC_IMASK)
813#endif 767#endif
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index af1bffa21dc1..2ca915ee181f 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -889,6 +889,66 @@ ENTRY(_ret_from_exception)
889 rts; 889 rts;
890ENDPROC(_ret_from_exception) 890ENDPROC(_ret_from_exception)
891 891
892#if defined(CONFIG_PREEMPT)
893
894ENTRY(_up_to_irq14)
895#if ANOMALY_05000281 || ANOMALY_05000461
896 r0.l = lo(SAFE_USER_INSTRUCTION);
897 r0.h = hi(SAFE_USER_INSTRUCTION);
898 reti = r0;
899#endif
900
901#ifdef CONFIG_DEBUG_HWERR
902 /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
903 r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
904#else
905 /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
906 r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
907#endif
908 sti r0;
909
910 p0.l = lo(EVT14);
911 p0.h = hi(EVT14);
912 p1.l = _evt_up_evt14;
913 p1.h = _evt_up_evt14;
914 [p0] = p1;
915 csync;
916
917 raise 14;
9181:
919 jump 1b;
920ENDPROC(_up_to_irq14)
921
922ENTRY(_evt_up_evt14)
923#ifdef CONFIG_DEBUG_HWERR
924 r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
925 sti r0;
926#else
927 cli r0;
928#endif
929#ifdef CONFIG_TRACE_IRQFLAGS
930 [--sp] = rets;
931 sp += -12;
932 call _trace_hardirqs_off;
933 sp += 12;
934 rets = [sp++];
935#endif
936 [--sp] = RETI;
937 SP += 4;
938
939 /* restore normal evt14 */
940 p0.l = lo(EVT14);
941 p0.h = hi(EVT14);
942 p1.l = _evt_evt14;
943 p1.h = _evt_evt14;
944 [p0] = p1;
945 csync;
946
947 rts;
948ENDPROC(_evt_up_evt14)
949
950#endif
951
892#ifdef CONFIG_IPIPE 952#ifdef CONFIG_IPIPE
893 953
894_resume_kernel_from_int: 954_resume_kernel_from_int:
@@ -902,8 +962,54 @@ _resume_kernel_from_int:
902 ( r7:4, p5:3 ) = [sp++]; 962 ( r7:4, p5:3 ) = [sp++];
903 rets = [sp++]; 963 rets = [sp++];
904 rts 964 rts
965#elif defined(CONFIG_PREEMPT)
966
967_resume_kernel_from_int:
968 /* check preempt_count */
969 r7 = sp;
970 r4.l = lo(ALIGN_PAGE_MASK);
971 r4.h = hi(ALIGN_PAGE_MASK);
972 r7 = r7 & r4;
973 p5 = r7;
974 r7 = [p5 + TI_PREEMPT];
975 cc = r7 == 0x0;
976 if !cc jump .Lreturn_to_kernel;
977.Lneed_schedule:
978 r7 = [p5 + TI_FLAGS];
979 r4.l = lo(_TIF_WORK_MASK);
980 r4.h = hi(_TIF_WORK_MASK);
981 r7 = r7 & r4;
982 cc = BITTST(r7, TIF_NEED_RESCHED);
983 if !cc jump .Lreturn_to_kernel;
984 /*
985 * let schedule done at level 15, otherwise sheduled process will run
986 * at high level and block low level interrupt
987 */
988 r6 = reti; /* save reti */
989 r5.l = .Lkernel_schedule;
990 r5.h = .Lkernel_schedule;
991 reti = r5;
992 rti;
993.Lkernel_schedule:
994 [--sp] = rets;
995 sp += -12;
996 pseudo_long_call _preempt_schedule_irq, p4;
997 sp += 12;
998 rets = [sp++];
999
1000 [--sp] = rets;
1001 sp += -12;
1002 /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
1003 pseudo_long_call _up_to_irq14, p4;
1004 sp += 12;
1005 rets = [sp++];
1006
1007 reti = r6; /* restore reti so that origin process can return to interrupted point */
1008
1009 jump .Lneed_schedule;
905#else 1010#else
906#define _resume_kernel_from_int 2f 1011
1012#define _resume_kernel_from_int .Lreturn_to_kernel
907#endif 1013#endif
908 1014
909ENTRY(_return_from_int) 1015ENTRY(_return_from_int)
@@ -913,7 +1019,7 @@ ENTRY(_return_from_int)
913 p2.h = hi(ILAT); 1019 p2.h = hi(ILAT);
914 r0 = [p2]; 1020 r0 = [p2];
915 cc = bittst (r0, EVT_IVG15_P); 1021 cc = bittst (r0, EVT_IVG15_P);
916 if cc jump 2f; 1022 if cc jump .Lreturn_to_kernel;
917 1023
918 /* if not return to user mode, get out */ 1024 /* if not return to user mode, get out */
919 p2.l = lo(IPEND); 1025 p2.l = lo(IPEND);
@@ -945,7 +1051,7 @@ ENTRY(_return_from_int)
945 STI r0; 1051 STI r0;
946 raise 15; /* raise evt15 to do signal or reschedule */ 1052 raise 15; /* raise evt15 to do signal or reschedule */
947 rti; 1053 rti;
9482: 1054.Lreturn_to_kernel:
949 rts; 1055 rts;
950ENDPROC(_return_from_int) 1056ENDPROC(_return_from_int)
951 1057
@@ -1631,6 +1737,7 @@ ENTRY(_sys_call_table)
1631 .long _sys_fanotify_init 1737 .long _sys_fanotify_init
1632 .long _sys_fanotify_mark 1738 .long _sys_fanotify_mark
1633 .long _sys_prlimit64 1739 .long _sys_prlimit64
1740 .long _sys_cacheflush
1634 1741
1635 .rept NR_syscalls-(.-_sys_call_table)/4 1742 .rept NR_syscalls-(.-_sys_call_table)/4
1636 .long _sys_ni_syscall 1743 .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index cee62cf4acd4..2df37db3b49b 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -116,7 +116,24 @@ __common_int_entry:
116 cc = r0 == 0; 116 cc = r0 == 0;
117 if cc jump .Lcommon_restore_context; 117 if cc jump .Lcommon_restore_context;
118#else /* CONFIG_IPIPE */ 118#else /* CONFIG_IPIPE */
119
120#ifdef CONFIG_PREEMPT
121 r7 = sp;
122 r4.l = lo(ALIGN_PAGE_MASK);
123 r4.h = hi(ALIGN_PAGE_MASK);
124 r7 = r7 & r4;
125 p5 = r7;
126 r7 = [p5 + TI_PREEMPT]; /* get preempt count */
127 r7 += 1; /* increment it */
128 [p5 + TI_PREEMPT] = r7;
129#endif
119 pseudo_long_call _do_irq, p2; 130 pseudo_long_call _do_irq, p2;
131
132#ifdef CONFIG_PREEMPT
133 r7 += -1;
134 [p5 + TI_PREEMPT] = r7; /* restore preempt count */
135#endif
136
120 SP += 12; 137 SP += 12;
121#endif /* CONFIG_IPIPE */ 138#endif /* CONFIG_IPIPE */
122 pseudo_long_call _return_from_int, p2; 139 pseudo_long_call _return_from_int, p2;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index eaece5f84e42..da7e3c63746b 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -511,7 +511,7 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
511 int i, irq = 0; 511 int i, irq = 0;
512 u32 status = bfin_read_EMAC_SYSTAT(); 512 u32 status = bfin_read_EMAC_SYSTAT();
513 513
514 for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) 514 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
515 if (status & (1L << i)) { 515 if (status & (1L << i)) {
516 irq = IRQ_MAC_PHYINT + i; 516 irq = IRQ_MAC_PHYINT + i;
517 break; 517 break;
@@ -529,8 +529,9 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
529 } else 529 } else
530 printk(KERN_ERR 530 printk(KERN_ERR
531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" 531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", 532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
533 __func__, __FILE__, __LINE__); 533 "(EMAC_SYSTAT=0x%X)\n",
534 __func__, __FILE__, __LINE__, status);
534} 535}
535#endif 536#endif
536 537
@@ -1298,7 +1299,7 @@ void do_irq(int vec, struct pt_regs *fp)
1298 } else { 1299 } else {
1299 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1300 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1300 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1301 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1301#if defined(SIC_ISR0) || defined(SICA_ISR0) 1302#if defined(SIC_ISR0)
1302 unsigned long sic_status[3]; 1303 unsigned long sic_status[3];
1303 1304
1304 if (smp_processor_id()) { 1305 if (smp_processor_id()) {
@@ -1378,7 +1379,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1378 if (likely(vec == EVT_IVTMR_P)) 1379 if (likely(vec == EVT_IVTMR_P))
1379 irq = IRQ_CORETMR; 1380 irq = IRQ_CORETMR;
1380 else { 1381 else {
1381#if defined(SIC_ISR0) || defined(SICA_ISR0) 1382#if defined(SIC_ISR0)
1382 unsigned long sic_status[3]; 1383 unsigned long sic_status[3];
1383 1384
1384 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1385 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index bb4e8fff4b55..f8435cd36c7c 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -158,5 +158,8 @@ void __init_refok free_initmem(void)
158 free_init_pages("unused kernel memory", 158 free_init_pages("unused kernel memory",
159 (unsigned long)(&__init_begin), 159 (unsigned long)(&__init_begin),
160 (unsigned long)(&__init_end)); 160 (unsigned long)(&__init_end));
161
162 if (memory_start == (unsigned long)(&__init_end))
163 memory_start = (unsigned long)(&__init_begin);
161#endif 164#endif
162} 165}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 13:43:13 -0500