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authorGraf Yang <graf.yang@analog.com>2009-01-07 10:14:39 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:39 -0500
commita0dcfb16e606ca095eb1e9e789aff5e41e9adb1a (patch)
treeb36a7e02f79a4b76af3f85d982a1fb07445fc727 /arch/blackfin
parent7419a327f6264bef869b195497aaf03b72ca17b7 (diff)
Blackfin arch: Fix bug - IrDA SIR build failed for BF533.
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h7
-rw-r--r--arch/blackfin/mach-bf533/include/mach/dma.h4
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h8
3 files changed, 13 insertions, 6 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index d80971b4e3aa..045184f81a29 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -44,6 +44,13 @@
44 44
45#define BFIN_UART_NR_PORTS 1 45#define BFIN_UART_NR_PORTS 1
46 46
47#define CH_UART_RX CH_UART0_RX
48#define CH_UART_TX CH_UART0_TX
49
50#define IRQ_UART_ERROR IRQ_UART0_ERROR
51#define IRQ_UART_RX IRQ_UART0_RX
52#define IRQ_UART_TX IRQ_UART0_TX
53
47#define OFFSET_THR 0x00 /* Transmit Holding register */ 54#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */ 55#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 56#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
index d689522b2bfb..fb34934c5ba8 100644
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ b/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -16,8 +16,8 @@
16#define CH_SPORT1_RX 3 16#define CH_SPORT1_RX 3
17#define CH_SPORT1_TX 4 17#define CH_SPORT1_TX 4
18#define CH_SPI 5 18#define CH_SPI 5
19#define CH_UART_RX 6 19#define CH_UART0_RX 6
20#define CH_UART_TX 7 20#define CH_UART0_TX 7
21#define CH_MEM_STREAM0_DEST 8 /* TX */ 21#define CH_MEM_STREAM0_DEST 8 /* TX */
22#define CH_MEM_STREAM0_SRC 9 /* RX */ 22#define CH_MEM_STREAM0_SRC 9 /* RX */
23#define CH_MEM_STREAM1_DEST 10 /* TX */ 23#define CH_MEM_STREAM1_DEST 10 /* TX */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 5aa38e5da6b7..e7dd315159df 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -90,16 +90,16 @@ Core Emulation **
90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ 90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ 91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ 92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
93#define IRQ_UART_ERROR 13 /*UART Error Interrupt */ 93#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
94#define IRQ_RTC 14 /*RTC Interrupt */ 94#define IRQ_RTC 14 /*RTC Interrupt */
95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ 95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ 96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ 97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ 98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ 99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
101#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ 101#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
102#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ 102#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
103#define IRQ_TMR0 23 /*Timer 0 */ 103#define IRQ_TMR0 23 /*Timer 0 */
104#define IRQ_TMR1 24 /*Timer 1 */ 104#define IRQ_TMR1 24 /*Timer 1 */
105#define IRQ_TMR2 25 /*Timer 2 */ 105#define IRQ_TMR2 25 /*Timer 2 */