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authorAndreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>2010-11-24 17:15:16 -0500
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:25 -0500
commit3ea9f2bf5a3b91ba18af9f25bfc9a32677ea47d8 (patch)
treef98aad3dbffc108c538b9587040ed02bbe1650d3 /arch/blackfin
parentd57bc0feaa958bc8a6a0b9d3a29f78c699e50d2a (diff)
Blackfin: DNP5370: new board port
Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/configs/DNP5370_defconfig121
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig6
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c418
4 files changed, 546 insertions, 0 deletions
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
new file mode 100644
index 000000000000..0ebc7d9aa426
--- /dev/null
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -0,0 +1,121 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="DNP5370"
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EMBEDDED=y
9CONFIG_SLOB=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_CFQ is not set
12CONFIG_BF537=y
13CONFIG_BF_REV_0_3=y
14CONFIG_DNP5370=y
15CONFIG_IRQ_ERROR=7
16# CONFIG_CYCLES_CLOCKSOURCE is not set
17CONFIG_C_CDPRIO=y
18CONFIG_C_AMBEN_B0_B1_B2=y
19CONFIG_PM=y
20# CONFIG_SUSPEND is not set
21CONFIG_NET=y
22CONFIG_PACKET=y
23CONFIG_UNIX=y
24CONFIG_INET=y
25CONFIG_IP_PNP=y
26CONFIG_IP_PNP_RARP=y
27CONFIG_SYN_COOKIES=y
28# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
29# CONFIG_INET_XFRM_MODE_TUNNEL is not set
30# CONFIG_INET_XFRM_MODE_BEET is not set
31# CONFIG_INET_LRO is not set
32# CONFIG_INET_DIAG is not set
33# CONFIG_IPV6 is not set
34CONFIG_LLC2=y
35CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
36CONFIG_MTD=y
37CONFIG_MTD_DEBUG=y
38CONFIG_MTD_DEBUG_VERBOSE=1
39CONFIG_MTD_PARTITIONS=y
40CONFIG_MTD_CHAR=y
41CONFIG_MTD_BLOCK=y
42CONFIG_NFTL=y
43CONFIG_NFTL_RW=y
44CONFIG_MTD_CFI=y
45CONFIG_MTD_CFI_AMDSTD=y
46CONFIG_MTD_ROM=y
47CONFIG_MTD_ABSENT=y
48CONFIG_MTD_COMPLEX_MAPPINGS=y
49CONFIG_MTD_PHYSMAP=y
50CONFIG_MTD_UCLINUX=y
51CONFIG_MTD_PLATRAM=y
52CONFIG_MTD_DATAFLASH=y
53CONFIG_MTD_BLOCK2MTD=y
54CONFIG_MTD_NAND=y
55CONFIG_MTD_NAND_PLATFORM=y
56CONFIG_BLK_DEV_LOOP=y
57CONFIG_BLK_DEV_RAM=y
58# CONFIG_MISC_DEVICES is not set
59CONFIG_NETDEVICES=y
60CONFIG_DAVICOM_PHY=y
61CONFIG_NET_ETHERNET=y
62CONFIG_BFIN_MAC=y
63# CONFIG_NETDEV_1000 is not set
64# CONFIG_NETDEV_10000 is not set
65# CONFIG_WLAN is not set
66# CONFIG_INPUT is not set
67# CONFIG_SERIO is not set
68# CONFIG_BFIN_DMA_INTERFACE is not set
69# CONFIG_VT is not set
70# CONFIG_DEVKMEM is not set
71CONFIG_BFIN_JTAG_COMM=y
72CONFIG_BFIN_JTAG_COMM_CONSOLE=y
73CONFIG_SERIAL_BFIN=y
74CONFIG_SERIAL_BFIN_CONSOLE=y
75CONFIG_SERIAL_BFIN_UART0=y
76CONFIG_LEGACY_PTY_COUNT=64
77# CONFIG_HW_RANDOM is not set
78CONFIG_I2C=y
79CONFIG_I2C_CHARDEV=y
80CONFIG_I2C_BLACKFIN_TWI=y
81CONFIG_SPI=y
82CONFIG_SPI_BFIN=y
83CONFIG_SPI_SPIDEV=y
84CONFIG_GPIOLIB=y
85CONFIG_GPIO_SYSFS=y
86CONFIG_SENSORS_LM75=y
87# CONFIG_USB_SUPPORT is not set
88CONFIG_MMC=y
89CONFIG_MMC_SPI=y
90CONFIG_DMADEVICES=y
91CONFIG_EXT2_FS=y
92CONFIG_EXT2_FS_XATTR=y
93# CONFIG_DNOTIFY is not set
94CONFIG_MSDOS_FS=y
95CONFIG_VFAT_FS=y
96CONFIG_FAT_DEFAULT_CODEPAGE=850
97CONFIG_JFFS2_FS=y
98CONFIG_CRAMFS=y
99CONFIG_ROMFS_FS=y
100CONFIG_ROMFS_BACKED_BY_BOTH=y
101# CONFIG_NETWORK_FILESYSTEMS is not set
102CONFIG_NLS_CODEPAGE_437=y
103CONFIG_NLS_CODEPAGE_850=y
104CONFIG_NLS_ISO8859_1=y
105CONFIG_DEBUG_KERNEL=y
106CONFIG_DEBUG_SHIRQ=y
107CONFIG_DETECT_HUNG_TASK=y
108CONFIG_DEBUG_OBJECTS=y
109CONFIG_DEBUG_LOCK_ALLOC=y
110CONFIG_DEBUG_KOBJECT=y
111CONFIG_DEBUG_INFO=y
112CONFIG_DEBUG_VM=y
113CONFIG_DEBUG_MEMORY_INIT=y
114CONFIG_DEBUG_LIST=y
115# CONFIG_RCU_CPU_STALL_DETECTOR is not set
116CONFIG_SYSCTL_SYSCALL_CHECK=y
117CONFIG_PAGE_POISONING=y
118# CONFIG_FTRACE is not set
119CONFIG_DEBUG_DOUBLEFAULT=y
120CONFIG_CPLB_INFO=y
121CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
39 help 39 help
40 Board supply package for CSP Minotaur 40 Board supply package for CSP Minotaur
41 41
42config DNP5370
43 bool "SSV Dil/NetPC DNP/5370"
44 depends on (BF537)
45 help
46 Board supply package for DNP/5370 DIL64 module
47
42endchoice 48endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
9obj-$(CONFIG_PNAV10) += pnav10.o 9obj-$(CONFIG_PNAV10) += pnav10.o
10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o 10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
11obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..e1e9ea02ad89
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,418 @@
1/*
2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
3 *
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
6 *
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/plat-ram.h>
22#include <linux/mtd/physmap.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/i2c.h>
28#include <linux/spi/mmc_spi.h>
29#include <linux/phy.h>
30#include <asm/dma.h>
31#include <asm/bfin5xx_spi.h>
32#include <asm/reboot.h>
33#include <asm/portmux.h>
34#include <asm/dpmc.h>
35
36/*
37 * Name the Board for the /proc/cpuinfo
38 */
39const char bfin_board_name[] = "DNP/5370";
40#define FLASH_MAC 0x202f0000
41#define CONFIG_MTD_PHYSMAP_LEN 0x300000
42
43#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44static struct platform_device rtc_device = {
45 .name = "rtc-bfin",
46 .id = -1,
47};
48#endif
49
50#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51#include <linux/bfin_mac.h>
52static const unsigned short bfin_mac_peripherals[] = P_RMII0;
53
54static struct bfin_phydev_platform_data bfin_phydev_data[] = {
55 {
56 .addr = 1,
57 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
58 },
59};
60
61static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
62 .phydev_number = 1,
63 .phydev_data = bfin_phydev_data,
64 .phy_mode = PHY_INTERFACE_MODE_RMII,
65 .mac_peripherals = bfin_mac_peripherals,
66};
67
68static struct platform_device bfin_mii_bus = {
69 .name = "bfin_mii_bus",
70 .dev = {
71 .platform_data = &bfin_mii_bus_data,
72 }
73};
74
75static struct platform_device bfin_mac_device = {
76 .name = "bfin_mac",
77 .dev = {
78 .platform_data = &bfin_mii_bus,
79 }
80};
81#endif
82
83#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
84static struct mtd_partition asmb_flash_partitions[] = {
85 {
86 .name = "bootloader(nor)",
87 .size = 0x30000,
88 .offset = 0,
89 }, {
90 .name = "linux kernel and rootfs(nor)",
91 .size = 0x300000 - 0x30000 - 0x10000,
92 .offset = MTDPART_OFS_APPEND,
93 }, {
94 .name = "MAC address(nor)",
95 .size = 0x10000,
96 .offset = MTDPART_OFS_APPEND,
97 .mask_flags = MTD_WRITEABLE,
98 }
99};
100
101static struct physmap_flash_data asmb_flash_data = {
102 .width = 1,
103 .parts = asmb_flash_partitions,
104 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
105};
106
107static struct resource asmb_flash_resource = {
108 .start = 0x20000000,
109 .end = 0x202fffff,
110 .flags = IORESOURCE_MEM,
111};
112
113/* 4 MB NOR flash attached to async memory banks 0-2,
114 * therefore only 3 MB visible.
115 */
116static struct platform_device asmb_flash_device = {
117 .name = "physmap-flash",
118 .id = 0,
119 .dev = {
120 .platform_data = &asmb_flash_data,
121 },
122 .num_resources = 1,
123 .resource = &asmb_flash_resource,
124};
125#endif
126
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128
129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
130
131#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
132
133static int bfin_mmc_spi_init(struct device *dev,
134 irqreturn_t (*detect_int)(int, void *), void *data)
135{
136 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
137 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
138}
139
140static void bfin_mmc_spi_exit(struct device *dev, void *data)
141{
142 free_irq(MMC_SPI_CARD_DETECT_INT, data);
143}
144
145static struct bfin5xx_spi_chip mmc_spi_chip_info = {
146 .enable_dma = 0, /* use no dma transfer with this chip*/
147 .bits_per_word = 8,
148};
149
150static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
151 .init = bfin_mmc_spi_init,
152 .exit = bfin_mmc_spi_exit,
153 .detect_delay = 100, /* msecs */
154};
155#endif
156
157#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
158/* This mapping is for at45db642 it has 1056 page size,
159 * partition size and offset should be page aligned
160 */
161static struct mtd_partition bfin_spi_dataflash_partitions[] = {
162 {
163 .name = "JFFS2 dataflash(nor)",
164#ifdef CONFIG_MTD_PAGESIZE_1024
165 .offset = 0x40000,
166 .size = 0x7C0000,
167#else
168 .offset = 0x0,
169 .size = 0x840000,
170#endif
171 }
172};
173
174static struct flash_platform_data bfin_spi_dataflash_data = {
175 .name = "mtd_dataflash",
176 .parts = bfin_spi_dataflash_partitions,
177 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
178 .type = "mtd_dataflash",
179};
180
181static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
182 .enable_dma = 0, /* use no dma transfer with this chip*/
183 .bits_per_word = 8,
184};
185#endif
186
187static struct spi_board_info bfin_spi_board_info[] __initdata = {
188/* SD/MMC card reader at SPI bus */
189#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
190 {
191 .modalias = "mmc_spi",
192 .max_speed_hz = 20000000,
193 .bus_num = 0,
194 .chip_select = 1,
195 .platform_data = &bfin_mmc_spi_pdata,
196 .controller_data = &mmc_spi_chip_info,
197 .mode = SPI_MODE_3,
198 },
199#endif
200
201/* 8 Megabyte Atmel NOR flash chip at SPI bus */
202#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
203 {
204 .modalias = "mtd_dataflash",
205 .max_speed_hz = 16700000,
206 .bus_num = 0,
207 .chip_select = 2,
208 .platform_data = &bfin_spi_dataflash_data,
209 .controller_data = &spi_dataflash_chip_info,
210 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
211 },
212#endif
213};
214
215/* SPI controller data */
216/* SPI (0) */
217static struct resource bfin_spi0_resource[] = {
218 [0] = {
219 .start = SPI0_REGBASE,
220 .end = SPI0_REGBASE + 0xFF,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = CH_SPI,
225 .end = CH_SPI,
226 .flags = IORESOURCE_DMA,
227 },
228 [2] = {
229 .start = IRQ_SPI,
230 .end = IRQ_SPI,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct bfin5xx_spi_master spi_bfin_master_info = {
236 .num_chipselect = 8,
237 .enable_dma = 1, /* master has the ability to do dma transfer */
238 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
239};
240
241static struct platform_device spi_bfin_master_device = {
242 .name = "bfin-spi",
243 .id = 0, /* Bus number */
244 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
245 .resource = bfin_spi0_resource,
246 .dev = {
247 .platform_data = &spi_bfin_master_info, /* Passed to driver */
248 },
249};
250#endif
251
252#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
253#ifdef CONFIG_SERIAL_BFIN_UART0
254static struct resource bfin_uart0_resources[] = {
255 {
256 .start = UART0_THR,
257 .end = UART0_GCTL+2,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = IRQ_UART0_RX,
262 .end = IRQ_UART0_RX+1,
263 .flags = IORESOURCE_IRQ,
264 },
265 {
266 .start = IRQ_UART0_ERROR,
267 .end = IRQ_UART0_ERROR,
268 .flags = IORESOURCE_IRQ,
269 },
270 {
271 .start = CH_UART0_TX,
272 .end = CH_UART0_TX,
273 .flags = IORESOURCE_DMA,
274 },
275 {
276 .start = CH_UART0_RX,
277 .end = CH_UART0_RX,
278 .flags = IORESOURCE_DMA,
279 },
280};
281
282static unsigned short bfin_uart0_peripherals[] = {
283 P_UART0_TX, P_UART0_RX, 0
284};
285
286static struct platform_device bfin_uart0_device = {
287 .name = "bfin-uart",
288 .id = 0,
289 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
290 .resource = bfin_uart0_resources,
291 .dev = {
292 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
293 },
294};
295#endif
296
297#ifdef CONFIG_SERIAL_BFIN_UART1
298static struct resource bfin_uart1_resources[] = {
299 {
300 .start = UART1_THR,
301 .end = UART1_GCTL+2,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX+1,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_ERROR,
311 .end = IRQ_UART1_ERROR,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324};
325
326static unsigned short bfin_uart1_peripherals[] = {
327 P_UART1_TX, P_UART1_RX, 0
328};
329
330static struct platform_device bfin_uart1_device = {
331 .name = "bfin-uart",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
334 .resource = bfin_uart1_resources,
335 .dev = {
336 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
337 },
338};
339#endif
340#endif
341
342#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
343static struct resource bfin_twi0_resource[] = {
344 [0] = {
345 .start = TWI0_REGBASE,
346 .end = TWI0_REGBASE + 0xff,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = IRQ_TWI,
351 .end = IRQ_TWI,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device i2c_bfin_twi_device = {
357 .name = "i2c-bfin-twi",
358 .id = 0,
359 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
360 .resource = bfin_twi0_resource,
361};
362#endif
363
364static struct platform_device *dnp5370_devices[] __initdata = {
365
366#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
367#ifdef CONFIG_SERIAL_BFIN_UART0
368 &bfin_uart0_device,
369#endif
370#ifdef CONFIG_SERIAL_BFIN_UART1
371 &bfin_uart1_device,
372#endif
373#endif
374
375#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
376 &asmb_flash_device,
377#endif
378
379#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
380 &bfin_mii_bus,
381 &bfin_mac_device,
382#endif
383
384#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
385 &spi_bfin_master_device,
386#endif
387
388#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
389 &i2c_bfin_twi_device,
390#endif
391
392#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
393 &rtc_device,
394#endif
395
396};
397
398static int __init dnp5370_init(void)
399{
400 printk(KERN_INFO "DNP/5370: registering device resources\n");
401 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
402 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
403 ARRAY_SIZE(bfin_spi_board_info));
404 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
405 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
406 return 0;
407}
408arch_initcall(dnp5370_init);
409
410/*
411 * Currently the MAC address is saved in Flash by U-Boot
412 */
413void bfin_get_ether_addr(char *addr)
414{
415 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
416 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
417}
418EXPORT_SYMBOL(bfin_get_ether_addr);
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