Merge branch 'master' into x86/memblock

Conflicts & resolutions: * arch/x86/xen/setup.c dc91c728fd "xen: allow extra memory to be in multiple regions" 24aa07882b "memblock, x86: Replace memblock_x86_reserve/free..." conflicted on xen_add_extra_mem() updates. The resolution is trivial as the latter just want to replace memblock_x86_reserve_range() with memblock_reserve(). * drivers/pci/intel-iommu.c 166e9278a3f "x86/ia64: intel-iommu: move to drivers/iommu/" 5dfe8660a3d "bootmem: Replace work_with_active_regions() with..." conflicted as the former moved the file under drivers/iommu/. Resolved by applying the chnages from the latter on the moved file. * mm/Kconfig 6661672053a "memblock: add NO_BOOTMEM config symbol" c378ddd53f9 "memblock, x86: Make ARCH_DISCARD_MEMBLOCK a config option" conflicted trivially. Both added config options. Just letting both add their own options resolves the conflict. * mm/memblock.c d1f0ece6cdc "mm/memblock.c: small function definition fixes" ed7b56a799c "memblock: Remove memblock_memory_can_coalesce()" confliected. The former updates function removed by the latter. Resolution is trivial. Signed-off-by: Tejun Heo <tj@kernel.org>
author: Tejun Heo <tj@kernel.org> 2011-11-28 12:46:22 -0500
committer: Tejun Heo <tj@kernel.org> 2011-11-28 12:46:22 -0500
commit: d4bbf7e7759afc172e2bfbc5c416324590049cdd (patch)
tree: 7eab5ee5481cd3dcf1162329fec827177640018a /arch/blackfin
parent: a150439c4a97db379f0ed6faa46fbbb6e7bf3cb2 (diff)
parent: 401d0069cb344f401bc9d264c31db55876ff78c0 (diff)
134 files changed, 2137 insertions, 2382 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d619b17c4413..abe5a9e85148 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -248,10 +248,6 @@ config HOTPLUG_CPU
        depends on SMP && HOTPLUG
        default y
-config HAVE_LEGACY_PER_CPU_AREA
-        def_bool y
-        depends on SMP
 config BF_REV_MIN
        int
        default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
@@ -953,6 +949,16 @@ config BFIN_GPTIMERS
          To compile this driver as a module, choose M here: the module
          will be called gptimers.
+config HAVE_PWM
+        tristate "Enable PWM API support"
+        depends on BFIN_GPTIMERS
+        help
+          Enable support for the Pulse Width Modulation framework (as
+          found in linux/pwm.h).
+          To compile this driver as a module, choose M here: the module
+          will be called pwm.
 choice
        prompt "Uncached DMA region"
        default DMA_UNCACHED_1M
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 56151b5dbc44..0e6d841b5d01 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -4,7 +4,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
@@ -40,7 +39,6 @@ CONFIG_EBIU_MODEVAL=0x1
 CONFIG_EBIU_FCTLVAL=0x6
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -55,7 +53,6 @@ CONFIG_IP_PNP=y
 CONFIG_CAN=m
 CONFIG_CAN_RAW=m
 CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
 CONFIG_CAN_BFIN=m
 CONFIG_IRDA=m
 CONFIG_IRLAN=m
@@ -67,7 +64,6 @@ CONFIG_BFIN_SIR3=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_FW_LOADER=m
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -105,12 +101,12 @@ CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_AD7877=m
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -163,6 +159,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OTG_BLACKLIST_HUB=y
 CONFIG_USB_MON=y
 CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_BLACKFIN=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK=m
@@ -185,8 +182,6 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
 CONFIG_CIFS=y
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
@@ -196,7 +191,6 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
@@ -206,5 +200,4 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 1c0a82a10591..d7ff2aee3fbc 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -58,13 +58,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=m
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 9e7c5379d3ff..5a0625aad6a0 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,5 +1,49 @@
 include include/asm-generic/Kbuild.asm
+generic-y += auxvec.h
+generic-y += bitsperlong.h
+generic-y += bugs.h
+generic-y += cputime.h
+generic-y += current.h
+generic-y += device.h
+generic-y += div64.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += fb.h
+generic-y += futex.h
+generic-y += hw_irq.h
+generic-y += ioctl.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += local64.h
+generic-y += local.h
+generic-y += mman.h
+generic-y += msgbuf.h
+generic-y += mutex.h
+generic-y += param.h
+generic-y += percpu.h
+generic-y += pgalloc.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += setup.h
+generic-y += shmbuf.h
+generic-y += shmparam.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += statfs.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += topology.h
+generic-y += types.h
+generic-y += ucontext.h
+generic-y += unaligned.h
+generic-y += user.h
+generic-y += xor.h
 header-y += bfin_sport.h
 header-y += cachectl.h
 header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index e48508957160..54c6e2887e9f 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -1,126 +1,33 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef __ARCH_BLACKFIN_ATOMIC__
 #define __ARCH_BLACKFIN_ATOMIC__
-#ifndef CONFIG_SMP
+#ifdef CONFIG_SMP
-# include <asm-generic/atomic.h>
-#else
-#include <linux/types.h>
-#include <asm/system.h> /* local_irq_XXX() */
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-#define ATOMIC_INIT(i)  { (i) }
-#define atomic_set(v, i)        (((v)->counter) = i)
-#define atomic_read(v)  __raw_uncached_fetch_asm(&(v)->counter)
+#include <linux/linkage.h>
 asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
 asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_clear_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_set_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
-static inline void atomic_add(int i, atomic_t *v)
+#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
-{
-        __raw_atomic_update_asm(&v->counter, i);
-}
-static inline void atomic_sub(int i, atomic_t *v)
-{
-        __raw_atomic_update_asm(&v->counter, -i);
-}
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-        return __raw_atomic_update_asm(&v->counter, i);
-}
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-        return __raw_atomic_update_asm(&v->counter, -i);
-}
-static inline void atomic_inc(volatile atomic_t *v)
-{
-        __raw_atomic_update_asm(&v->counter, 1);
-}
-static inline void atomic_dec(volatile atomic_t *v)
-{
-        __raw_atomic_update_asm(&v->counter, -1);
-}
-static inline void atomic_clear_mask(int mask, atomic_t *v)
-{
-        __raw_atomic_clear_asm(&v->counter, mask);
-}
-static inline void atomic_set_mask(int mask, atomic_t *v)
-{
-        __raw_atomic_set_asm(&v->counter, mask);
-}
-static inline int atomic_test_mask(int mask, atomic_t *v)
-{
-        return __raw_atomic_test_asm(&v->counter, mask);
-}
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc() barrier()
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic_inc_return(v) atomic_add_return(1,(v))
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+#define atomic_add_return(i, v) __raw_atomic_update_asm(&(v)->counter, i)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+#define atomic_sub_return(i, v) __raw_atomic_update_asm(&(v)->counter, -(i))
-#include <asm-generic/atomic-long.h>
+#define atomic_clear_mask(m, v) __raw_atomic_clear_asm(&(v)->counter, m)
+#define atomic_set_mask(m, v)   __raw_atomic_set_asm(&(v)->counter, m)
 #endif
-#include <asm-generic/atomic64.h>
+#include <asm-generic/atomic.h>
 #endif
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h
deleted file mode 100644
index 41fa68b71287..000000000000
--- a/arch/blackfin/include/asm/auxvec.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/auxvec.h>
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 7fd0ec7b5b0f..ecacdf34768b 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -32,6 +32,8 @@ struct work_struct;
 struct bfin_serial_port {
        struct uart_port port;
        unsigned int old_status;
+        int tx_irq;
+        int rx_irq;
        int status_irq;
 #ifndef BFIN_UART_BF54X_STYLE
        unsigned int lsr;
diff --git a/arch/blackfin/include/asm/bitsperlong.h b/arch/blackfin/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13b2..000000000000
--- a/arch/blackfin/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index eb7c1441d8f9..0928700b6bc4 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -1,9 +1,9 @@
 /*
 * Common header file for Blackfin family of processors.
 *
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
 */
 #ifndef _BLACKFIN_H_
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h
deleted file mode 100644
index 61791e1ad9f5..000000000000
--- a/arch/blackfin/include/asm/bugs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bugs.h>
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h
deleted file mode 100644
index 6d68ad7e0ea3..000000000000
--- a/arch/blackfin/include/asm/cputime.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/cputime.h>
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
deleted file mode 100644
index 4c51401b5537..000000000000
--- a/arch/blackfin/include/asm/current.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/current.h>
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h
deleted file mode 100644
index f0a4c256403b..000000000000
--- a/arch/blackfin/include/asm/device.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/device.h>
diff --git a/arch/blackfin/include/asm/div64.h b/arch/blackfin/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/blackfin/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index d9dbc1a53534..dac0c97242bb 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -10,7 +10,7 @@
 #include <linux/interrupt.h>
 #include <mach/dma.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/blackfin.h>
 #include <asm/page.h>
 #include <asm-generic/dma.h>
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index edf2a2ad5183..c4ec959dad78 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -117,7 +117,6 @@
 #ifndef __ASSEMBLY__
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void do_hibernate(int wakeup);
 void set_dram_srfs(void);
@@ -134,32 +133,6 @@ struct bfin_dpmc_platform_data {
        unsigned short vr_settling_time; /* in us */
 };
-#else
-#define PM_PUSH(x) \
-        R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
-        [--SP] =  R0;\
-#define PM_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
-#define PM_SYS_PUSH(x) \
-        R0 = [P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-#define PM_SYS_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - PLL_CTL)] = R0;\
-#define PM_SYS_PUSH16(x) \
-        R0 = w[P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-#define PM_SYS_POP16(x) \
-        R0 = [SP++];\
-        w[P0 + (x - PLL_CTL)] = R0;\
 #endif
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h
deleted file mode 100644
index 3711bd9d50bd..000000000000
--- a/arch/blackfin/include/asm/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/emergency-restart.h>
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
deleted file mode 100644
index 4c82b503d92f..000000000000
--- a/arch/blackfin/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h
deleted file mode 100644
index 3a4988e8df45..000000000000
--- a/arch/blackfin/include/asm/fb.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/fb.h>
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h
deleted file mode 100644
index 0b745828f42b..000000000000
--- a/arch/blackfin/include/asm/futex.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/futex.h>
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 1ef8417f5d27..5a25856381ff 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -16,58 +16,13 @@
 #include <mach/gpio.h>
-#define GPIO_0  0
-#define GPIO_1  1
-#define GPIO_2  2
-#define GPIO_3  3
-#define GPIO_4  4
-#define GPIO_5  5
-#define GPIO_6  6
-#define GPIO_7  7
-#define GPIO_8  8
-#define GPIO_9  9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
 #define PERIPHERAL_USAGE 1
 #define GPIO_USAGE 0
+#ifndef BFIN_GPIO_PINT
+# define BFIN_GPIO_PINT 0
+#endif
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
@@ -89,7 +44,7 @@
 * MODIFICATION HISTORY :
 **************************************************************/
-#ifndef CONFIG_BF54x
+#if !BFIN_GPIO_PINT
 void set_gpio_dir(unsigned, unsigned short);
 void set_gpio_inen(unsigned, unsigned short);
 void set_gpio_polar(unsigned, unsigned short);
@@ -164,6 +119,10 @@ struct gpio_port_t {
 #ifdef BFIN_SPECIAL_GPIO_BANKS
 void bfin_special_gpio_free(unsigned gpio);
 int bfin_special_gpio_request(unsigned gpio, const char *label);
+# ifdef CONFIG_PM
+void bfin_special_gpio_pm_hibernate_restore(void);
+void bfin_special_gpio_pm_hibernate_suspend(void);
+# endif
 #endif
 #ifdef CONFIG_PM
@@ -182,7 +141,7 @@ static inline void bfin_pm_standby_restore(void)
 void bfin_gpio_pm_hibernate_restore(void);
 void bfin_gpio_pm_hibernate_suspend(void);
-#ifndef CONFIG_BF54x
+# if !BFIN_GPIO_PINT
 int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
 struct gpio_port_s {
@@ -199,8 +158,9 @@ struct gpio_port_s {
        unsigned short reserved;
        unsigned short mux;
 };
-#endif /*CONFIG_BF54x*/
+# endif
 #endif /*CONFIG_PM*/
 /***********************************************************
 *
 * FUNCTIONS: Blackfin GPIO Driver
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38657dac1235..38bddcb190c8 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -193,6 +193,16 @@ uint16_t get_enabled_gptimers(void);
 uint32_t get_gptimer_status(unsigned int group);
 void     set_gptimer_status(unsigned int group, uint32_t value);
+static inline void enable_gptimer(unsigned int timer_id)
+{
+        enable_gptimers(1 << timer_id);
+}
+static inline void disable_gptimer(unsigned int timer_id)
+{
+        disable_gptimers(1 << timer_id);
+}
 /*
 * All Blackfin system MMRs are padded to 32bits even if the register
 * itself is only 16bits.  So use a helper macro to streamline this.
@@ -209,6 +219,15 @@ struct bfin_gptimer_regs {
        u32 width;
 };
+/*
+ * bfin group timer registers layout
+ */
+struct bfin_gptimer_group_regs {
+        __BFP(enable);
+        __BFP(disable);
+        u32 status;
+};
 #undef __BFP
 #endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
deleted file mode 100644
index 1f5ef7da0045..000000000000
--- a/arch/blackfin/include/asm/hw_irq.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hw_irq.h>
diff --git a/arch/blackfin/include/asm/ioctl.h b/arch/blackfin/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/arch/blackfin/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/blackfin/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 9e0cc0e2534f..17b5e92e3bc6 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -32,7 +32,7 @@
 #include <asm/ptrace.h>
 #include <asm/irq.h>
 #include <asm/bitops.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/traps.h>
 #include <asm/bitsperlong.h>
diff --git a/arch/blackfin/include/asm/irq_regs.h b/arch/blackfin/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/blackfin/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index b4bbb75a9e15..43eb4749de3d 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -18,12 +18,12 @@
 extern unsigned long bfin_irq_flags;
 #endif
-static inline void bfin_sti(unsigned long flags)
+static inline notrace void bfin_sti(unsigned long flags)
 {
        asm volatile("sti %0;" : : "d" (flags));
 }
-static inline unsigned long bfin_cli(void)
+static inline notrace unsigned long bfin_cli(void)
 {
        unsigned long flags;
        asm volatile("cli %0;" : "=d" (flags));
@@ -40,22 +40,22 @@ static inline unsigned long bfin_cli(void)
 /*
 * Hard, untraced CPU interrupt flag manipulation and access.
 */
-static inline void __hard_local_irq_disable(void)
+static inline notrace void __hard_local_irq_disable(void)
 {
        bfin_cli();
 }
-static inline void __hard_local_irq_enable(void)
+static inline notrace void __hard_local_irq_enable(void)
 {
        bfin_sti(bfin_irq_flags);
 }
-static inline unsigned long hard_local_save_flags(void)
+static inline notrace unsigned long hard_local_save_flags(void)
 {
        return bfin_read_IMASK();
 }
-static inline unsigned long __hard_local_irq_save(void)
+static inline notrace unsigned long __hard_local_irq_save(void)
 {
        unsigned long flags;
        flags = bfin_cli();
@@ -65,18 +65,18 @@ static inline unsigned long __hard_local_irq_save(void)
        return flags;
 }
-static inline int hard_irqs_disabled_flags(unsigned long flags)
+static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
 {
        return (flags & ~0x3f) == 0;
 }
-static inline int hard_irqs_disabled(void)
+static inline notrace int hard_irqs_disabled(void)
 {
        unsigned long flags = hard_local_save_flags();
        return hard_irqs_disabled_flags(flags);
 }
-static inline void __hard_local_irq_restore(unsigned long flags)
+static inline notrace void __hard_local_irq_restore(unsigned long flags)
 {
        if (!hard_irqs_disabled_flags(flags))
                __hard_local_irq_enable();
@@ -113,31 +113,31 @@ void ipipe_check_context(struct ipipe_domain *ipd);
 /*
 * Interrupt pipe interface to linux/irqflags.h.
 */
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
        __check_irqop_context();
        __ipipe_stall_root();
        barrier();
 }
-static inline void arch_local_irq_enable(void)
+static inline notrace void arch_local_irq_enable(void)
 {
        barrier();
        __check_irqop_context();
        __ipipe_unstall_root();
 }
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
        return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
 }
-static inline int arch_irqs_disabled_flags(unsigned long flags)
+static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
 {
        return flags == bfin_no_irqs;
 }
-static inline unsigned long arch_local_irq_save(void)
+static inline notrace unsigned long arch_local_irq_save(void)
 {
        unsigned long flags;
@@ -148,13 +148,13 @@ static inline unsigned long arch_local_irq_save(void)
        return flags;
 }
-static inline void arch_local_irq_restore(unsigned long flags)
+static inline notrace void arch_local_irq_restore(unsigned long flags)
 {
        __check_irqop_context();
        __ipipe_restore_root(flags == bfin_no_irqs);
 }
-static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
+static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
 {
        /*
         * Merge virtual and real interrupt mask bits into a single
@@ -163,7 +163,7 @@ static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
        return (real & ~(1 << 31)) | ((virt != 0) << 31);
 }
-static inline int arch_demangle_irq_bits(unsigned long *x)
+static inline notrace int arch_demangle_irq_bits(unsigned long *x)
 {
        int virt = (*x & (1 << 31)) != 0;
        *x &= ~(1L << 31);
@@ -174,7 +174,7 @@ static inline int arch_demangle_irq_bits(unsigned long *x)
 * Interface to various arch routines that may be traced.
 */
 #ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline void hard_local_irq_disable(void)
+static inline notrace void hard_local_irq_disable(void)
 {
        if (!hard_irqs_disabled()) {
                __hard_local_irq_disable();
@@ -182,7 +182,7 @@ static inline void hard_local_irq_disable(void)
        }
 }
-static inline void hard_local_irq_enable(void)
+static inline notrace void hard_local_irq_enable(void)
 {
        if (hard_irqs_disabled()) {
                ipipe_trace_end(0x80000000);
@@ -190,7 +190,7 @@ static inline void hard_local_irq_enable(void)
        }
 }
-static inline unsigned long hard_local_irq_save(void)
+static inline notrace unsigned long hard_local_irq_save(void)
 {
        unsigned long flags = hard_local_save_flags();
        if (!hard_irqs_disabled_flags(flags)) {
@@ -200,7 +200,7 @@ static inline unsigned long hard_local_irq_save(void)
        return flags;
 }
-static inline void hard_local_irq_restore(unsigned long flags)
+static inline notrace void hard_local_irq_restore(unsigned long flags)
 {
        if (!hard_irqs_disabled_flags(flags)) {
                ipipe_trace_end(0x80000001);
diff --git a/arch/blackfin/include/asm/kdebug.h b/arch/blackfin/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/blackfin/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
deleted file mode 100644
index 3575c64af42a..000000000000
--- a/arch/blackfin/include/asm/kmap_types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kmap_types.h>
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/arch/blackfin/include/asm/local.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local.h>
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/blackfin/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab1..000000000000
--- a/arch/blackfin/include/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/mman.h>
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
index 4282b169ead9..ed5689b82c9f 100644
--- a/arch/blackfin/include/asm/module.h
+++ b/arch/blackfin/include/asm/module.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef _ASM_BFIN_MODULE_H
 #define _ASM_BFIN_MODULE_H
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h
deleted file mode 100644
index 809134c644a6..000000000000
--- a/arch/blackfin/include/asm/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/msgbuf.h>
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
deleted file mode 100644
index f726e3a80ad0..000000000000
--- a/arch/blackfin/include/asm/mutex.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _ASM_MUTEX_H
-#define _ASM_MUTEX_H
-#ifndef CONFIG_SMP
-#include <asm-generic/mutex.h>
-#else
-static inline void
-__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                fail_fn(count);
-        else
-                smp_mb();
-}
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                return fail_fn(count);
-        else {
-                smp_mb();
-                return 0;
-        }
-}
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        smp_mb();
-        if (unlikely(atomic_inc_return(count) <= 0))
-                fail_fn(count);
-}
-#define __mutex_slowpath_needs_to_unlock()              1
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        /*
-         * We have two variants here. The cmpxchg based one is the best one
-         * because it never induce a false contention state.  It is included
-         * here because architectures using the inc/dec algorithms over the
-         * xchg ones are much more likely to support cmpxchg natively.
-         *
-         * If not we fall back to the spinlock based variant - that is
-         * just as efficient (and simpler) as a 'destructive' probing of
-         * the mutex state would be.
-         */
-#ifdef __HAVE_ARCH_CMPXCHG
-        if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
-                smp_mb();
-                return 1;
-        }
-        return 0;
-#else
-        return fail_fn(count);
-#endif
-}
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index d0ce975bcd48..7202404966f6 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef _BLACKFIN_PAGE_H
 #define _BLACKFIN_PAGE_H
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h
deleted file mode 100644
index 965d45427975..000000000000
--- a/arch/blackfin/include/asm/param.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/param.h>
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index d49bb261d9b7..28c2498c9c98 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -54,6 +54,16 @@ struct blackfin_pda {			/* Per-processor Data Area */
 #endif
 };
+struct blackfin_initial_pda {
+        void *retx;
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+        void *dcplb_doublefault_addr;
+        void *icplb_doublefault_addr;
+        void *retx_doublefault;
+        unsigned seqstat_doublefault;
+#endif
+};
 extern struct blackfin_pda cpu_pda[];
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
deleted file mode 100644
index 06a959d67234..000000000000
--- a/arch/blackfin/include/asm/percpu.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/percpu.h>
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h
deleted file mode 100644
index f261cb7dda06..000000000000
--- a/arch/blackfin/include/asm/pgalloc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/pgalloc.h>
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 7854d4367c15..10d8641180f2 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -102,7 +102,6 @@ struct pt_regs {
 /* user_mode returns true if only one bit is set in IPEND, other than the
   master interrupt enable.  */
 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-extern void show_regs(struct pt_regs *);
 #define arch_has_single_step()  (1)
 /* common code demands this function */
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h
deleted file mode 100644
index 04bc4db8921b..000000000000
--- a/arch/blackfin/include/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/resource.h>
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
deleted file mode 100644
index d177a1588958..000000000000
--- a/arch/blackfin/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BLACKFIN_SCATTERLIST_H
-#define _BLACKFIN_SCATTERLIST_H
-#include <asm-generic/scatterlist.h>
-#endif                          /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 14a3e66d9167..fbd408475725 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef _BLACKFIN_SECTIONS_H
 #define _BLACKFIN_SECTIONS_H
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h
deleted file mode 100644
index 7673b83cfef7..000000000000
--- a/arch/blackfin/include/asm/sembuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sembuf.h>
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
deleted file mode 100644
index a0cb0caff152..000000000000
--- a/arch/blackfin/include/asm/serial.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/serial.h>
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
deleted file mode 100644
index 552df83f1a49..000000000000
--- a/arch/blackfin/include/asm/setup.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/setup.h>
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h
deleted file mode 100644
index 83c05fc2de38..000000000000
--- a/arch/blackfin/include/asm/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/shmbuf.h>
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h
deleted file mode 100644
index 93f30deb95d0..000000000000
--- a/arch/blackfin/include/asm/shmparam.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/shmparam.h>
diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h
index ce4081a4d815..906bdc1f5fda 100644
--- a/arch/blackfin/include/asm/sigcontext.h
+++ b/arch/blackfin/include/asm/sigcontext.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef _ASM_BLACKFIN_SIGCONTEXT_H
 #define _ASM_BLACKFIN_SIGCONTEXT_H
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h
deleted file mode 100644
index 6b71384b9d8b..000000000000
--- a/arch/blackfin/include/asm/socket.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/socket.h>
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h
deleted file mode 100644
index def6d4746ee7..000000000000
--- a/arch/blackfin/include/asm/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sockios.h>
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1f286e71c21f..490c7caa02d9 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
- *
+ *
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2 or later.
- */
+ */
 #ifndef __BFIN_SPINLOCK_H
 #define __BFIN_SPINLOCK_H
@@ -11,7 +11,7 @@
 # include <asm-generic/spinlock.h>
 #else
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h
deleted file mode 100644
index 0b91fe198c20..000000000000
--- a/arch/blackfin/include/asm/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/statfs.h>
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h
deleted file mode 100644
index 3935b106de79..000000000000
--- a/arch/blackfin/include/asm/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termbits.h>
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h
deleted file mode 100644
index 280d78a9d966..000000000000
--- a/arch/blackfin/include/asm/termios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termios.h>
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h
deleted file mode 100644
index 5428f333a02c..000000000000
--- a/arch/blackfin/include/asm/topology.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/topology.h>
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index b9e79bc580dd..000000000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/types.h>
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index 1c0d190adaef..5cc111502822 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -195,17 +195,17 @@ static inline unsigned long __must_check
 copy_from_user(void *to, const void __user *from, unsigned long n)
 {
        if (access_ok(VERIFY_READ, from, n))
-                memcpy(to, from, n);
+                memcpy(to, (const void __force *)from, n);
        else
                return n;
        return 0;
 }
 static inline unsigned long __must_check
-copy_to_user(void *to, const void __user *from, unsigned long n)
+copy_to_user(void __user *to, const void *from, unsigned long n)
 {
        if (access_ok(VERIFY_WRITE, to, n))
-                memcpy(to, from, n);
+                memcpy((void __force *)to, from, n);
        else
                return n;
        return 0;
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/blackfin/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ucontext.h>
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb2111f..000000000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h
deleted file mode 100644
index 4792a60831e4..000000000000
--- a/arch/blackfin/include/asm/user.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/user.h>
diff --git a/arch/blackfin/include/asm/xor.h b/arch/blackfin/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/blackfin/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index d550b24d9e9b..1f88edd4572a 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
 CFLAGS_REMOVE_ftrace.o = -pg
+obj-$(CONFIG_HAVE_PWM)               += pwm.o
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
 obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
@@ -37,6 +38,6 @@ obj-$(CONFIG_PERF_EVENTS)            += perf_event.o
 # the kgdb test puts code into L2 and without linker
 # relaxation, we need to force long calls to/from it
-CFLAGS_kgdb_test.o := -mlong-calls -O0
+CFLAGS_kgdb_test.o := -mlong-calls
 obj-$(CONFIG_DEBUG_MMRS)             += debug-mmrs.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index bd32c09b9349..17e35465a416 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -138,6 +138,16 @@ int main(void)
        DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
        DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
 #endif
+        /* PDA initial management */
+        DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+        DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
+        DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
+        DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
+        DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
+#endif
 #ifdef CONFIG_SMP
        /* Inter-core lock (in L2 SRAM) */
        DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bcf8cf6fe412..02796b88443d 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -118,6 +118,9 @@ static struct str_ident {
 #if defined(CONFIG_PM)
 static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
+# ifdef BF538_FAMILY
+static unsigned short port_fer_saved[3];
+# endif
 #endif
 static void gpio_error(unsigned gpio)
@@ -604,6 +607,11 @@ void bfin_gpio_pm_hibernate_suspend(void)
 {
        int i, bank;
+#ifdef BF538_FAMILY
+        for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
+                port_fer_saved[i] = *port_fer[i];
+#endif
        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                bank = gpio_bank(i);
@@ -625,6 +633,10 @@ void bfin_gpio_pm_hibernate_suspend(void)
                gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
        }
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+        bfin_special_gpio_pm_hibernate_suspend();
+#endif
        AWA_DUMMY_READ(maska);
 }
@@ -632,6 +644,11 @@ void bfin_gpio_pm_hibernate_restore(void)
 {
        int i, bank;
+#ifdef BF538_FAMILY
+        for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
+                *port_fer[i] = port_fer_saved[i];
+#endif
        for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                bank = gpio_bank(i);
@@ -653,6 +670,11 @@ void bfin_gpio_pm_hibernate_restore(void)
                gpio_array[bank]->both  = gpio_bank_saved[bank].both;
                gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
        }
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+        bfin_special_gpio_pm_hibernate_restore();
+#endif
        AWA_DUMMY_READ(maska);
 }
@@ -691,9 +713,9 @@ void bfin_gpio_pm_hibernate_restore(void)
                gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
                gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
                gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
-                gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
                gpio_array[bank]->data_set = gpio_bank_saved[bank].data
-                                                | gpio_bank_saved[bank].dir;
+                                                & gpio_bank_saved[bank].dir;
+                gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
        }
 }
 #endif
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index fce4807ceef9..92f664826281 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -27,7 +27,7 @@
 #define PORT_MUX BFIN_PORT_MUX
 #endif
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
+#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
 #define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
 #define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
 #define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
@@ -223,7 +223,8 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
        __DMA(CURR_DESC_PTR, curr_desc_ptr);
        __DMA(CURR_ADDR, curr_addr);
        __DMA(IRQ_STATUS, irq_status);
-        __DMA(PERIPHERAL_MAP, peripheral_map);
+        if (strcmp(pfx, "IMDMA") != 0)
+                __DMA(PERIPHERAL_MAP, peripheral_map);
        __DMA(CURR_X_COUNT, curr_x_count);
        __DMA(CURR_Y_COUNT, curr_y_count);
 }
@@ -277,6 +278,32 @@ bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 }
 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
+#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
+#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf;
+        if (num == -1) {
+                _buf = buf + sprintf(buf, "TIMER_");
+                __GPTIMER_GROUP(ENABLE, enable);
+                __GPTIMER_GROUP(DISABLE, disable);
+                __GPTIMER_GROUP(STATUS, status);
+        } else {
+                /* These MMRs are a bit odd as the group # is a suffix */
+                _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
+                d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
+                _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
+                d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
+                _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
+                d(buf, 32, base + GPTIMER_GROUP_OFF(status));
+        }
+}
+#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
 /*
 * Handshake MDMA
 */
@@ -296,6 +323,29 @@ bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 /*
+ * Peripheral Interrupts (PINT/GPIO)
+ */
+#ifdef PINT0_MASK_SET
+#define __PINT(uname, lname) __REGS(pint, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
+        __PINT(MASK_SET, mask_set);
+        __PINT(MASK_CLEAR, mask_clear);
+        __PINT(REQUEST, request);
+        __PINT(ASSIGN, assign);
+        __PINT(EDGE_SET, edge_set);
+        __PINT(EDGE_CLEAR, edge_clear);
+        __PINT(INVERT_SET, invert_set);
+        __PINT(INVERT_CLEAR, invert_clear);
+        __PINT(PINSTATE, pinstate);
+        __PINT(LATCH, latch);
+}
+#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
+#endif
+/*
 * Port/GPIO
 */
 #define bfin_gpio_regs gpio_port_t
@@ -747,7 +797,7 @@ static int __init bfin_debug_mmrs_init(void)
 #endif
        parent = debugfs_create_dir("dmac", top);
-#ifdef DMA_TC_CNT
+#ifdef DMAC_TC_CNT
        D16(DMAC_TC_CNT);
        D16(DMAC_TC_PER);
 #endif
@@ -1005,29 +1055,19 @@ static int __init bfin_debug_mmrs_init(void)
 #endif
        parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_DISABLE
+#ifdef TIMER_ENABLE
-        D16(TIMER_DISABLE);
+        GPTIMER_GROUP(TIMER_ENABLE, -1);
-        D16(TIMER_ENABLE);
-        D32(TIMER_STATUS);
 #endif
-#ifdef TIMER_DISABLE0
+#ifdef TIMER_ENABLE0
-        D16(TIMER_DISABLE0);
+        GPTIMER_GROUP(TIMER_ENABLE0, 0);
-        D16(TIMER_ENABLE0);
-        D32(TIMER_STATUS0);
 #endif
-#ifdef TIMER_DISABLE1
+#ifdef TIMER_ENABLE1
-        D16(TIMER_DISABLE1);
+        GPTIMER_GROUP(TIMER_ENABLE1, 1);
-        D16(TIMER_ENABLE1);
-        D32(TIMER_STATUS1);
 #endif
        /* XXX: Should convert BF561 MMR names */
 #ifdef TMRS4_DISABLE
-        D16(TMRS4_DISABLE);
+        GPTIMER_GROUP(TMRS4_ENABLE, 0);
-        D16(TMRS4_ENABLE);
+        GPTIMER_GROUP(TMRS8_ENABLE, 1);
-        D32(TMRS4_STATUS);
-        D16(TMRS8_DISABLE);
-        D16(TMRS8_ENABLE);
-        D32(TMRS8_STATUS);
 #endif
        GPTIMER(0);
        GPTIMER(1);
@@ -1253,6 +1293,14 @@ static int __init bfin_debug_mmrs_init(void)
        D32(OTP_DATA3);
 #endif
+#ifdef PINT0_MASK_SET
+        parent = debugfs_create_dir("pint", top);
+        PINT(0);
+        PINT(1);
+        PINT(2);
+        PINT(3);
+#endif
 #ifdef PIXC_CTL
        parent = debugfs_create_dir("pixc", top);
        D16(PIXC_CTL);
@@ -1816,7 +1864,6 @@ static int __init bfin_debug_mmrs_init(void)
        {
                int num;
                unsigned long base;
-                char *_buf, buf[32];
                base = PORTA_FER;
                for (num = 0; num < 10; ++num) {
@@ -1824,24 +1871,6 @@ static int __init bfin_debug_mmrs_init(void)
                        base += sizeof(struct bfin_gpio_regs);
                }
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-                parent = debugfs_create_dir("pint", top);
-                base = PINT0_MASK_SET;
-                for (num = 0; num < 4; ++num) {
-                        _buf = REGS_STR_PFX(buf, PINT, num);
-                        __PINT(MASK_SET, mask_set);
-                        __PINT(MASK_CLEAR, mask_clear);
-                        __PINT(IRQ, irq);
-                        __PINT(ASSIGN, assign);
-                        __PINT(EDGE_SET, edge_set);
-                        __PINT(EDGE_CLEAR, edge_clear);
-                        __PINT(INVERT_SET, invert_set);
-                        __PINT(INVERT_CLEAR, invert_clear);
-                        __PINT(PINSTATE, pinstate);
-                        __PINT(LATCH, latch);
-                        base += sizeof(struct bfin_pint_regs);
-                }
        }
 #endif  /* BF54x */
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index 04ddcfeb7981..f0d1118f1825 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -12,6 +12,7 @@
 #include <linux/spinlock.h>
 #include <linux/dma-mapping.h>
 #include <linux/scatterlist.h>
+#include <linux/export.h>
 static spinlock_t dma_page_lock;
 static unsigned long *dma_page;
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
index 48808a12b427..9277905b82cf 100644
--- a/arch/blackfin/kernel/ftrace.c
+++ b/arch/blackfin/kernel/ftrace.c
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/uaccess.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/cacheflush.h>
 #ifdef CONFIG_DYNAMIC_FTRACE
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 8b81dc04488a..06459f4bf43a 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -25,49 +25,33 @@
 #define BFIN_TIMER_NUM_GROUP  (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
-typedef struct {
+static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
-        uint16_t config;
-        uint16_t __pad;
-        uint32_t counter;
-        uint32_t period;
-        uint32_t width;
-} GPTIMER_timer_regs;
-typedef struct {
-        uint16_t enable;
-        uint16_t __pad0;
-        uint16_t disable;
-        uint16_t __pad1;
-        uint32_t status;
-} GPTIMER_group_regs;
-static volatile GPTIMER_timer_regs *const timer_regs[MAX_BLACKFIN_GPTIMERS] =
 {
-        (GPTIMER_timer_regs *)TIMER0_CONFIG,
+        (void *)TIMER0_CONFIG,
-        (GPTIMER_timer_regs *)TIMER1_CONFIG,
+        (void *)TIMER1_CONFIG,
-        (GPTIMER_timer_regs *)TIMER2_CONFIG,
+        (void *)TIMER2_CONFIG,
 #if (MAX_BLACKFIN_GPTIMERS > 3)
-        (GPTIMER_timer_regs *)TIMER3_CONFIG,
+        (void *)TIMER3_CONFIG,
-        (GPTIMER_timer_regs *)TIMER4_CONFIG,
+        (void *)TIMER4_CONFIG,
-        (GPTIMER_timer_regs *)TIMER5_CONFIG,
+        (void *)TIMER5_CONFIG,
-        (GPTIMER_timer_regs *)TIMER6_CONFIG,
+        (void *)TIMER6_CONFIG,
-        (GPTIMER_timer_regs *)TIMER7_CONFIG,
+        (void *)TIMER7_CONFIG,
 # if (MAX_BLACKFIN_GPTIMERS > 8)
-        (GPTIMER_timer_regs *)TIMER8_CONFIG,
+        (void *)TIMER8_CONFIG,
-        (GPTIMER_timer_regs *)TIMER9_CONFIG,
+        (void *)TIMER9_CONFIG,
-        (GPTIMER_timer_regs *)TIMER10_CONFIG,
+        (void *)TIMER10_CONFIG,
 #  if (MAX_BLACKFIN_GPTIMERS > 11)
-        (GPTIMER_timer_regs *)TIMER11_CONFIG,
+        (void *)TIMER11_CONFIG,
 #  endif
 # endif
 #endif
 };
-static volatile GPTIMER_group_regs *const group_regs[BFIN_TIMER_NUM_GROUP] =
+static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
 {
-        (GPTIMER_group_regs *)TIMER0_GROUP_REG,
+        (void *)TIMER0_GROUP_REG,
 #if (MAX_BLACKFIN_GPTIMERS > 8)
-        (GPTIMER_group_regs *)TIMER8_GROUP_REG,
+        (void *)TIMER8_GROUP_REG,
 #endif
 };
@@ -140,7 +124,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
 void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->width = value;
+        bfin_write(&timer_regs[timer_id]->width, value);
        SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_pwidth);
@@ -148,14 +132,14 @@ EXPORT_SYMBOL(set_gptimer_pwidth);
 uint32_t get_gptimer_pwidth(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->width;
+        return bfin_read(&timer_regs[timer_id]->width);
 }
 EXPORT_SYMBOL(get_gptimer_pwidth);
 void set_gptimer_period(unsigned int timer_id, uint32_t period)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->period = period;
+        bfin_write(&timer_regs[timer_id]->period, period);
        SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_period);
@@ -163,71 +147,76 @@ EXPORT_SYMBOL(set_gptimer_period);
 uint32_t get_gptimer_period(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->period;
+        return bfin_read(&timer_regs[timer_id]->period);
 }
 EXPORT_SYMBOL(get_gptimer_period);
 uint32_t get_gptimer_count(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->counter;
+        return bfin_read(&timer_regs[timer_id]->counter);
 }
 EXPORT_SYMBOL(get_gptimer_count);
 uint32_t get_gptimer_status(unsigned int group)
 {
        tassert(group < BFIN_TIMER_NUM_GROUP);
-        return group_regs[group]->status;
+        return bfin_read(&group_regs[group]->status);
 }
 EXPORT_SYMBOL(get_gptimer_status);
 void set_gptimer_status(unsigned int group, uint32_t value)
 {
        tassert(group < BFIN_TIMER_NUM_GROUP);
-        group_regs[group]->status = value;
+        bfin_write(&group_regs[group]->status, value);
        SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_status);
+static uint32_t read_gptimer_status(unsigned int timer_id)
+{
+        return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
+}
 int get_gptimer_intr(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_intr);
 void clear_gptimer_intr(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
 }
 EXPORT_SYMBOL(clear_gptimer_intr);
 int get_gptimer_over(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_over);
 void clear_gptimer_over(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
 }
 EXPORT_SYMBOL(clear_gptimer_over);
 int get_gptimer_run(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
+        return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_run);
 void set_gptimer_config(unsigned int timer_id, uint16_t config)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config = config;
+        bfin_write(&timer_regs[timer_id]->config, config);
        SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_config);
@@ -235,7 +224,7 @@ EXPORT_SYMBOL(set_gptimer_config);
 uint16_t get_gptimer_config(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        return timer_regs[timer_id]->config;
+        return bfin_read(&timer_regs[timer_id]->config);
 }
 EXPORT_SYMBOL(get_gptimer_config);
@@ -244,7 +233,7 @@ void enable_gptimers(uint16_t mask)
        int i;
        tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
        for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
-                group_regs[i]->enable = mask & 0xFF;
+                bfin_write(&group_regs[i]->enable, mask & 0xFF);
                mask >>= 8;
        }
        SSYNC();
@@ -257,7 +246,7 @@ static void _disable_gptimers(uint16_t mask)
        uint16_t m = mask;
        tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
        for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
-                group_regs[i]->disable = m & 0xFF;
+                bfin_write(&group_regs[i]->disable, m & 0xFF);
                m >>= 8;
        }
 }
@@ -268,7 +257,7 @@ void disable_gptimers(uint16_t mask)
        _disable_gptimers(mask);
        for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
                if (mask & (1 << i))
-                        group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i];
+                        bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
        SSYNC();
 }
 EXPORT_SYMBOL(disable_gptimers);
@@ -283,7 +272,7 @@ EXPORT_SYMBOL(disable_gptimers_sync);
 void set_gptimer_pulse_hi(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config |= TIMER_PULSE_HI;
+        bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
        SSYNC();
 }
 EXPORT_SYMBOL(set_gptimer_pulse_hi);
@@ -291,7 +280,7 @@ EXPORT_SYMBOL(set_gptimer_pulse_hi);
 void clear_gptimer_pulse_hi(unsigned int timer_id)
 {
        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
-        timer_regs[timer_id]->config &= ~TIMER_PULSE_HI;
+        bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
        SSYNC();
 }
 EXPORT_SYMBOL(clear_gptimer_pulse_hi);
@@ -301,7 +290,7 @@ uint16_t get_enabled_gptimers(void)
        int i;
        uint16_t result = 0;
        for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
-                result |= (group_regs[i]->enable << (i << 3));
+                result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
        return result;
 }
 EXPORT_SYMBOL(get_enabled_gptimers);
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 486426f8a0d7..dbe11220cc53 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -32,7 +32,7 @@
 #include <linux/unistd.h>
 #include <linux/io.h>
 #include <asm/system.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/irq_handler.h>
 DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 2a6e9dbb62a5..4a7dcfea98af 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -50,8 +50,7 @@ void kgdb_l2_test(void)
 #endif
+noinline int kgdb_test(char *name, int len, int count, int z)
-int kgdb_test(char *name, int len, int count, int z)
 {
        pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
        count = z;
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
index 35e350cad9d9..4489efc52883 100644
--- a/arch/blackfin/kernel/module.c
+++ b/arch/blackfin/kernel/module.c
@@ -16,19 +16,6 @@
 #include <asm/cacheflush.h>
 #include <asm/uaccess.h>
-void *module_alloc(unsigned long size)
-{
-        if (size == 0)
-                return NULL;
-        return vmalloc(size);
-}
-/* Free memory returned from module_alloc */
-void module_free(struct module *mod, void *module_region)
-{
-        vfree(module_region);
-}
 /* Transfer the section to the L1 memory */
 int
 module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
@@ -150,14 +137,6 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
        return 0;
 }
-int
-apply_relocate(Elf_Shdr * sechdrs, const char *strtab,
-               unsigned int symindex, unsigned int relsec, struct module *mod)
-{
-        pr_err(".rel unsupported\n");
-        return -ENOEXEC;
-}
 /*************************************************************************/
 /* FUNCTION : apply_relocate_add                                         */
 /* ABSTRACT : Blackfin specific relocation handling for the loadable     */
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
index 679d0db35256..9919d29287dc 100644
--- a/arch/blackfin/kernel/nmi.c
+++ b/arch/blackfin/kernel/nmi.c
@@ -18,7 +18,7 @@
 #include <linux/smp.h>
 #include <linux/timer.h>
 #include <asm/blackfin.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/bfin_watchdog.h>
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
index 04300f29c0e7..e47d19ae3e06 100644
--- a/arch/blackfin/kernel/perf_event.c
+++ b/arch/blackfin/kernel/perf_event.c
@@ -24,6 +24,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/perf_event.h>
 #include <asm/bfin_pfmon.h>
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 6a660fa921b5..6a80a9e9fc4a 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -140,7 +140,6 @@ EXPORT_SYMBOL(kernel_thread);
 */
 void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
 {
-        set_fs(USER_DS);
        regs->pc = new_ip;
        if (current->mm)
                regs->p5 = current->mm->start_data;
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
new file mode 100644
index 000000000000..33f5942733bd
--- /dev/null
+++ b/arch/blackfin/kernel/pwm.c
@@ -0,0 +1,100 @@
+/*
+ * Blackfin Pulse Width Modulation (PWM) core
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/module.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <asm/gptimers.h>
+#include <asm/portmux.h>
+struct pwm_device {
+        unsigned id;
+        unsigned short pin;
+};
+static const unsigned short pwm_to_gptimer_per[] = {
+        P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
+        P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
+};
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int ret;
+        /* XXX: pwm_id really should be unsigned */
+        if (pwm_id < 0)
+                return NULL;
+        pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+        if (!pwm)
+                return pwm;
+        pwm->id = pwm_id;
+        if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
+                goto err;
+        pwm->pin = pwm_to_gptimer_per[pwm->id];
+        ret = peripheral_request(pwm->pin, label);
+        if (ret)
+                goto err;
+        return pwm;
+ err:
+        kfree(pwm);
+        return NULL;
+}
+EXPORT_SYMBOL(pwm_request);
+void pwm_free(struct pwm_device *pwm)
+{
+        peripheral_free(pwm->pin);
+        kfree(pwm);
+}
+EXPORT_SYMBOL(pwm_free);
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long period, duty;
+        unsigned long long val;
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+        val = (unsigned long long)get_sclk() * period_ns;
+        do_div(val, NSEC_PER_SEC);
+        period = val;
+        val = (unsigned long long)period * duty_ns;
+        do_div(val, period_ns);
+        duty = period - val;
+        if (duty >= period)
+                duty = period - 1;
+        set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
+        set_gptimer_pwidth(pwm->id, duty);
+        set_gptimer_period(pwm->id, period);
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+int pwm_enable(struct pwm_device *pwm)
+{
+        enable_gptimer(pwm->id);
+        return 0;
+}
+EXPORT_SYMBOL(pwm_enable);
+void pwm_disable(struct pwm_device *pwm)
+{
+        disable_gptimer(pwm->id);
+}
+EXPORT_SYMBOL(pwm_disable);
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 488bdc51aaa5..c4c0081b1996 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -54,7 +54,9 @@ static void bfin_reset(void)
        /* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-        bfin_read_SWRST();
+        /* Seems to be fixed with newer parts though ... */
+        if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
+                bfin_read_SWRST();
 #endif
        /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 536bd9d7e0cf..dfa2525a442d 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -54,8 +54,7 @@ EXPORT_SYMBOL(mtd_size);
 #endif
 char __initdata command_line[COMMAND_LINE_SIZE];
-void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
+struct blackfin_initial_pda __initdata initial_pda;
-        *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
 /* boot memmap, for parsing "memmap=" */
 #define BFIN_MEMMAP_MAX         128 /* number of entries in bfin_memmap */
@@ -957,13 +956,16 @@ void __init setup_arch(char **cmdline_p)
                printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
                /* We assume the crashing kernel, and the current symbol table match */
-                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
+                printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
-                        (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
+                        initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
-                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
+                        initial_pda.retx_doublefault);
-                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
+                        initial_pda.dcplb_doublefault_addr);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
+                        initial_pda.icplb_doublefault_addr);
 #endif
                printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
-                        init_retx);
+                        initial_pda.retx);
        } else if (_bfin_swrst & RESET_WDOG)
                printk(KERN_INFO "Recovering from Watchdog event\n");
        else if (_bfin_swrst & RESET_SOFTWARE)
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index 89448ed7065d..d998383cb956 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -41,6 +41,7 @@ asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len)
 #if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE)
 #include <linux/fb.h>
+#include <linux/export.h>
 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
        unsigned long len, unsigned long pgoff, unsigned long flags)
 {
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index 9e9b60d969dc..1bcf3a3c57d8 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -188,8 +188,7 @@ irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
 static struct irqaction gptmr0_irq = {
        .name           = "Blackfin GPTimer0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | \
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
-                          IRQF_IRQPOLL | IRQF_PERCPU,
        .handler        = bfin_gptmr0_interrupt,
 };
@@ -297,8 +296,7 @@ irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
 static struct irqaction coretmr_irq = {
        .name           = "Blackfin CoreTimer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | \
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
-                          IRQF_IRQPOLL | IRQF_PERCPU,
        .handler        = bfin_coretmr_interrupt,
 };
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 8d73724c0092..2310b249675f 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -25,7 +25,6 @@
 static struct irqaction bfin_timer_irq = {
        .name = "Blackfin Timer Tick",
-        .flags = IRQF_DISABLED
 };
 #if defined(CONFIG_IPIPE)
@@ -51,7 +50,7 @@ void __init setup_core_timer(void)
        u32 tcount;
        /* power up the timer, but don't enable it just yet */
-        bfin_write_TCNTL(1);
+        bfin_write_TCNTL(TMPWR);
        CSYNC();
        /* the TSCALE prescaler counter */
@@ -64,7 +63,7 @@ void __init setup_core_timer(void)
        /* now enable the timer */
        CSYNC();
-        bfin_write_TCNTL(7);
+        bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
 }
 #endif
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 3ac5b66d14aa..ba35864b2b74 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -155,6 +155,7 @@ SECTIONS
                SECURITY_INITCALL
                INIT_RAM_FS
+                . = ALIGN(PAGE_SIZE);
                ___per_cpu_load = .;
                PERCPU_INPUT(32)
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 1d9f631a7f94..bde92a19970e 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -11,55 +11,75 @@ menu "BF518 Specific Configuration"
 comment "Alternative Multiplexing Scheme"
 choice
-        prompt "SPORT0"
+        prompt "PWM Channel Pins"
-        default BF518_SPORT0_PORTG
+        default BF518_PWM_ALL_PORTF
        help
-          Select PORT used for SPORT0. See Hardware Reference Manual
+          Select pins used for the PWM channels:
+            PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
-config BF518_SPORT0_PORTF
+          See the Hardware Reference Manual for more details.
-        bool "PORT F"
+config BF518_PWM_ALL_PORTF
+        bool "PF1 - PF6"
        help
-          PORT F
+          PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
-config BF518_SPORT0_PORTG
+config BF518_PWM_PORTF_PORTG
-        bool "PORT G"
+        bool "PF11 - PF14 / PG1 - PG2"
        help
-          PORT G
+          PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
+          PG{1,2} <-> PWM_{CH,CL}
 endchoice
 choice
-        prompt "SPORT0 TSCLK Location"
+        prompt "PWM Sync Pin"
-        depends on BF518_SPORT0_PORTG
+        default BF518_PWM_SYNC_PF7
-        default BF518_SPORT0_TSCLK_PG10
        help
-          Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
+          Select the pin used for PWM_SYNC.
-config BF518_SPORT0_TSCLK_PG10
+          See the Hardware Reference Manual for more details.
-        bool "PORT PG10"
-        help
+config BF518_PWM_SYNC_PF7
-          PORT PG10
+        bool "PF7"
+config BF518_PWM_SYNC_PF15
+        bool "PF15"
+endchoice
-config BF518_SPORT0_TSCLK_PG14
+choice
-        bool "PORT PG14"
+        prompt "PWM Trip B Pin"
+        default BF518_PWM_TRIPB_PG10
        help
-          PORT PG14
+          Select the pin used for PWM_TRIPB.
+          See the Hardware Reference Manual for more details.
+config BF518_PWM_TRIPB_PG10
+        bool "PG10"
+config BF518_PWM_TRIPB_PG14
+        bool "PG14"
 endchoice
 choice
-        prompt "UART1"
+        prompt "PPI / Timer Pins"
-        default BF518_UART1_PORTF
+        default BF518_PPI_TMR_PG5
        help
-          Select PORT used for UART1. See Hardware Reference Manual
+          Select pins used for PPI/Timer:
+            PPICLK PPIFS1 PPIFS2
+            TMRCLK TMR0 TMR1
-config BF518_UART1_PORTF
+          See the Hardware Reference Manual for more details.
-        bool "PORT F"
+config BF518_PPI_TMR_PG5
+        bool "PG5 - PG7"
        help
-          PORT F
+          PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-config BF518_UART1_PORTG
+config BF518_PPI_TMR_PG12
-        bool "PORT G"
+        bool "PG12 - PG14"
        help
-          PORT G
+          PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
 endchoice
 comment "Hysteresis/Schmitt Trigger Control"
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index c0ccadcfa44e..d1c0c0cff3ef 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -7,6 +7,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -187,43 +188,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-#if defined(CONFIG_NET_DSA_KSZ8893M) \
-        || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
-/* SPI SWITCH CHIP */
-static struct bfin5xx_spi_chip spi_switch_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -239,21 +213,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -269,18 +228,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 #if defined(CONFIG_NET_DSA_KSZ8893M) \
        || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
@@ -290,7 +237,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 1,
                .platform_data = NULL,
-                .controller_data = &spi_switch_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -314,7 +260,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -324,7 +269,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                .mode = SPI_MODE_0,
        },
 #endif
@@ -334,7 +278,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -343,7 +286,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -431,8 +373,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -474,8 +421,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 50fc5c89e379..5470bf89e52e 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -138,32 +138,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -179,21 +163,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -209,18 +178,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
        {
                .modalias = "mmc_spi",
@@ -239,7 +196,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -249,7 +205,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                .mode = SPI_MODE_0,
        },
 #endif
@@ -259,7 +214,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -268,7 +222,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -356,8 +309,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -399,8 +357,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index d2f076fbbc9e..56383f7cbc07 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -11,10 +11,9 @@
 */
 /* This file should be up to date with:
- *  - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
 */
-/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
 #if __SILICON_REVISION__ < 0
 # error will not work on BF518 silicon version
 #endif
@@ -77,19 +76,29 @@
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
 /* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
+#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
@@ -157,6 +166,5 @@
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
 #define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index cd84a569b04e..b3b806f468da 100644
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -81,9 +81,15 @@
 #define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
 #define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#ifndef CONFIG_BF518_PPI_TMR_PG12
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#else
 #define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
 #define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
 #define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#endif
 #define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
 /* SPI Port Mux */
@@ -139,9 +145,15 @@
 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
 /* Timer */
+#ifndef CONFIG_BF518_PPI_TMR_PG12
 #define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
 #define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
 #define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#else
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 #define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
 #define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
 #define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
@@ -158,23 +170,33 @@
 #define P_TWI0_SDA      (P_DONTCARE)
 /* PWM */
-#define P_PWM0_AH               (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#ifndef CONFIG_BF518_PWM_PORTF_PORTG
-#define P_PWM0_AL               (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_BH               (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BL               (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_CH               (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CL               (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_SYNC             (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#else
-#define P_PWM1_AH               (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL               (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH               (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL               (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH               (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL               (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC             (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#endif
+#ifndef CONFIG_BF518_PWM_SYNC_PF15
+#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#else
+#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#endif
+#ifndef CONFIG_BF518_PWM_TRIPB_PG14
+#define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
+#else
 #define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#endif
 /* RSI */
 #define P_RSI_DATA0             (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index ccab4c689dc3..5bc6938157ad 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -7,6 +7,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -265,29 +266,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -328,7 +312,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -347,7 +330,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
@@ -399,8 +381,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -442,8 +429,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index c9d6dc88f0e6..cd289698b4dd 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -8,6 +8,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -354,40 +355,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -403,21 +380,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -433,18 +395,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
@@ -452,7 +402,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -473,7 +422,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -483,7 +431,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                .mode = SPI_MODE_0,
        },
 #endif
@@ -493,7 +440,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
@@ -594,8 +540,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -637,8 +588,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index b7101aa6e3aa..9f792eafd1cc 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -7,6 +7,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -253,32 +254,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (sst25wf040) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -311,35 +296,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
-         && defined(CONFIG_SND_SOC_WM8731_SPI)
-static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -355,18 +311,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
        {
                .modalias = "mmc_spi",
@@ -385,7 +329,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -396,7 +339,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 5,
-                .controller_data = &spi_ad7879_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -407,7 +349,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select    = 5,
-                .controller_data = &spi_wm8731_chip_info,
                .mode = SPI_MODE_0,
        },
 #endif
@@ -417,7 +358,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -426,7 +366,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -479,8 +418,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -522,8 +466,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index e67ac7720668..3ecafff5d2ef 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -7,6 +7,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -409,6 +410,9 @@ static struct resource net2272_bfin_resources[] = {
                .end = 0x20300000 + 0x100,
                .flags = IORESOURCE_MEM,
        }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                .start = IRQ_PF7,
                .end = IRQ_PF7,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -448,40 +452,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -513,20 +493,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
@@ -574,9 +540,25 @@ static struct resource bfin_snd_resources[][4] = {
        BFIN_SND_RES(0),
        BFIN_SND_RES(1),
 };
+#endif
-static struct platform_device bfin_pcm = {
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
-        .name = "bfin-pcm-audio",
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
+        .id = -1,
+};
+#endif
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
        .id = -1,
 };
 #endif
@@ -605,13 +587,6 @@ static struct platform_device bfin_tdm = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -627,18 +602,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
@@ -647,7 +610,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 4,
                .platform_data = "ad1836",
-                .controller_data = &ad1836_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -670,7 +632,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -681,7 +642,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 3,
-                .controller_data = &spi_ad7879_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -691,7 +651,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -700,7 +659,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 7,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -753,8 +711,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -796,8 +759,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -1276,9 +1244,16 @@ static struct platform_device *stamp_devices[] __initdata = {
        &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_i2s_pcm,
-        &bfin_pcm,
+#endif
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_tdm_pcm,
+#endif
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
 #endif
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 18d303dd5627..3a92c4318d2d 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -8,6 +8,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -314,29 +315,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-/*
- * tll6527m V1.0 does not support native spi slave selects
- * hence DMA mode will not be useful since the ADC needs
- * CS to toggle for each sample and cs_change_per_word
- * seems to be removed from spi_bfin5xx.c
- */
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -359,21 +343,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
-        || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
@@ -382,24 +351,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
 #if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
-static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
 #include <linux/spi/mcp23s08.h>
 static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
        .chip[0].is_present = true,
@@ -429,22 +381,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC)
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc",
-                                /* Name of spi_driver for this device */
-                .max_speed_hz = 10000000,
-                                /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
-                 /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-                .mode = SPI_MODE_0,
-        },
-#endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
        {
                .modalias = "mmc_spi",
@@ -470,7 +406,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                                        /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
-                .controller_data = &spi_ad7879_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -482,7 +417,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
                .mode = SPI_CPHA | SPI_CPOL,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -491,7 +425,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,
                .bus_num = 0,
                .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -502,7 +435,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
-                .controller_data = &spi_mcp23s08_sys_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
        {
@@ -511,7 +443,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
-                .controller_data = &spi_mcp23s08_usr_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -565,8 +496,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -609,8 +545,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index e66a7e89cd3c..688470611e15 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -11,8 +11,8 @@
 */
 /* This file should be up to date with:
- *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
 /* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
 #define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
 /* Incorrect Default Internal Voltage Regulator Setting */
 #define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
+#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
 #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (1)
+#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Mode 1 Short Packet Data Corruption */
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (1)
+#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
 #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* USB Rx DMA hang */
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
 #define ANOMALY_05000466 (1)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
 #define ANOMALY_05000467 (1)
 /* PLL Latches Incorrect Settings During Reset */
 #define ANOMALY_05000469 (1)
 /* Incorrect Default MSEL Value in PLL_CTL */
 #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
 /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
 #define ANOMALY_05000483 (1)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
 /* The CODEC Zero-Cross Detect Feature is not Functional */
 #define ANOMALY_05000487 (1)
-/* IFLUSH sucks at life */
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index d4bfcea56828..47cadd316e76 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -54,7 +54,8 @@ static struct resource dm9000_resources[] = {
        [2] = {
                .start  = IRQ_PF10,
                .end    = IRQ_PF10,
-                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH),
+                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                           IORESOURCE_IRQ_SHAREABLE),
        },
 };
@@ -159,22 +160,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
@@ -195,24 +180,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 4,     /* actual baudrate is SCLK/(2xspeed_hz) */
-                .bus_num = 1, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 16,
                .bus_num = 1,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
@@ -265,8 +238,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 87b5af3693c1..18817d57c7a1 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -102,21 +102,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -151,7 +142,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 7,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
@@ -203,8 +193,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 4d5604eaa7c2..2c8f30ef6a7b 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -59,29 +59,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-/* SPI ADC chip */
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -99,24 +82,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,               /* Framework bus number */
-                .chip_select = 2,           /* Framework chip select. */
-                .platform_data = NULL,      /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
@@ -250,8 +221,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index b67b91d82242..144556e14499 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -210,29 +210,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -250,24 +227,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -276,7 +241,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
@@ -328,8 +292,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index a377d8afea03..b597d4e50d58 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -110,7 +110,6 @@ static struct platform_device dm9000_device2 = {
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,                /* if 1 - block!!! */
-        .bits_per_word = 8,
 };
 #endif
@@ -152,8 +151,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 43224ef00b8c..2afd02e14bd1 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -80,6 +80,9 @@ static struct resource net2272_bfin_resources[] = {
                .end = 0x20300000 + 0x100,
                .flags = IORESOURCE_MEM,
        }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                .start = IRQ_PF10,
                .end = IRQ_PF10,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -172,29 +175,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -221,7 +201,6 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
        .pio_interrupt = 0,
 };
 #endif
@@ -240,17 +219,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
@@ -258,7 +226,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 4,
                .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -269,7 +236,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -332,8 +298,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX + 1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -659,6 +630,41 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
+        ret = gpio_request(GPIO_PF0, "net2272");
+        if (ret)
+                return ret;
+        ret = gpio_request(GPIO_PF1, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PF0);
+                return ret;
+        }
+        ret = gpio_request(GPIO_PF11, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PF0);
+                gpio_free(GPIO_PF1);
+                return ret;
+        }
+        gpio_direction_output(GPIO_PF0, 0);
+        gpio_direction_output(GPIO_PF1, 1);
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF11, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF11, 1);
+#endif
+        return 0;
+}
 static int __init stamp_init(void)
 {
        int ret;
@@ -685,6 +691,9 @@ static int __init stamp_init(void)
        }
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
        return 0;
 }
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 72aa59440f82..03f2b40912a3 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -11,7 +11,7 @@
 */
 /* This file should be up to date with:
- *  - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -152,7 +152,7 @@
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
@@ -210,18 +210,25 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
 * here to show running on older silicon just isn't feasible.
 */
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index d582b810e7a7..604a430038e1 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -8,6 +8,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/etherdevice.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
@@ -61,29 +62,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -101,24 +85,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
@@ -334,8 +306,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -395,8 +372,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -634,7 +616,7 @@ static struct platform_device bfin_mac_device = {
 static struct pata_platform_info bfin_pata_platform_data = {
        .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+        .irq_type = IRQF_TRIGGER_HIGH,
 };
 static struct resource bfin_pata_resources[] = {
@@ -766,6 +748,24 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PG14, "net2272");
+        if (ret)
+                return ret;
+        /* Reset USB Chip, PG14 */
+        gpio_direction_output(GPIO_PG14, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PG14, 1);
+#endif
+        return 0;
+}
 static int __init cm_bf537e_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -777,6 +777,10 @@ static int __init cm_bf537e_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        return 0;
 }
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index cbb8098604c5..d916b46a44fe 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/etherdevice.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -62,29 +63,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -102,24 +86,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
@@ -335,8 +307,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -378,8 +355,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -599,7 +581,7 @@ static struct platform_device bfin_mac_device = {
 static struct pata_platform_info bfin_pata_platform_data = {
        .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+        .irq_type = IRQF_TRIGGER_HIGH,
 };
 static struct resource bfin_pata_resources[] = {
@@ -731,6 +713,36 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PH15, driver_name);
+        if (ret)
+                return ret;
+        ret = gpio_request(GPIO_PH13, "net2272");
+        if (ret) {
+                gpio_free(GPIO_PH15);
+                return ret;
+        }
+        /* Set PH15 Low make /AMS2 work properly */
+        gpio_direction_output(GPIO_PH15, 0);
+        /* enable CLKBUF output */
+        bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PH13, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PH13, 1);
+#endif
+        return 0;
+}
 static int __init cm_bf537u_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -742,6 +754,10 @@ static int __init cm_bf537u_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        return 0;
 }
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 6b4ff4605bff..5f307228be63 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -12,6 +12,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -130,7 +131,6 @@ static struct platform_device asmb_flash_device = {
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma    = 0,      /* use no dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
@@ -161,7 +161,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
        .enable_dma    = 0,      /* use no dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
@@ -238,8 +237,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -282,8 +286,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end   = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end   = IRQ_UART1_RX+1,
+                .end   = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index bfb3671a78da..3901dd093b90 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -159,14 +159,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -242,8 +240,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -285,8 +288,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 9389f03e3b0a..aebd31c845f0 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -8,6 +8,7 @@
 #include <linux/device.h>
 #include <linux/etherdevice.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -100,6 +101,7 @@ static struct platform_device smc91x_device = {
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 #include <linux/bfin_mac.h>
+#include <linux/export.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
@@ -184,40 +186,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -248,18 +226,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
@@ -267,7 +233,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -288,7 +253,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
        .bus_num                = 0,
        .chip_select            = 5,
-        .controller_data = &spi_ad7877_chip_info,
 },
 #endif
@@ -346,8 +310,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -389,8 +358,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 76db1d483173..7fbb0bbf8676 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -7,6 +7,7 @@
 */
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -367,6 +368,9 @@ static struct resource net2272_bfin_resources[] = {
                .end = 0x20300000 + 0x100,
                .flags = IORESOURCE_MEM,
        }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                .start = IRQ_PF7,
                .end = IRQ_PF7,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -533,49 +537,11 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD193X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
-static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
-        || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
-static struct bfin5xx_spi_chip adav801_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
 #include <linux/input/ad714x.h>
-static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
        {
@@ -685,7 +651,6 @@ static struct ad714x_platform_data ad7142_i2c_platform_data = {
 #if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
 static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
@@ -697,7 +662,6 @@ static unsigned short ad2s120x_platform_data[] = {
 static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
@@ -714,14 +678,12 @@ static unsigned short ad2s1210_platform_data[] = {
 static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
 static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
@@ -735,7 +697,6 @@ static unsigned short ad7816_platform_data[] = {
 static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -749,7 +710,6 @@ static unsigned long adt7310_platform_data[3] = {
 static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -758,11 +718,6 @@ static unsigned short ad7298_platform_data[] = {
        GPIO_PF7, /* busy_pin */
        0,
 };
-static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 #endif
 #if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
@@ -773,7 +728,6 @@ static unsigned long adt7316_spi_data[2] = {
 static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -800,18 +754,12 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
        .pio_interrupt = 0,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 #include <linux/spi/ad7877.h>
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -883,39 +831,13 @@ static const struct adxl34x_platform_data adxl34x_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
 #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
 static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
        .enable_dma     = 1,
-        .bits_per_word  = 8,
 };
 #endif
 #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
-static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
-        .bits_per_word = 16,
-};
 #include <linux/spi/adf702x.h>
 #define TXREG 0x0160A470
 static const u32 adf7021_regs[] = {
@@ -959,10 +881,6 @@ static inline void adf702x_mac_init(void) {}
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 #include <linux/spi/ads7846.h>
-static struct bfin5xx_spi_chip ad7873_spi_chip_info = {
-        .bits_per_word  = 8,
-};
 static int ads7873_get_pendown_state(void)
 {
        return gpio_get_value(GPIO_PF6);
@@ -1009,21 +927,12 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 /* DataFlash chip */
 static struct bfin5xx_spi_chip data_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
 static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
@@ -1053,27 +962,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) \
-        || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+        || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        {
-                .modalias = "ad183x",
+                .modalias = "ad1836",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
                .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -1084,18 +981,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 5,
-                .controller_data = &ad1938_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
+#if defined(CONFIG_SND_SOC_ADAV80X) || defined(CONFIG_SND_SOC_ADV80X_MODULE)
        {
-                .modalias = "adav80x",
+                .modalias = "adav801",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &adav801_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -1109,7 +1004,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 5,
                .mode = SPI_MODE_3,
                .platform_data = &ad7147_spi_platform_data,
-                .controller_data = &ad7147_spi_chip_info,
        },
 #endif
@@ -1188,7 +1082,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 4,            /* CS, change it for your board */
                .platform_data = ad7298_platform_data,
-                .controller_data = &ad7298_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -1225,7 +1118,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select  = 1,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -1236,7 +1128,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spi_ad7879_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -1246,7 +1137,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -1255,7 +1145,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 2,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -1278,7 +1167,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz   = 5000000,    /* max spi clock (SCK) speed in HZ */
                .bus_num        = 0,
                .chip_select    = 2,
-                .controller_data = &spi_adxl34x_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -1288,7 +1176,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 16000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
-                .controller_data = &adf7021_spi_chip_info,
                .platform_data = &adf7021_platform_data,
                .mode = SPI_MODE_0,
        },
@@ -1300,7 +1187,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .irq = IRQ_PF6,
                .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
-                .controller_data = &ad7873_spi_chip_info,
                .platform_data = &ad7873_pdata,
                .mode = SPI_MODE_0,
        },
@@ -1681,8 +1567,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -1736,8 +1627,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -2216,7 +2112,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
+#if defined(CONFIG_SND_SOC_ADAV80X) || defined(CONFIG_SND_SOC_ADAV80X_MODULE)
        {
                I2C_BOARD_INFO("adav803", 0x10),
        },
@@ -2249,23 +2145,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_AD7414) || defined(CONFIG_AD7414_MODULE)
-        {
-                I2C_BOARD_INFO("ad7414", 0x9),
-                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
-        },
-#endif
-#if defined(CONFIG_AD7416) || defined(CONFIG_AD7416_MODULE)
-        {
-                I2C_BOARD_INFO("ad7417", 0xb),
-                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
-                .platform_data = (void *)GPIO_PF4,
-        },
-#endif
 #if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE)
        {
                I2C_BOARD_INFO("ade7854", 0x38),
@@ -2276,15 +2155,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        {
                I2C_BOARD_INFO("adt75", 0x9),
                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
-        },
-#endif
-#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE)
-        {
-                I2C_BOARD_INFO("adt7408", 0x18),
-                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
        },
 #endif
@@ -2293,7 +2163,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                I2C_BOARD_INFO("adt7410", 0x48),
                /* CT critical temperature event. line 0 */
                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
                .platform_data = (void *)&adt7410_platform_data,
        },
 #endif
@@ -2302,7 +2171,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        {
                I2C_BOARD_INFO("ad7291", 0x20),
                .irq = IRQ_PG5,
-                .irq_flags = IRQF_TRIGGER_LOW,
        },
 #endif
@@ -2390,6 +2258,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                I2C_BOARD_INFO("adau1361", 0x38),
        },
 #endif
+#if defined(CONFIG_SND_SOC_ADAU1701) || defined(CONFIG_SND_SOC_ADAU1701_MODULE)
+        {
+                I2C_BOARD_INFO("adau1701", 0x34),
+        },
+#endif
 #if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
        {
                I2C_BOARD_INFO("ad5258", 0x18),
@@ -2503,7 +2376,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #define PATA_INT        IRQ_PF5
 static struct pata_platform_info bfin_pata_platform_data = {
        .ioport_shift = 1,
-        .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+        .irq_flags = IRQF_TRIGGER_HIGH,
 };
 static struct resource bfin_pata_resources[] = {
@@ -2632,20 +2505,44 @@ static struct resource bfin_snd_resources[][4] = {
        BFIN_SND_RES(0),
        BFIN_SND_RES(1),
 };
+#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
-static struct platform_device bfin_pcm = {
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        .name = "bfin-pcm-audio",
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
+        .id = -1,
+};
+#endif
+#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
 static struct platform_device bfin_ad73311_codec_device = {
        .name = "ad73311",
        .id = -1,
 };
 #endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X_MODULE)
+static struct platform_device bfin_eval_adav801_device = {
+        .name = "bfin-eval-adav801",
+        .id = -1,
+};
+#endif
 #if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
@@ -2760,6 +2657,20 @@ static struct platform_device iio_gpio_trigger = {
 };
 #endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373_MODULE)
+static struct platform_device bf5xx_adau1373_device = {
+        .name = "bfin-eval-adau1373",
+};
+#endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701_MODULE)
+static struct platform_device bf5xx_adau1701_device = {
+        .name = "bfin-eval-adau1701",
+};
+#endif
 static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
@@ -2869,13 +2780,19 @@ static struct platform_device *stamp_devices[] __initdata = {
        &stamp_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+        &bfin_i2s_pcm,
-        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#endif
-        &bfin_pcm,
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_tdm_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
+#endif
+#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
        &bfin_ad73311_codec_device,
 #endif
@@ -2914,8 +2831,41 @@ static struct platform_device *stamp_devices[] __initdata = {
        defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
        &iio_gpio_trigger,
 #endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373_MODULE)
+        &bf5xx_adau1373_device,
+#endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701_MODULE)
+        &bf5xx_adau1701_device,
+#endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X_MODULE)
+        &bfin_eval_adav801_device,
+#endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PF6, "net2272");
+        if (ret)
+                return ret;
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF6, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF6, 1);
+#endif
+        return 0;
+}
 static int __init stamp_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -2926,6 +2876,9 @@ static int __init stamp_init(void)
                                ARRAY_SIZE(bfin_i2c_board_info));
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        return 0;
 }
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 164a7e02c022..6917ce2fa55e 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/etherdevice.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -62,29 +63,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -102,24 +86,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
@@ -335,8 +307,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -378,8 +355,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -601,7 +583,7 @@ static struct platform_device bfin_mac_device = {
 static struct pata_platform_info bfin_pata_platform_data = {
        .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+        .irq_type = IRQF_TRIGGER_HIGH,
 };
 static struct resource bfin_pata_resources[] = {
@@ -733,6 +715,24 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PG14, "net2272");
+        if (ret)
+                return ret;
+        /* Reset USB Chip, PG14 */
+        gpio_direction_output(GPIO_PG14, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PG14, 1);
+#endif
+        return 0;
+}
 static int __init tcm_bf537_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -744,6 +744,10 @@ static int __init tcm_bf537_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        return 0;
 }
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 7f8e5a9f5db6..543cd3fb305e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -11,7 +11,7 @@
 */
 /* This file should be up to date with:
- *  - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -44,18 +44,12 @@
 #define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
 #define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (1)
 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
 #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
 /* EMAC TX DMA Error After an Early Frame Abort */
@@ -98,7 +92,7 @@
 #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
 /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
 #define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
@@ -162,9 +156,9 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
@@ -172,8 +166,26 @@
 #define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* Buffered CLKIN Output Is Disabled by Default */
+#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index e61424ef35eb..8356eb599f19 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -49,8 +49,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -104,8 +109,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -147,8 +157,13 @@ static struct resource bfin_uart2_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART2_TX,
+                .end = IRQ_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART2_RX,
-                .end = IRQ_UART2_RX+1,
+                .end = IRQ_UART2_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -502,7 +517,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
@@ -523,13 +537,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
@@ -559,20 +566,6 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
-static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
-        .enable_dma     = 0,
-        .bits_per_word  = 8,
-};
-#endif
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -595,7 +588,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spi_ad7879_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -605,7 +597,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 2,
-                .controller_data = &lq035q1_spi_chip_info,
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
@@ -615,7 +606,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
index 180b1252679f..471a9b184d5b 100644
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -1,7 +1,7 @@
 /*
 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
 *
- * Copyright 2009 Analog Devices Inc.
+ * Copyright 2009-2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */
@@ -121,3 +121,38 @@ static int __init bf538_extgpio_setup(void)
                gpiochip_add(&bf538_porte_chip);
 }
 arch_initcall(bf538_extgpio_setup);
+#ifdef CONFIG_PM
+static struct {
+        u16 data, dir, inen;
+} gpio_bank_saved[3];
+static void __iomem * const port_bases[3] = {
+        (void *)PORTCIO,
+        (void *)PORTDIO,
+        (void *)PORTEIO,
+};
+void bfin_special_gpio_pm_hibernate_suspend(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
+                gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
+                gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
+                gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
+        }
+}
+void bfin_special_gpio_pm_hibernate_restore(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
+                write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
+                write_PORTIO_SET(port_bases[i],
+                        gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
+                write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
+        }
+}
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 55e7d0712a94..b6ca99788710 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -11,8 +11,8 @@
 */
 /* This file should be up to date with:
- *  - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ *  - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- *  - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ *  - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -56,25 +56,21 @@
 #define ANOMALY_05000229 (1)
 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
 #define ANOMALY_05000233 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Maximum External Clock Speed for Timers */
 #define ANOMALY_05000253 (1)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
 #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
+#define ANOMALY_05000272 (ANOMALY_BF538)
 /* Writes to Synchronous SDRAM Memory May Be Lost */
 #define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
 #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
 #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
@@ -102,8 +98,10 @@
 #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
 #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
+#define ANOMALY_05000317 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000318 */
 /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
+#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)     /* XXX: Same as 05000317 */
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
 #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -134,16 +132,32 @@
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 #define ANOMALY_05000462 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 8a5beeece996..3561c7d8935b 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -8,7 +8,10 @@
 #define _MACH_GPIO_H_
 #define MAX_BLACKFIN_GPIOS 16
+#ifdef CONFIG_GPIOLIB
+/* We only use the special logic with GPIOLIB devices */
 #define BFIN_SPECIAL_GPIO_BANKS 3
+#endif
 #define GPIO_PF0        0       /* PF */
 #define GPIO_PF1        1
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index d11502ac5623..0350eacec21b 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -135,8 +135,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -178,8 +183,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -237,8 +247,13 @@ static struct resource bfin_uart2_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART2_TX,
+                .end = IRQ_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART2_RX,
-                .end = IRQ_UART2_RX+1,
+                .end = IRQ_UART2_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -280,8 +295,13 @@ static struct resource bfin_uart3_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART3_TX,
+                .end = IRQ_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART3_RX,
-                .end = IRQ_UART3_RX+1,
+                .end = IRQ_UART3_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -861,16 +881,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -886,13 +900,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bf54x_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -915,7 +922,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
        .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
        .bus_num                = 0,
        .chip_select            = 2,
-        .controller_data = &spi_ad7877_chip_info,
 },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -924,7 +930,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 311bf9970fe7..bb868ac0fe2d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -241,8 +241,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART0_RX,
-                .end = IRQ_UART0_RX+1,
+                .end = IRQ_UART0_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -284,8 +289,13 @@ static struct resource bfin_uart1_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART1_RX,
-                .end = IRQ_UART1_RX+1,
+                .end = IRQ_UART1_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -343,8 +353,13 @@ static struct resource bfin_uart2_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART2_TX,
+                .end = IRQ_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART2_RX,
-                .end = IRQ_UART2_RX+1,
+                .end = IRQ_UART2_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -386,8 +401,13 @@ static struct resource bfin_uart3_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART3_TX,
+                .end = IRQ_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART3_RX,
-                .end = IRQ_UART3_RX+1,
+                .end = IRQ_UART3_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -1018,24 +1038,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
 };
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
-static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -1051,20 +1057,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
-static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
-        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
        || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1086,7 +1078,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 1,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@@ -1097,7 +1088,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
                .bus_num                = 0,
                .chip_select            = 2,
-                .controller_data = &spi_ad7877_chip_info,
        },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1106,7 +1096,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@@ -1117,7 +1106,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num                = 1,
                .chip_select            = 2,
-                .controller_data = &spi_adxl34x_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 9e70785bdde3..ac96ee83b00e 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -11,7 +11,7 @@
 */
 /* This file should be up to date with:
- *  - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -29,117 +29,37 @@
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (1)
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* FIFO Boot Mode Not Functional */
 #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
 /*
 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
 *       shows that the fix itself does not cover all cases.
 */
 #define ANOMALY_05000353 (1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
 #define ANOMALY_05000357 (1)
 /* External Memory Read Access Hangs Core With PLL Bypass */
 #define ANOMALY_05000360 (1)
 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
 #define ANOMALY_05000365 (1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
 #define ANOMALY_05000369 (1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
 #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
 #define ANOMALY_05000379 (1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Some ATAPI Modes Are Not Functional */
-#define ANOMALY_05000383 (1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
 /* Lockbox SESR Disallows Certain User Interrupts */
 #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@@ -161,7 +81,7 @@
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_05000416 (1)
 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@@ -174,8 +94,6 @@
 #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
 /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
 #define ANOMALY_05000434 (1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@@ -186,34 +104,32 @@
 #define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
 /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
 #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Mode 1 Short Packet Data Corruption */
+/* USB DMA Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 #define ANOMALY_05000456 (1)
 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 #define ANOMALY_05000457 (1)
 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
+#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
+#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
 /* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (1)
+#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
 /* USB TX DMA Hang */
-#define ANOMALY_05000464 (1)
+#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA hang */
+/* USB Rx DMA Hang */
 #define ANOMALY_05000465 (1)
 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
+#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
+#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
+/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (1)
+#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -223,9 +139,111 @@
 /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
 #define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
+#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
+#define ANOMALY_05000500 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
+#define ANOMALY_05000502 (1)
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+/* False Hardware Error when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 7db433514e3f..35c8ced46158 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -170,6 +170,8 @@
 #define MAX_BLACKFIN_GPIOS 160
+#define BFIN_GPIO_PINT 1
 #ifndef __ASSEMBLY__
 struct gpio_port_t {
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 533b8095b540..10dc142c518d 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -438,7 +438,7 @@
 struct bfin_pint_regs {
        u32 mask_set;
        u32 mask_clear;
-        u32 irq;
+        u32 request;
        u32 assign;
        u32 edge_set;
        u32 edge_clear;
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 9231a942892b..b1b7339b6ba7 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -203,8 +203,13 @@ static struct resource bfin_uart0_resources[] = {
         .flags = IORESOURCE_MEM,
         },
        {
+         .start = IRQ_UART_TX,
+         .end = IRQ_UART_TX,
+         .flags = IORESOURCE_IRQ,
+         },
+        {
         .start = IRQ_UART_RX,
-         .end = IRQ_UART_RX + 1,
+         .end = IRQ_UART_RX,
         .flags = IORESOURCE_IRQ,
         },
        {
@@ -364,14 +369,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
 /* DataFlash chip */
 static struct bfin5xx_spi_chip data_flash_chip_info = {
        .enable_dma = 0,        /* use dma transfer with this chip */
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -420,7 +417,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
         .bus_num = 0,
         .chip_select = 3,
-         .controller_data = &spidev_chip_info,
         },
 #endif
 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 87595cd38afe..c017cf07ed4e 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -60,29 +60,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
 /* SPI flash chip (m25p64) */
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
-        .bits_per_word = 8,
-};
-#endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-/* SPI ADC chip */
-static struct bfin5xx_spi_chip spi_adc_chip_info = {
-        .enable_dma = 1,         /* use dma transfer with this chip*/
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
 };
 #endif
@@ -100,24 +77,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
-        {
-                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
-                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. */
-                .platform_data = NULL, /* No spi_driver specific config */
-                .controller_data = &spi_adc_chip_info,
-        },
-#endif
 #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 4,
-                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -126,7 +91,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &mmc_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -313,8 +277,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART_TX,
+                .end = IRQ_UART_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART_RX,
-                .end = IRQ_UART_RX+1,
+                .end = IRQ_UART_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -384,7 +353,7 @@ static struct platform_device bfin_sir0_device = {
 static struct pata_platform_info bfin_pata_platform_data = {
        .ioport_shift = 2,
-        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+        .irq_type = IRQF_TRIGGER_HIGH,
 };
 static struct resource bfin_pata_resources[] = {
@@ -532,6 +501,24 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PF46, "net2272");
+        if (ret)
+                return ret;
+        /* Reset USB Chip, PF46 */
+        gpio_direction_output(GPIO_PF46, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF46, 1);
+#endif
+        return 0;
+}
 static int __init cm_bf561_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -543,6 +530,10 @@ static int __init cm_bf561_init(void)
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        return 0;
 }
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 5067984a62e7..27f22ed381d9 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -108,6 +108,9 @@ static struct resource net2272_bfin_resources[] = {
                .end = 0x2C000000 + 0x7F,
                .flags = IORESOURCE_MEM,
        }, {
+                .start = 1,
+                .flags = IORESOURCE_BUS,
+        }, {
                .start = IRQ_PF10,
                .end = IRQ_PF10,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -169,8 +172,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART_TX,
+                .end = IRQ_UART_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART_RX,
-                .end = IRQ_UART_RX+1,
+                .end = IRQ_UART_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
@@ -283,21 +291,6 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
-static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 16,
-};
-#endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-static struct bfin5xx_spi_chip spidev_chip_info = {
-        .enable_dma = 0,
-        .bits_per_word = 8,
-};
-#endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
@@ -345,7 +338,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 4,
                .platform_data = "ad1836", /* only includes chip name for the moment */
-                .controller_data = &ad1836_spi_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
@@ -355,7 +347,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0,
                .chip_select = 1,
-                .controller_data = &spidev_chip_info,
        },
 #endif
 };
@@ -516,6 +507,24 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 };
+static int __init net2272_init(void)
+{
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+        int ret;
+        ret = gpio_request(GPIO_PF11, "net2272");
+        if (ret)
+                return ret;
+        /* Reset the USB chip */
+        gpio_direction_output(GPIO_PF11, 0);
+        mdelay(2);
+        gpio_set_value(GPIO_PF11, 1);
+#endif
+        return 0;
+}
 static int __init ezkit_init(void)
 {
        int ret;
@@ -542,6 +551,9 @@ static int __init ezkit_init(void)
        udelay(400);
 #endif
+        if (net2272_init())
+                pr_warning("unable to configure net2272; it probably won't work\n");
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
        return 0;
 }
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index bb056e60f6ed..1a57bc986aad 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -51,8 +51,13 @@ static struct resource bfin_uart0_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        {
+                .start = IRQ_UART_TX,
+                .end = IRQ_UART_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
                .start = IRQ_UART_RX,
-                .end = IRQ_UART_RX+1,
+                .end = IRQ_UART_RX,
                .flags = IORESOURCE_IRQ,
        },
        {
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22b5ab773027..836baeed303a 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -11,7 +11,7 @@
 */
 /* This file should be up to date with:
- *  - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -26,62 +26,16 @@
 #define ANOMALY_05000074 (1)
 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
 /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
 #define ANOMALY_05000120 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
 /* SIGNBITS Instruction Not Functional under Certain Conditions */
 #define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
 /* IMDMA S1/D1 Channel May Stall */
 #define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
 #define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
 #define ANOMALY_05000166 (1)
 /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
@@ -92,10 +46,6 @@
 #define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
 /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
 #define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
 /* Cache Fill Buffer Data lost */
 #define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
 /* Overlapping Sequencer and Memory Stalls */
@@ -124,8 +74,6 @@
 #define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
 /* PPI Not Functional at Core Voltage < 1Volt */
 #define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
 #define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
@@ -217,10 +165,10 @@
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error when ISR Context Is Not Restored */
 /* Temporarily walk around for bug 5423 till this issue is confirmed by
 * official anomaly document. It looks 05000281 still exists on bf561
 * v0.5.
@@ -274,8 +222,6 @@
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
 /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -298,16 +244,82 @@
 #define ANOMALY_05000462 (1)
 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
 #define ANOMALY_05000471 (1)
-/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 #define ANOMALY_05000473 (1)
-/* Possible Lockup Condition whem Modifying PLL from External Memory */
+/* Possible Lockup Condition when Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* PLL May Latch Incorrect Values Coming Out of Reset */
+#define ANOMALY_05000489 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 #define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
+/*
+ * These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Erroneous Exception when Enabling Cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000119 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 57d5eab59faf..f9f8b2adf4ba 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -58,9 +58,9 @@
 #define GPIO_PF46       46
 #define GPIO_PF47       47
-#define PORT_FIO0 GPIO_0
+#define PORT_FIO0 GPIO_PF0
-#define PORT_FIO1 GPIO_16
+#define PORT_FIO1 GPIO_PF16
-#define PORT_FIO2 GPIO_32
+#define PORT_FIO2 GPIO_PF32
 #include <mach-common/ports-f.h>
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4c462838f4e1..01e5408620ac 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -23,108 +23,78 @@
 #define INITIAL_STACK   (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
 ENTRY(_coreb_trampoline_start)
-        /* Set the SYSCFG register */
+        /* Enable Cycle Counter and Nesting Of Interrupts */
-        R0 = 0x36;
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
-        SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+        R0 = SYSCFG_SNEN;
-        R0 = 0;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-        /*Clear Out All the data and pointer  Registers*/
+#endif
-        R1 = R0;
+        SYSCFG = R0;
-        R2 = R0;
-        R3 = R0;
-        R4 = R0;
-        R5 = R0;
-        R6 = R0;
-        R7 = R0;
-        P0 = R0;
-        P1 = R0;
-        P2 = R0;
-        P3 = R0;
-        P4 = R0;
-        P5 = R0;
-        LC0 = r0;
-        LC1 = r0;
-        L0 = r0;
-        L1 = r0;
-        L2 = r0;
-        L3 = r0;
-        /* Clear Out All the DAG Registers*/
-        B0 = r0;
-        B1 = r0;
-        B2 = r0;
-        B3 = r0;
-        I0 = r0;
-        I1 = r0;
-        I2 = r0;
-        I3 = r0;
-        M0 = r0;
-        M1 = r0;
-        M2 = r0;
-        M3 = r0;
-        trace_buffer_init(p0,r0);
+        /* Optimization register tricks: keep a base value in the
+         * reserved P registers so we use the load/store with an
+         * offset syntax.  R0 = [P5 + <constant>];
+         *   P5 - core MMR base
+         *   R6 - 0
+         */
+        r6 = 0;
+        p5.l = 0;
+        p5.h = hi(COREMMR_BASE);
-        /* Turn off the icache */
+        /* Zero out registers required by Blackfin ABI */
-        p0.l = LO(IMEM_CONTROL);
-        p0.h = HI(IMEM_CONTROL);
-        R1 = [p0];
-        R0 = ~ENICPLB;
-        R0 = R0 & R1;
-        /* Disabling of CPLBs should be proceeded by a CSYNC */
+        /* Disable circular buffers */
+        L0 = r6;
+        L1 = r6;
+        L2 = r6;
+        L3 = r6;
+        /* Disable hardware loops in case we were started by 'go' */
+        LC0 = r6;
+        LC1 = r6;
+        /*
+         * Clear ITEST_COMMAND and DTEST_COMMAND registers,
+         * Leaving these as non-zero can confuse the emulator
+         */
+        [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
+        [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
        CSYNC;
-        [p0] = R0;
+        trace_buffer_init(p0,r0);
+        /* Turn off the icache */
+        r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
+        BITCLR (r1, ENICPLB_P);
+        [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
        SSYNC;
        /* Turn off the dcache */
-        p0.l = LO(DMEM_CONTROL);
+        r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
-        p0.h = HI(DMEM_CONTROL);
+        BITCLR (r1, ENDCPLB_P);
-        R1 = [p0];
+        [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
-        R0 = ~ENDCPLB;
-        R0 = R0 & R1;
-        /* Disabling of CPLBs should be proceeded by a CSYNC */
-        CSYNC;
-        [p0] = R0;
        SSYNC;
        /* in case of double faults, save a few things */
-        p0.l = _init_retx_coreb;
+        p1.l = _initial_pda_coreb;
-        p0.h = _init_retx_coreb;
+        p1.h = _initial_pda_coreb;
-        R0 = RETX;
+        r4 = RETX;
-        [P0] = R0;
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
        /* Only save these if we are storing them,
         * This happens here, since L1 gets clobbered
         * below
         */
        GET_PDA(p0, r0);
-        r7 = [p0 + PDA_DF_RETX];
+        r0 = [p0 + PDA_DF_RETX];
-        p1.l = _init_saved_retx_coreb;
+        r1 = [p0 + PDA_DF_DCPLB];
-        p1.h = _init_saved_retx_coreb;
+        r2 = [p0 + PDA_DF_ICPLB];
-        [p1] = r7;
+        r3 = [p0 + PDA_DF_SEQSTAT];
+        [p1 + PDA_INIT_DF_RETX] = r0;
-        r7 = [p0 + PDA_DF_DCPLB];
+        [p1 + PDA_INIT_DF_DCPLB] = r1;
-        p1.l = _init_saved_dcplb_fault_addr_coreb;
+        [p1 + PDA_INIT_DF_ICPLB] = r2;
-        p1.h = _init_saved_dcplb_fault_addr_coreb;
+        [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-        [p1] = r7;
-        r7 = [p0 + PDA_DF_ICPLB];
-        p1.l = _init_saved_icplb_fault_addr_coreb;
-        p1.h = _init_saved_icplb_fault_addr_coreb;
-        [p1] = r7;
-        r7 = [p0 + PDA_DF_SEQSTAT];
-        p1.l = _init_saved_seqstat_coreb;
-        p1.h = _init_saved_seqstat_coreb;
-        [p1] = r7;
 #endif
+        [p1 + PDA_INIT_RETX] = r4;
        /* Initialize stack pointer */
        sp.l = lo(INITIAL_STACK);
@@ -138,19 +108,13 @@ ENTRY(_coreb_trampoline_start)
        /* EVT15 = _real_start */
-        p0.l = lo(EVT15);
-        p0.h = hi(EVT15);
        p1.l = _coreb_start;
        p1.h = _coreb_start;
-        [p0] = p1;
+        [p5 + (EVT15 - COREMMR_BASE)] = p1;
        csync;
-        p0.l = lo(IMASK);
+        r0 = EVT_IVG15 (z);
-        p0.h = hi(IMASK);
+        sti r0;
-        p1.l = IMASK_IVG15;
-        p1.h = 0x0;
-        [p0] = p1;
-        csync;
        raise 15;
        p0.l = .LWAIT_HERE;
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 85abd8be1343..db22401e7605 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -114,7 +114,7 @@ void __init platform_request_ipi(int irq, void *handler)
        int ret;
        const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
-        ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
+        ret = request_irq(irq, handler, IRQF_PERCPU, name, handler);
        if (ret)
                panic("Cannot request %s for IPI service", name);
 }
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 85dc6d69f9c0..2e6eefd812f4 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -7,6 +7,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 9cfdd49a3127..1c534d298de4 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -12,8 +12,8 @@
 .section .l1.text
 ENTRY(_sleep_mode)
-        [--SP] = ( R7:0, P5:0 );
+        [--SP] = (R7:4, P5:3);
-        [--SP] =  RETS;
+        [--SP] = RETS;
        call _set_sic_iwr;
@@ -46,15 +46,25 @@ ENTRY(_sleep_mode)
        call _test_pll_locked;
        RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
+        (R7:4, P5:3) = [SP++];
        RTS;
 ENDPROC(_sleep_mode)
+/*
+ * This func never returns as it puts the part into hibernate, and
+ * is only called from do_hibernate, so we don't bother saving or
+ * restoring any of the normal C runtime state.  When we wake up,
+ * the entry point will be in do_hibernate and not here.
+ *
+ * We accept just one argument -- the value to write to VR_CTL.
+ */
 ENTRY(_hibernate_mode)
-        [--SP] = ( R7:0, P5:0 );
+        /* Save/setup the regs we need early for minor pipeline optimization */
-        [--SP] =  RETS;
+        R4 = R0;
+        P3.H = hi(VR_CTL);
+        P3.L = lo(VR_CTL);
-        R3 = R0;
+        /* Disable all wakeup sources */
        R0 = IWR_DISABLE_ALL;
        R1 = IWR_DISABLE_ALL;
        R2 = IWR_DISABLE_ALL;
@@ -62,10 +72,8 @@ ENTRY(_hibernate_mode)
        call _set_dram_srfs;
        SSYNC;
-        P0.H = hi(VR_CTL);
+        /* Finally, we climb into our cave to hibernate */
-        P0.L = lo(VR_CTL);
+        W[P3] = R4.L;
-        W[P0] = R3.L;
        CLI R2;
        IDLE;
 .Lforever:
@@ -73,8 +81,8 @@ ENTRY(_hibernate_mode)
 ENDPROC(_hibernate_mode)
 ENTRY(_sleep_deeper)
-        [--SP] = ( R7:0, P5:0 );
+        [--SP] = (R7:4, P5:3);
-        [--SP] =  RETS;
+        [--SP] = RETS;
        CLI R4;
@@ -167,7 +175,7 @@ ENTRY(_sleep_deeper)
        STI R4;
        RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
+        (R7:4, P5:3) = [SP++];
        RTS;
 ENDPROC(_sleep_deeper)
@@ -188,21 +196,20 @@ ENTRY(_set_dram_srfs)
 #else                           /* SDRAM */
        P0.L = lo(EBIU_SDGCTL);
        P0.H = hi(EBIU_SDGCTL);
+        P1.L = lo(EBIU_SDSTAT);
+        P1.H = hi(EBIU_SDSTAT);
        R2 = [P0];
        BITSET(R2, 24); /* SRFS enter self-refresh mode */
        [P0] = R2;
        SSYNC;
-        P0.L = lo(EBIU_SDSTAT);
-        P0.H = hi(EBIU_SDSTAT);
 1:
-        R2 = w[P0];
+        R2 = w[P1];
        SSYNC;
        cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
        if !cc jump 1b;
-        P0.L = lo(EBIU_SDGCTL);
-        P0.H = hi(EBIU_SDGCTL);
        R2 = [P0];
        BITCLR(R2, 0); /* SCTLE disable CLKOUT */
        [P0] = R2;
@@ -212,6 +219,7 @@ ENDPROC(_set_dram_srfs)
 ENTRY(_unset_dram_srfs)
        /*  set the dram out of self refresh mode */
 #if defined(EBIU_RSTCTL)        /* DDR */
        P0.H = hi(EBIU_RSTCTL);
        P0.L = lo(EBIU_RSTCTL);
@@ -219,42 +227,39 @@ ENTRY(_unset_dram_srfs)
        BITCLR(R2, 3); /* clear SRREQ bit */
        [P0] = R2;
 #elif defined(EBIU_SDGCTL)      /* SDRAM */
+        /* release CLKOUT from self-refresh */
-        P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
+        P0.L = lo(EBIU_SDGCTL);
        P0.H = hi(EBIU_SDGCTL);
        R2 = [P0];
        BITSET(R2, 0); /* SCTLE enable CLKOUT */
        [P0] = R2
        SSYNC;
-        P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
+        /* release SDRAM from self-refresh */
-        P0.H = hi(EBIU_SDGCTL);
        R2 = [P0];
        BITCLR(R2, 24); /* clear SRFS bit */
        [P0] = R2
 #endif
        SSYNC;
        RTS;
 ENDPROC(_unset_dram_srfs)
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
+#ifdef SIC_IWR0
-        defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
+        P0.H = hi(SYSMMR_BASE);
-        P0.H = hi(SIC_IWR0);
+        P0.L = lo(SYSMMR_BASE);
-        P0.L = lo(SIC_IWR0);
+        [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
-        P1.H = hi(SIC_IWR1);
+        [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
-        P1.L = lo(SIC_IWR1);
+# ifdef SIC_IWR2
-        [P1] = R1;
+        [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
-#if defined(CONFIG_BF54x)
+# endif
-        P1.H = hi(SIC_IWR2);
-        P1.L = lo(SIC_IWR2);
-        [P1] = R2;
-#endif
 #else
        P0.H = hi(SIC_IWR);
        P0.L = lo(SIC_IWR);
-#endif
        [P0] = R0;
+#endif
        SSYNC;
        RTS;
@@ -272,206 +277,55 @@ ENDPROC(_test_pll_locked)
 .section .text
-ENTRY(_do_hibernate)
+#define PM_REG0  R7
-        [--SP] = ( R7:0, P5:0 );
+#define PM_REG1  R6
-        [--SP] =  RETS;
+#define PM_REG2  R5
-        /* Save System MMRs */
+#define PM_REG3  R4
-        R2 = R0;
+#define PM_REG4  R3
-        P0.H = hi(PLL_CTL);
+#define PM_REG5  R2
-        P0.L = lo(PLL_CTL);
+#define PM_REG6  R1
+#define PM_REG7  R0
-#ifdef SIC_IMASK0
+#define PM_REG8  P5
-        PM_SYS_PUSH(SIC_IMASK0)
+#define PM_REG9  P4
-#endif
+#define PM_REG10 P3
-#ifdef SIC_IMASK1
+#define PM_REG11 P2
-        PM_SYS_PUSH(SIC_IMASK1)
+#define PM_REG12 P1
-#endif
+#define PM_REG13 P0
-#ifdef SIC_IMASK2
-        PM_SYS_PUSH(SIC_IMASK2)
+#define PM_REGSET0  R7:7
-#endif
+#define PM_REGSET1  R7:6
-#ifdef SIC_IMASK
+#define PM_REGSET2  R7:5
-        PM_SYS_PUSH(SIC_IMASK)
+#define PM_REGSET3  R7:4
-#endif
+#define PM_REGSET4  R7:3
-#ifdef SIC_IAR0
+#define PM_REGSET5  R7:2
-        PM_SYS_PUSH(SIC_IAR0)
+#define PM_REGSET6  R7:1
-        PM_SYS_PUSH(SIC_IAR1)
+#define PM_REGSET7  R7:0
-        PM_SYS_PUSH(SIC_IAR2)
+#define PM_REGSET8  R7:0, P5:5
-#endif
+#define PM_REGSET9  R7:0, P5:4
-#ifdef SIC_IAR3
+#define PM_REGSET10 R7:0, P5:3
-        PM_SYS_PUSH(SIC_IAR3)
+#define PM_REGSET11 R7:0, P5:2
-#endif
+#define PM_REGSET12 R7:0, P5:1
-#ifdef SIC_IAR4
+#define PM_REGSET13 R7:0, P5:0
-        PM_SYS_PUSH(SIC_IAR4)
-        PM_SYS_PUSH(SIC_IAR5)
+#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-        PM_SYS_PUSH(SIC_IAR6)
+#define _PM_POP(n, x, w, base)  w[FP + ((x) - (base))] = PM_REG##n;
-#endif
+#define PM_PUSH_SYNC(n)         [--sp] = (PM_REGSET##n);
-#ifdef SIC_IAR7
+#define PM_POP_SYNC(n)          (PM_REGSET##n) = [sp++];
-        PM_SYS_PUSH(SIC_IAR7)
+#define PM_PUSH(n, x)           PM_REG##n = [FP++];
-#endif
+#define PM_POP(n, x)            [FP--] = PM_REG##n;
-#ifdef SIC_IAR8
+#define PM_CORE_PUSH(n, x)      _PM_PUSH(n, x, , COREMMR_BASE)
-        PM_SYS_PUSH(SIC_IAR8)
+#define PM_CORE_POP(n, x)       _PM_POP(n, x, , COREMMR_BASE)
-        PM_SYS_PUSH(SIC_IAR9)
+#define PM_SYS_PUSH(n, x)       _PM_PUSH(n, x, , SYSMMR_BASE)
-        PM_SYS_PUSH(SIC_IAR10)
+#define PM_SYS_POP(n, x)        _PM_POP(n, x, , SYSMMR_BASE)
-        PM_SYS_PUSH(SIC_IAR11)
+#define PM_SYS_PUSH16(n, x)     _PM_PUSH(n, x, w, SYSMMR_BASE)
-#endif
+#define PM_SYS_POP16(n, x)      _PM_POP(n, x, w, SYSMMR_BASE)
-#ifdef SIC_IWR
+ENTRY(_do_hibernate)
-        PM_SYS_PUSH(SIC_IWR)
+        /*
-#endif
+         * Save the core regs early so we can blow them away when
-#ifdef SIC_IWR0
+         * saving/restoring MMR states
-        PM_SYS_PUSH(SIC_IWR0)
+         */
-#endif
+        [--sp] = (R7:0, P5:0);
-#ifdef SIC_IWR1
-        PM_SYS_PUSH(SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
-        PM_SYS_PUSH(SIC_IWR2)
-#endif
-#ifdef PINT0_ASSIGN
-        PM_SYS_PUSH(PINT0_MASK_SET)
-        PM_SYS_PUSH(PINT1_MASK_SET)
-        PM_SYS_PUSH(PINT2_MASK_SET)
-        PM_SYS_PUSH(PINT3_MASK_SET)
-        PM_SYS_PUSH(PINT0_ASSIGN)
-        PM_SYS_PUSH(PINT1_ASSIGN)
-        PM_SYS_PUSH(PINT2_ASSIGN)
-        PM_SYS_PUSH(PINT3_ASSIGN)
-        PM_SYS_PUSH(PINT0_INVERT_SET)
-        PM_SYS_PUSH(PINT1_INVERT_SET)
-        PM_SYS_PUSH(PINT2_INVERT_SET)
-        PM_SYS_PUSH(PINT3_INVERT_SET)
-        PM_SYS_PUSH(PINT0_EDGE_SET)
-        PM_SYS_PUSH(PINT1_EDGE_SET)
-        PM_SYS_PUSH(PINT2_EDGE_SET)
-        PM_SYS_PUSH(PINT3_EDGE_SET)
-#endif
-        PM_SYS_PUSH(EBIU_AMBCTL0)
-        PM_SYS_PUSH(EBIU_AMBCTL1)
-        PM_SYS_PUSH16(EBIU_AMGCTL)
-#ifdef EBIU_FCTL
-        PM_SYS_PUSH(EBIU_MBSCTL)
-        PM_SYS_PUSH(EBIU_MODE)
-        PM_SYS_PUSH(EBIU_FCTL)
-#endif
-#ifdef PORTCIO_FER
-        PM_SYS_PUSH16(PORTCIO_DIR)
-        PM_SYS_PUSH16(PORTCIO_INEN)
-        PM_SYS_PUSH16(PORTCIO)
-        PM_SYS_PUSH16(PORTCIO_FER)
-        PM_SYS_PUSH16(PORTDIO_DIR)
-        PM_SYS_PUSH16(PORTDIO_INEN)
-        PM_SYS_PUSH16(PORTDIO)
-        PM_SYS_PUSH16(PORTDIO_FER)
-        PM_SYS_PUSH16(PORTEIO_DIR)
-        PM_SYS_PUSH16(PORTEIO_INEN)
-        PM_SYS_PUSH16(PORTEIO)
-        PM_SYS_PUSH16(PORTEIO_FER)
-#endif
-        PM_SYS_PUSH16(SYSCR)
-        /* Save Core MMRs */
-        P0.H = hi(SRAM_BASE_ADDRESS);
-        P0.L = lo(SRAM_BASE_ADDRESS);
-        PM_PUSH(DMEM_CONTROL)
-        PM_PUSH(DCPLB_ADDR0)
-        PM_PUSH(DCPLB_ADDR1)
-        PM_PUSH(DCPLB_ADDR2)
-        PM_PUSH(DCPLB_ADDR3)
-        PM_PUSH(DCPLB_ADDR4)
-        PM_PUSH(DCPLB_ADDR5)
-        PM_PUSH(DCPLB_ADDR6)
-        PM_PUSH(DCPLB_ADDR7)
-        PM_PUSH(DCPLB_ADDR8)
-        PM_PUSH(DCPLB_ADDR9)
-        PM_PUSH(DCPLB_ADDR10)
-        PM_PUSH(DCPLB_ADDR11)
-        PM_PUSH(DCPLB_ADDR12)
-        PM_PUSH(DCPLB_ADDR13)
-        PM_PUSH(DCPLB_ADDR14)
-        PM_PUSH(DCPLB_ADDR15)
-        PM_PUSH(DCPLB_DATA0)
-        PM_PUSH(DCPLB_DATA1)
-        PM_PUSH(DCPLB_DATA2)
-        PM_PUSH(DCPLB_DATA3)
-        PM_PUSH(DCPLB_DATA4)
-        PM_PUSH(DCPLB_DATA5)
-        PM_PUSH(DCPLB_DATA6)
-        PM_PUSH(DCPLB_DATA7)
-        PM_PUSH(DCPLB_DATA8)
-        PM_PUSH(DCPLB_DATA9)
-        PM_PUSH(DCPLB_DATA10)
-        PM_PUSH(DCPLB_DATA11)
-        PM_PUSH(DCPLB_DATA12)
-        PM_PUSH(DCPLB_DATA13)
-        PM_PUSH(DCPLB_DATA14)
-        PM_PUSH(DCPLB_DATA15)
-        PM_PUSH(IMEM_CONTROL)
-        PM_PUSH(ICPLB_ADDR0)
-        PM_PUSH(ICPLB_ADDR1)
-        PM_PUSH(ICPLB_ADDR2)
-        PM_PUSH(ICPLB_ADDR3)
-        PM_PUSH(ICPLB_ADDR4)
-        PM_PUSH(ICPLB_ADDR5)
-        PM_PUSH(ICPLB_ADDR6)
-        PM_PUSH(ICPLB_ADDR7)
-        PM_PUSH(ICPLB_ADDR8)
-        PM_PUSH(ICPLB_ADDR9)
-        PM_PUSH(ICPLB_ADDR10)
-        PM_PUSH(ICPLB_ADDR11)
-        PM_PUSH(ICPLB_ADDR12)
-        PM_PUSH(ICPLB_ADDR13)
-        PM_PUSH(ICPLB_ADDR14)
-        PM_PUSH(ICPLB_ADDR15)
-        PM_PUSH(ICPLB_DATA0)
-        PM_PUSH(ICPLB_DATA1)
-        PM_PUSH(ICPLB_DATA2)
-        PM_PUSH(ICPLB_DATA3)
-        PM_PUSH(ICPLB_DATA4)
-        PM_PUSH(ICPLB_DATA5)
-        PM_PUSH(ICPLB_DATA6)
-        PM_PUSH(ICPLB_DATA7)
-        PM_PUSH(ICPLB_DATA8)
-        PM_PUSH(ICPLB_DATA9)
-        PM_PUSH(ICPLB_DATA10)
-        PM_PUSH(ICPLB_DATA11)
-        PM_PUSH(ICPLB_DATA12)
-        PM_PUSH(ICPLB_DATA13)
-        PM_PUSH(ICPLB_DATA14)
-        PM_PUSH(ICPLB_DATA15)
-        PM_PUSH(EVT0)
-        PM_PUSH(EVT1)
-        PM_PUSH(EVT2)
-        PM_PUSH(EVT3)
-        PM_PUSH(EVT4)
-        PM_PUSH(EVT5)
-        PM_PUSH(EVT6)
-        PM_PUSH(EVT7)
-        PM_PUSH(EVT8)
-        PM_PUSH(EVT9)
-        PM_PUSH(EVT10)
-        PM_PUSH(EVT11)
-        PM_PUSH(EVT12)
-        PM_PUSH(EVT13)
-        PM_PUSH(EVT14)
-        PM_PUSH(EVT15)
-        PM_PUSH(IMASK)
-        PM_PUSH(ILAT)
-        PM_PUSH(IPRIO)
-        PM_PUSH(TCNTL)
-        PM_PUSH(TPERIOD)
-        PM_PUSH(TSCALE)
-        PM_PUSH(TCOUNT)
-        PM_PUSH(TBUFCTL)
-        /* Save Core Registers */
-        [--sp] = SYSCFG;
-        [--sp] = ( R7:0, P5:0 );
        [--sp] = fp;
        [--sp] = usp;
@@ -506,47 +360,497 @@ ENTRY(_do_hibernate)
        [--sp] = LB0;
        [--sp] = LB1;
+        /* We can't push RETI directly as that'll change IPEND[4] */
+        r7 = RETI;
+        [--sp] = RETS;
        [--sp] = ASTAT;
        [--sp] = CYCLES;
        [--sp] = CYCLES2;
+        [--sp] = SYSCFG;
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
        [--sp] = SEQSTAT;
+        [--sp] = r7;
+        /* Save first func arg in M3 */
+        M3 = R0;
+        /* Save system MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+#ifdef SIC_IMASK0
+        PM_SYS_PUSH(0, SIC_IMASK0)
+        PM_SYS_PUSH(1, SIC_IMASK1)
+# ifdef SIC_IMASK2
+        PM_SYS_PUSH(2, SIC_IMASK2)
+# endif
+#else
+        PM_SYS_PUSH(0, SIC_IMASK)
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_PUSH(3, SIC_IAR0)
+        PM_SYS_PUSH(4, SIC_IAR1)
+        PM_SYS_PUSH(5, SIC_IAR2)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_PUSH(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR4
+        PM_SYS_PUSH(7, SIC_IAR4)
+        PM_SYS_PUSH(8, SIC_IAR5)
+        PM_SYS_PUSH(9, SIC_IAR6)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_PUSH(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR8
+        PM_SYS_PUSH(11, SIC_IAR8)
+        PM_SYS_PUSH(12, SIC_IAR9)
+        PM_SYS_PUSH(13, SIC_IAR10)
+#endif
+        PM_PUSH_SYNC(13)
+#ifdef SIC_IAR11
+        PM_SYS_PUSH(0, SIC_IAR11)
+#endif
+#ifdef SIC_IWR
+        PM_SYS_PUSH(1, SIC_IWR)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_PUSH(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_PUSH(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR2
+        PM_SYS_PUSH(3, SIC_IWR2)
+#endif
+#ifdef PINT0_ASSIGN
+        PM_SYS_PUSH(4, PINT0_MASK_SET)
+        PM_SYS_PUSH(5, PINT1_MASK_SET)
+        PM_SYS_PUSH(6, PINT2_MASK_SET)
+        PM_SYS_PUSH(7, PINT3_MASK_SET)
+        PM_SYS_PUSH(8, PINT0_ASSIGN)
+        PM_SYS_PUSH(9, PINT1_ASSIGN)
+        PM_SYS_PUSH(10, PINT2_ASSIGN)
+        PM_SYS_PUSH(11, PINT3_ASSIGN)
+        PM_SYS_PUSH(12, PINT0_INVERT_SET)
+        PM_SYS_PUSH(13, PINT1_INVERT_SET)
+        PM_PUSH_SYNC(13)
+        PM_SYS_PUSH(0, PINT2_INVERT_SET)
+        PM_SYS_PUSH(1, PINT3_INVERT_SET)
+        PM_SYS_PUSH(2, PINT0_EDGE_SET)
+        PM_SYS_PUSH(3, PINT1_EDGE_SET)
+        PM_SYS_PUSH(4, PINT2_EDGE_SET)
+        PM_SYS_PUSH(5, PINT3_EDGE_SET)
+#endif
+        PM_SYS_PUSH16(6, SYSCR)
+        PM_SYS_PUSH16(7, EBIU_AMGCTL)
+        PM_SYS_PUSH(8, EBIU_AMBCTL0)
+        PM_SYS_PUSH(9, EBIU_AMBCTL1)
+#ifdef EBIU_FCTL
+        PM_SYS_PUSH(10, EBIU_MBSCTL)
+        PM_SYS_PUSH(11, EBIU_MODE)
+        PM_SYS_PUSH(12, EBIU_FCTL)
+        PM_PUSH_SYNC(12)
+#else
+        PM_PUSH_SYNC(9)
+#endif
+        /* Save Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR0);
+        I2.L = lo(DCPLB_DATA0);
+        I3.L = lo(ICPLB_ADDR0);
+        B0.L = lo(ICPLB_DATA0);
+        B1.L = lo(EVT2);
+        B2.L = lo(IMASK);
+        B3.L = lo(TCNTL);
+        /* DCPLB Addr */
+        FP = I1;
+        PM_PUSH(0, DCPLB_ADDR0)
+        PM_PUSH(1, DCPLB_ADDR1)
+        PM_PUSH(2, DCPLB_ADDR2)
+        PM_PUSH(3, DCPLB_ADDR3)
+        PM_PUSH(4, DCPLB_ADDR4)
+        PM_PUSH(5, DCPLB_ADDR5)
+        PM_PUSH(6, DCPLB_ADDR6)
+        PM_PUSH(7, DCPLB_ADDR7)
+        PM_PUSH(8, DCPLB_ADDR8)
+        PM_PUSH(9, DCPLB_ADDR9)
+        PM_PUSH(10, DCPLB_ADDR10)
+        PM_PUSH(11, DCPLB_ADDR11)
+        PM_PUSH(12, DCPLB_ADDR12)
+        PM_PUSH(13, DCPLB_ADDR13)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_ADDR14)
+        PM_PUSH(1, DCPLB_ADDR15)
+        /* DCPLB Data */
+        FP = I2;
+        PM_PUSH(2, DCPLB_DATA0)
+        PM_PUSH(3, DCPLB_DATA1)
+        PM_PUSH(4, DCPLB_DATA2)
+        PM_PUSH(5, DCPLB_DATA3)
+        PM_PUSH(6, DCPLB_DATA4)
+        PM_PUSH(7, DCPLB_DATA5)
+        PM_PUSH(8, DCPLB_DATA6)
+        PM_PUSH(9, DCPLB_DATA7)
+        PM_PUSH(10, DCPLB_DATA8)
+        PM_PUSH(11, DCPLB_DATA9)
+        PM_PUSH(12, DCPLB_DATA10)
+        PM_PUSH(13, DCPLB_DATA11)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_DATA12)
+        PM_PUSH(1, DCPLB_DATA13)
+        PM_PUSH(2, DCPLB_DATA14)
+        PM_PUSH(3, DCPLB_DATA15)
+        /* ICPLB Addr */
+        FP = I3;
+        PM_PUSH(4, ICPLB_ADDR0)
+        PM_PUSH(5, ICPLB_ADDR1)
+        PM_PUSH(6, ICPLB_ADDR2)
+        PM_PUSH(7, ICPLB_ADDR3)
+        PM_PUSH(8, ICPLB_ADDR4)
+        PM_PUSH(9, ICPLB_ADDR5)
+        PM_PUSH(10, ICPLB_ADDR6)
+        PM_PUSH(11, ICPLB_ADDR7)
+        PM_PUSH(12, ICPLB_ADDR8)
+        PM_PUSH(13, ICPLB_ADDR9)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_ADDR10)
+        PM_PUSH(1, ICPLB_ADDR11)
+        PM_PUSH(2, ICPLB_ADDR12)
+        PM_PUSH(3, ICPLB_ADDR13)
+        PM_PUSH(4, ICPLB_ADDR14)
+        PM_PUSH(5, ICPLB_ADDR15)
+        /* ICPLB Data */
+        FP = B0;
+        PM_PUSH(6, ICPLB_DATA0)
+        PM_PUSH(7, ICPLB_DATA1)
+        PM_PUSH(8, ICPLB_DATA2)
+        PM_PUSH(9, ICPLB_DATA3)
+        PM_PUSH(10, ICPLB_DATA4)
+        PM_PUSH(11, ICPLB_DATA5)
+        PM_PUSH(12, ICPLB_DATA6)
+        PM_PUSH(13, ICPLB_DATA7)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_DATA8)
+        PM_PUSH(1, ICPLB_DATA9)
+        PM_PUSH(2, ICPLB_DATA10)
+        PM_PUSH(3, ICPLB_DATA11)
+        PM_PUSH(4, ICPLB_DATA12)
+        PM_PUSH(5, ICPLB_DATA13)
+        PM_PUSH(6, ICPLB_DATA14)
+        PM_PUSH(7, ICPLB_DATA15)
+        /* Event Vectors */
+        FP = B1;
+        PM_PUSH(8, EVT2)
+        PM_PUSH(9, EVT3)
+        FP += 4;        /* EVT4 */
+        PM_PUSH(10, EVT5)
+        PM_PUSH(11, EVT6)
+        PM_PUSH(12, EVT7)
+        PM_PUSH(13, EVT8)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, EVT9)
+        PM_PUSH(1, EVT10)
+        PM_PUSH(2, EVT11)
+        PM_PUSH(3, EVT12)
+        PM_PUSH(4, EVT13)
+        PM_PUSH(5, EVT14)
+        PM_PUSH(6, EVT15)
+        /* CEC */
+        FP = B2;
+        PM_PUSH(7, IMASK)
+        FP += 4;        /* IPEND */
+        PM_PUSH(8, ILAT)
+        PM_PUSH(9, IPRIO)
+        /* Core Timer */
+        FP = B3;
+        PM_PUSH(10, TCNTL)
+        PM_PUSH(11, TPERIOD)
+        PM_PUSH(12, TSCALE)
+        PM_PUSH(13, TCOUNT)
+        PM_PUSH_SYNC(13)
+        /* Misc non-contiguous registers */
+        FP = I0;
+        PM_CORE_PUSH(0, DMEM_CONTROL);
+        PM_CORE_PUSH(1, IMEM_CONTROL);
+        PM_CORE_PUSH(2, TBUFCTL);
+        PM_PUSH_SYNC(2)
+        /* Setup args to hibernate mode early for pipeline optimization */
+        R0 = M3;
+        P1.H = _hibernate_mode;
+        P1.L = _hibernate_mode;
        /* Save Magic, return address and Stack Pointer */
-        P0.H = 0;
+        P0 = 0;
-        P0.L = 0;
+        R1.H = 0xDEAD;  /* Hibernate Magic */
-        R0.H = 0xDEAD;  /* Hibernate Magic */
+        R1.L = 0xBEEF;
-        R0.L = 0xBEEF;
+        R2.H = .Lpm_resume_here;
-        [P0++] = R0;    /* Store Hibernate Magic */
+        R2.L = .Lpm_resume_here;
-        R0.H = .Lpm_resume_here;
+        [P0++] = R1;    /* Store Hibernate Magic */
-        R0.L = .Lpm_resume_here;
+        [P0++] = R2;    /* Save Return Address */
-        [P0++] = R0;    /* Save Return Address */
        [P0++] = SP;    /* Save Stack Pointer */
-        P0.H = _hibernate_mode;
-        P0.L = _hibernate_mode;
+        /* Must use an indirect call as we need to jump to L1 */
-        R0 = R2;
+        call (P1); /* Goodbye */
-        call (P0); /* Goodbye */
 .Lpm_resume_here:
+        /* Restore Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR15);
+        I2.L = lo(DCPLB_DATA15);
+        I3.L = lo(ICPLB_ADDR15);
+        B0.L = lo(ICPLB_DATA15);
+        B1.L = lo(EVT15);
+        B2.L = lo(IPRIO);
+        B3.L = lo(TCOUNT);
+        /* Misc non-contiguous registers */
+        FP = I0;
+        PM_POP_SYNC(2)
+        PM_CORE_POP(2, TBUFCTL)
+        PM_CORE_POP(1, IMEM_CONTROL)
+        PM_CORE_POP(0, DMEM_CONTROL)
+        /* Core Timer */
+        PM_POP_SYNC(13)
+        FP = B3;
+        PM_POP(13, TCOUNT)
+        PM_POP(12, TSCALE)
+        PM_POP(11, TPERIOD)
+        PM_POP(10, TCNTL)
+        /* CEC */
+        FP = B2;
+        PM_POP(9, IPRIO)
+        PM_POP(8, ILAT)
+        FP += -4;       /* IPEND */
+        PM_POP(7, IMASK)
+        /* Event Vectors */
+        FP = B1;
+        PM_POP(6, EVT15)
+        PM_POP(5, EVT14)
+        PM_POP(4, EVT13)
+        PM_POP(3, EVT12)
+        PM_POP(2, EVT11)
+        PM_POP(1, EVT10)
+        PM_POP(0, EVT9)
+        PM_POP_SYNC(13)
+        PM_POP(13, EVT8)
+        PM_POP(12, EVT7)
+        PM_POP(11, EVT6)
+        PM_POP(10, EVT5)
+        FP += -4;       /* EVT4 */
+        PM_POP(9, EVT3)
+        PM_POP(8, EVT2)
+        /* ICPLB Data */
+        FP = B0;
+        PM_POP(7, ICPLB_DATA15)
+        PM_POP(6, ICPLB_DATA14)
+        PM_POP(5, ICPLB_DATA13)
+        PM_POP(4, ICPLB_DATA12)
+        PM_POP(3, ICPLB_DATA11)
+        PM_POP(2, ICPLB_DATA10)
+        PM_POP(1, ICPLB_DATA9)
+        PM_POP(0, ICPLB_DATA8)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_DATA7)
+        PM_POP(12, ICPLB_DATA6)
+        PM_POP(11, ICPLB_DATA5)
+        PM_POP(10, ICPLB_DATA4)
+        PM_POP(9, ICPLB_DATA3)
+        PM_POP(8, ICPLB_DATA2)
+        PM_POP(7, ICPLB_DATA1)
+        PM_POP(6, ICPLB_DATA0)
+        /* ICPLB Addr */
+        FP = I3;
+        PM_POP(5, ICPLB_ADDR15)
+        PM_POP(4, ICPLB_ADDR14)
+        PM_POP(3, ICPLB_ADDR13)
+        PM_POP(2, ICPLB_ADDR12)
+        PM_POP(1, ICPLB_ADDR11)
+        PM_POP(0, ICPLB_ADDR10)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_ADDR9)
+        PM_POP(12, ICPLB_ADDR8)
+        PM_POP(11, ICPLB_ADDR7)
+        PM_POP(10, ICPLB_ADDR6)
+        PM_POP(9, ICPLB_ADDR5)
+        PM_POP(8, ICPLB_ADDR4)
+        PM_POP(7, ICPLB_ADDR3)
+        PM_POP(6, ICPLB_ADDR2)
+        PM_POP(5, ICPLB_ADDR1)
+        PM_POP(4, ICPLB_ADDR0)
+        /* DCPLB Data */
+        FP = I2;
+        PM_POP(3, DCPLB_DATA15)
+        PM_POP(2, DCPLB_DATA14)
+        PM_POP(1, DCPLB_DATA13)
+        PM_POP(0, DCPLB_DATA12)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_DATA11)
+        PM_POP(12, DCPLB_DATA10)
+        PM_POP(11, DCPLB_DATA9)
+        PM_POP(10, DCPLB_DATA8)
+        PM_POP(9, DCPLB_DATA7)
+        PM_POP(8, DCPLB_DATA6)
+        PM_POP(7, DCPLB_DATA5)
+        PM_POP(6, DCPLB_DATA4)
+        PM_POP(5, DCPLB_DATA3)
+        PM_POP(4, DCPLB_DATA2)
+        PM_POP(3, DCPLB_DATA1)
+        PM_POP(2, DCPLB_DATA0)
+        /* DCPLB Addr */
+        FP = I1;
+        PM_POP(1, DCPLB_ADDR15)
+        PM_POP(0, DCPLB_ADDR14)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_ADDR13)
+        PM_POP(12, DCPLB_ADDR12)
+        PM_POP(11, DCPLB_ADDR11)
+        PM_POP(10, DCPLB_ADDR10)
+        PM_POP(9, DCPLB_ADDR9)
+        PM_POP(8, DCPLB_ADDR8)
+        PM_POP(7, DCPLB_ADDR7)
+        PM_POP(6, DCPLB_ADDR6)
+        PM_POP(5, DCPLB_ADDR5)
+        PM_POP(4, DCPLB_ADDR4)
+        PM_POP(3, DCPLB_ADDR3)
+        PM_POP(2, DCPLB_ADDR2)
+        PM_POP(1, DCPLB_ADDR1)
+        PM_POP(0, DCPLB_ADDR0)
+        /* Restore System MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+#ifdef EBIU_FCTL
+        PM_POP_SYNC(12)
+        PM_SYS_POP(12, EBIU_FCTL)
+        PM_SYS_POP(11, EBIU_MODE)
+        PM_SYS_POP(10, EBIU_MBSCTL)
+#else
+        PM_POP_SYNC(9)
+#endif
+        PM_SYS_POP(9, EBIU_AMBCTL1)
+        PM_SYS_POP(8, EBIU_AMBCTL0)
+        PM_SYS_POP16(7, EBIU_AMGCTL)
+        PM_SYS_POP16(6, SYSCR)
+#ifdef PINT0_ASSIGN
+        PM_SYS_POP(5, PINT3_EDGE_SET)
+        PM_SYS_POP(4, PINT2_EDGE_SET)
+        PM_SYS_POP(3, PINT1_EDGE_SET)
+        PM_SYS_POP(2, PINT0_EDGE_SET)
+        PM_SYS_POP(1, PINT3_INVERT_SET)
+        PM_SYS_POP(0, PINT2_INVERT_SET)
+        PM_POP_SYNC(13)
+        PM_SYS_POP(13, PINT1_INVERT_SET)
+        PM_SYS_POP(12, PINT0_INVERT_SET)
+        PM_SYS_POP(11, PINT3_ASSIGN)
+        PM_SYS_POP(10, PINT2_ASSIGN)
+        PM_SYS_POP(9, PINT1_ASSIGN)
+        PM_SYS_POP(8, PINT0_ASSIGN)
+        PM_SYS_POP(7, PINT3_MASK_SET)
+        PM_SYS_POP(6, PINT2_MASK_SET)
+        PM_SYS_POP(5, PINT1_MASK_SET)
+        PM_SYS_POP(4, PINT0_MASK_SET)
+#endif
+#ifdef SIC_IWR2
+        PM_SYS_POP(3, SIC_IWR2)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_POP(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_POP(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR
+        PM_SYS_POP(1, SIC_IWR)
+#endif
+#ifdef SIC_IAR11
+        PM_SYS_POP(0, SIC_IAR11)
+#endif
+        PM_POP_SYNC(13)
+#ifdef SIC_IAR8
+        PM_SYS_POP(13, SIC_IAR10)
+        PM_SYS_POP(12, SIC_IAR9)
+        PM_SYS_POP(11, SIC_IAR8)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_POP(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR6
+        PM_SYS_POP(9, SIC_IAR6)
+        PM_SYS_POP(8, SIC_IAR5)
+        PM_SYS_POP(7, SIC_IAR4)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_POP(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_POP(5, SIC_IAR2)
+        PM_SYS_POP(4, SIC_IAR1)
+        PM_SYS_POP(3, SIC_IAR0)
+#endif
+#ifdef SIC_IMASK0
+# ifdef SIC_IMASK2
+        PM_SYS_POP(2, SIC_IMASK2)
+# endif
+        PM_SYS_POP(1, SIC_IMASK1)
+        PM_SYS_POP(0, SIC_IMASK0)
+#else
+        PM_SYS_POP(0, SIC_IMASK)
+#endif
        /* Restore Core Registers */
+        RETI = [sp++];
        SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
        RETX = [sp++];
-        r0 = [sp++];
+        SYSCFG = [sp++];
-        RETI = r0;
-        RETS = [sp++];
        CYCLES2 = [sp++];
        CYCLES = [sp++];
        ASTAT = [sp++];
+        RETS = [sp++];
        LB1 = [sp++];
        LB0 = [sp++];
@@ -581,204 +885,10 @@ ENTRY(_do_hibernate)
        usp = [sp++];
        fp = [sp++];
+        (R7:0, P5:0) = [sp++];
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        SYSCFG = [sp++];
-        /* Restore Core MMRs */
-        PM_POP(TBUFCTL)
-        PM_POP(TCOUNT)
-        PM_POP(TSCALE)
-        PM_POP(TPERIOD)
-        PM_POP(TCNTL)
-        PM_POP(IPRIO)
-        PM_POP(ILAT)
-        PM_POP(IMASK)
-        PM_POP(EVT15)
-        PM_POP(EVT14)
-        PM_POP(EVT13)
-        PM_POP(EVT12)
-        PM_POP(EVT11)
-        PM_POP(EVT10)
-        PM_POP(EVT9)
-        PM_POP(EVT8)
-        PM_POP(EVT7)
-        PM_POP(EVT6)
-        PM_POP(EVT5)
-        PM_POP(EVT4)
-        PM_POP(EVT3)
-        PM_POP(EVT2)
-        PM_POP(EVT1)
-        PM_POP(EVT0)
-        PM_POP(ICPLB_DATA15)
-        PM_POP(ICPLB_DATA14)
-        PM_POP(ICPLB_DATA13)
-        PM_POP(ICPLB_DATA12)
-        PM_POP(ICPLB_DATA11)
-        PM_POP(ICPLB_DATA10)
-        PM_POP(ICPLB_DATA9)
-        PM_POP(ICPLB_DATA8)
-        PM_POP(ICPLB_DATA7)
-        PM_POP(ICPLB_DATA6)
-        PM_POP(ICPLB_DATA5)
-        PM_POP(ICPLB_DATA4)
-        PM_POP(ICPLB_DATA3)
-        PM_POP(ICPLB_DATA2)
-        PM_POP(ICPLB_DATA1)
-        PM_POP(ICPLB_DATA0)
-        PM_POP(ICPLB_ADDR15)
-        PM_POP(ICPLB_ADDR14)
-        PM_POP(ICPLB_ADDR13)
-        PM_POP(ICPLB_ADDR12)
-        PM_POP(ICPLB_ADDR11)
-        PM_POP(ICPLB_ADDR10)
-        PM_POP(ICPLB_ADDR9)
-        PM_POP(ICPLB_ADDR8)
-        PM_POP(ICPLB_ADDR7)
-        PM_POP(ICPLB_ADDR6)
-        PM_POP(ICPLB_ADDR5)
-        PM_POP(ICPLB_ADDR4)
-        PM_POP(ICPLB_ADDR3)
-        PM_POP(ICPLB_ADDR2)
-        PM_POP(ICPLB_ADDR1)
-        PM_POP(ICPLB_ADDR0)
-        PM_POP(IMEM_CONTROL)
-        PM_POP(DCPLB_DATA15)
-        PM_POP(DCPLB_DATA14)
-        PM_POP(DCPLB_DATA13)
-        PM_POP(DCPLB_DATA12)
-        PM_POP(DCPLB_DATA11)
-        PM_POP(DCPLB_DATA10)
-        PM_POP(DCPLB_DATA9)
-        PM_POP(DCPLB_DATA8)
-        PM_POP(DCPLB_DATA7)
-        PM_POP(DCPLB_DATA6)
-        PM_POP(DCPLB_DATA5)
-        PM_POP(DCPLB_DATA4)
-        PM_POP(DCPLB_DATA3)
-        PM_POP(DCPLB_DATA2)
-        PM_POP(DCPLB_DATA1)
-        PM_POP(DCPLB_DATA0)
-        PM_POP(DCPLB_ADDR15)
-        PM_POP(DCPLB_ADDR14)
-        PM_POP(DCPLB_ADDR13)
-        PM_POP(DCPLB_ADDR12)
-        PM_POP(DCPLB_ADDR11)
-        PM_POP(DCPLB_ADDR10)
-        PM_POP(DCPLB_ADDR9)
-        PM_POP(DCPLB_ADDR8)
-        PM_POP(DCPLB_ADDR7)
-        PM_POP(DCPLB_ADDR6)
-        PM_POP(DCPLB_ADDR5)
-        PM_POP(DCPLB_ADDR4)
-        PM_POP(DCPLB_ADDR3)
-        PM_POP(DCPLB_ADDR2)
-        PM_POP(DCPLB_ADDR1)
-        PM_POP(DCPLB_ADDR0)
-        PM_POP(DMEM_CONTROL)
-        /* Restore System MMRs */
-        P0.H = hi(PLL_CTL);
-        P0.L = lo(PLL_CTL);
-        PM_SYS_POP16(SYSCR)
-#ifdef PORTCIO_FER
-        PM_SYS_POP16(PORTEIO_FER)
-        PM_SYS_POP16(PORTEIO)
-        PM_SYS_POP16(PORTEIO_INEN)
-        PM_SYS_POP16(PORTEIO_DIR)
-        PM_SYS_POP16(PORTDIO_FER)
-        PM_SYS_POP16(PORTDIO)
-        PM_SYS_POP16(PORTDIO_INEN)
-        PM_SYS_POP16(PORTDIO_DIR)
-        PM_SYS_POP16(PORTCIO_FER)
-        PM_SYS_POP16(PORTCIO)
-        PM_SYS_POP16(PORTCIO_INEN)
-        PM_SYS_POP16(PORTCIO_DIR)
-#endif
-#ifdef EBIU_FCTL
-        PM_SYS_POP(EBIU_FCTL)
-        PM_SYS_POP(EBIU_MODE)
-        PM_SYS_POP(EBIU_MBSCTL)
-#endif
-        PM_SYS_POP16(EBIU_AMGCTL)
-        PM_SYS_POP(EBIU_AMBCTL1)
-        PM_SYS_POP(EBIU_AMBCTL0)
-#ifdef PINT0_ASSIGN
-        PM_SYS_POP(PINT3_EDGE_SET)
-        PM_SYS_POP(PINT2_EDGE_SET)
-        PM_SYS_POP(PINT1_EDGE_SET)
-        PM_SYS_POP(PINT0_EDGE_SET)
-        PM_SYS_POP(PINT3_INVERT_SET)
-        PM_SYS_POP(PINT2_INVERT_SET)
-        PM_SYS_POP(PINT1_INVERT_SET)
-        PM_SYS_POP(PINT0_INVERT_SET)
-        PM_SYS_POP(PINT3_ASSIGN)
-        PM_SYS_POP(PINT2_ASSIGN)
-        PM_SYS_POP(PINT1_ASSIGN)
-        PM_SYS_POP(PINT0_ASSIGN)
-        PM_SYS_POP(PINT3_MASK_SET)
-        PM_SYS_POP(PINT2_MASK_SET)
-        PM_SYS_POP(PINT1_MASK_SET)
-        PM_SYS_POP(PINT0_MASK_SET)
-#endif
-#ifdef SIC_IWR2
-        PM_SYS_POP(SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
-        PM_SYS_POP(SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
-        PM_SYS_POP(SIC_IWR0)
-#endif
-#ifdef SIC_IWR
-        PM_SYS_POP(SIC_IWR)
-#endif
-#ifdef SIC_IAR8
-        PM_SYS_POP(SIC_IAR11)
-        PM_SYS_POP(SIC_IAR10)
-        PM_SYS_POP(SIC_IAR9)
-        PM_SYS_POP(SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
-        PM_SYS_POP(SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
-        PM_SYS_POP(SIC_IAR6)
-        PM_SYS_POP(SIC_IAR5)
-        PM_SYS_POP(SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
-        PM_SYS_POP(SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
-        PM_SYS_POP(SIC_IAR2)
-        PM_SYS_POP(SIC_IAR1)
-        PM_SYS_POP(SIC_IAR0)
-#endif
-#ifdef SIC_IMASK
-        PM_SYS_POP(SIC_IMASK)
-#endif
-#ifdef SIC_IMASK2
-        PM_SYS_POP(SIC_IMASK2)
-#endif
-#ifdef SIC_IMASK1
-        PM_SYS_POP(SIC_IMASK1)
-#endif
-#ifdef SIC_IMASK0
-        PM_SYS_POP(SIC_IMASK0)
-#endif
        [--sp] = RETI;  /* Clear Global Interrupt Disable */
        SP += 4;
-        RETS = [SP++];
-        ( R7:0, P5:0 ) = [SP++];
        RTS;
 ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 225d311c9701..e4137297b790 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1543,7 +1543,7 @@ ENTRY(_sys_call_table)
        .long _sys_ni_syscall   /* for vm86 */
        .long _sys_ni_syscall   /* old "query_module" */
        .long _sys_ni_syscall   /* sys_poll */
-        .long _sys_nfsservctl
+        .long _sys_ni_syscall   /* old nfsservctl */
        .long _sys_setresgid    /* setresgid16 */       /* 170 */
        .long _sys_getresgid    /* getresgid16 */
        .long _sys_prctl
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 76de5724c1e3..8b4d98854403 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -85,37 +85,25 @@ ENTRY(__start)
        SSYNC;
        /* in case of double faults, save a few things */
-        p0.l = _init_retx;
+        p1.l = _initial_pda;
-        p0.h = _init_retx;
+        p1.h = _initial_pda;
-        R0 = RETX;
+        r4 = RETX;
-        [P0] = R0;
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
        /* Only save these if we are storing them,
         * This happens here, since L1 gets clobbered
         * below
         */
        GET_PDA(p0, r0);
-        r5 = [p0 + PDA_DF_RETX];
+        r0 = [p0 + PDA_DF_RETX];
-        p1.l = _init_saved_retx;
+        r1 = [p0 + PDA_DF_DCPLB];
-        p1.h = _init_saved_retx;
+        r2 = [p0 + PDA_DF_ICPLB];
-        [p1] = r5;
+        r3 = [p0 + PDA_DF_SEQSTAT];
+        [p1 + PDA_INIT_DF_RETX] = r0;
-        r5 = [p0 + PDA_DF_DCPLB];
+        [p1 + PDA_INIT_DF_DCPLB] = r1;
-        p1.l = _init_saved_dcplb_fault_addr;
+        [p1 + PDA_INIT_DF_ICPLB] = r2;
-        p1.h = _init_saved_dcplb_fault_addr;
+        [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-        [p1] = r5;
-        r5 = [p0 + PDA_DF_ICPLB];
-        p1.l = _init_saved_icplb_fault_addr;
-        p1.h = _init_saved_icplb_fault_addr;
-        [p1] = r5;
-        r5 = [p0 + PDA_DF_SEQSTAT];
-        p1.l = _init_saved_seqstat;
-        p1.h = _init_saved_seqstat;
-        [p1] = r5;
 #endif
+        [p1 + PDA_INIT_RETX] = r4;
        /* Initialize stack pointer */
        sp.l = _init_thread_union + THREAD_SIZE;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1177369f9922..332dace6af34 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -444,7 +444,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 extern void bfin_gpio_irq_prepare(unsigned gpio);
-#if !defined(CONFIG_BF54x)
+#if !BFIN_GPIO_PINT
 static void bfin_gpio_ack_irq(struct irq_data *d)
 {
@@ -633,7 +633,7 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
        bfin_demux_gpio_block(irq);
 }
-#else                           /* CONFIG_BF54x */
+#else
 #define NR_PINT_SYS_IRQS        4
 #define NR_PINT_BITS            32
@@ -647,24 +647,11 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 static unsigned char irq2pint_lut[NR_PINTS];
 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
-struct pin_int_t {
+static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
-        unsigned int mask_set;
+        (struct bfin_pint_regs *)PINT0_MASK_SET,
-        unsigned int mask_clear;
+        (struct bfin_pint_regs *)PINT1_MASK_SET,
-        unsigned int request;
+        (struct bfin_pint_regs *)PINT2_MASK_SET,
-        unsigned int assign;
+        (struct bfin_pint_regs *)PINT3_MASK_SET,
-        unsigned int edge_set;
-        unsigned int edge_clear;
-        unsigned int invert_set;
-        unsigned int invert_clear;
-        unsigned int pinstate;
-        unsigned int latch;
-};
-static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
-        (struct pin_int_t *)PINT0_MASK_SET,
-        (struct pin_int_t *)PINT1_MASK_SET,
-        (struct pin_int_t *)PINT2_MASK_SET,
-        (struct pin_int_t *)PINT3_MASK_SET,
 };
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
@@ -981,7 +968,7 @@ int __init init_arch_irq(void)
        local_irq_disable();
-#ifdef CONFIG_BF54x
+#if BFIN_GPIO_PINT
 # ifdef CONFIG_PINTx_REASSIGN
        pint[0]->assign = CONFIG_PINT0_ASSIGN;
        pint[1]->assign = CONFIG_PINT1_ASSIGN;
@@ -999,16 +986,16 @@ int __init init_arch_irq(void)
                        irq_set_chip(irq, &bfin_internal_irqchip);
                switch (irq) {
-#if defined(BF537_FAMILY)
+#if BFIN_GPIO_PINT
-                case IRQ_PH_INTA_MAC_RX:
-                case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
-                case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF54x)
                case IRQ_PINT0:
                case IRQ_PINT1:
                case IRQ_PINT2:
                case IRQ_PINT3:
+#elif defined(BF537_FAMILY)
+                case IRQ_PH_INTA_MAC_RX:
+                case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
+                case IRQ_PROG_INTA:
 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
                case IRQ_PORTF_INTA:
                case IRQ_PORTG_INTA:
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 35e7e1eb0188..0784a52389c8 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -23,7 +23,7 @@
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/irq_handler.h>
 #include <asm/mmu_context.h>
@@ -45,9 +45,7 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
 #endif
-void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
+struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
-        *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
-        *init_saved_dcplb_fault_addr_coreb;
 #define BFIN_IPI_RESCHEDULE   0
 #define BFIN_IPI_CALL_FUNC    1
@@ -297,10 +295,15 @@ EXPORT_SYMBOL_GPL(smp_call_function_single);
 void smp_send_reschedule(int cpu)
 {
+        cpumask_t callmap;
        /* simply trigger an ipi */
        if (cpu_is_offline(cpu))
                return;
-        platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
+        cpumask_clear(&callmap);
+        cpumask_set_cpu(cpu, &callmap);
+        smp_send_message(callmap, BFIN_IPI_RESCHEDULE, NULL, NULL, 0);
        return;
 }
@@ -369,13 +372,16 @@ void __cpuinit secondary_start_kernel(void)
        if (_bfin_swrst & SWRST_DBL_FAULT_B) {
                printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
-                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
+                printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
-                        (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
+                        initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
-                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
+                        initial_pda_coreb.retx_doublefault);
-                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
+                        initial_pda_coreb.dcplb_doublefault_addr);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
+                        initial_pda_coreb.icplb_doublefault_addr);
 #endif
                printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
-                        init_retx_coreb);
+                        initial_pda_coreb.retx);
        }
        /*
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index f8435cd36c7c..78daae084915 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -8,6 +8,7 @@
 #include <linux/swap.h>
 #include <linux/bootmem.h>
 #include <linux/uaccess.h>
+#include <linux/export.h>
 #include <asm/bfin-global.h>
 #include <asm/pda.h>
 #include <asm/cplbinit.h>
author	Tejun Heo <tj@kernel.org>	2011-11-28 12:46:22 -0500
committer	Tejun Heo <tj@kernel.org>	2011-11-28 12:46:22 -0500
commit	d4bbf7e7759afc172e2bfbc5c416324590049cdd (patch)
tree	7eab5ee5481cd3dcf1162329fec827177640018a /arch/blackfin
parent	a150439c4a97db379f0ed6faa46fbbb6e7bf3cb2 (diff)
parent	401d0069cb344f401bc9d264c31db55876ff78c0 (diff)