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authorGraf Yang <graf.yang@analog.com>2009-07-10 07:34:51 -0400
committerMike Frysinger <vapier@gentoo.org>2009-07-16 01:52:51 -0400
commit5bc6e3cfe6db5f33c60f042a9ba203431f334756 (patch)
treeff171234a9d19171e955bc1d05279e38c4b39f97 /arch/blackfin
parentf574a76a3b19848ac61814756716e26f85f2c3f7 (diff)
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c23
1 files changed, 17 insertions, 6 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index d6c067782e63..685f160a5a36 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
72 } 72 }
73 73
74 /* Cover L1 memory. One 4M area for code and data each is enough. */ 74 /* Cover L1 memory. One 4M area for code and data each is enough. */
75 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { 75 if (cpu == 0) {
76 d_tbl[i_d].addr = L1_DATA_A_START; 76 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
77 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 77 d_tbl[i_d].addr = L1_DATA_A_START;
78 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
79 }
80 i_tbl[i_i].addr = L1_CODE_START;
81 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
78 } 82 }
79 i_tbl[i_i].addr = L1_CODE_START; 83#ifdef CONFIG_SMP
80 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 84 else {
81 85 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
86 d_tbl[i_d].addr = COREB_L1_DATA_A_START;
87 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
88 }
89 i_tbl[i_i].addr = COREB_L1_CODE_START;
90 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
91 }
92#endif
82 first_switched_dcplb = i_d; 93 first_switched_dcplb = i_d;
83 first_switched_icplb = i_i; 94 first_switched_icplb = i_i;
84 95