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authorMike Frysinger <vapier@gentoo.org>2010-10-19 14:44:23 -0400
committerMike Frysinger <vapier@gentoo.org>2010-10-22 16:30:02 -0400
commit39c999697bf43a97b877fa43cbc9c2a4d1a3a461 (patch)
treed0f2432e89f7f36f9f2a39aed80527d072273bb0 /arch/blackfin
parent9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582 (diff)
Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
This matches all the other Blackfin ports and keep us from having to write bf561-specific code in many places. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf561/coreb.c4
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h33
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h76
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h37
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c16
-rw-r--r--arch/blackfin/mach-bf561/smp.c24
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S50
-rw-r--r--arch/blackfin/mach-common/ints-priority.c4
8 files changed, 87 insertions, 157 deletions
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 396cedb59fdb..619790247499 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
29 29
30 switch (cmd) { 30 switch (cmd) {
31 case CMD_COREB_START: 31 case CMD_COREB_START:
32 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); 32 bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
33 break; 33 break;
34 case CMD_COREB_STOP: 34 case CMD_COREB_STOP:
35 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); 35 bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); 36 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
37 break; 37 break;
38 case CMD_COREB_RESET: 38 case CMD_COREB_RESET:
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 67d6bdcd3fa8..6c7dc58c018c 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -24,29 +24,16 @@
24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 24#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 25#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
26 26
27#define SIC_IWR0 SICA_IWR0 27/* Weird muxer funcs which pick SIC regs from IMASK base */
28#define SIC_IWR1 SICA_IWR1 28#define __SIC_MUX(base, x) ((base) + ((x) << 2))
29#define SIC_IAR0 SICA_IAR0 29#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
30#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 30#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
31#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 31#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
32#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 32#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
33#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 33#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
34 34#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
35#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
38#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
39#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
40#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
41
42#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
43#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
44#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
45#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
46#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
47#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
48#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
49#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
50 37
51#define BFIN_UART_NR_PORTS 1 38#define BFIN_UART_NR_PORTS 1
52 39
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index cc0416a5fa02..2bab99152495 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -30,49 +30,41 @@
30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 30#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
31#define bfin_read_CHIPID() bfin_read32(CHIPID) 31#define bfin_read_CHIPID() bfin_read32(CHIPID)
32 32
33/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
34#define bfin_read_SWRST() bfin_read_SICA_SWRST()
35#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
36#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
37#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
38
39/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 33/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
40#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 34#define bfin_read_SWRST() bfin_read16(SWRST)
41#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 35#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
42#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) 36#define bfin_read_SYSCR() bfin_read16(SYSCR)
43#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) 37#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
44#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) 38#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
45#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) 39#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
46#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) 40#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
47#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) 41#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
48#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) 42#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
49#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) 43#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
50#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) 44#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
51#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) 45#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
52#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) 46#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
53#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) 47#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
54#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) 48#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
55#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) 49#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
56#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) 50#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
57#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) 51#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
58#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) 52#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
59#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) 53#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
60#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) 54#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
61#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) 55#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
62#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) 56#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
63#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) 57#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
64#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) 58#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
65#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) 59#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
66#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) 60#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
67#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) 61#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
68#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) 62#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
69#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) 63#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
70#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) 64#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
71#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) 65#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
72#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) 66#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
73#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) 67#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
74#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
75#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
76 68
77/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 69/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
78#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) 70#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 6f59ac669f10..79e048d452e0 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -28,32 +28,29 @@
28#define CHIPID 0xFFC00014 /* Chip ID Register */ 28#define CHIPID 0xFFC00014 /* Chip ID Register */
29 29
30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 30/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
31#define SWRST SICA_SWRST
32#define SYSCR SICA_SYSCR
33#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) 31#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
34#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) 32#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
35#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) 33#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
36#define RESET_SOFTWARE (SWRST_OCCURRED) 34#define RESET_SOFTWARE (SWRST_OCCURRED)
37 35
38/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 36/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
39#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 37#define SWRST 0xFFC00100 /* Software Reset register */
40#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ 38#define SYSCR 0xFFC00104 /* System Reset Configuration register */
41#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ 39#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
42#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ 40#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
43#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ 41#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
44#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ 42#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
45#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ 43#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
46#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ 44#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
47#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ 45#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
48#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ 46#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
49#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ 47#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
50#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ 48#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
51#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ 49#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
52#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ 50#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
53#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ 51#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
54#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ 52#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
55#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ 53#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
56#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
57 54
58/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 55/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
59#define SICB_SWRST 0xFFC01100 /* reserved */ 56#define SICB_SWRST 0xFFC01100 /* reserved */
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index b4424172ad9e..7ee9262fe132 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -13,7 +13,7 @@
13void __init program_IAR(void) 13void __init program_IAR(void)
14{ 14{
15 /* Program the IAR0 Register with the configured priority */ 15 /* Program the IAR0 Register with the configured priority */
16 bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | 16 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | 17 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | 18 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | 19 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
@@ -22,7 +22,7 @@ void __init program_IAR(void)
22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | 22 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); 23 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
24 24
25 bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | 25 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | 26 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | 27 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | 28 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
@@ -31,7 +31,7 @@ void __init program_IAR(void)
31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | 31 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); 32 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
33 33
34 bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | 34 bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | 35 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | 36 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | 37 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
@@ -40,7 +40,7 @@ void __init program_IAR(void)
40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | 40 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); 41 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
42 42
43 bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | 43 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | 44 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | 45 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | 46 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
@@ -49,7 +49,7 @@ void __init program_IAR(void)
49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | 49 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); 50 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
51 51
52 bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | 52 bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | 53 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | 54 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | 55 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
@@ -58,7 +58,7 @@ void __init program_IAR(void)
58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | 58 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); 59 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
60 60
61 bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | 61 bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | 62 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | 63 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | 64 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
@@ -67,7 +67,7 @@ void __init program_IAR(void)
67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | 67 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); 68 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
69 69
70 bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | 70 bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | 71 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | 72 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | 73 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
@@ -76,7 +76,7 @@ void __init program_IAR(void)
76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | 76 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); 77 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
78 78
79 bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | 79 bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | 80 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | 81 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | 82 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 3b9a4bf7dacc..f540ed1257d6 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
52void __cpuinit platform_secondary_init(unsigned int cpu) 52void __cpuinit platform_secondary_init(unsigned int cpu)
53{ 53{
54 /* Clone setup for peripheral interrupt sources from CoreA. */ 54 /* Clone setup for peripheral interrupt sources from CoreA. */
55 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); 55 bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
56 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); 56 bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
57 SSYNC(); 57 SSYNC();
58 58
59 /* Clone setup for IARs from CoreA. */ 59 /* Clone setup for IARs from CoreA. */
60 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); 60 bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
61 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); 61 bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
62 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); 62 bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
63 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); 63 bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
64 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); 64 bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
65 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); 65 bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
66 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); 66 bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
67 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); 67 bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
68 bfin_write_SICB_IWR0(IWR_DISABLE_ALL); 68 bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL); 69 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
70 SSYNC(); 70 SSYNC();
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
86 86
87 spin_lock(&boot_lock); 87 spin_lock(&boot_lock);
88 88
89 if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { 89 if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
90 /* CoreB already running, sending ipi to wakeup it */ 90 /* CoreB already running, sending ipi to wakeup it */
91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); 91 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
92 } else { 92 } else {
93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ 93 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
94 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); 94 bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
95 SSYNC(); 95 SSYNC();
96 } 96 }
97 97
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 5969d86836a5..9cfdd49a3127 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -292,13 +292,7 @@ ENTRY(_do_hibernate)
292#ifdef SIC_IMASK 292#ifdef SIC_IMASK
293 PM_SYS_PUSH(SIC_IMASK) 293 PM_SYS_PUSH(SIC_IMASK)
294#endif 294#endif
295#ifdef SICA_IMASK0 295#ifdef SIC_IAR0
296 PM_SYS_PUSH(SICA_IMASK0)
297#endif
298#ifdef SICA_IMASK1
299 PM_SYS_PUSH(SICA_IMASK1)
300#endif
301#ifdef SIC_IAR2
302 PM_SYS_PUSH(SIC_IAR0) 296 PM_SYS_PUSH(SIC_IAR0)
303 PM_SYS_PUSH(SIC_IAR1) 297 PM_SYS_PUSH(SIC_IAR1)
304 PM_SYS_PUSH(SIC_IAR2) 298 PM_SYS_PUSH(SIC_IAR2)
@@ -321,17 +315,6 @@ ENTRY(_do_hibernate)
321 PM_SYS_PUSH(SIC_IAR11) 315 PM_SYS_PUSH(SIC_IAR11)
322#endif 316#endif
323 317
324#ifdef SICA_IAR0
325 PM_SYS_PUSH(SICA_IAR0)
326 PM_SYS_PUSH(SICA_IAR1)
327 PM_SYS_PUSH(SICA_IAR2)
328 PM_SYS_PUSH(SICA_IAR3)
329 PM_SYS_PUSH(SICA_IAR4)
330 PM_SYS_PUSH(SICA_IAR5)
331 PM_SYS_PUSH(SICA_IAR6)
332 PM_SYS_PUSH(SICA_IAR7)
333#endif
334
335#ifdef SIC_IWR 318#ifdef SIC_IWR
336 PM_SYS_PUSH(SIC_IWR) 319 PM_SYS_PUSH(SIC_IWR)
337#endif 320#endif
@@ -344,12 +327,6 @@ ENTRY(_do_hibernate)
344#ifdef SIC_IWR2 327#ifdef SIC_IWR2
345 PM_SYS_PUSH(SIC_IWR2) 328 PM_SYS_PUSH(SIC_IWR2)
346#endif 329#endif
347#ifdef SICA_IWR0
348 PM_SYS_PUSH(SICA_IWR0)
349#endif
350#ifdef SICA_IWR1
351 PM_SYS_PUSH(SICA_IWR1)
352#endif
353 330
354#ifdef PINT0_ASSIGN 331#ifdef PINT0_ASSIGN
355 PM_SYS_PUSH(PINT0_MASK_SET) 332 PM_SYS_PUSH(PINT0_MASK_SET)
@@ -750,12 +727,6 @@ ENTRY(_do_hibernate)
750 PM_SYS_POP(PINT0_MASK_SET) 727 PM_SYS_POP(PINT0_MASK_SET)
751#endif 728#endif
752 729
753#ifdef SICA_IWR1
754 PM_SYS_POP(SICA_IWR1)
755#endif
756#ifdef SICA_IWR0
757 PM_SYS_POP(SICA_IWR0)
758#endif
759#ifdef SIC_IWR2 730#ifdef SIC_IWR2
760 PM_SYS_POP(SIC_IWR2) 731 PM_SYS_POP(SIC_IWR2)
761#endif 732#endif
@@ -769,17 +740,6 @@ ENTRY(_do_hibernate)
769 PM_SYS_POP(SIC_IWR) 740 PM_SYS_POP(SIC_IWR)
770#endif 741#endif
771 742
772#ifdef SICA_IAR0
773 PM_SYS_POP(SICA_IAR7)
774 PM_SYS_POP(SICA_IAR6)
775 PM_SYS_POP(SICA_IAR5)
776 PM_SYS_POP(SICA_IAR4)
777 PM_SYS_POP(SICA_IAR3)
778 PM_SYS_POP(SICA_IAR2)
779 PM_SYS_POP(SICA_IAR1)
780 PM_SYS_POP(SICA_IAR0)
781#endif
782
783#ifdef SIC_IAR8 743#ifdef SIC_IAR8
784 PM_SYS_POP(SIC_IAR11) 744 PM_SYS_POP(SIC_IAR11)
785 PM_SYS_POP(SIC_IAR10) 745 PM_SYS_POP(SIC_IAR10)
@@ -797,17 +757,11 @@ ENTRY(_do_hibernate)
797#ifdef SIC_IAR3 757#ifdef SIC_IAR3
798 PM_SYS_POP(SIC_IAR3) 758 PM_SYS_POP(SIC_IAR3)
799#endif 759#endif
800#ifdef SIC_IAR2 760#ifdef SIC_IAR0
801 PM_SYS_POP(SIC_IAR2) 761 PM_SYS_POP(SIC_IAR2)
802 PM_SYS_POP(SIC_IAR1) 762 PM_SYS_POP(SIC_IAR1)
803 PM_SYS_POP(SIC_IAR0) 763 PM_SYS_POP(SIC_IAR0)
804#endif 764#endif
805#ifdef SICA_IMASK1
806 PM_SYS_POP(SICA_IMASK1)
807#endif
808#ifdef SICA_IMASK0
809 PM_SYS_POP(SICA_IMASK0)
810#endif
811#ifdef SIC_IMASK 765#ifdef SIC_IMASK
812 PM_SYS_POP(SIC_IMASK) 766 PM_SYS_POP(SIC_IMASK)
813#endif 767#endif
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 0df4fb57f5ba..da7e3c63746b 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1299,7 +1299,7 @@ void do_irq(int vec, struct pt_regs *fp)
1299 } else { 1299 } else {
1300 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1300 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1301 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1301 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1302#if defined(SIC_ISR0) || defined(SICA_ISR0) 1302#if defined(SIC_ISR0)
1303 unsigned long sic_status[3]; 1303 unsigned long sic_status[3];
1304 1304
1305 if (smp_processor_id()) { 1305 if (smp_processor_id()) {
@@ -1379,7 +1379,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1379 if (likely(vec == EVT_IVTMR_P)) 1379 if (likely(vec == EVT_IVTMR_P))
1380 irq = IRQ_CORETMR; 1380 irq = IRQ_CORETMR;
1381 else { 1381 else {
1382#if defined(SIC_ISR0) || defined(SICA_ISR0) 1382#if defined(SIC_ISR0)
1383 unsigned long sic_status[3]; 1383 unsigned long sic_status[3];
1384 1384
1385 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1385 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 16:00:07 -0500