diff options
author | Robin Getz <robin.getz@analog.com> | 2007-10-10 11:55:26 -0400 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-10 11:55:26 -0400 |
commit | 3bebca2d20796dd3dc62c5d3e74148087c7ce5bd (patch) | |
tree | fdb5eb8eb774fa5e8df41ebbf0e0d2c82b9ff627 /arch/blackfin | |
parent | a298049180d2c56fc8ac1796b24973bf4f019cc7 (diff) |
Blackfin arch: to do some consolidation of common code and common name spaces
now all BLKFIN should be BFIN, should be no functional changes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin')
-rw-r--r-- | arch/blackfin/Kconfig | 20 | ||||
-rw-r--r-- | arch/blackfin/configs/BF533-EZKIT_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/configs/BF533-STAMP_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/configs/BF537-STAMP_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/configs/BF548-EZKIT_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/configs/BF561-EZKIT_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/configs/PNAV-10_defconfig | 12 | ||||
-rw-r--r-- | arch/blackfin/kernel/cacheinit.c | 5 | ||||
-rw-r--r-- | arch/blackfin/kernel/cplbinit.c | 5 | ||||
-rw-r--r-- | arch/blackfin/kernel/process.c | 2 | ||||
-rw-r--r-- | arch/blackfin/kernel/setup.c | 29 | ||||
-rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 5 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cacheinit.S | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cplbhdlr.S | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cplbmgr.S | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-common/lock.S | 4 |
16 files changed, 84 insertions, 76 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index a7a6e0c5827d..17f946920159 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -722,22 +722,22 @@ endchoice | |||
722 | 722 | ||
723 | 723 | ||
724 | comment "Cache Support" | 724 | comment "Cache Support" |
725 | config BLKFIN_CACHE | 725 | config BFIN_ICACHE |
726 | bool "Enable ICACHE" | 726 | bool "Enable ICACHE" |
727 | config BLKFIN_DCACHE | 727 | config BFIN_DCACHE |
728 | bool "Enable DCACHE" | 728 | bool "Enable DCACHE" |
729 | config BLKFIN_DCACHE_BANKA | 729 | config BFIN_DCACHE_BANKA |
730 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" | 730 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
731 | depends on BLKFIN_DCACHE && !BF531 | 731 | depends on BFIN_DCACHE && !BF531 |
732 | default n | 732 | default n |
733 | config BLKFIN_CACHE_LOCK | 733 | config BFIN_ICACHE_LOCK |
734 | bool "Enable Cache Locking" | 734 | bool "Enable Instruction Cache Locking" |
735 | 735 | ||
736 | choice | 736 | choice |
737 | prompt "Policy" | 737 | prompt "Policy" |
738 | depends on BLKFIN_DCACHE | 738 | depends on BFIN_DCACHE |
739 | default BLKFIN_WB | 739 | default BFIN_WB |
740 | config BLKFIN_WB | 740 | config BFIN_WB |
741 | bool "Write back" | 741 | bool "Write back" |
742 | help | 742 | help |
743 | Write Back Policy: | 743 | Write Back Policy: |
@@ -754,7 +754,7 @@ config BLKFIN_WB | |||
754 | If you are unsure of the options and you want to be safe, | 754 | If you are unsure of the options and you want to be safe, |
755 | then go with Write Through. | 755 | then go with Write Through. |
756 | 756 | ||
757 | config BLKFIN_WT | 757 | config BFIN_WT |
758 | bool "Write through" | 758 | bool "Write through" |
759 | help | 759 | help |
760 | Write Back Policy: | 760 | Write Back Policy: |
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 1cf1ab28dc66..02141827e595 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig | |||
@@ -243,12 +243,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
243 | # | 243 | # |
244 | # Cache Support | 244 | # Cache Support |
245 | # | 245 | # |
246 | CONFIG_BLKFIN_CACHE=y | 246 | CONFIG_BFIN_ICACHE=y |
247 | CONFIG_BLKFIN_DCACHE=y | 247 | CONFIG_BFIN_DCACHE=y |
248 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 248 | # CONFIG_BFIN_DCACHE_BANKA is not set |
249 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 249 | # CONFIG_BFIN_ICACHE_LOCK is not set |
250 | # CONFIG_BLKFIN_WB is not set | 250 | # CONFIG_BFIN_WB is not set |
251 | CONFIG_BLKFIN_WT=y | 251 | CONFIG_BFIN_WT=y |
252 | CONFIG_L1_MAX_PIECE=16 | 252 | CONFIG_L1_MAX_PIECE=16 |
253 | 253 | ||
254 | # | 254 | # |
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index 64b7f1b3b2af..3dbe22d7d909 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig | |||
@@ -255,12 +255,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
255 | # | 255 | # |
256 | # Cache Support | 256 | # Cache Support |
257 | # | 257 | # |
258 | CONFIG_BLKFIN_CACHE=y | 258 | CONFIG_BFIN_ICACHE=y |
259 | CONFIG_BLKFIN_DCACHE=y | 259 | CONFIG_BFIN_DCACHE=y |
260 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 260 | # CONFIG_BFIN_DCACHE_BANKA is not set |
261 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 261 | # CONFIG_BFIN_ICACHE_LOCK is not set |
262 | # CONFIG_BLKFIN_WB is not set | 262 | # CONFIG_BFIN_WB is not set |
263 | CONFIG_BLKFIN_WT=y | 263 | CONFIG_BFIN_WT=y |
264 | CONFIG_L1_MAX_PIECE=16 | 264 | CONFIG_L1_MAX_PIECE=16 |
265 | 265 | ||
266 | # | 266 | # |
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index ccf09dc09a18..a28e0316e90c 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig | |||
@@ -258,12 +258,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
258 | # | 258 | # |
259 | # Cache Support | 259 | # Cache Support |
260 | # | 260 | # |
261 | CONFIG_BLKFIN_CACHE=y | 261 | CONFIG_BFIN_ICACHE=y |
262 | CONFIG_BLKFIN_DCACHE=y | 262 | CONFIG_BFIN_DCACHE=y |
263 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 263 | # CONFIG_BFIN_DCACHE_BANKA is not set |
264 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 264 | # CONFIG_BFIN_ICACHE_LOCK is not set |
265 | # CONFIG_BLKFIN_WB is not set | 265 | # CONFIG_BFIN_WB is not set |
266 | CONFIG_BLKFIN_WT=y | 266 | CONFIG_BFIN_WT=y |
267 | CONFIG_L1_MAX_PIECE=16 | 267 | CONFIG_L1_MAX_PIECE=16 |
268 | 268 | ||
269 | # | 269 | # |
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index ac8390fafa9c..8f3b1de6a939 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig | |||
@@ -306,12 +306,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
306 | # | 306 | # |
307 | # Cache Support | 307 | # Cache Support |
308 | # | 308 | # |
309 | CONFIG_BLKFIN_CACHE=y | 309 | CONFIG_BFIN_ICACHE=y |
310 | CONFIG_BLKFIN_DCACHE=y | 310 | CONFIG_BFIN_DCACHE=y |
311 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 311 | # CONFIG_BFIN_DCACHE_BANKA is not set |
312 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 312 | # CONFIG_BFIN_ICACHE_LOCK is not set |
313 | # CONFIG_BLKFIN_WB is not set | 313 | # CONFIG_BFIN_WB is not set |
314 | CONFIG_BLKFIN_WT=y | 314 | CONFIG_BFIN_WT=y |
315 | CONFIG_L1_MAX_PIECE=16 | 315 | CONFIG_L1_MAX_PIECE=16 |
316 | 316 | ||
317 | # | 317 | # |
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 51c0b6f97798..698a2492424e 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig | |||
@@ -288,12 +288,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
288 | # | 288 | # |
289 | # Cache Support | 289 | # Cache Support |
290 | # | 290 | # |
291 | CONFIG_BLKFIN_CACHE=y | 291 | CONFIG_BFIN_ICACHE=y |
292 | CONFIG_BLKFIN_DCACHE=y | 292 | CONFIG_BFIN_DCACHE=y |
293 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 293 | # CONFIG_BFIN_DCACHE_BANKA is not set |
294 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 294 | # CONFIG_BFIN_ICACHE_LOCK is not set |
295 | # CONFIG_BLKFIN_WB is not set | 295 | # CONFIG_BFIN_WB is not set |
296 | CONFIG_BLKFIN_WT=y | 296 | CONFIG_BFIN_WT=y |
297 | CONFIG_L1_MAX_PIECE=16 | 297 | CONFIG_L1_MAX_PIECE=16 |
298 | 298 | ||
299 | # | 299 | # |
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index 983ed181c896..dbb0c4f399fb 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig | |||
@@ -257,12 +257,12 @@ CONFIG_DMA_UNCACHED_1M=y | |||
257 | # | 257 | # |
258 | # Cache Support | 258 | # Cache Support |
259 | # | 259 | # |
260 | CONFIG_BLKFIN_CACHE=y | 260 | CONFIG_BFIN_ICACHE=y |
261 | CONFIG_BLKFIN_DCACHE=y | 261 | CONFIG_BFIN_DCACHE=y |
262 | # CONFIG_BLKFIN_DCACHE_BANKA is not set | 262 | # CONFIG_BFIN_DCACHE_BANKA is not set |
263 | # CONFIG_BLKFIN_CACHE_LOCK is not set | 263 | # CONFIG_BFIN_ICACHE_LOCK is not set |
264 | CONFIG_BLKFIN_WB=y | 264 | CONFIG_BFIN_WB=y |
265 | # CONFIG_BLKFIN_WT is not set | 265 | # CONFIG_BFIN_WT is not set |
266 | CONFIG_L1_MAX_PIECE=16 | 266 | CONFIG_L1_MAX_PIECE=16 |
267 | 267 | ||
268 | # | 268 | # |
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c index 4d41a40e8133..62cbba7364b0 100644 --- a/arch/blackfin/kernel/cacheinit.c +++ b/arch/blackfin/kernel/cacheinit.c | |||
@@ -21,9 +21,10 @@ | |||
21 | 21 | ||
22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
23 | #include <asm/blackfin.h> | 23 | #include <asm/blackfin.h> |
24 | #include <asm/cplb.h> | ||
24 | #include <asm/cplbinit.h> | 25 | #include <asm/cplbinit.h> |
25 | 26 | ||
26 | #if defined(CONFIG_BLKFIN_CACHE) | 27 | #if defined(CONFIG_BFIN_ICACHE) |
27 | void bfin_icache_init(void) | 28 | void bfin_icache_init(void) |
28 | { | 29 | { |
29 | unsigned long *table = icplb_table; | 30 | unsigned long *table = icplb_table; |
@@ -44,7 +45,7 @@ void bfin_icache_init(void) | |||
44 | } | 45 | } |
45 | #endif | 46 | #endif |
46 | 47 | ||
47 | #if defined(CONFIG_BLKFIN_DCACHE) | 48 | #if defined(CONFIG_BFIN_DCACHE) |
48 | void bfin_dcache_init(void) | 49 | void bfin_dcache_init(void) |
49 | { | 50 | { |
50 | unsigned long *table = dcplb_table; | 51 | unsigned long *table = dcplb_table; |
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c index 3b1c87c9fd51..f2db6a5e2b5b 100644 --- a/arch/blackfin/kernel/cplbinit.c +++ b/arch/blackfin/kernel/cplbinit.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
24 | 24 | ||
25 | #include <asm/blackfin.h> | 25 | #include <asm/blackfin.h> |
26 | #include <asm/cplb.h> | ||
26 | #include <asm/cplbinit.h> | 27 | #include <asm/cplbinit.h> |
27 | 28 | ||
28 | u_long icplb_table[MAX_CPLBS+1]; | 29 | u_long icplb_table[MAX_CPLBS+1]; |
@@ -56,7 +57,7 @@ struct s_cplb { | |||
56 | struct cplb_tab switch_d; | 57 | struct cplb_tab switch_d; |
57 | }; | 58 | }; |
58 | 59 | ||
59 | #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) | 60 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
60 | static struct cplb_desc cplb_data[] = { | 61 | static struct cplb_desc cplb_data[] = { |
61 | { | 62 | { |
62 | .start = 0, | 63 | .start = 0, |
@@ -230,7 +231,7 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en | |||
230 | cplb_data[i].psize, | 231 | cplb_data[i].psize, |
231 | cplb_data[i].i_conf); | 232 | cplb_data[i].i_conf); |
232 | } else { | 233 | } else { |
233 | #if defined(CONFIG_BLKFIN_CACHE) | 234 | #if defined(CONFIG_BFIN_ICACHE) |
234 | if (ANOMALY_05000263 && i == SDRAM_KERN) { | 235 | if (ANOMALY_05000263 && i == SDRAM_KERN) { |
235 | fill_cplbtab(t, | 236 | fill_cplbtab(t, |
236 | cplb_data[i].start, | 237 | cplb_data[i].start, |
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 6a7aefe48346..22e790419868 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c | |||
@@ -136,7 +136,7 @@ void cpu_idle(void) | |||
136 | 136 | ||
137 | void machine_restart(char *__unused) | 137 | void machine_restart(char *__unused) |
138 | { | 138 | { |
139 | #if defined(CONFIG_BLKFIN_CACHE) | 139 | #if defined(CONFIG_BFIN_ICACHE) |
140 | bfin_write_IMEM_CONTROL(0x01); | 140 | bfin_write_IMEM_CONTROL(0x01); |
141 | SSYNC(); | 141 | SSYNC(); |
142 | #endif | 142 | #endif |
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 02c15272f8ef..448e6aab73ac 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <linux/cramfs_fs.h> | 39 | #include <linux/cramfs_fs.h> |
40 | #include <linux/romfs_fs.h> | 40 | #include <linux/romfs_fs.h> |
41 | 41 | ||
42 | #include <asm/cplb.h> | ||
42 | #include <asm/cacheflush.h> | 43 | #include <asm/cacheflush.h> |
43 | #include <asm/blackfin.h> | 44 | #include <asm/blackfin.h> |
44 | #include <asm/cplbinit.h> | 45 | #include <asm/cplbinit.h> |
@@ -66,21 +67,21 @@ char __initdata command_line[COMMAND_LINE_SIZE]; | |||
66 | 67 | ||
67 | void __init bf53x_cache_init(void) | 68 | void __init bf53x_cache_init(void) |
68 | { | 69 | { |
69 | #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) | 70 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
70 | generate_cpl_tables(); | 71 | generate_cpl_tables(); |
71 | #endif | 72 | #endif |
72 | 73 | ||
73 | #ifdef CONFIG_BLKFIN_CACHE | 74 | #ifdef CONFIG_BFIN_ICACHE |
74 | bfin_icache_init(); | 75 | bfin_icache_init(); |
75 | printk(KERN_INFO "Instruction Cache Enabled\n"); | 76 | printk(KERN_INFO "Instruction Cache Enabled\n"); |
76 | #endif | 77 | #endif |
77 | 78 | ||
78 | #ifdef CONFIG_BLKFIN_DCACHE | 79 | #ifdef CONFIG_BFIN_DCACHE |
79 | bfin_dcache_init(); | 80 | bfin_dcache_init(); |
80 | printk(KERN_INFO "Data Cache Enabled" | 81 | printk(KERN_INFO "Data Cache Enabled" |
81 | # if defined CONFIG_BLKFIN_WB | 82 | # if defined CONFIG_BFIN_WB |
82 | " (write-back)" | 83 | " (write-back)" |
83 | # elif defined CONFIG_BLKFIN_WT | 84 | # elif defined CONFIG_BFIN_WT |
84 | " (write-through)" | 85 | " (write-through)" |
85 | # endif | 86 | # endif |
86 | "\n"); | 87 | "\n"); |
@@ -262,7 +263,7 @@ void __init setup_arch(char **cmdline_p) | |||
262 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | 263 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) |
263 | mtd_size = | 264 | mtd_size = |
264 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | 265 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); |
265 | # if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) | 266 | # if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) |
266 | /* Due to a Hardware Anomaly we need to limit the size of usable | 267 | /* Due to a Hardware Anomaly we need to limit the size of usable |
267 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 268 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
268 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 269 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
@@ -291,7 +292,7 @@ void __init setup_arch(char **cmdline_p) | |||
291 | _ebss = memory_mtd_start; /* define _ebss for compatible */ | 292 | _ebss = memory_mtd_start; /* define _ebss for compatible */ |
292 | #endif /* CONFIG_MTD_UCLINUX */ | 293 | #endif /* CONFIG_MTD_UCLINUX */ |
293 | 294 | ||
294 | #if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) | 295 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) |
295 | /* Due to a Hardware Anomaly we need to limit the size of usable | 296 | /* Due to a Hardware Anomaly we need to limit the size of usable |
296 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 297 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
297 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 298 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
@@ -535,9 +536,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
535 | seq_printf(m, "I-CACHE:\tOFF\n"); | 536 | seq_printf(m, "I-CACHE:\tOFF\n"); |
536 | if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE)) | 537 | if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE)) |
537 | seq_printf(m, "D-CACHE:\tON" | 538 | seq_printf(m, "D-CACHE:\tON" |
538 | #if defined CONFIG_BLKFIN_WB | 539 | #if defined CONFIG_BFIN_WB |
539 | " (write-back)" | 540 | " (write-back)" |
540 | #elif defined CONFIG_BLKFIN_WT | 541 | #elif defined CONFIG_BFIN_WT |
541 | " (write-through)" | 542 | " (write-through)" |
542 | #endif | 543 | #endif |
543 | "\n"); | 544 | "\n"); |
@@ -566,15 +567,15 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
566 | } | 567 | } |
567 | 568 | ||
568 | 569 | ||
569 | seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024); | 570 | seq_printf(m, "I-CACHE Size:\t%dKB\n", BFIN_ICACHESIZE / 1024); |
570 | seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size); | 571 | seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size); |
571 | seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n", | 572 | seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n", |
572 | BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES); | 573 | BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); |
573 | seq_printf(m, | 574 | seq_printf(m, |
574 | "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", | 575 | "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
575 | dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS, | 576 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
576 | BLKFIN_DLINES); | 577 | BFIN_DLINES); |
577 | #ifdef CONFIG_BLKFIN_CACHE_LOCK | 578 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
578 | switch (read_iloc()) { | 579 | switch (read_iloc()) { |
579 | case WAY0_L: | 580 | case WAY0_L: |
580 | seq_printf(m, "Way0 Locked-Down\n"); | 581 | seq_printf(m, "Way0 Locked-Down\n"); |
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index f9160d83b91f..2f6ce397780f 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c | |||
@@ -53,3 +53,8 @@ | |||
53 | # endif | 53 | # endif |
54 | 54 | ||
55 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 55 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
56 | |||
57 | #if (CONFIG_MEM_SIZE % 4) | ||
58 | #error "SDRAM mem size must be multible of 4MB" | ||
59 | #endif | ||
60 | |||
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S index afa0adfac6c3..22fada0c1cb3 100644 --- a/arch/blackfin/mach-common/cacheinit.S +++ b/arch/blackfin/mach-common/cacheinit.S | |||
@@ -39,7 +39,7 @@ | |||
39 | .text | 39 | .text |
40 | 40 | ||
41 | #if ANOMALY_05000125 | 41 | #if ANOMALY_05000125 |
42 | #if defined(CONFIG_BLKFIN_CACHE) | 42 | #if defined(CONFIG_BFIN_ICACHE) |
43 | ENTRY(_bfin_write_IMEM_CONTROL) | 43 | ENTRY(_bfin_write_IMEM_CONTROL) |
44 | 44 | ||
45 | /* Enable Instruction Cache */ | 45 | /* Enable Instruction Cache */ |
@@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL) | |||
58 | ENDPROC(_bfin_write_IMEM_CONTROL) | 58 | ENDPROC(_bfin_write_IMEM_CONTROL) |
59 | #endif | 59 | #endif |
60 | 60 | ||
61 | #if defined(CONFIG_BLKFIN_DCACHE) | 61 | #if defined(CONFIG_BFIN_DCACHE) |
62 | ENTRY(_bfin_write_DMEM_CONTROL) | 62 | ENTRY(_bfin_write_DMEM_CONTROL) |
63 | P0.l = (DMEM_CONTROL & 0xFFFF); | 63 | P0.l = LO(DMEM_CONTROL); |
64 | P0.h = (DMEM_CONTROL >> 16); | 64 | P0.h = HI(DMEM_CONTROL); |
65 | 65 | ||
66 | CLI R1; | 66 | CLI R1; |
67 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | 67 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ |
diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/mach-common/cplbhdlr.S index 2f3c72c23997..2788532de72b 100644 --- a/arch/blackfin/mach-common/cplbhdlr.S +++ b/arch/blackfin/mach-common/cplbhdlr.S | |||
@@ -69,14 +69,14 @@ ENTRY(__cplb_hdr) | |||
69 | 69 | ||
70 | .Lis_icplb_miss: | 70 | .Lis_icplb_miss: |
71 | 71 | ||
72 | #if defined(CONFIG_BLKFIN_CACHE) || defined(CONFIG_BLKFIN_DCACHE) | 72 | #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) |
73 | # if defined(CONFIG_BLKFIN_CACHE) && !defined(CONFIG_BLKFIN_DCACHE) | 73 | # if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE) |
74 | R1 = CPLB_ENABLE_ICACHE; | 74 | R1 = CPLB_ENABLE_ICACHE; |
75 | # endif | 75 | # endif |
76 | # if !defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) | 76 | # if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) |
77 | R1 = CPLB_ENABLE_DCACHE; | 77 | R1 = CPLB_ENABLE_DCACHE; |
78 | # endif | 78 | # endif |
79 | # if defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) | 79 | # if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) |
80 | R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; | 80 | R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; |
81 | # endif | 81 | # endif |
82 | #else | 82 | #else |
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S index cef94c13f956..946703ef48ff 100644 --- a/arch/blackfin/mach-common/cplbmgr.S +++ b/arch/blackfin/mach-common/cplbmgr.S | |||
@@ -565,7 +565,7 @@ ENTRY(_cplb_mgr) | |||
565 | * cost of first-write exceptions to mark the page as dirty. | 565 | * cost of first-write exceptions to mark the page as dirty. |
566 | */ | 566 | */ |
567 | 567 | ||
568 | #ifdef CONFIG_BLKFIN_WT | 568 | #ifdef CONFIG_BFIN_WT |
569 | BITSET(R6, 14); /* Set WT*/ | 569 | BITSET(R6, 14); /* Set WT*/ |
570 | #endif | 570 | #endif |
571 | 571 | ||
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 190edb3cdc84..28b87fe9ce3c 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S | |||
@@ -33,7 +33,7 @@ | |||
33 | 33 | ||
34 | .text | 34 | .text |
35 | 35 | ||
36 | #ifdef CONFIG_BLKFIN_CACHE_LOCK | 36 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
37 | 37 | ||
38 | /* When you come here, it is assumed that | 38 | /* When you come here, it is assumed that |
39 | * R0 - Which way to be locked | 39 | * R0 - Which way to be locked |
@@ -189,7 +189,7 @@ ENTRY(_cache_lock) | |||
189 | RTS; | 189 | RTS; |
190 | ENDPROC(_cache_lock) | 190 | ENDPROC(_cache_lock) |
191 | 191 | ||
192 | #endif /* BLKFIN_CACHE_LOCK */ | 192 | #endif /* BFIN_ICACHE_LOCK */ |
193 | 193 | ||
194 | /* Return the ILOC bits of IMEM_CONTROL | 194 | /* Return the ILOC bits of IMEM_CONTROL |
195 | */ | 195 | */ |