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authorsteven miao <realmz6@gmail.com>2010-10-22 04:48:41 -0400
committerMike Frysinger <vapier@gentoo.org>2011-03-18 03:49:23 -0400
commit55835175a03392d2e4d9bff9d482312d118f304e (patch)
tree51157bc604b5c5baa917bd22f420fa6291d5da76 /arch/blackfin
parent6ce0466d631d40662e2ab9ec5a05019482bd1074 (diff)
Blackfin: bf54x: add kconfig for UART2/3 DMA channel assignments
The BF54x lacks dedicated DMA channels for the UART peripherals and need to be muxed between others. So add a kconfig option so people can select which channels the UARTs will use so they can pick between SPORTs and the less commonly used EPPI/PIXC peripherals. Signed-off-by: steven miao <realmz6@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c32
-rw-r--r--arch/blackfin/mach-bf548/Kconfig59
-rw-r--r--arch/blackfin/mach-bf548/include/mach/dma.h28
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h4
4 files changed, 102 insertions, 21 deletions
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 1e485dfdc9f2..6ce8dce753c9 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -84,6 +84,24 @@ static int __init proc_dma_init(void)
84late_initcall(proc_dma_init); 84late_initcall(proc_dma_init);
85#endif 85#endif
86 86
87static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
88{
89#ifdef CONFIG_BF54x
90 unsigned int per_map;
91
92 switch (channel) {
93 case CH_UART2_RX: per_map = 0xC << 12; break;
94 case CH_UART2_TX: per_map = 0xD << 12; break;
95 case CH_UART3_RX: per_map = 0xE << 12; break;
96 case CH_UART3_TX: per_map = 0xF << 12; break;
97 default: return;
98 }
99
100 if (strncmp(device_id, "BFIN_UART", 9) == 0)
101 dma_ch[channel].regs->peripheral_map = per_map;
102#endif
103}
104
87/** 105/**
88 * request_dma - request a DMA channel 106 * request_dma - request a DMA channel
89 * 107 *
@@ -111,19 +129,7 @@ int request_dma(unsigned int channel, const char *device_id)
111 return -EBUSY; 129 return -EBUSY;
112 } 130 }
113 131
114#ifdef CONFIG_BF54x 132 set_dma_peripheral_map(channel, device_id);
115 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
116 unsigned int per_map;
117 per_map = dma_ch[channel].regs->peripheral_map & 0xFFF;
118 if (strncmp(device_id, "BFIN_UART", 9) == 0)
119 dma_ch[channel].regs->peripheral_map = per_map |
120 ((channel - CH_UART2_RX + 0xC)<<12);
121 else
122 dma_ch[channel].regs->peripheral_map = per_map |
123 ((channel - CH_UART2_RX + 0x6)<<12);
124 }
125#endif
126
127 dma_ch[channel].device_id = device_id; 133 dma_ch[channel].device_id = device_id;
128 dma_ch[channel].irq = 0; 134 dma_ch[channel].irq = 0;
129 135
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 70189a0d1a19..94acb586832e 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -42,6 +42,65 @@ config BF548_ATAPI_ALTERNATIVE_PORT
42 async address or GPIO port F and G. Select y to route it 42 async address or GPIO port F and G. Select y to route it
43 to GPIO. 43 to GPIO.
44 44
45choice
46 prompt "UART2 DMA channel selection"
47 depends on SERIAL_BFIN_UART2
48 default UART2_DMA_RX_ON_DMA18
49 help
50 UART2 DMA channel selection
51 RX -> DMA18
52 TX -> DMA19
53 or
54 RX -> DMA13
55 TX -> DMA14
56
57config UART2_DMA_RX_ON_DMA18
58 bool "UART2 DMA RX -> DMA18 TX -> DMA19"
59 help
60 UART2 DMA channel assignment
61 RX -> DMA18
62 TX -> DMA19
63 use SPORT2 default DMA channel
64
65config UART2_DMA_RX_ON_DMA13
66 bool "UART2 DMA RX -> DMA13 TX -> DMA14"
67 help
68 UART2 DMA channel assignment
69 RX -> DMA13
70 TX -> DMA14
71 use EPPI1 EPPI2 default DMA channel
72endchoice
73
74choice
75 prompt "UART3 DMA channel selection"
76 depends on SERIAL_BFIN_UART3
77 default UART3_DMA_RX_ON_DMA20
78 help
79 UART3 DMA channel selection
80 RX -> DMA20
81 TX -> DMA21
82 or
83 RX -> DMA15
84 TX -> DMA16
85
86config UART3_DMA_RX_ON_DMA20
87 bool "UART3 DMA RX -> DMA20 TX -> DMA21"
88 help
89 UART3 DMA channel assignment
90 RX -> DMA20
91 TX -> DMA21
92 use SPORT3 default DMA channel
93
94config UART3_DMA_RX_ON_DMA15
95 bool "UART3 DMA RX -> DMA15 TX -> DMA16"
96 help
97 UART3 DMA channel assignment
98 RX -> DMA15
99 TX -> DMA16
100 use PIXC default DMA channel
101
102endchoice
103
45comment "Interrupt Priority Assignment" 104comment "Interrupt Priority Assignment"
46menu "Priority" 105menu "Priority"
47 106
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
index a30d242c7398..1a1091b071fd 100644
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -27,17 +27,37 @@
27#define CH_PIXC_OVERLAY 16 27#define CH_PIXC_OVERLAY 16
28#define CH_PIXC_OUTPUT 17 28#define CH_PIXC_OUTPUT 17
29#define CH_SPORT2_RX 18 29#define CH_SPORT2_RX 18
30#define CH_UART2_RX 18
31#define CH_SPORT2_TX 19 30#define CH_SPORT2_TX 19
32#define CH_UART2_TX 19
33#define CH_SPORT3_RX 20 31#define CH_SPORT3_RX 20
34#define CH_UART3_RX 20
35#define CH_SPORT3_TX 21 32#define CH_SPORT3_TX 21
36#define CH_UART3_TX 21
37#define CH_SDH 22 33#define CH_SDH 22
38#define CH_NFC 22 34#define CH_NFC 22
39#define CH_SPI2 23 35#define CH_SPI2 23
40 36
37#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
38#define CH_UART2_RX 13
39#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
40#define CH_UART2_TX 14
41#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
42#else /* Default USE SPORT2's DMA Channel */
43#define CH_UART2_RX 18
44#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
45#define CH_UART2_TX 19
46#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
47#endif
48
49#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
50#define CH_UART3_RX 15
51#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
52#define CH_UART3_TX 16
53#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
54#else /* Default USE SPORT3's DMA Channel */
55#define CH_UART3_RX 20
56#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
57#define CH_UART3_TX 21
58#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
59#endif
60
41#define CH_MEM_STREAM0_DEST 24 61#define CH_MEM_STREAM0_DEST 24
42#define CH_MEM_STREAM0_SRC 25 62#define CH_MEM_STREAM0_SRC 25
43#define CH_MEM_STREAM1_DEST 26 63#define CH_MEM_STREAM1_DEST 26
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 99fd1b2c53d8..7f87787e7738 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -74,13 +74,9 @@ Events (highest priority) EMU 0
74#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ 74#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
75#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ 75#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
76#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ 76#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
77#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
78#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ 77#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
79#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
80#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ 78#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
81#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
82#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ 79#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
83#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
84#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ 80#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
85#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ 81#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
86#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ 82#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */