aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 22:43:33 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 22:43:33 -0500
commit4ef58d4e2ad1fa2a3e5bbf41af2284671fca8cf8 (patch)
tree856ba96302a36014736747e8464f80eeb827bbdd /arch/blackfin
parentf6c4c8195b5e7878823caa1181be404d9e86d369 (diff)
parentd014d043869cdc591f3a33243d3481fa4479c2d0 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (42 commits) tree-wide: fix misspelling of "definition" in comments reiserfs: fix misspelling of "journaled" doc: Fix a typo in slub.txt. inotify: remove superfluous return code check hdlc: spelling fix in find_pvc() comment doc: fix regulator docs cut-and-pasteism mtd: Fix comment in Kconfig doc: Fix IRQ chip docs tree-wide: fix assorted typos all over the place drivers/ata/libata-sff.c: comment spelling fixes fix typos/grammos in Documentation/edac.txt sysctl: add missing comments fs/debugfs/inode.c: fix comment typos sgivwfb: Make use of ARRAY_SIZE. sky2: fix sky2_link_down copy/paste comment error tree-wide: fix typos "couter" -> "counter" tree-wide: fix typos "offest" -> "offset" fix kerneldoc for set_irq_msi() spidev: fix double "of of" in comment comment typo fix: sybsystem -> subsystem ...
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/traps.c2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h4
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h4
8 files changed, 15 insertions, 15 deletions
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 6b7325d634af..78cb3d38f899 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -619,7 +619,7 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
619 619
620/* 620/*
621 * Similar to get_user, do some address checking, then dereference 621 * Similar to get_user, do some address checking, then dereference
622 * Return true on sucess, false on bad address 622 * Return true on success, false on bad address
623 */ 623 */
624static bool get_instruction(unsigned short *val, unsigned short *address) 624static bool get_instruction(unsigned short *val, unsigned short *address)
625{ 625{
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index e06f4112c695..f9fd2b2a2956 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -542,7 +542,7 @@
542#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ 542#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
543#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ 543#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
544#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ 544#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
545#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ 545#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
546#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ 546#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
547#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 547#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
548#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 548#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@@ -550,7 +550,7 @@
550#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ 550#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
551#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ 551#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
552#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ 552#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
553#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ 553#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
554#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ 554#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
555#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 555#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
556#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ 556#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index f821700716ee..b9dbb73d7ef0 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -544,7 +544,7 @@
544#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ 544#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
545#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ 545#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
546#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ 546#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
547#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ 547#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
548#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ 548#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
549#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 549#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
550#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 550#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@@ -552,7 +552,7 @@
552#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ 552#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
553#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ 553#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
554#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ 554#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
555#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ 555#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
556#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ 556#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
557#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 557#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
558#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ 558#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index cebb14feb1ba..a6d20ca57683 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -934,7 +934,7 @@
934#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ 934#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
935#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ 935#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
936#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ 936#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
937#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ 937#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
938#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ 938#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
939#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 939#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
940#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 940#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
@@ -942,7 +942,7 @@
942#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ 942#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
943#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ 943#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
944#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ 944#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
945#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ 945#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
946#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ 946#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
947#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 947#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
948#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ 948#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index dd414ae4ba4c..39f588dcd382 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -491,7 +491,7 @@
491#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ 491#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
492#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ 492#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
493#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ 493#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
494#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ 494#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
495#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ 495#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
496#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ 496#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
497#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ 497#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@@ -501,7 +501,7 @@
501#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ 501#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
502#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ 502#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
503#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ 503#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
504#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ 504#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
505#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ 505#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
506#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ 506#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
507#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ 507#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 5a9dbabe0a68..c4dcf302d9f5 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -470,7 +470,7 @@
470#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ 470#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
471#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ 471#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
472#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ 472#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
473#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ 473#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
474#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ 474#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
475#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ 475#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
476#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ 476#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@@ -480,7 +480,7 @@
480#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ 480#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
481#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ 481#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
482#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ 482#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
483#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ 483#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
484#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ 484#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
485#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ 485#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
486#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ 486#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 82cd593f7391..a5079980968c 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -853,7 +853,7 @@
853#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ 853#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
854#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ 854#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
855#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ 855#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
856#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ 856#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
857#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ 857#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
858#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ 858#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
859#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ 859#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@@ -863,7 +863,7 @@
863#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ 863#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
864#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ 864#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
865#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ 865#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
866#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ 866#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
867#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ 867#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
868#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ 868#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
869#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ 869#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 6fc6e39ab61b..f7f043560c6f 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1024,7 +1024,7 @@
1024#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ 1024#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1025#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ 1025#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1026#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ 1026#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1027#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ 1027#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
1028#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ 1028#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1029#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ 1029#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1030#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ 1030#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
@@ -1034,7 +1034,7 @@
1034#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ 1034#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1035#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ 1035#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1036#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ 1036#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1037#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ 1037#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
1038#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ 1038#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1039#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ 1039#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1040#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ 1040#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 19:44:05 -0500