diff options
author | Graf Yang <graf.yang@analog.com> | 2009-05-08 03:42:12 -0400 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:39 -0400 |
commit | 8af7ffa0d5460586e0f06b2f045a6a2631224b61 (patch) | |
tree | ffe294585cb5bb82f1319c58ffc62ece6b4346f2 /arch/blackfin | |
parent | 1fa9be72b558c39459f98835eb86dbb4ef4da30b (diff) |
Blackfin: add workaround for anomaly 05000287
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cacheinit.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c index c6ff947f9d37..d5a86c3017f7 100644 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c | |||
@@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) | |||
55 | } | 55 | } |
56 | 56 | ||
57 | ctrl = bfin_read_DMEM_CONTROL(); | 57 | ctrl = bfin_read_DMEM_CONTROL(); |
58 | ctrl |= DMEM_CNTR; | 58 | |
59 | /* | ||
60 | * Anomaly notes: | ||
61 | * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL | ||
62 | * register, so that the port preferences for DAG0 and DAG1 are set | ||
63 | * to port B | ||
64 | */ | ||
65 | ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); | ||
59 | bfin_write_DMEM_CONTROL(ctrl); | 66 | bfin_write_DMEM_CONTROL(ctrl); |
60 | SSYNC(); | 67 | SSYNC(); |
61 | } | 68 | } |