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authorCliff Cai <cliff.cai@analog.com>2009-01-07 10:14:38 -0500
committerBryan Wu <cooloney@kernel.org>2009-01-07 10:14:38 -0500
commit14a959101e166abd4165f5a53db5f3dbe4e16fb9 (patch)
tree43021adfee1a052caace973217c548a9594e8ee7 /arch/blackfin
parent6ea28f0ba24d5eb7055b83cd78f51c92a8d7f3e5 (diff)
Blackfin arch: add sdh support for bf518f-ezbrd
Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h68
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h135
2 files changed, 203 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 74e079d9cf72..bafb370cfb3c 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -211,4 +211,72 @@
211#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) 211#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
212#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) 212#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
213 213
214/* Removable Storage Interface Registers */
215
216#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
217#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
218#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
219#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
220#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
221#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
222#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
223#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
224#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
225#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
226#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
227#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
228#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
229#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
230#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
231#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
232#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
233#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
234#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
235#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
236#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
237#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
238#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
239#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
240#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
241#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
242#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
243#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
244#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
245#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
246#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
247#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
248#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
249#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
250#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
251#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
252#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
253#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
254#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
255#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
256#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
257#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
258#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
259#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
260#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
261#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
262#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
263#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
264#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
265#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
266#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
267#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
268#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
269#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
270#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
271#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
272#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
273#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
274#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
275#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
276#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
277#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
278#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
279#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
280
281
214#endif /* _CDEF_BF518_H */ 282#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index 4eaade15dd76..6e982abf4ede 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -513,4 +513,139 @@
513#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ 513#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
514#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ 514#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
515 515
516/* ********************************************************** */
517/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
518/* and MULTI BIT READ MACROS */
519/* ********************************************************** */
520
521/* Bit masks for SDH_COMMAND */
522
523#define CMD_IDX 0x3f /* Command Index */
524#define CMD_RSP 0x40 /* Response */
525#define CMD_L_RSP 0x80 /* Long Response */
526#define CMD_INT_E 0x100 /* Command Interrupt */
527#define CMD_PEND_E 0x200 /* Command Pending */
528#define CMD_E 0x400 /* Command Enable */
529
530/* Bit masks for SDH_PWR_CTL */
531
532#define PWR_ON 0x3 /* Power On */
533#if 0
534#define TBD 0x3c /* TBD */
535#endif
536#define SD_CMD_OD 0x40 /* Open Drain Output */
537#define ROD_CTL 0x80 /* Rod Control */
538
539/* Bit masks for SDH_CLK_CTL */
540
541#define CLKDIV 0xff /* MC_CLK Divisor */
542#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
543#define PWR_SV_E 0x200 /* Power Save Enable */
544#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
545#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
546
547/* Bit masks for SDH_RESP_CMD */
548
549#define RESP_CMD 0x3f /* Response Command */
550
551/* Bit masks for SDH_DATA_CTL */
552
553#define DTX_E 0x1 /* Data Transfer Enable */
554#define DTX_DIR 0x2 /* Data Transfer Direction */
555#define DTX_MODE 0x4 /* Data Transfer Mode */
556#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
557#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
558
559/* Bit masks for SDH_STATUS */
560
561#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
562#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
563#define CMD_TIME_OUT 0x4 /* CMD Time Out */
564#define DAT_TIME_OUT 0x8 /* Data Time Out */
565#define TX_UNDERRUN 0x10 /* Transmit Underrun */
566#define RX_OVERRUN 0x20 /* Receive Overrun */
567#define CMD_RESP_END 0x40 /* CMD Response End */
568#define CMD_SENT 0x80 /* CMD Sent */
569#define DAT_END 0x100 /* Data End */
570#define START_BIT_ERR 0x200 /* Start Bit Error */
571#define DAT_BLK_END 0x400 /* Data Block End */
572#define CMD_ACT 0x800 /* CMD Active */
573#define TX_ACT 0x1000 /* Transmit Active */
574#define RX_ACT 0x2000 /* Receive Active */
575#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
576#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
577#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
578#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
579#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
580#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
581#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
582#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
583
584/* Bit masks for SDH_STATUS_CLR */
585
586#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
587#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
588#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
589#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
590#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
591#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
592#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
593#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
594#define DAT_END_STAT 0x100 /* Data End Status */
595#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
596#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
597
598/* Bit masks for SDH_MASK0 */
599
600#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
601#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
602#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
603#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
604#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
605#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
606#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
607#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
608#define DAT_END_MASK 0x100 /* Data End Mask */
609#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
610#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
611#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
612#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
613#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
614#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
615#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
616#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
617#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
618#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
619#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
620#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
621#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
622
623/* Bit masks for SDH_FIFO_CNT */
624
625#define FIFO_COUNT 0x7fff /* FIFO Count */
626
627/* Bit masks for SDH_E_STATUS */
628
629#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
630#define SD_CARD_DET 0x10 /* SD Card Detect */
631
632/* Bit masks for SDH_E_MASK */
633
634#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
635#define SCD_MSK 0x40 /* Mask Card Detect */
636
637/* Bit masks for SDH_CFG */
638
639#define CLKS_EN 0x1 /* Clocks Enable */
640#define SD4E 0x4 /* SDIO 4-Bit Enable */
641#define MWE 0x8 /* Moving Window Enable */
642#define SD_RST 0x10 /* SDMMC Reset */
643#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
644#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
645#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
646
647/* Bit masks for SDH_RD_WAIT_EN */
648
649#define RWR 0x1 /* Read Wait Request */
650
516#endif /* _DEF_BF518_H */ 651#endif /* _DEF_BF518_H */