diff options
author | Mike Frysinger <vapier@gentoo.org> | 2010-02-16 04:03:18 -0500 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2011-01-10 07:18:04 -0500 |
commit | cfbf1677a336d5e3db6e80d1ed58fbf4b29450ed (patch) | |
tree | b8499f4dfe8c1c2b5c713080d2b327c6b39aa8db /arch/blackfin | |
parent | efb2d31c1c62de9a0e42b2b1981d1a90fc0b4618 (diff) |
Blackfin: switch to asm-generic/io.h
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r-- | arch/blackfin/include/asm/io.h | 238 |
1 files changed, 37 insertions, 201 deletions
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 7d89cca5722a..dccae26805b0 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2004-2009 Analog Devices Inc. | 2 | * Copyright 2004-2010 Analog Devices Inc. |
3 | * | 3 | * |
4 | * Licensed under the GPL-2 or later. | 4 | * Licensed under the GPL-2 or later. |
5 | */ | 5 | */ |
@@ -7,148 +7,48 @@ | |||
7 | #ifndef _BFIN_IO_H | 7 | #ifndef _BFIN_IO_H |
8 | #define _BFIN_IO_H | 8 | #define _BFIN_IO_H |
9 | 9 | ||
10 | #ifdef __KERNEL__ | ||
11 | |||
12 | #ifndef __ASSEMBLY__ | ||
13 | #include <linux/types.h> | ||
14 | #endif | ||
15 | #include <linux/compiler.h> | 10 | #include <linux/compiler.h> |
16 | 11 | #include <linux/types.h> | |
17 | /* | 12 | #include <asm/byteorder.h> |
18 | * These are for ISA/PCI shared memory _only_ and should never be used | 13 | |
19 | * on any other type of memory, including Zorro memory. They are meant to | 14 | #define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \ |
20 | * access the bus in the bus byte order which is little-endian!. | 15 | static inline type __raw_read##size(const volatile void __iomem *addr) \ |
21 | * | 16 | { \ |
22 | * readX/writeX() are used to access memory mapped devices. On some | 17 | unsigned int val; \ |
23 | * architectures the memory mapped IO stuff needs to be accessed | 18 | int tmp; \ |
24 | * differently. On the bfin architecture, we just read/write the | 19 | __asm__ __volatile__ ( \ |
25 | * memory location directly. | 20 | "cli %1;" \ |
26 | */ | 21 | "NOP; NOP; SSYNC;" \ |
27 | #ifndef __ASSEMBLY__ | 22 | "%0 = "#asm" [%2] "#asm_sign";" \ |
28 | 23 | "sti %1;" \ | |
29 | static inline unsigned char readb(const volatile void __iomem *addr) | 24 | : "=d"(val), "=d"(tmp) \ |
30 | { | 25 | : "a"(addr) \ |
31 | unsigned int val; | 26 | ); \ |
32 | int tmp; | 27 | return (type) val; \ |
33 | |||
34 | __asm__ __volatile__ ( | ||
35 | "cli %1;" | ||
36 | "NOP; NOP; SSYNC;" | ||
37 | "%0 = b [%2] (z);" | ||
38 | "sti %1;" | ||
39 | : "=d"(val), "=d"(tmp) | ||
40 | : "a"(addr) | ||
41 | ); | ||
42 | |||
43 | return (unsigned char) val; | ||
44 | } | ||
45 | |||
46 | static inline unsigned short readw(const volatile void __iomem *addr) | ||
47 | { | ||
48 | unsigned int val; | ||
49 | int tmp; | ||
50 | |||
51 | __asm__ __volatile__ ( | ||
52 | "cli %1;" | ||
53 | "NOP; NOP; SSYNC;" | ||
54 | "%0 = w [%2] (z);" | ||
55 | "sti %1;" | ||
56 | : "=d"(val), "=d"(tmp) | ||
57 | : "a"(addr) | ||
58 | ); | ||
59 | |||
60 | return (unsigned short) val; | ||
61 | } | ||
62 | |||
63 | static inline unsigned int readl(const volatile void __iomem *addr) | ||
64 | { | ||
65 | unsigned int val; | ||
66 | int tmp; | ||
67 | |||
68 | __asm__ __volatile__ ( | ||
69 | "cli %1;" | ||
70 | "NOP; NOP; SSYNC;" | ||
71 | "%0 = [%2];" | ||
72 | "sti %1;" | ||
73 | : "=d"(val), "=d"(tmp) | ||
74 | : "a"(addr) | ||
75 | ); | ||
76 | |||
77 | return val; | ||
78 | } | 28 | } |
79 | 29 | DECLARE_BFIN_RAW_READX(b, u8, b, (z)) | |
80 | #endif /* __ASSEMBLY__ */ | 30 | #define __raw_readb __raw_readb |
81 | 31 | DECLARE_BFIN_RAW_READX(w, u16, w, (z)) | |
82 | #define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) | 32 | #define __raw_readw __raw_readw |
83 | #define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) | 33 | DECLARE_BFIN_RAW_READX(l, u32, , ) |
84 | #define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) | 34 | #define __raw_readl __raw_readl |
85 | |||
86 | #define __raw_readb readb | ||
87 | #define __raw_readw readw | ||
88 | #define __raw_readl readl | ||
89 | #define __raw_writeb writeb | ||
90 | #define __raw_writew writew | ||
91 | #define __raw_writel writel | ||
92 | #define memset_io(a, b, c) memset((void *)(a), (b), (c)) | ||
93 | #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) | ||
94 | #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) | ||
95 | |||
96 | /* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ | ||
97 | #define __io(port) ((void *)(unsigned long)(port)) | ||
98 | |||
99 | #define inb(port) readb(__io(port)) | ||
100 | #define inw(port) readw(__io(port)) | ||
101 | #define inl(port) readl(__io(port)) | ||
102 | #define outb(x, port) writeb(x, __io(port)) | ||
103 | #define outw(x, port) writew(x, __io(port)) | ||
104 | #define outl(x, port) writel(x, __io(port)) | ||
105 | |||
106 | #define inb_p(port) inb(__io(port)) | ||
107 | #define inw_p(port) inw(__io(port)) | ||
108 | #define inl_p(port) inl(__io(port)) | ||
109 | #define outb_p(x, port) outb(x, __io(port)) | ||
110 | #define outw_p(x, port) outw(x, __io(port)) | ||
111 | #define outl_p(x, port) outl(x, __io(port)) | ||
112 | |||
113 | #define ioread8_rep(a, d, c) readsb(a, d, c) | ||
114 | #define ioread16_rep(a, d, c) readsw(a, d, c) | ||
115 | #define ioread32_rep(a, d, c) readsl(a, d, c) | ||
116 | #define iowrite8_rep(a, s, c) writesb(a, s, c) | ||
117 | #define iowrite16_rep(a, s, c) writesw(a, s, c) | ||
118 | #define iowrite32_rep(a, s, c) writesl(a, s, c) | ||
119 | |||
120 | #define ioread8(x) readb(x) | ||
121 | #define ioread16(x) readw(x) | ||
122 | #define ioread32(x) readl(x) | ||
123 | #define iowrite8(val, x) writeb(val, x) | ||
124 | #define iowrite16(val, x) writew(val, x) | ||
125 | #define iowrite32(val, x) writel(val, x) | ||
126 | |||
127 | /** | ||
128 | * I/O write barrier | ||
129 | * | ||
130 | * Ensure ordering of I/O space writes. This will make sure that writes | ||
131 | * following the barrier will arrive after all previous writes. | ||
132 | */ | ||
133 | #define mmiowb() do { SSYNC(); wmb(); } while (0) | ||
134 | |||
135 | #define IO_SPACE_LIMIT 0xffffffff | ||
136 | |||
137 | /* Values for nocacheflag and cmode */ | ||
138 | #define IOMAP_NOCACHE_SER 1 | ||
139 | |||
140 | #ifndef __ASSEMBLY__ | ||
141 | 35 | ||
142 | extern void outsb(unsigned long port, const void *addr, unsigned long count); | 36 | extern void outsb(unsigned long port, const void *addr, unsigned long count); |
143 | extern void outsw(unsigned long port, const void *addr, unsigned long count); | 37 | extern void outsw(unsigned long port, const void *addr, unsigned long count); |
144 | extern void outsw_8(unsigned long port, const void *addr, unsigned long count); | 38 | extern void outsw_8(unsigned long port, const void *addr, unsigned long count); |
145 | extern void outsl(unsigned long port, const void *addr, unsigned long count); | 39 | extern void outsl(unsigned long port, const void *addr, unsigned long count); |
40 | #define outsb outsb | ||
41 | #define outsw outsw | ||
42 | #define outsl outsl | ||
146 | 43 | ||
147 | extern void insb(unsigned long port, void *addr, unsigned long count); | 44 | extern void insb(unsigned long port, void *addr, unsigned long count); |
148 | extern void insw(unsigned long port, void *addr, unsigned long count); | 45 | extern void insw(unsigned long port, void *addr, unsigned long count); |
149 | extern void insw_8(unsigned long port, void *addr, unsigned long count); | 46 | extern void insw_8(unsigned long port, void *addr, unsigned long count); |
150 | extern void insl(unsigned long port, void *addr, unsigned long count); | 47 | extern void insl(unsigned long port, void *addr, unsigned long count); |
151 | extern void insl_16(unsigned long port, void *addr, unsigned long count); | 48 | extern void insl_16(unsigned long port, void *addr, unsigned long count); |
49 | #define insb insb | ||
50 | #define insw insw | ||
51 | #define insl insl | ||
152 | 52 | ||
153 | extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); | 53 | extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); |
154 | extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); | 54 | extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); |
@@ -158,78 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count); | |||
158 | extern void dma_insw(unsigned long port, void *addr, unsigned short count); | 58 | extern void dma_insw(unsigned long port, void *addr, unsigned short count); |
159 | extern void dma_insl(unsigned long port, void *addr, unsigned short count); | 59 | extern void dma_insl(unsigned long port, void *addr, unsigned short count); |
160 | 60 | ||
161 | /* | 61 | /** |
162 | * Map some physical address range into the kernel address space. | 62 | * I/O write barrier |
163 | */ | 63 | * |
164 | static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size, | 64 | * Ensure ordering of I/O space writes. This will make sure that writes |
165 | int cacheflag) | 65 | * following the barrier will arrive after all previous writes. |
166 | { | ||
167 | return (void __iomem *)physaddr; | ||
168 | } | ||
169 | |||
170 | /* | ||
171 | * Unmap a ioremap()ed region again | ||
172 | */ | ||
173 | static inline void iounmap(void *addr) | ||
174 | { | ||
175 | } | ||
176 | |||
177 | /* | ||
178 | * __iounmap unmaps nearly everything, so be careful | ||
179 | * it doesn't free currently pointer/page tables anymore but it | ||
180 | * wans't used anyway and might be added later. | ||
181 | */ | ||
182 | static inline void __iounmap(void *addr, unsigned long size) | ||
183 | { | ||
184 | } | ||
185 | |||
186 | /* | ||
187 | * Set new cache mode for some kernel address space. | ||
188 | * The caller must push data for that range itself, if such data may already | ||
189 | * be in the cache. | ||
190 | */ | 66 | */ |
191 | static inline void kernel_set_cachemode(void *addr, unsigned long size, | 67 | #define mmiowb() do { SSYNC(); wmb(); } while (0) |
192 | int cmode) | ||
193 | { | ||
194 | } | ||
195 | |||
196 | static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) | ||
197 | { | ||
198 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
199 | } | ||
200 | static inline void __iomem *ioremap_nocache(unsigned long physaddr, | ||
201 | unsigned long size) | ||
202 | { | ||
203 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
204 | } | ||
205 | 68 | ||
206 | extern void blkfin_inv_cache_all(void); | 69 | #include <asm-generic/io.h> |
207 | 70 | ||
208 | #endif | 71 | #endif |
209 | |||
210 | #define ioport_map(port, nr) ((void __iomem*)(port)) | ||
211 | #define ioport_unmap(addr) | ||
212 | |||
213 | /* Pages to physical address... */ | ||
214 | #define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) | ||
215 | |||
216 | #define phys_to_virt(vaddr) ((void *) (vaddr)) | ||
217 | #define virt_to_phys(vaddr) ((unsigned long) (vaddr)) | ||
218 | |||
219 | #define virt_to_bus virt_to_phys | ||
220 | #define bus_to_virt phys_to_virt | ||
221 | |||
222 | /* | ||
223 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
224 | * access | ||
225 | */ | ||
226 | #define xlate_dev_mem_ptr(p) __va(p) | ||
227 | |||
228 | /* | ||
229 | * Convert a virtual cached pointer to an uncached pointer | ||
230 | */ | ||
231 | #define xlate_dev_kmem_ptr(p) p | ||
232 | |||
233 | #endif /* __KERNEL__ */ | ||
234 | |||
235 | #endif /* _BFIN_IO_H */ | ||