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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:52:35 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-16 13:52:35 -0500
commit525995d77ca08dfc2ba6f8e606f93694271dbd66 (patch)
treebe9ddad66cd1301eea8dab7814cbda144a909e35 /arch/blackfin
parente4bdda1bc3123a9e65f4dd93a23041fde8ed3dc2 (diff)
parent64a2b168023bfd09037ba760838762e56c44178e (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (88 commits) Blackfin: Convert BUG() to use unreachable() Blackfin: define __NR_recvmmsg Blackfin: drop duplicate sched_clock Blackfin: NOMPU: skip DMA ICPLB hole when it is redundant Blackfin: MPU: add missing __init markings Blackfin: add support for TIF_NOTIFY_RESUME Blackfin: kgdb_test: clean up code a bit Blackfin: convert kgdbtest to proc_fops Blackfin: convert cyc2ns() to clocksource_cyc2ns() Blackfin: ip0x: pull in asm/portmux.h for P_xxx defines Blackfin: drop unused ax88180 resources Blackfin: bf537-stamp: add ADF702x network driver resources Blackfin: bf537-stamp: add CAN resources Blackfin: bf537-stamp: add AD5258 i2c address Blackfin: bf537-stamp: add adau1761 i2c address Blackfin: bf537-stamp: add adau1371 i2c address Blackfin: bf537-stamp: add ADP8870 resources Blackfin: bf537-stamp: kill AD714x board-specific Kconfigs Blackfin: bf537-stamp: update ADP5520 resources Blackfin: bf537-stamp: add ADXL346 orientation sensing support ...
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/Kconfig41
-rw-r--r--arch/blackfin/Makefile4
-rw-r--r--arch/blackfin/boot/Makefile6
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig14
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig2
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig2
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig2
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig2
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig7
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig2
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig332
-rw-r--r--arch/blackfin/configs/BF561-ACVILON_defconfig1643
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig214
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig2
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig390
-rw-r--r--arch/blackfin/configs/CM-BF533_defconfig631
-rw-r--r--arch/blackfin/configs/CM-BF537E_defconfig334
-rw-r--r--arch/blackfin/configs/CM-BF537U_defconfig620
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig793
-rw-r--r--arch/blackfin/configs/CM-BF561_defconfig558
-rw-r--r--arch/blackfin/configs/H8606_defconfig2
-rw-r--r--arch/blackfin/configs/IP0X_defconfig2
-rw-r--r--arch/blackfin/configs/PNAV-10_defconfig2
-rw-r--r--arch/blackfin/configs/SRV1_defconfig4
-rw-r--r--arch/blackfin/configs/TCM-BF537_defconfig577
-rw-r--r--arch/blackfin/include/asm/bfin-global.h10
-rw-r--r--arch/blackfin/include/asm/bug.h2
-rw-r--r--arch/blackfin/include/asm/cacheflush.h1
-rw-r--r--arch/blackfin/include/asm/checksum.h70
-rw-r--r--arch/blackfin/include/asm/clocks.h2
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h121
-rw-r--r--arch/blackfin/include/asm/dma.h93
-rw-r--r--arch/blackfin/include/asm/dpmc.h107
-rw-r--r--arch/blackfin/include/asm/gpio.h5
-rw-r--r--arch/blackfin/include/asm/gptimers.h32
-rw-r--r--arch/blackfin/include/asm/io.h95
-rw-r--r--arch/blackfin/include/asm/ipipe.h14
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h26
-rw-r--r--arch/blackfin/include/asm/irqflags.h13
-rw-r--r--arch/blackfin/include/asm/kgdb.h3
-rw-r--r--arch/blackfin/include/asm/mem_init.h153
-rw-r--r--arch/blackfin/include/asm/mmu_context.h33
-rw-r--r--arch/blackfin/include/asm/pci.h130
-rw-r--r--arch/blackfin/include/asm/ptrace.h6
-rw-r--r--arch/blackfin/include/asm/sections.h16
-rw-r--r--arch/blackfin/include/asm/thread_info.h2
-rw-r--r--arch/blackfin/include/asm/trace.h2
-rw-r--r--arch/blackfin/include/asm/uaccess.h4
-rw-r--r--arch/blackfin/include/asm/unistd.h3
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c52
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c99
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c2
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c13
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c31
-rw-r--r--arch/blackfin/kernel/dma-mapping.c68
-rw-r--r--arch/blackfin/kernel/gptimers.c32
-rw-r--r--arch/blackfin/kernel/ipipe.c67
-rw-r--r--arch/blackfin/kernel/kgdb.c17
-rw-r--r--arch/blackfin/kernel/kgdb_test.c67
-rw-r--r--arch/blackfin/kernel/process.c95
-rw-r--r--arch/blackfin/kernel/ptrace.c13
-rw-r--r--arch/blackfin/kernel/setup.c46
-rw-r--r--arch/blackfin/kernel/signal.c18
-rw-r--r--arch/blackfin/kernel/time-ts.c47
-rw-r--r--arch/blackfin/kernel/time.c8
-rw-r--r--arch/blackfin/kernel/traps.c45
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S28
-rw-r--r--arch/blackfin/lib/Makefile2
-rw-r--r--arch/blackfin/lib/checksum.c125
-rw-r--r--arch/blackfin/mach-bf518/Kconfig4
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h13
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h80
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h247
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h75
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h45
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h213
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h592
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h186
-rw-r--r--arch/blackfin/mach-bf527/Kconfig4
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c48
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c62
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF525.h11
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h424
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h23
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h11
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h679
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h186
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c8
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c15
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c6
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h115
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c46
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c386
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bf537.h10
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h95
-rw-r--r--arch/blackfin/mach-bf538/Makefile1
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c42
-rw-r--r--arch/blackfin/mach-bf538/ext-gpio.c123
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h1261
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h7
-rw-r--r--arch/blackfin/mach-bf538/include/mach/portmux.h2
-rw-r--r--arch/blackfin/mach-bf548/Kconfig24
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c59
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bf548.h12
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF547.h12
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF548.h788
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF549.h1533
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h1203
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h2526
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h289
-rw-r--r--arch/blackfin/mach-bf561/boards/Kconfig7
-rw-r--r--arch/blackfin/mach-bf561/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c551
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c28
-rw-r--r--arch/blackfin/mach-bf561/coreb.c8
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h101
-rw-r--r--arch/blackfin/mach-bf561/smp.c17
-rw-r--r--arch/blackfin/mach-common/clocks-init.c1
-rw-r--r--arch/blackfin/mach-common/cpufreq.c5
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S30
-rw-r--r--arch/blackfin/mach-common/entry.S4
-rw-r--r--arch/blackfin/mach-common/ints-priority.c15
-rw-r--r--arch/blackfin/mach-common/smp.c16
131 files changed, 6757 insertions, 13563 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 2180433213b7..53c1e1d45c68 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -32,6 +32,9 @@ config BLACKFIN
32 select HAVE_OPROFILE 32 select HAVE_OPROFILE
33 select ARCH_WANT_OPTIONAL_GPIOLIB 33 select ARCH_WANT_OPTIONAL_GPIOLIB
34 34
35config GENERIC_CSUM
36 def_bool y
37
35config GENERIC_BUG 38config GENERIC_BUG
36 def_bool y 39 def_bool y
37 depends on BUG 40 depends on BUG
@@ -177,7 +180,7 @@ config BF539
177 help 180 help
178 BF539 Processor Support. 181 BF539 Processor Support.
179 182
180config BF542 183config BF542_std
181 bool "BF542" 184 bool "BF542"
182 help 185 help
183 BF542 Processor Support. 186 BF542 Processor Support.
@@ -187,7 +190,7 @@ config BF542M
187 help 190 help
188 BF542 Processor Support. 191 BF542 Processor Support.
189 192
190config BF544 193config BF544_std
191 bool "BF544" 194 bool "BF544"
192 help 195 help
193 BF544 Processor Support. 196 BF544 Processor Support.
@@ -197,7 +200,7 @@ config BF544M
197 help 200 help
198 BF544 Processor Support. 201 BF544 Processor Support.
199 202
200config BF547 203config BF547_std
201 bool "BF547" 204 bool "BF547"
202 help 205 help
203 BF547 Processor Support. 206 BF547 Processor Support.
@@ -207,7 +210,7 @@ config BF547M
207 help 210 help
208 BF547 Processor Support. 211 BF547 Processor Support.
209 212
210config BF548 213config BF548_std
211 bool "BF548" 214 bool "BF548"
212 help 215 help
213 BF548 Processor Support. 216 BF548 Processor Support.
@@ -217,7 +220,7 @@ config BF548M
217 help 220 help
218 BF548 Processor Support. 221 BF548 Processor Support.
219 222
220config BF549 223config BF549_std
221 bool "BF549" 224 bool "BF549"
222 help 225 help
223 BF549 Processor Support. 226 BF549 Processor Support.
@@ -311,31 +314,11 @@ config BF_REV_NONE
311 314
312endchoice 315endchoice
313 316
314config BF51x
315 bool
316 depends on (BF512 || BF514 || BF516 || BF518)
317 default y
318
319config BF52x
320 bool
321 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
322 default y
323
324config BF53x 317config BF53x
325 bool 318 bool
326 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
327 default y 320 default y
328 321
329config BF54xM
330 bool
331 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
332 default y
333
334config BF54x
335 bool
336 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
337 default y
338
339config MEM_GENERIC_BOARD 322config MEM_GENERIC_BOARD
340 bool 323 bool
341 depends on GENERIC_BOARD 324 depends on GENERIC_BOARD
@@ -917,6 +900,12 @@ config DMA_UNCACHED_2M
917 bool "Enable 2M DMA region" 900 bool "Enable 2M DMA region"
918config DMA_UNCACHED_1M 901config DMA_UNCACHED_1M
919 bool "Enable 1M DMA region" 902 bool "Enable 1M DMA region"
903config DMA_UNCACHED_512K
904 bool "Enable 512K DMA region"
905config DMA_UNCACHED_256K
906 bool "Enable 256K DMA region"
907config DMA_UNCACHED_128K
908 bool "Enable 128K DMA region"
920config DMA_UNCACHED_NONE 909config DMA_UNCACHED_NONE
921 bool "Disable DMA region" 910 bool "Disable DMA region"
922endchoice 911endchoice
@@ -1278,6 +1267,8 @@ source "net/Kconfig"
1278 1267
1279source "drivers/Kconfig" 1268source "drivers/Kconfig"
1280 1269
1270source "drivers/firmware/Kconfig"
1271
1281source "fs/Kconfig" 1272source "fs/Kconfig"
1282 1273
1283source "arch/blackfin/Kconfig.debug" 1274source "arch/blackfin/Kconfig.debug"
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index f063b772934b..d4c7177e7656 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -16,6 +16,7 @@ GZFLAGS := -9
16KBUILD_CFLAGS += $(call cc-option,-mno-fdpic) 16KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
17KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) 17KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
18CFLAGS_MODULE += -mlong-calls 18CFLAGS_MODULE += -mlong-calls
19LDFLAGS_MODULE += -m elf32bfin
19KALLSYMS += --symbol-prefix=_ 20KALLSYMS += --symbol-prefix=_
20 21
21KBUILD_DEFCONFIG := BF537-STAMP_defconfig 22KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -137,7 +138,7 @@ archclean:
137 138
138INSTALL_PATH ?= /tftpboot 139INSTALL_PATH ?= /tftpboot
139boot := arch/$(ARCH)/boot 140boot := arch/$(ARCH)/boot
140BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma 141BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
141PHONY += $(BOOT_TARGETS) install 142PHONY += $(BOOT_TARGETS) install
142KBUILD_IMAGE := $(boot)/vmImage 143KBUILD_IMAGE := $(boot)/vmImage
143 144
@@ -151,6 +152,7 @@ install:
151 152
152define archhelp 153define archhelp
153 echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)' 154 echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)'
155 echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
154 echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' 156 echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
155 echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' 157 echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
156 echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' 158 echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index fd9ccc5fea10..e9c48c6f8c1f 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -8,7 +8,7 @@
8 8
9MKIMAGE := $(srctree)/scripts/mkuboot.sh 9MKIMAGE := $(srctree)/scripts/mkuboot.sh
10 10
11targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma 11targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma
12extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma 12extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
13 13
14quiet_cmd_uimage = UIMAGE $@ 14quiet_cmd_uimage = UIMAGE $@
@@ -29,6 +29,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
29$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE 29$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
30 $(call if_changed,lzma) 30 $(call if_changed,lzma)
31 31
32$(obj)/vmImage.bin: $(obj)/vmlinux.bin
33 $(call if_changed,uimage,none)
34
32$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 35$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
33 $(call if_changed,uimage,bzip2) 36 $(call if_changed,uimage,bzip2)
34 37
@@ -38,6 +41,7 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
38$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma 41$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
39 $(call if_changed,uimage,lzma) 42 $(call if_changed,uimage,lzma)
40 43
44suffix-y := bin
41suffix-$(CONFIG_KERNEL_GZIP) := gz 45suffix-$(CONFIG_KERNEL_GZIP) := gz
42suffix-$(CONFIG_KERNEL_BZIP2) := bz2 46suffix-$(CONFIG_KERNEL_BZIP2) := bz2
43suffix-$(CONFIG_KERNEL_LZMA) := lzma 47suffix-$(CONFIG_KERNEL_LZMA) := lzma
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 9905b26009e5..e31559419817 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -316,6 +317,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
316# CONFIG_PHYS_ADDR_T_64BIT is not set 317# CONFIG_PHYS_ADDR_T_64BIT is not set
317CONFIG_ZONE_DMA_FLAG=1 318CONFIG_ZONE_DMA_FLAG=1
318CONFIG_VIRT_TO_BUS=y 319CONFIG_VIRT_TO_BUS=y
320CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
319CONFIG_BFIN_GPTIMERS=m 321CONFIG_BFIN_GPTIMERS=m
320# CONFIG_DMA_UNCACHED_4M is not set 322# CONFIG_DMA_UNCACHED_4M is not set
321# CONFIG_DMA_UNCACHED_2M is not set 323# CONFIG_DMA_UNCACHED_2M is not set
@@ -438,17 +440,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
438# CONFIG_TIPC is not set 440# CONFIG_TIPC is not set
439# CONFIG_ATM is not set 441# CONFIG_ATM is not set
440# CONFIG_BRIDGE is not set 442# CONFIG_BRIDGE is not set
441CONFIG_NET_DSA=y 443# CONFIG_NET_DSA is not set
442# CONFIG_NET_DSA_TAG_DSA is not set
443# CONFIG_NET_DSA_TAG_EDSA is not set
444# CONFIG_NET_DSA_TAG_TRAILER is not set
445CONFIG_NET_DSA_TAG_STPID=y
446# CONFIG_NET_DSA_MV88E6XXX is not set
447# CONFIG_NET_DSA_MV88E6060 is not set
448# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
449# CONFIG_NET_DSA_MV88E6131 is not set
450# CONFIG_NET_DSA_MV88E6123_61_65 is not set
451CONFIG_NET_DSA_KSZ8893M=y
452# CONFIG_VLAN_8021Q is not set 444# CONFIG_VLAN_8021Q is not set
453# CONFIG_DECNET is not set 445# CONFIG_DECNET is not set
454# CONFIG_LLC2 is not set 446# CONFIG_LLC2 is not set
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 9dc682088023..075e0fdcb399 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
321# CONFIG_PHYS_ADDR_T_64BIT is not set 322# CONFIG_PHYS_ADDR_T_64BIT is not set
322CONFIG_ZONE_DMA_FLAG=1 323CONFIG_ZONE_DMA_FLAG=1
323CONFIG_VIRT_TO_BUS=y 324CONFIG_VIRT_TO_BUS=y
325CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
324CONFIG_BFIN_GPTIMERS=m 326CONFIG_BFIN_GPTIMERS=m
325# CONFIG_DMA_UNCACHED_4M is not set 327# CONFIG_DMA_UNCACHED_4M is not set
326# CONFIG_DMA_UNCACHED_2M is not set 328# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 77e35d4baf53..6d1a623fb149 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -321,6 +322,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
321# CONFIG_PHYS_ADDR_T_64BIT is not set 322# CONFIG_PHYS_ADDR_T_64BIT is not set
322CONFIG_ZONE_DMA_FLAG=1 323CONFIG_ZONE_DMA_FLAG=1
323CONFIG_VIRT_TO_BUS=y 324CONFIG_VIRT_TO_BUS=y
325CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
324CONFIG_BFIN_GPTIMERS=y 326CONFIG_BFIN_GPTIMERS=y
325# CONFIG_DMA_UNCACHED_4M is not set 327# CONFIG_DMA_UNCACHED_4M is not set
326# CONFIG_DMA_UNCACHED_2M is not set 328# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 4c044805cb5c..50f9a23ccdbd 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
283# CONFIG_PHYS_ADDR_T_64BIT is not set 284# CONFIG_PHYS_ADDR_T_64BIT is not set
284CONFIG_ZONE_DMA_FLAG=1 285CONFIG_ZONE_DMA_FLAG=1
285CONFIG_VIRT_TO_BUS=y 286CONFIG_VIRT_TO_BUS=y
287CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
286CONFIG_BFIN_GPTIMERS=m 288CONFIG_BFIN_GPTIMERS=m
287# CONFIG_DMA_UNCACHED_4M is not set 289# CONFIG_DMA_UNCACHED_4M is not set
288# CONFIG_DMA_UNCACHED_2M is not set 290# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index c99bbcd09a68..6c60c8286318 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -283,6 +284,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
283# CONFIG_PHYS_ADDR_T_64BIT is not set 284# CONFIG_PHYS_ADDR_T_64BIT is not set
284CONFIG_ZONE_DMA_FLAG=1 285CONFIG_ZONE_DMA_FLAG=1
285CONFIG_VIRT_TO_BUS=y 286CONFIG_VIRT_TO_BUS=y
287CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
286CONFIG_BFIN_GPTIMERS=m 288CONFIG_BFIN_GPTIMERS=m
287# CONFIG_DMA_UNCACHED_4M is not set 289# CONFIG_DMA_UNCACHED_4M is not set
288# CONFIG_DMA_UNCACHED_2M is not set 290# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 092ffda80e68..2908595b67c5 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -290,6 +291,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
290# CONFIG_PHYS_ADDR_T_64BIT is not set 291# CONFIG_PHYS_ADDR_T_64BIT is not set
291CONFIG_ZONE_DMA_FLAG=1 292CONFIG_ZONE_DMA_FLAG=1
292CONFIG_VIRT_TO_BUS=y 293CONFIG_VIRT_TO_BUS=y
294CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
293CONFIG_BFIN_GPTIMERS=m 295CONFIG_BFIN_GPTIMERS=m
294# CONFIG_DMA_UNCACHED_4M is not set 296# CONFIG_DMA_UNCACHED_4M is not set
295# CONFIG_DMA_UNCACHED_2M is not set 297# CONFIG_DMA_UNCACHED_2M is not set
@@ -704,10 +706,7 @@ CONFIG_CONFIG_INPUT_PCF8574=m
704# 706#
705# Hardware I/O ports 707# Hardware I/O ports
706# 708#
707CONFIG_SERIO=y 709# CONFIG_SERIO is not set
708CONFIG_SERIO_SERPORT=y
709CONFIG_SERIO_LIBPS2=y
710# CONFIG_SERIO_RAW is not set
711# CONFIG_GAMEPORT is not set 710# CONFIG_GAMEPORT is not set
712 711
713# 712#
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index fa698a89f6fe..09ea2499555e 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -67,6 +67,7 @@ CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 71# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 72# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 73CONFIG_HAVE_OPROFILE=y
@@ -301,6 +302,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
301# CONFIG_PHYS_ADDR_T_64BIT is not set 302# CONFIG_PHYS_ADDR_T_64BIT is not set
302CONFIG_ZONE_DMA_FLAG=1 303CONFIG_ZONE_DMA_FLAG=1
303CONFIG_VIRT_TO_BUS=y 304CONFIG_VIRT_TO_BUS=y
305CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
304CONFIG_BFIN_GPTIMERS=m 306CONFIG_BFIN_GPTIMERS=m
305# CONFIG_DMA_UNCACHED_4M is not set 307# CONFIG_DMA_UNCACHED_4M is not set
306# CONFIG_DMA_UNCACHED_2M is not set 308# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index f773ad1155d4..eb3e98b6f3f0 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,22 +1,29 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28.10 3# Linux kernel version: 2.6.31.5
4# Thu May 21 05:50:01 2009 4# Mon Nov 2 22:02:56 2009
5# 5#
6# CONFIG_MMU is not set 6# CONFIG_MMU is not set
7# CONFIG_FPU is not set 7# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y 10CONFIG_BLACKFIN=y
11CONFIG_GENERIC_CSUM=y
12CONFIG_GENERIC_BUG=y
11CONFIG_ZONE_DMA=y 13CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 14CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 15CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y 16CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y 17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_GPIO=y 19CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14 20CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y 21CONFIG_GENERIC_CALIBRATE_DELAY=y
22CONFIG_LOCKDEP_SUPPORT=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_TRACE_IRQFLAGS_SUPPORT=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 25CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
26CONFIG_CONSTRUCTORS=y
20 27
21# 28#
22# General setup 29# General setup
@@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32 33CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION="" 34CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y 35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_HAVE_KERNEL_GZIP=y
37CONFIG_HAVE_KERNEL_BZIP2=y
38CONFIG_HAVE_KERNEL_LZMA=y
39CONFIG_KERNEL_GZIP=y
40# CONFIG_KERNEL_BZIP2 is not set
41# CONFIG_KERNEL_LZMA is not set
29CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set 45# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
34# CONFIG_AUDIT is not set 47# CONFIG_AUDIT is not set
48
49#
50# RCU Subsystem
51#
52CONFIG_CLASSIC_RCU=y
53# CONFIG_TREE_RCU is not set
54# CONFIG_PREEMPT_RCU is not set
55# CONFIG_TREE_RCU_TRACE is not set
56# CONFIG_PREEMPT_RCU_TRACE is not set
35CONFIG_IKCONFIG=y 57CONFIG_IKCONFIG=y
36CONFIG_IKCONFIG_PROC=y 58CONFIG_IKCONFIG_PROC=y
37CONFIG_LOG_BUF_SHIFT=14 59CONFIG_LOG_BUF_SHIFT=14
38# CONFIG_CGROUPS is not set
39# CONFIG_GROUP_SCHED is not set 60# CONFIG_GROUP_SCHED is not set
61# CONFIG_CGROUPS is not set
40# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
41# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
42# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
43CONFIG_BLK_DEV_INITRD=y 65CONFIG_BLK_DEV_INITRD=y
44CONFIG_INITRAMFS_SOURCE="" 66CONFIG_INITRAMFS_SOURCE=""
67CONFIG_RD_GZIP=y
68# CONFIG_RD_BZIP2 is not set
69# CONFIG_RD_LZMA is not set
45# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 70# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
46CONFIG_SYSCTL=y 71CONFIG_SYSCTL=y
47CONFIG_ANON_INODES=y 72CONFIG_ANON_INODES=y
@@ -62,17 +87,28 @@ CONFIG_EPOLL=y
62# CONFIG_TIMERFD is not set 87# CONFIG_TIMERFD is not set
63# CONFIG_EVENTFD is not set 88# CONFIG_EVENTFD is not set
64# CONFIG_AIO is not set 89# CONFIG_AIO is not set
90
91#
92# Performance Counters
93#
65CONFIG_VM_EVENT_COUNTERS=y 94CONFIG_VM_EVENT_COUNTERS=y
95# CONFIG_STRIP_ASM_SYMS is not set
66CONFIG_COMPAT_BRK=y 96CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 97CONFIG_SLAB=y
68# CONFIG_SLUB is not set 98# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 99# CONFIG_SLOB is not set
100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 102# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 103CONFIG_HAVE_OPROFILE=y
104
105#
106# GCOV-based kernel profiling
107#
108# CONFIG_GCOV_KERNEL is not set
109# CONFIG_SLOW_WORK is not set
73# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
74CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
75CONFIG_TINY_SHMEM=y
76CONFIG_BASE_SMALL=0 112CONFIG_BASE_SMALL=0
77CONFIG_MODULES=y 113CONFIG_MODULES=y
78# CONFIG_MODULE_FORCE_LOAD is not set 114# CONFIG_MODULE_FORCE_LOAD is not set
@@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set 116# CONFIG_MODULE_FORCE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set 117# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set 118# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y 119CONFIG_BLOCK=y
85# CONFIG_LBD is not set 120# CONFIG_LBDAF is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set 121# CONFIG_BLK_DEV_BSG is not set
89# CONFIG_BLK_DEV_INTEGRITY is not set 122# CONFIG_BLK_DEV_INTEGRITY is not set
90 123
@@ -94,13 +127,12 @@ CONFIG_BLOCK=y
94CONFIG_IOSCHED_NOOP=y 127CONFIG_IOSCHED_NOOP=y
95CONFIG_IOSCHED_AS=y 128CONFIG_IOSCHED_AS=y
96# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
97CONFIG_IOSCHED_CFQ=y 130# CONFIG_IOSCHED_CFQ is not set
98CONFIG_DEFAULT_AS=y 131CONFIG_DEFAULT_AS=y
99# CONFIG_DEFAULT_DEADLINE is not set 132# CONFIG_DEFAULT_DEADLINE is not set
100# CONFIG_DEFAULT_CFQ is not set 133# CONFIG_DEFAULT_CFQ is not set
101# CONFIG_DEFAULT_NOOP is not set 134# CONFIG_DEFAULT_NOOP is not set
102CONFIG_DEFAULT_IOSCHED="anticipatory" 135CONFIG_DEFAULT_IOSCHED="anticipatory"
103CONFIG_CLASSIC_RCU=y
104# CONFIG_PREEMPT_NONE is not set 136# CONFIG_PREEMPT_NONE is not set
105CONFIG_PREEMPT_VOLUNTARY=y 137CONFIG_PREEMPT_VOLUNTARY=y
106# CONFIG_PREEMPT is not set 138# CONFIG_PREEMPT is not set
@@ -137,7 +169,7 @@ CONFIG_PREEMPT_VOLUNTARY=y
137# CONFIG_BF544M is not set 169# CONFIG_BF544M is not set
138# CONFIG_BF547 is not set 170# CONFIG_BF547 is not set
139# CONFIG_BF547M is not set 171# CONFIG_BF547M is not set
140CONFIG_BF548=y 172CONFIG_BF548_std=y
141# CONFIG_BF548M is not set 173# CONFIG_BF548M is not set
142# CONFIG_BF549 is not set 174# CONFIG_BF549 is not set
143# CONFIG_BF549M is not set 175# CONFIG_BF549M is not set
@@ -195,7 +227,7 @@ CONFIG_BFIN548_EZKIT=y
195# 227#
196# BF548 Specific Configuration 228# BF548 Specific Configuration
197# 229#
198# CONFIG_DEB_DMA_URGENT is not set 230CONFIG_DEB_DMA_URGENT=y
199# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set 231# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
200 232
201# 233#
@@ -352,10 +384,11 @@ CONFIG_FLATMEM=y
352CONFIG_FLAT_NODE_MEM_MAP=y 384CONFIG_FLAT_NODE_MEM_MAP=y
353CONFIG_PAGEFLAGS_EXTENDED=y 385CONFIG_PAGEFLAGS_EXTENDED=y
354CONFIG_SPLIT_PTLOCK_CPUS=4 386CONFIG_SPLIT_PTLOCK_CPUS=4
355# CONFIG_RESOURCES_64BIT is not set
356# CONFIG_PHYS_ADDR_T_64BIT is not set 387# CONFIG_PHYS_ADDR_T_64BIT is not set
357CONFIG_ZONE_DMA_FLAG=1 388CONFIG_ZONE_DMA_FLAG=1
358CONFIG_VIRT_TO_BUS=y 389CONFIG_VIRT_TO_BUS=y
390CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
391CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
359CONFIG_BFIN_GPTIMERS=m 392CONFIG_BFIN_GPTIMERS=m
360# CONFIG_DMA_UNCACHED_4M is not set 393# CONFIG_DMA_UNCACHED_4M is not set
361CONFIG_DMA_UNCACHED_2M=y 394CONFIG_DMA_UNCACHED_2M=y
@@ -366,14 +399,13 @@ CONFIG_DMA_UNCACHED_2M=y
366# Cache Support 399# Cache Support
367# 400#
368CONFIG_BFIN_ICACHE=y 401CONFIG_BFIN_ICACHE=y
369# CONFIG_BFIN_ICACHE_LOCK is not set 402CONFIG_BFIN_EXTMEM_ICACHEABLE=y
403# CONFIG_BFIN_L2_ICACHEABLE is not set
370CONFIG_BFIN_DCACHE=y 404CONFIG_BFIN_DCACHE=y
371# CONFIG_BFIN_DCACHE_BANKA is not set 405# CONFIG_BFIN_DCACHE_BANKA is not set
372CONFIG_BFIN_EXTMEM_ICACHEABLE=y
373CONFIG_BFIN_EXTMEM_DCACHEABLE=y 406CONFIG_BFIN_EXTMEM_DCACHEABLE=y
374CONFIG_BFIN_EXTMEM_WRITEBACK=y 407# CONFIG_BFIN_EXTMEM_WRITEBACK is not set
375# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 408CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
376# CONFIG_BFIN_L2_ICACHEABLE is not set
377# CONFIG_BFIN_L2_DCACHEABLE is not set 409# CONFIG_BFIN_L2_DCACHEABLE is not set
378 410
379# 411#
@@ -382,7 +414,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
382# CONFIG_MPU is not set 414# CONFIG_MPU is not set
383 415
384# 416#
385# Asynchonous Memory Configuration 417# Asynchronous Memory Configuration
386# 418#
387 419
388# 420#
@@ -441,11 +473,6 @@ CONFIG_NET=y
441CONFIG_PACKET=y 473CONFIG_PACKET=y
442# CONFIG_PACKET_MMAP is not set 474# CONFIG_PACKET_MMAP is not set
443CONFIG_UNIX=y 475CONFIG_UNIX=y
444CONFIG_XFRM=y
445# CONFIG_XFRM_USER is not set
446# CONFIG_XFRM_SUB_POLICY is not set
447# CONFIG_XFRM_MIGRATE is not set
448# CONFIG_XFRM_STATISTICS is not set
449# CONFIG_NET_KEY is not set 476# CONFIG_NET_KEY is not set
450CONFIG_INET=y 477CONFIG_INET=y
451# CONFIG_IP_MULTICAST is not set 478# CONFIG_IP_MULTICAST is not set
@@ -469,13 +496,11 @@ CONFIG_IP_PNP=y
469# CONFIG_INET_XFRM_MODE_BEET is not set 496# CONFIG_INET_XFRM_MODE_BEET is not set
470# CONFIG_INET_LRO is not set 497# CONFIG_INET_LRO is not set
471# CONFIG_INET_DIAG is not set 498# CONFIG_INET_DIAG is not set
472CONFIG_INET_TCP_DIAG=y
473# CONFIG_TCP_CONG_ADVANCED is not set 499# CONFIG_TCP_CONG_ADVANCED is not set
474CONFIG_TCP_CONG_CUBIC=y 500CONFIG_TCP_CONG_CUBIC=y
475CONFIG_DEFAULT_TCP_CONG="cubic" 501CONFIG_DEFAULT_TCP_CONG="cubic"
476# CONFIG_TCP_MD5SIG is not set 502# CONFIG_TCP_MD5SIG is not set
477# CONFIG_IPV6 is not set 503# CONFIG_IPV6 is not set
478# CONFIG_NETLABEL is not set
479# CONFIG_NETWORK_SECMARK is not set 504# CONFIG_NETWORK_SECMARK is not set
480# CONFIG_NETFILTER is not set 505# CONFIG_NETFILTER is not set
481# CONFIG_IP_DCCP is not set 506# CONFIG_IP_DCCP is not set
@@ -493,7 +518,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
493# CONFIG_LAPB is not set 518# CONFIG_LAPB is not set
494# CONFIG_ECONET is not set 519# CONFIG_ECONET is not set
495# CONFIG_WAN_ROUTER is not set 520# CONFIG_WAN_ROUTER is not set
521# CONFIG_PHONET is not set
522# CONFIG_IEEE802154 is not set
496# CONFIG_NET_SCHED is not set 523# CONFIG_NET_SCHED is not set
524# CONFIG_DCB is not set
497 525
498# 526#
499# Network testing 527# Network testing
@@ -548,14 +576,10 @@ CONFIG_SIR_BFIN_DMA=y
548# CONFIG_MCS_FIR is not set 576# CONFIG_MCS_FIR is not set
549# CONFIG_BT is not set 577# CONFIG_BT is not set
550# CONFIG_AF_RXRPC is not set 578# CONFIG_AF_RXRPC is not set
551# CONFIG_PHONET is not set 579# CONFIG_WIRELESS is not set
552CONFIG_WIRELESS=y
553# CONFIG_CFG80211 is not set
554CONFIG_WIRELESS_OLD_REGULATORY=y
555CONFIG_WIRELESS_EXT=y 580CONFIG_WIRELESS_EXT=y
556CONFIG_WIRELESS_EXT_SYSFS=y 581CONFIG_LIB80211=m
557# CONFIG_MAC80211 is not set 582# CONFIG_WIMAX is not set
558# CONFIG_IEEE80211 is not set
559# CONFIG_RFKILL is not set 583# CONFIG_RFKILL is not set
560# CONFIG_NET_9P is not set 584# CONFIG_NET_9P is not set
561 585
@@ -578,6 +602,7 @@ CONFIG_EXTRA_FIRMWARE=""
578# CONFIG_CONNECTOR is not set 602# CONFIG_CONNECTOR is not set
579CONFIG_MTD=y 603CONFIG_MTD=y
580# CONFIG_MTD_DEBUG is not set 604# CONFIG_MTD_DEBUG is not set
605# CONFIG_MTD_TESTS is not set
581# CONFIG_MTD_CONCAT is not set 606# CONFIG_MTD_CONCAT is not set
582CONFIG_MTD_PARTITIONS=y 607CONFIG_MTD_PARTITIONS=y
583# CONFIG_MTD_REDBOOT_PARTS is not set 608# CONFIG_MTD_REDBOOT_PARTS is not set
@@ -653,7 +678,6 @@ CONFIG_MTD_NAND=y
653# CONFIG_MTD_NAND_VERIFY_WRITE is not set 678# CONFIG_MTD_NAND_VERIFY_WRITE is not set
654# CONFIG_MTD_NAND_ECC_SMC is not set 679# CONFIG_MTD_NAND_ECC_SMC is not set
655# CONFIG_MTD_NAND_MUSEUM_IDS is not set 680# CONFIG_MTD_NAND_MUSEUM_IDS is not set
656# CONFIG_MTD_NAND_BFIN is not set
657CONFIG_MTD_NAND_IDS=y 681CONFIG_MTD_NAND_IDS=y
658CONFIG_MTD_NAND_BF5XX=y 682CONFIG_MTD_NAND_BF5XX=y
659CONFIG_MTD_NAND_BF5XX_HWECC=y 683CONFIG_MTD_NAND_BF5XX_HWECC=y
@@ -665,6 +689,11 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y
665# CONFIG_MTD_ONENAND is not set 689# CONFIG_MTD_ONENAND is not set
666 690
667# 691#
692# LPDDR flash memory drivers
693#
694# CONFIG_MTD_LPDDR is not set
695
696#
668# UBI - Unsorted block images 697# UBI - Unsorted block images
669# 698#
670# CONFIG_MTD_UBI is not set 699# CONFIG_MTD_UBI is not set
@@ -682,10 +711,20 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
682# CONFIG_ATA_OVER_ETH is not set 711# CONFIG_ATA_OVER_ETH is not set
683# CONFIG_BLK_DEV_HD is not set 712# CONFIG_BLK_DEV_HD is not set
684CONFIG_MISC_DEVICES=y 713CONFIG_MISC_DEVICES=y
685# CONFIG_EEPROM_93CX6 is not set
686# CONFIG_ICS932S401 is not set 714# CONFIG_ICS932S401 is not set
687# CONFIG_ENCLOSURE_SERVICES is not set 715# CONFIG_ENCLOSURE_SERVICES is not set
716# CONFIG_ISL29003 is not set
717# CONFIG_AD525X_DPOT is not set
688# CONFIG_C2PORT is not set 718# CONFIG_C2PORT is not set
719
720#
721# EEPROM support
722#
723# CONFIG_EEPROM_AT24 is not set
724# CONFIG_EEPROM_AT25 is not set
725# CONFIG_EEPROM_LEGACY is not set
726# CONFIG_EEPROM_MAX6875 is not set
727# CONFIG_EEPROM_93CX6 is not set
689CONFIG_HAVE_IDE=y 728CONFIG_HAVE_IDE=y
690# CONFIG_IDE is not set 729# CONFIG_IDE is not set
691 730
@@ -709,10 +748,6 @@ CONFIG_BLK_DEV_SR=m
709# CONFIG_BLK_DEV_SR_VENDOR is not set 748# CONFIG_BLK_DEV_SR_VENDOR is not set
710# CONFIG_CHR_DEV_SG is not set 749# CONFIG_CHR_DEV_SG is not set
711# CONFIG_CHR_DEV_SCH is not set 750# CONFIG_CHR_DEV_SCH is not set
712
713#
714# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
715#
716# CONFIG_SCSI_MULTI_LUN is not set 751# CONFIG_SCSI_MULTI_LUN is not set
717# CONFIG_SCSI_CONSTANTS is not set 752# CONFIG_SCSI_CONSTANTS is not set
718# CONFIG_SCSI_LOGGING is not set 753# CONFIG_SCSI_LOGGING is not set
@@ -729,6 +764,7 @@ CONFIG_SCSI_WAIT_SCAN=m
729# CONFIG_SCSI_SRP_ATTRS is not set 764# CONFIG_SCSI_SRP_ATTRS is not set
730# CONFIG_SCSI_LOWLEVEL is not set 765# CONFIG_SCSI_LOWLEVEL is not set
731# CONFIG_SCSI_DH is not set 766# CONFIG_SCSI_DH is not set
767# CONFIG_SCSI_OSD_INITIATOR is not set
732CONFIG_ATA=y 768CONFIG_ATA=y
733# CONFIG_ATA_NONSTANDARD is not set 769# CONFIG_ATA_NONSTANDARD is not set
734CONFIG_SATA_PMP=y 770CONFIG_SATA_PMP=y
@@ -744,13 +780,34 @@ CONFIG_NETDEVICES=y
744# CONFIG_EQUALIZER is not set 780# CONFIG_EQUALIZER is not set
745# CONFIG_TUN is not set 781# CONFIG_TUN is not set
746# CONFIG_VETH is not set 782# CONFIG_VETH is not set
747# CONFIG_PHYLIB is not set 783CONFIG_PHYLIB=y
784
785#
786# MII PHY device drivers
787#
788# CONFIG_MARVELL_PHY is not set
789# CONFIG_DAVICOM_PHY is not set
790# CONFIG_QSEMI_PHY is not set
791# CONFIG_LXT_PHY is not set
792# CONFIG_CICADA_PHY is not set
793# CONFIG_VITESSE_PHY is not set
794# CONFIG_SMSC_PHY is not set
795# CONFIG_BROADCOM_PHY is not set
796# CONFIG_ICPLUS_PHY is not set
797# CONFIG_REALTEK_PHY is not set
798# CONFIG_NATIONAL_PHY is not set
799# CONFIG_STE10XP is not set
800# CONFIG_LSI_ET1011C_PHY is not set
801# CONFIG_FIXED_PHY is not set
802# CONFIG_MDIO_BITBANG is not set
748CONFIG_NET_ETHERNET=y 803CONFIG_NET_ETHERNET=y
749CONFIG_MII=y 804CONFIG_MII=y
750# CONFIG_SMC91X is not set 805# CONFIG_SMC91X is not set
751CONFIG_SMSC911X=y
752# CONFIG_DM9000 is not set 806# CONFIG_DM9000 is not set
753# CONFIG_ENC28J60 is not set 807# CONFIG_ENC28J60 is not set
808# CONFIG_ETHOC is not set
809CONFIG_SMSC911X=y
810# CONFIG_DNET is not set
754# CONFIG_IBM_NEW_EMAC_ZMII is not set 811# CONFIG_IBM_NEW_EMAC_ZMII is not set
755# CONFIG_IBM_NEW_EMAC_RGMII is not set 812# CONFIG_IBM_NEW_EMAC_RGMII is not set
756# CONFIG_IBM_NEW_EMAC_TAH is not set 813# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -759,6 +816,8 @@ CONFIG_SMSC911X=y
759# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set 816# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
760# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set 817# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
761# CONFIG_B44 is not set 818# CONFIG_B44 is not set
819# CONFIG_KS8842 is not set
820# CONFIG_KS8851 is not set
762# CONFIG_NETDEV_1000 is not set 821# CONFIG_NETDEV_1000 is not set
763# CONFIG_NETDEV_10000 is not set 822# CONFIG_NETDEV_10000 is not set
764 823
@@ -771,13 +830,16 @@ CONFIG_LIBERTAS=m
771# CONFIG_LIBERTAS_USB is not set 830# CONFIG_LIBERTAS_USB is not set
772CONFIG_LIBERTAS_SDIO=m 831CONFIG_LIBERTAS_SDIO=m
773CONFIG_POWEROF2_BLOCKSIZE_ONLY=y 832CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
833# CONFIG_LIBERTAS_SPI is not set
774# CONFIG_LIBERTAS_DEBUG is not set 834# CONFIG_LIBERTAS_DEBUG is not set
775# CONFIG_USB_ZD1201 is not set 835# CONFIG_USB_ZD1201 is not set
776# CONFIG_USB_NET_RNDIS_WLAN is not set
777# CONFIG_IWLWIFI_LEDS is not set
778# CONFIG_HOSTAP is not set 836# CONFIG_HOSTAP is not set
779 837
780# 838#
839# Enable WiMAX (Networking options) to see the WiMAX drivers
840#
841
842#
781# USB Network Adapters 843# USB Network Adapters
782# 844#
783# CONFIG_USB_CATC is not set 845# CONFIG_USB_CATC is not set
@@ -813,28 +875,31 @@ CONFIG_INPUT_EVBUG=m
813# Input Device Drivers 875# Input Device Drivers
814# 876#
815CONFIG_INPUT_KEYBOARD=y 877CONFIG_INPUT_KEYBOARD=y
878# CONFIG_KEYBOARD_ADP5588 is not set
816# CONFIG_KEYBOARD_ATKBD is not set 879# CONFIG_KEYBOARD_ATKBD is not set
817# CONFIG_KEYBOARD_SUNKBD is not set 880CONFIG_KEYBOARD_BFIN=y
818# CONFIG_KEYBOARD_LKKBD is not set 881# CONFIG_KEYBOARD_LKKBD is not set
819# CONFIG_KEYBOARD_XTKBD is not set
820# CONFIG_KEYBOARD_NEWTON is not set
821# CONFIG_KEYBOARD_STOWAWAY is not set
822# CONFIG_KEYBOARD_GPIO is not set 882# CONFIG_KEYBOARD_GPIO is not set
823CONFIG_KEYBOARD_BFIN=y 883# CONFIG_KEYBOARD_MATRIX is not set
884# CONFIG_KEYBOARD_NEWTON is not set
824# CONFIG_KEYBOARD_OPENCORES is not set 885# CONFIG_KEYBOARD_OPENCORES is not set
825# CONFIG_KEYBOARD_ADP5588 is not set 886# CONFIG_KEYBOARD_STOWAWAY is not set
887# CONFIG_KEYBOARD_SUNKBD is not set
888# CONFIG_KEYBOARD_XTKBD is not set
826# CONFIG_INPUT_MOUSE is not set 889# CONFIG_INPUT_MOUSE is not set
827# CONFIG_INPUT_JOYSTICK is not set 890# CONFIG_INPUT_JOYSTICK is not set
828# CONFIG_INPUT_TABLET is not set 891# CONFIG_INPUT_TABLET is not set
829CONFIG_INPUT_TOUCHSCREEN=y 892CONFIG_INPUT_TOUCHSCREEN=y
893# CONFIG_TOUCHSCREEN_ADS7846 is not set
830CONFIG_TOUCHSCREEN_AD7877=m 894CONFIG_TOUCHSCREEN_AD7877=m
831# CONFIG_TOUCHSCREEN_AD7879_I2C is not set 895# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
832# CONFIG_TOUCHSCREEN_AD7879_SPI is not set 896# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
833# CONFIG_TOUCHSCREEN_AD7879 is not set 897# CONFIG_TOUCHSCREEN_AD7879 is not set
834# CONFIG_TOUCHSCREEN_ADS7846 is not set 898# CONFIG_TOUCHSCREEN_EETI is not set
835# CONFIG_TOUCHSCREEN_FUJITSU is not set 899# CONFIG_TOUCHSCREEN_FUJITSU is not set
836# CONFIG_TOUCHSCREEN_GUNZE is not set 900# CONFIG_TOUCHSCREEN_GUNZE is not set
837# CONFIG_TOUCHSCREEN_ELO is not set 901# CONFIG_TOUCHSCREEN_ELO is not set
902# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
838# CONFIG_TOUCHSCREEN_MTOUCH is not set 903# CONFIG_TOUCHSCREEN_MTOUCH is not set
839# CONFIG_TOUCHSCREEN_INEXIO is not set 904# CONFIG_TOUCHSCREEN_INEXIO is not set
840# CONFIG_TOUCHSCREEN_MK712 is not set 905# CONFIG_TOUCHSCREEN_MK712 is not set
@@ -844,6 +909,8 @@ CONFIG_TOUCHSCREEN_AD7877=m
844# CONFIG_TOUCHSCREEN_WM97XX is not set 909# CONFIG_TOUCHSCREEN_WM97XX is not set
845# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set 910# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
846# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 911# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
912# CONFIG_TOUCHSCREEN_TSC2007 is not set
913# CONFIG_TOUCHSCREEN_W90X900 is not set
847CONFIG_INPUT_MISC=y 914CONFIG_INPUT_MISC=y
848# CONFIG_INPUT_ATI_REMOTE is not set 915# CONFIG_INPUT_ATI_REMOTE is not set
849# CONFIG_INPUT_ATI_REMOTE2 is not set 916# CONFIG_INPUT_ATI_REMOTE2 is not set
@@ -852,7 +919,11 @@ CONFIG_INPUT_MISC=y
852# CONFIG_INPUT_YEALINK is not set 919# CONFIG_INPUT_YEALINK is not set
853# CONFIG_INPUT_CM109 is not set 920# CONFIG_INPUT_CM109 is not set
854# CONFIG_INPUT_UINPUT is not set 921# CONFIG_INPUT_UINPUT is not set
855# CONFIG_CONFIG_INPUT_PCF8574 is not set 922# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
923# CONFIG_INPUT_BFIN_ROTARY is not set
924# CONFIG_INPUT_AD714X is not set
925# CONFIG_INPUT_ADXL34X is not set
926# CONFIG_INPUT_PCF8574 is not set
856 927
857# 928#
858# Hardware I/O ports 929# Hardware I/O ports
@@ -863,16 +934,13 @@ CONFIG_INPUT_MISC=y
863# 934#
864# Character devices 935# Character devices
865# 936#
866# CONFIG_AD9960 is not set
867CONFIG_BFIN_DMA_INTERFACE=m 937CONFIG_BFIN_DMA_INTERFACE=m
868# CONFIG_BFIN_PPI is not set 938# CONFIG_BFIN_PPI is not set
869# CONFIG_BFIN_PPIFCD is not set 939# CONFIG_BFIN_PPIFCD is not set
870# CONFIG_BFIN_SIMPLE_TIMER is not set 940# CONFIG_BFIN_SIMPLE_TIMER is not set
871# CONFIG_BFIN_SPI_ADC is not set 941# CONFIG_BFIN_SPI_ADC is not set
872CONFIG_BFIN_SPORT=m 942CONFIG_BFIN_SPORT=m
873# CONFIG_BFIN_TIMER_LATENCY is not set
874# CONFIG_BFIN_TWI_LCD is not set 943# CONFIG_BFIN_TWI_LCD is not set
875CONFIG_SIMPLE_GPIO=m
876CONFIG_VT=y 944CONFIG_VT=y
877CONFIG_CONSOLE_TRANSLATIONS=y 945CONFIG_CONSOLE_TRANSLATIONS=y
878CONFIG_VT_CONSOLE=y 946CONFIG_VT_CONSOLE=y
@@ -890,6 +958,7 @@ CONFIG_BFIN_JTAG_COMM=m
890# 958#
891# Non-8250 serial port support 959# Non-8250 serial port support
892# 960#
961# CONFIG_SERIAL_MAX3100 is not set
893CONFIG_SERIAL_BFIN=y 962CONFIG_SERIAL_BFIN=y
894CONFIG_SERIAL_BFIN_CONSOLE=y 963CONFIG_SERIAL_BFIN_CONSOLE=y
895CONFIG_SERIAL_BFIN_DMA=y 964CONFIG_SERIAL_BFIN_DMA=y
@@ -903,6 +972,7 @@ CONFIG_SERIAL_CORE=y
903CONFIG_SERIAL_CORE_CONSOLE=y 972CONFIG_SERIAL_CORE_CONSOLE=y
904# CONFIG_SERIAL_BFIN_SPORT is not set 973# CONFIG_SERIAL_BFIN_SPORT is not set
905CONFIG_UNIX98_PTYS=y 974CONFIG_UNIX98_PTYS=y
975# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
906# CONFIG_LEGACY_PTYS is not set 976# CONFIG_LEGACY_PTYS is not set
907CONFIG_BFIN_OTP=y 977CONFIG_BFIN_OTP=y
908# CONFIG_BFIN_OTP_WRITE_ENABLE is not set 978# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@@ -951,14 +1021,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
951# Miscellaneous I2C Chip support 1021# Miscellaneous I2C Chip support
952# 1022#
953# CONFIG_DS1682 is not set 1023# CONFIG_DS1682 is not set
954# CONFIG_EEPROM_AT24 is not set
955# CONFIG_SENSORS_AD5252 is not set
956# CONFIG_EEPROM_LEGACY is not set
957# CONFIG_SENSORS_PCF8574 is not set 1024# CONFIG_SENSORS_PCF8574 is not set
958# CONFIG_PCF8575 is not set 1025# CONFIG_PCF8575 is not set
959# CONFIG_SENSORS_PCA9539 is not set 1026# CONFIG_SENSORS_PCA9539 is not set
960# CONFIG_SENSORS_PCF8591 is not set
961# CONFIG_SENSORS_MAX6875 is not set
962# CONFIG_SENSORS_TSL2550 is not set 1027# CONFIG_SENSORS_TSL2550 is not set
963# CONFIG_I2C_DEBUG_CORE is not set 1028# CONFIG_I2C_DEBUG_CORE is not set
964# CONFIG_I2C_DEBUG_ALGO is not set 1029# CONFIG_I2C_DEBUG_ALGO is not set
@@ -975,13 +1040,18 @@ CONFIG_SPI_BFIN=y
975# CONFIG_SPI_BFIN_LOCK is not set 1040# CONFIG_SPI_BFIN_LOCK is not set
976# CONFIG_SPI_BFIN_SPORT is not set 1041# CONFIG_SPI_BFIN_SPORT is not set
977# CONFIG_SPI_BITBANG is not set 1042# CONFIG_SPI_BITBANG is not set
1043# CONFIG_SPI_GPIO is not set
978 1044
979# 1045#
980# SPI Protocol Masters 1046# SPI Protocol Masters
981# 1047#
982# CONFIG_EEPROM_AT25 is not set
983# CONFIG_SPI_SPIDEV is not set 1048# CONFIG_SPI_SPIDEV is not set
984# CONFIG_SPI_TLE62X0 is not set 1049# CONFIG_SPI_TLE62X0 is not set
1050
1051#
1052# PPS support
1053#
1054# CONFIG_PPS is not set
985CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 1055CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
986CONFIG_GPIOLIB=y 1056CONFIG_GPIOLIB=y
987# CONFIG_DEBUG_GPIO is not set 1057# CONFIG_DEBUG_GPIO is not set
@@ -997,6 +1067,7 @@ CONFIG_GPIO_SYSFS=y
997# CONFIG_GPIO_MAX732X is not set 1067# CONFIG_GPIO_MAX732X is not set
998# CONFIG_GPIO_PCA953X is not set 1068# CONFIG_GPIO_PCA953X is not set
999# CONFIG_GPIO_PCF857X is not set 1069# CONFIG_GPIO_PCF857X is not set
1070# CONFIG_GPIO_ADP5588 is not set
1000 1071
1001# 1072#
1002# PCI GPIO expanders: 1073# PCI GPIO expanders:
@@ -1038,28 +1109,19 @@ CONFIG_SSB_POSSIBLE=y
1038# CONFIG_MFD_CORE is not set 1109# CONFIG_MFD_CORE is not set
1039# CONFIG_MFD_SM501 is not set 1110# CONFIG_MFD_SM501 is not set
1040# CONFIG_HTC_PASIC3 is not set 1111# CONFIG_HTC_PASIC3 is not set
1112# CONFIG_UCB1400_CORE is not set
1113# CONFIG_TPS65010 is not set
1114# CONFIG_TWL4030_CORE is not set
1041# CONFIG_MFD_TMIO is not set 1115# CONFIG_MFD_TMIO is not set
1042# CONFIG_PMIC_DA903X is not set 1116# CONFIG_PMIC_DA903X is not set
1043# CONFIG_PMIC_ADP5520 is not set 1117# CONFIG_PMIC_ADP5520 is not set
1044# CONFIG_MFD_WM8400 is not set 1118# CONFIG_MFD_WM8400 is not set
1045# CONFIG_MFD_WM8350_I2C is not set 1119# CONFIG_MFD_WM8350_I2C is not set
1120# CONFIG_MFD_PCF50633 is not set
1121# CONFIG_AB3100_CORE is not set
1122# CONFIG_EZX_PCAP is not set
1046# CONFIG_REGULATOR is not set 1123# CONFIG_REGULATOR is not set
1047 1124# CONFIG_MEDIA_SUPPORT is not set
1048#
1049# Multimedia devices
1050#
1051
1052#
1053# Multimedia core support
1054#
1055# CONFIG_VIDEO_DEV is not set
1056# CONFIG_DVB_CORE is not set
1057# CONFIG_VIDEO_MEDIA is not set
1058
1059#
1060# Multimedia drivers
1061#
1062# CONFIG_DAB is not set
1063 1125
1064# 1126#
1065# Graphics support 1127# Graphics support
@@ -1096,6 +1158,7 @@ CONFIG_FB_BF54X_LQ043=y
1096# CONFIG_FB_VIRTUAL is not set 1158# CONFIG_FB_VIRTUAL is not set
1097# CONFIG_FB_METRONOME is not set 1159# CONFIG_FB_METRONOME is not set
1098# CONFIG_FB_MB862XX is not set 1160# CONFIG_FB_MB862XX is not set
1161# CONFIG_FB_BROADSHEET is not set
1099# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1162# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1100 1163
1101# 1164#
@@ -1132,6 +1195,7 @@ CONFIG_SOUND_OSS_CORE=y
1132CONFIG_SND=y 1195CONFIG_SND=y
1133CONFIG_SND_TIMER=y 1196CONFIG_SND_TIMER=y
1134CONFIG_SND_PCM=y 1197CONFIG_SND_PCM=y
1198CONFIG_SND_JACK=y
1135# CONFIG_SND_SEQUENCER is not set 1199# CONFIG_SND_SEQUENCER is not set
1136CONFIG_SND_OSSEMUL=y 1200CONFIG_SND_OSSEMUL=y
1137CONFIG_SND_MIXER_OSS=y 1201CONFIG_SND_MIXER_OSS=y
@@ -1142,6 +1206,11 @@ CONFIG_SND_SUPPORT_OLD_API=y
1142CONFIG_SND_VERBOSE_PROCFS=y 1206CONFIG_SND_VERBOSE_PROCFS=y
1143# CONFIG_SND_VERBOSE_PRINTK is not set 1207# CONFIG_SND_VERBOSE_PRINTK is not set
1144# CONFIG_SND_DEBUG is not set 1208# CONFIG_SND_DEBUG is not set
1209# CONFIG_SND_RAWMIDI_SEQ is not set
1210# CONFIG_SND_OPL3_LIB_SEQ is not set
1211# CONFIG_SND_OPL4_LIB_SEQ is not set
1212# CONFIG_SND_SBAWE_SEQ is not set
1213# CONFIG_SND_EMU10K1_SEQ is not set
1145CONFIG_SND_DRIVERS=y 1214CONFIG_SND_DRIVERS=y
1146# CONFIG_SND_DUMMY is not set 1215# CONFIG_SND_DUMMY is not set
1147# CONFIG_SND_MTPAV is not set 1216# CONFIG_SND_MTPAV is not set
@@ -1152,7 +1221,6 @@ CONFIG_SND_SPI=y
1152# 1221#
1153# ALSA Blackfin devices 1222# ALSA Blackfin devices
1154# 1223#
1155# CONFIG_SND_BLACKFIN_AD1836 is not set
1156# CONFIG_SND_BFIN_AD73322 is not set 1224# CONFIG_SND_BFIN_AD73322 is not set
1157CONFIG_SND_USB=y 1225CONFIG_SND_USB=y
1158# CONFIG_SND_USB_AUDIO is not set 1226# CONFIG_SND_USB_AUDIO is not set
@@ -1160,15 +1228,17 @@ CONFIG_SND_USB=y
1160CONFIG_SND_SOC=y 1228CONFIG_SND_SOC=y
1161CONFIG_SND_SOC_AC97_BUS=y 1229CONFIG_SND_SOC_AC97_BUS=y
1162# CONFIG_SND_BF5XX_I2S is not set 1230# CONFIG_SND_BF5XX_I2S is not set
1231# CONFIG_SND_BF5XX_TDM is not set
1163CONFIG_SND_BF5XX_AC97=y 1232CONFIG_SND_BF5XX_AC97=y
1164CONFIG_SND_BF5XX_MMAP_SUPPORT=y 1233CONFIG_SND_BF5XX_MMAP_SUPPORT=y
1165# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set 1234# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
1235CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
1236CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
1237CONFIG_SND_BF5XX_SOC_AD1980=y
1166CONFIG_SND_BF5XX_SOC_SPORT=y 1238CONFIG_SND_BF5XX_SOC_SPORT=y
1167CONFIG_SND_BF5XX_SOC_AC97=y 1239CONFIG_SND_BF5XX_SOC_AC97=y
1168CONFIG_SND_BF5XX_SOC_AD1980=y
1169CONFIG_SND_BF5XX_SPORT_NUM=0 1240CONFIG_SND_BF5XX_SPORT_NUM=0
1170CONFIG_SND_BF5XX_HAVE_COLD_RESET=y 1241CONFIG_SND_SOC_I2C_AND_SPI=y
1171CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
1172# CONFIG_SND_SOC_ALL_CODECS is not set 1242# CONFIG_SND_SOC_ALL_CODECS is not set
1173CONFIG_SND_SOC_AD1980=y 1243CONFIG_SND_SOC_AD1980=y
1174# CONFIG_SOUND_PRIME is not set 1244# CONFIG_SOUND_PRIME is not set
@@ -1188,30 +1258,34 @@ CONFIG_USB_HID=y
1188# 1258#
1189# Special HID drivers 1259# Special HID drivers
1190# 1260#
1191CONFIG_HID_COMPAT=y
1192CONFIG_HID_A4TECH=y 1261CONFIG_HID_A4TECH=y
1193CONFIG_HID_APPLE=y 1262CONFIG_HID_APPLE=y
1194CONFIG_HID_BELKIN=y 1263CONFIG_HID_BELKIN=y
1195CONFIG_HID_BRIGHT=y
1196CONFIG_HID_CHERRY=y 1264CONFIG_HID_CHERRY=y
1197CONFIG_HID_CHICONY=y 1265CONFIG_HID_CHICONY=y
1198CONFIG_HID_CYPRESS=y 1266CONFIG_HID_CYPRESS=y
1199CONFIG_HID_DELL=y 1267# CONFIG_HID_DRAGONRISE is not set
1200CONFIG_HID_EZKEY=y 1268CONFIG_HID_EZKEY=y
1269# CONFIG_HID_KYE is not set
1201CONFIG_HID_GYRATION=y 1270CONFIG_HID_GYRATION=y
1271# CONFIG_HID_KENSINGTON is not set
1202CONFIG_HID_LOGITECH=y 1272CONFIG_HID_LOGITECH=y
1203# CONFIG_LOGITECH_FF is not set 1273# CONFIG_LOGITECH_FF is not set
1204# CONFIG_LOGIRUMBLEPAD2_FF is not set 1274# CONFIG_LOGIRUMBLEPAD2_FF is not set
1205CONFIG_HID_MICROSOFT=y 1275CONFIG_HID_MICROSOFT=y
1206CONFIG_HID_MONTEREY=y 1276CONFIG_HID_MONTEREY=y
1277# CONFIG_HID_NTRIG is not set
1207CONFIG_HID_PANTHERLORD=y 1278CONFIG_HID_PANTHERLORD=y
1208# CONFIG_PANTHERLORD_FF is not set 1279# CONFIG_PANTHERLORD_FF is not set
1209CONFIG_HID_PETALYNX=y 1280CONFIG_HID_PETALYNX=y
1210CONFIG_HID_SAMSUNG=y 1281CONFIG_HID_SAMSUNG=y
1211CONFIG_HID_SONY=y 1282CONFIG_HID_SONY=y
1212CONFIG_HID_SUNPLUS=y 1283CONFIG_HID_SUNPLUS=y
1213CONFIG_THRUSTMASTER_FF=m 1284# CONFIG_HID_GREENASIA is not set
1214CONFIG_ZEROPLUS_FF=m 1285# CONFIG_HID_SMARTJOYPLUS is not set
1286# CONFIG_HID_TOPSEED is not set
1287# CONFIG_HID_THRUSTMASTER is not set
1288# CONFIG_HID_ZEROPLUS is not set
1215CONFIG_USB_SUPPORT=y 1289CONFIG_USB_SUPPORT=y
1216CONFIG_USB_ARCH_HAS_HCD=y 1290CONFIG_USB_ARCH_HAS_HCD=y
1217# CONFIG_USB_ARCH_HAS_OHCI is not set 1291# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -1237,6 +1311,7 @@ CONFIG_USB_MON=y
1237# USB Host Controller Drivers 1311# USB Host Controller Drivers
1238# 1312#
1239# CONFIG_USB_C67X00_HCD is not set 1313# CONFIG_USB_C67X00_HCD is not set
1314# CONFIG_USB_OXU210HP_HCD is not set
1240# CONFIG_USB_ISP116X_HCD is not set 1315# CONFIG_USB_ISP116X_HCD is not set
1241# CONFIG_USB_ISP1760_HCD is not set 1316# CONFIG_USB_ISP1760_HCD is not set
1242# CONFIG_USB_ISP1362_HCD is not set 1317# CONFIG_USB_ISP1362_HCD is not set
@@ -1267,18 +1342,17 @@ CONFIG_USB_INVENTRA_DMA=y
1267# CONFIG_USB_TMC is not set 1342# CONFIG_USB_TMC is not set
1268 1343
1269# 1344#
1270# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 1345# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1271# 1346#
1272 1347
1273# 1348#
1274# see USB_STORAGE Help for more information 1349# also be needed; see USB_STORAGE Help for more info
1275# 1350#
1276CONFIG_USB_STORAGE=y 1351CONFIG_USB_STORAGE=y
1277# CONFIG_USB_STORAGE_DEBUG is not set 1352# CONFIG_USB_STORAGE_DEBUG is not set
1278# CONFIG_USB_STORAGE_DATAFAB is not set 1353# CONFIG_USB_STORAGE_DATAFAB is not set
1279# CONFIG_USB_STORAGE_FREECOM is not set 1354# CONFIG_USB_STORAGE_FREECOM is not set
1280# CONFIG_USB_STORAGE_ISD200 is not set 1355# CONFIG_USB_STORAGE_ISD200 is not set
1281# CONFIG_USB_STORAGE_DPCM is not set
1282# CONFIG_USB_STORAGE_USBAT is not set 1356# CONFIG_USB_STORAGE_USBAT is not set
1283# CONFIG_USB_STORAGE_SDDR09 is not set 1357# CONFIG_USB_STORAGE_SDDR09 is not set
1284# CONFIG_USB_STORAGE_SDDR55 is not set 1358# CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1314,7 +1388,6 @@ CONFIG_USB_STORAGE=y
1314# CONFIG_USB_LED is not set 1388# CONFIG_USB_LED is not set
1315# CONFIG_USB_CYPRESS_CY7C63 is not set 1389# CONFIG_USB_CYPRESS_CY7C63 is not set
1316# CONFIG_USB_CYTHERM is not set 1390# CONFIG_USB_CYTHERM is not set
1317# CONFIG_USB_PHIDGET is not set
1318# CONFIG_USB_IDMOUSE is not set 1391# CONFIG_USB_IDMOUSE is not set
1319# CONFIG_USB_FTDI_ELAN is not set 1392# CONFIG_USB_FTDI_ELAN is not set
1320# CONFIG_USB_APPLEDISPLAY is not set 1393# CONFIG_USB_APPLEDISPLAY is not set
@@ -1326,6 +1399,13 @@ CONFIG_USB_STORAGE=y
1326# CONFIG_USB_ISIGHTFW is not set 1399# CONFIG_USB_ISIGHTFW is not set
1327# CONFIG_USB_VST is not set 1400# CONFIG_USB_VST is not set
1328# CONFIG_USB_GADGET is not set 1401# CONFIG_USB_GADGET is not set
1402
1403#
1404# OTG and related infrastructure
1405#
1406CONFIG_USB_OTG_UTILS=y
1407# CONFIG_USB_GPIO_VBUS is not set
1408CONFIG_NOP_USB_XCEIV=y
1329CONFIG_MMC=y 1409CONFIG_MMC=y
1330# CONFIG_MMC_DEBUG is not set 1410# CONFIG_MMC_DEBUG is not set
1331# CONFIG_MMC_UNSAFE_RESUME is not set 1411# CONFIG_MMC_UNSAFE_RESUME is not set
@@ -1380,6 +1460,7 @@ CONFIG_RTC_INTF_DEV=y
1380# CONFIG_RTC_DRV_S35390A is not set 1460# CONFIG_RTC_DRV_S35390A is not set
1381# CONFIG_RTC_DRV_FM3130 is not set 1461# CONFIG_RTC_DRV_FM3130 is not set
1382# CONFIG_RTC_DRV_RX8581 is not set 1462# CONFIG_RTC_DRV_RX8581 is not set
1463# CONFIG_RTC_DRV_RX8025 is not set
1383 1464
1384# 1465#
1385# SPI RTC drivers 1466# SPI RTC drivers
@@ -1411,10 +1492,21 @@ CONFIG_RTC_INTF_DEV=y
1411# 1492#
1412CONFIG_RTC_DRV_BFIN=y 1493CONFIG_RTC_DRV_BFIN=y
1413# CONFIG_DMADEVICES is not set 1494# CONFIG_DMADEVICES is not set
1495# CONFIG_AUXDISPLAY is not set
1414# CONFIG_UIO is not set 1496# CONFIG_UIO is not set
1497
1498#
1499# TI VLYNQ
1500#
1415# CONFIG_STAGING is not set 1501# CONFIG_STAGING is not set
1416 1502
1417# 1503#
1504# Firmware Drivers
1505#
1506# CONFIG_FIRMWARE_MEMMAP is not set
1507# CONFIG_SIGMA is not set
1508
1509#
1418# File systems 1510# File systems
1419# 1511#
1420CONFIG_EXT2_FS=y 1512CONFIG_EXT2_FS=y
@@ -1427,9 +1519,11 @@ CONFIG_FS_MBCACHE=y
1427# CONFIG_REISERFS_FS is not set 1519# CONFIG_REISERFS_FS is not set
1428# CONFIG_JFS_FS is not set 1520# CONFIG_JFS_FS is not set
1429# CONFIG_FS_POSIX_ACL is not set 1521# CONFIG_FS_POSIX_ACL is not set
1430CONFIG_FILE_LOCKING=y
1431# CONFIG_XFS_FS is not set 1522# CONFIG_XFS_FS is not set
1432# CONFIG_OCFS2_FS is not set 1523# CONFIG_OCFS2_FS is not set
1524# CONFIG_BTRFS_FS is not set
1525CONFIG_FILE_LOCKING=y
1526CONFIG_FSNOTIFY=y
1433# CONFIG_DNOTIFY is not set 1527# CONFIG_DNOTIFY is not set
1434CONFIG_INOTIFY=y 1528CONFIG_INOTIFY=y
1435CONFIG_INOTIFY_USER=y 1529CONFIG_INOTIFY_USER=y
@@ -1439,6 +1533,11 @@ CONFIG_INOTIFY_USER=y
1439# CONFIG_FUSE_FS is not set 1533# CONFIG_FUSE_FS is not set
1440 1534
1441# 1535#
1536# Caches
1537#
1538# CONFIG_FSCACHE is not set
1539
1540#
1442# CD-ROM/DVD Filesystems 1541# CD-ROM/DVD Filesystems
1443# 1542#
1444CONFIG_ISO9660_FS=m 1543CONFIG_ISO9660_FS=m
@@ -1467,10 +1566,7 @@ CONFIG_SYSFS=y
1467# CONFIG_TMPFS is not set 1566# CONFIG_TMPFS is not set
1468# CONFIG_HUGETLB_PAGE is not set 1567# CONFIG_HUGETLB_PAGE is not set
1469# CONFIG_CONFIGFS_FS is not set 1568# CONFIG_CONFIGFS_FS is not set
1470 1569CONFIG_MISC_FILESYSTEMS=y
1471#
1472# Miscellaneous filesystems
1473#
1474# CONFIG_ADFS_FS is not set 1570# CONFIG_ADFS_FS is not set
1475# CONFIG_AFFS_FS is not set 1571# CONFIG_AFFS_FS is not set
1476# CONFIG_HFS_FS is not set 1572# CONFIG_HFS_FS is not set
@@ -1489,17 +1585,8 @@ CONFIG_JFFS2_ZLIB=y
1489# CONFIG_JFFS2_LZO is not set 1585# CONFIG_JFFS2_LZO is not set
1490CONFIG_JFFS2_RTIME=y 1586CONFIG_JFFS2_RTIME=y
1491# CONFIG_JFFS2_RUBIN is not set 1587# CONFIG_JFFS2_RUBIN is not set
1492CONFIG_YAFFS_FS=m
1493CONFIG_YAFFS_YAFFS1=y
1494# CONFIG_YAFFS_9BYTE_TAGS is not set
1495# CONFIG_YAFFS_DOES_ECC is not set
1496CONFIG_YAFFS_YAFFS2=y
1497CONFIG_YAFFS_AUTO_YAFFS2=y
1498# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
1499# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
1500# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
1501CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
1502# CONFIG_CRAMFS is not set 1588# CONFIG_CRAMFS is not set
1589# CONFIG_SQUASHFS is not set
1503# CONFIG_VXFS_FS is not set 1590# CONFIG_VXFS_FS is not set
1504# CONFIG_MINIX_FS is not set 1591# CONFIG_MINIX_FS is not set
1505# CONFIG_OMFS_FS is not set 1592# CONFIG_OMFS_FS is not set
@@ -1508,6 +1595,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
1508# CONFIG_ROMFS_FS is not set 1595# CONFIG_ROMFS_FS is not set
1509# CONFIG_SYSV_FS is not set 1596# CONFIG_SYSV_FS is not set
1510# CONFIG_UFS_FS is not set 1597# CONFIG_UFS_FS is not set
1598# CONFIG_NILFS2_FS is not set
1511CONFIG_NETWORK_FILESYSTEMS=y 1599CONFIG_NETWORK_FILESYSTEMS=y
1512CONFIG_NFS_FS=m 1600CONFIG_NFS_FS=m
1513CONFIG_NFS_V3=y 1601CONFIG_NFS_V3=y
@@ -1522,7 +1610,6 @@ CONFIG_LOCKD_V4=y
1522CONFIG_EXPORTFS=m 1610CONFIG_EXPORTFS=m
1523CONFIG_NFS_COMMON=y 1611CONFIG_NFS_COMMON=y
1524CONFIG_SUNRPC=m 1612CONFIG_SUNRPC=m
1525# CONFIG_SUNRPC_REGISTER_V4 is not set
1526# CONFIG_RPCSEC_GSS_KRB5 is not set 1613# CONFIG_RPCSEC_GSS_KRB5 is not set
1527# CONFIG_RPCSEC_GSS_SPKM3 is not set 1614# CONFIG_RPCSEC_GSS_SPKM3 is not set
1528CONFIG_SMB_FS=m 1615CONFIG_SMB_FS=m
@@ -1596,11 +1683,15 @@ CONFIG_FRAME_WARN=1024
1596# CONFIG_UNUSED_SYMBOLS is not set 1683# CONFIG_UNUSED_SYMBOLS is not set
1597CONFIG_DEBUG_FS=y 1684CONFIG_DEBUG_FS=y
1598# CONFIG_HEADERS_CHECK is not set 1685# CONFIG_HEADERS_CHECK is not set
1686CONFIG_DEBUG_SECTION_MISMATCH=y
1599CONFIG_DEBUG_KERNEL=y 1687CONFIG_DEBUG_KERNEL=y
1600CONFIG_DEBUG_SHIRQ=y 1688CONFIG_DEBUG_SHIRQ=y
1601CONFIG_DETECT_SOFTLOCKUP=y 1689CONFIG_DETECT_SOFTLOCKUP=y
1602# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1690# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1603CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1691CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1692CONFIG_DETECT_HUNG_TASK=y
1693# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1694CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1604CONFIG_SCHED_DEBUG=y 1695CONFIG_SCHED_DEBUG=y
1605# CONFIG_SCHEDSTATS is not set 1696# CONFIG_SCHEDSTATS is not set
1606# CONFIG_TIMER_STATS is not set 1697# CONFIG_TIMER_STATS is not set
@@ -1608,16 +1699,21 @@ CONFIG_SCHED_DEBUG=y
1608# CONFIG_DEBUG_SLAB is not set 1699# CONFIG_DEBUG_SLAB is not set
1609# CONFIG_DEBUG_SPINLOCK is not set 1700# CONFIG_DEBUG_SPINLOCK is not set
1610# CONFIG_DEBUG_MUTEXES is not set 1701# CONFIG_DEBUG_MUTEXES is not set
1702# CONFIG_DEBUG_LOCK_ALLOC is not set
1703# CONFIG_PROVE_LOCKING is not set
1704# CONFIG_LOCK_STAT is not set
1611# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1705# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1612# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1706# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1613# CONFIG_DEBUG_KOBJECT is not set 1707# CONFIG_DEBUG_KOBJECT is not set
1614CONFIG_DEBUG_BUGVERBOSE=y 1708CONFIG_DEBUG_BUGVERBOSE=y
1615CONFIG_DEBUG_INFO=y 1709CONFIG_DEBUG_INFO=y
1616# CONFIG_DEBUG_VM is not set 1710# CONFIG_DEBUG_VM is not set
1711# CONFIG_DEBUG_NOMMU_REGIONS is not set
1617# CONFIG_DEBUG_WRITECOUNT is not set 1712# CONFIG_DEBUG_WRITECOUNT is not set
1618# CONFIG_DEBUG_MEMORY_INIT is not set 1713# CONFIG_DEBUG_MEMORY_INIT is not set
1619# CONFIG_DEBUG_LIST is not set 1714# CONFIG_DEBUG_LIST is not set
1620# CONFIG_DEBUG_SG is not set 1715# CONFIG_DEBUG_SG is not set
1716# CONFIG_DEBUG_NOTIFIERS is not set
1621# CONFIG_FRAME_POINTER is not set 1717# CONFIG_FRAME_POINTER is not set
1622# CONFIG_BOOT_PRINTK_DELAY is not set 1718# CONFIG_BOOT_PRINTK_DELAY is not set
1623# CONFIG_RCU_TORTURE_TEST is not set 1719# CONFIG_RCU_TORTURE_TEST is not set
@@ -1625,17 +1721,16 @@ CONFIG_DEBUG_INFO=y
1625# CONFIG_BACKTRACE_SELF_TEST is not set 1721# CONFIG_BACKTRACE_SELF_TEST is not set
1626# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1722# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1627# CONFIG_FAULT_INJECTION is not set 1723# CONFIG_FAULT_INJECTION is not set
1628 1724# CONFIG_PAGE_POISONING is not set
1629# 1725CONFIG_HAVE_FUNCTION_TRACER=y
1630# Tracers 1726CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1631# 1727CONFIG_TRACING_SUPPORT=y
1632# CONFIG_SCHED_TRACER is not set 1728# CONFIG_FTRACE is not set
1633# CONFIG_CONTEXT_SWITCH_TRACER is not set 1729# CONFIG_DYNAMIC_DEBUG is not set
1634# CONFIG_BOOT_TRACER is not set
1635# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1636# CONFIG_SAMPLES is not set 1730# CONFIG_SAMPLES is not set
1637CONFIG_HAVE_ARCH_KGDB=y 1731CONFIG_HAVE_ARCH_KGDB=y
1638# CONFIG_KGDB is not set 1732# CONFIG_KGDB is not set
1733# CONFIG_KMEMCHECK is not set
1639# CONFIG_DEBUG_STACKOVERFLOW is not set 1734# CONFIG_DEBUG_STACKOVERFLOW is not set
1640# CONFIG_DEBUG_STACK_USAGE is not set 1735# CONFIG_DEBUG_STACK_USAGE is not set
1641CONFIG_DEBUG_VERBOSE=y 1736CONFIG_DEBUG_VERBOSE=y
@@ -1657,17 +1752,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
1657CONFIG_EARLY_PRINTK=y 1752CONFIG_EARLY_PRINTK=y
1658CONFIG_CPLB_INFO=y 1753CONFIG_CPLB_INFO=y
1659CONFIG_ACCESS_CHECK=y 1754CONFIG_ACCESS_CHECK=y
1755# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1660 1756
1661# 1757#
1662# Security options 1758# Security options
1663# 1759#
1664# CONFIG_KEYS is not set 1760# CONFIG_KEYS is not set
1665CONFIG_SECURITY=y 1761# CONFIG_SECURITY is not set
1666# CONFIG_SECURITYFS is not set 1762# CONFIG_SECURITYFS is not set
1667# CONFIG_SECURITY_NETWORK is not set
1668# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1763# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1669# CONFIG_SECURITY_ROOTPLUG is not set
1670CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1671CONFIG_CRYPTO=y 1764CONFIG_CRYPTO=y
1672 1765
1673# 1766#
@@ -1746,6 +1839,7 @@ CONFIG_CRYPTO=y
1746# Compression 1839# Compression
1747# 1840#
1748# CONFIG_CRYPTO_DEFLATE is not set 1841# CONFIG_CRYPTO_DEFLATE is not set
1842# CONFIG_CRYPTO_ZLIB is not set
1749# CONFIG_CRYPTO_LZO is not set 1843# CONFIG_CRYPTO_LZO is not set
1750 1844
1751# 1845#
@@ -1753,11 +1847,13 @@ CONFIG_CRYPTO=y
1753# 1847#
1754# CONFIG_CRYPTO_ANSI_CPRNG is not set 1848# CONFIG_CRYPTO_ANSI_CPRNG is not set
1755CONFIG_CRYPTO_HW=y 1849CONFIG_CRYPTO_HW=y
1850# CONFIG_BINARY_PRINTF is not set
1756 1851
1757# 1852#
1758# Library routines 1853# Library routines
1759# 1854#
1760CONFIG_BITREVERSE=y 1855CONFIG_BITREVERSE=y
1856CONFIG_GENERIC_FIND_LAST_BIT=y
1761CONFIG_CRC_CCITT=m 1857CONFIG_CRC_CCITT=m
1762# CONFIG_CRC16 is not set 1858# CONFIG_CRC16 is not set
1763# CONFIG_CRC_T10DIF is not set 1859# CONFIG_CRC_T10DIF is not set
@@ -1767,6 +1863,8 @@ CONFIG_CRC32=y
1767# CONFIG_LIBCRC32C is not set 1863# CONFIG_LIBCRC32C is not set
1768CONFIG_ZLIB_INFLATE=y 1864CONFIG_ZLIB_INFLATE=y
1769CONFIG_ZLIB_DEFLATE=m 1865CONFIG_ZLIB_DEFLATE=m
1866CONFIG_DECOMPRESS_GZIP=y
1770CONFIG_HAS_IOMEM=y 1867CONFIG_HAS_IOMEM=y
1771CONFIG_HAS_IOPORT=y 1868CONFIG_HAS_IOPORT=y
1772CONFIG_HAS_DMA=y 1869CONFIG_HAS_DMA=y
1870CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
new file mode 100644
index 000000000000..b9b0f93d0bd3
--- /dev/null
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -0,0 +1,1643 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31.4
4# Sat Oct 24 12:15:32 2009
5#
6# CONFIG_MMU is not set
7# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y
11CONFIG_GENERIC_CSUM=y
12CONFIG_GENERIC_BUG=y
13CONFIG_ZONE_DMA=y
14CONFIG_GENERIC_FIND_NEXT_BIT=y
15CONFIG_GENERIC_HWEIGHT=y
16CONFIG_GENERIC_HARDIRQS=y
17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
19CONFIG_GENERIC_GPIO=y
20CONFIG_FORCE_MAX_ZONEORDER=14
21CONFIG_GENERIC_CALIBRATE_DELAY=y
22CONFIG_LOCKDEP_SUPPORT=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_TRACE_IRQFLAGS_SUPPORT=y
25CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
26CONFIG_CONSTRUCTORS=y
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_HAVE_KERNEL_GZIP=y
37CONFIG_HAVE_KERNEL_BZIP2=y
38CONFIG_HAVE_KERNEL_LZMA=y
39CONFIG_KERNEL_GZIP=y
40# CONFIG_KERNEL_BZIP2 is not set
41# CONFIG_KERNEL_LZMA is not set
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_AUDIT is not set
48
49#
50# RCU Subsystem
51#
52CONFIG_CLASSIC_RCU=y
53# CONFIG_TREE_RCU is not set
54# CONFIG_PREEMPT_RCU is not set
55# CONFIG_TREE_RCU_TRACE is not set
56# CONFIG_PREEMPT_RCU_TRACE is not set
57CONFIG_IKCONFIG=y
58CONFIG_IKCONFIG_PROC=y
59CONFIG_LOG_BUF_SHIFT=14
60# CONFIG_GROUP_SCHED is not set
61# CONFIG_CGROUPS is not set
62CONFIG_SYSFS_DEPRECATED=y
63CONFIG_SYSFS_DEPRECATED_V2=y
64# CONFIG_RELAY is not set
65# CONFIG_NAMESPACES is not set
66# CONFIG_BLK_DEV_INITRD is not set
67# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
68CONFIG_SYSCTL=y
69CONFIG_ANON_INODES=y
70CONFIG_EMBEDDED=y
71CONFIG_UID16=y
72# CONFIG_SYSCTL_SYSCALL is not set
73CONFIG_KALLSYMS=y
74# CONFIG_KALLSYMS_ALL is not set
75# CONFIG_KALLSYMS_EXTRA_PASS is not set
76CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y
78CONFIG_BUG=y
79# CONFIG_ELF_CORE is not set
80CONFIG_BASE_FULL=y
81# CONFIG_FUTEX is not set
82CONFIG_EPOLL=y
83# CONFIG_SIGNALFD is not set
84# CONFIG_TIMERFD is not set
85# CONFIG_EVENTFD is not set
86# CONFIG_AIO is not set
87
88#
89# Performance Counters
90#
91CONFIG_VM_EVENT_COUNTERS=y
92# CONFIG_STRIP_ASM_SYMS is not set
93CONFIG_COMPAT_BRK=y
94CONFIG_SLAB=y
95# CONFIG_SLUB is not set
96# CONFIG_SLOB is not set
97# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set
98# CONFIG_PROFILING is not set
99# CONFIG_MARKERS is not set
100CONFIG_HAVE_OPROFILE=y
101
102#
103# GCOV-based kernel profiling
104#
105# CONFIG_GCOV_KERNEL is not set
106# CONFIG_SLOW_WORK is not set
107# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
108CONFIG_SLABINFO=y
109CONFIG_BASE_SMALL=0
110CONFIG_MODULES=y
111# CONFIG_MODULE_FORCE_LOAD is not set
112CONFIG_MODULE_UNLOAD=y
113# CONFIG_MODULE_FORCE_UNLOAD is not set
114# CONFIG_MODVERSIONS is not set
115# CONFIG_MODULE_SRCVERSION_ALL is not set
116CONFIG_BLOCK=y
117CONFIG_LBDAF=y
118# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set
120
121#
122# IO Schedulers
123#
124CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126# CONFIG_IOSCHED_DEADLINE is not set
127CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory"
133# CONFIG_PREEMPT_NONE is not set
134CONFIG_PREEMPT_VOLUNTARY=y
135# CONFIG_PREEMPT is not set
136# CONFIG_FREEZER is not set
137
138#
139# Blackfin Processor Options
140#
141
142#
143# Processor and Board Settings
144#
145# CONFIG_BF512 is not set
146# CONFIG_BF514 is not set
147# CONFIG_BF516 is not set
148# CONFIG_BF518 is not set
149# CONFIG_BF522 is not set
150# CONFIG_BF523 is not set
151# CONFIG_BF524 is not set
152# CONFIG_BF525 is not set
153# CONFIG_BF526 is not set
154# CONFIG_BF527 is not set
155# CONFIG_BF531 is not set
156# CONFIG_BF532 is not set
157# CONFIG_BF533 is not set
158# CONFIG_BF534 is not set
159# CONFIG_BF536 is not set
160# CONFIG_BF537 is not set
161# CONFIG_BF538 is not set
162# CONFIG_BF539 is not set
163# CONFIG_BF542 is not set
164# CONFIG_BF542M is not set
165# CONFIG_BF544 is not set
166# CONFIG_BF544M is not set
167# CONFIG_BF547 is not set
168# CONFIG_BF547M is not set
169# CONFIG_BF548 is not set
170# CONFIG_BF548M is not set
171# CONFIG_BF549 is not set
172# CONFIG_BF549M is not set
173CONFIG_BF561=y
174# CONFIG_SMP is not set
175CONFIG_BF_REV_MIN=3
176CONFIG_BF_REV_MAX=5
177# CONFIG_BF_REV_0_0 is not set
178# CONFIG_BF_REV_0_1 is not set
179# CONFIG_BF_REV_0_2 is not set
180# CONFIG_BF_REV_0_3 is not set
181# CONFIG_BF_REV_0_4 is not set
182CONFIG_BF_REV_0_5=y
183# CONFIG_BF_REV_0_6 is not set
184# CONFIG_BF_REV_ANY is not set
185# CONFIG_BF_REV_NONE is not set
186CONFIG_IRQ_PLL_WAKEUP=7
187CONFIG_IRQ_SPORT0_ERROR=7
188CONFIG_IRQ_SPORT1_ERROR=7
189CONFIG_IRQ_TIMER0=10
190CONFIG_IRQ_TIMER1=10
191CONFIG_IRQ_TIMER2=10
192CONFIG_IRQ_TIMER3=10
193CONFIG_IRQ_TIMER4=10
194CONFIG_IRQ_TIMER5=10
195CONFIG_IRQ_TIMER6=10
196CONFIG_IRQ_TIMER7=10
197CONFIG_IRQ_SPI_ERROR=7
198# CONFIG_BFIN561_EZKIT is not set
199# CONFIG_BFIN561_TEPLA is not set
200# CONFIG_BFIN561_BLUETECHNIX_CM is not set
201CONFIG_BFIN561_ACVILON=y
202
203#
204# BF561 Specific Configuration
205#
206
207#
208# Core B Support
209#
210# CONFIG_BF561_COREB is not set
211
212#
213# Interrupt Priority Assignment
214#
215
216#
217# Priority
218#
219CONFIG_IRQ_DMA1_ERROR=7
220CONFIG_IRQ_DMA2_ERROR=7
221CONFIG_IRQ_IMDMA_ERROR=7
222CONFIG_IRQ_PPI0_ERROR=7
223CONFIG_IRQ_PPI1_ERROR=7
224CONFIG_IRQ_UART_ERROR=7
225CONFIG_IRQ_RESERVED_ERROR=7
226CONFIG_IRQ_DMA1_0=8
227CONFIG_IRQ_DMA1_1=8
228CONFIG_IRQ_DMA1_2=8
229CONFIG_IRQ_DMA1_3=8
230CONFIG_IRQ_DMA1_4=8
231CONFIG_IRQ_DMA1_5=8
232CONFIG_IRQ_DMA1_6=8
233CONFIG_IRQ_DMA1_7=8
234CONFIG_IRQ_DMA1_8=8
235CONFIG_IRQ_DMA1_9=8
236CONFIG_IRQ_DMA1_10=8
237CONFIG_IRQ_DMA1_11=8
238CONFIG_IRQ_DMA2_0=9
239CONFIG_IRQ_DMA2_1=9
240CONFIG_IRQ_DMA2_2=9
241CONFIG_IRQ_DMA2_3=9
242CONFIG_IRQ_DMA2_4=9
243CONFIG_IRQ_DMA2_5=9
244CONFIG_IRQ_DMA2_6=9
245CONFIG_IRQ_DMA2_7=9
246CONFIG_IRQ_DMA2_8=9
247CONFIG_IRQ_DMA2_9=9
248CONFIG_IRQ_DMA2_10=9
249CONFIG_IRQ_DMA2_11=9
250CONFIG_IRQ_TIMER8=10
251CONFIG_IRQ_TIMER9=10
252CONFIG_IRQ_TIMER10=10
253CONFIG_IRQ_TIMER11=10
254CONFIG_IRQ_PROG0_INTA=11
255CONFIG_IRQ_PROG0_INTB=11
256CONFIG_IRQ_PROG1_INTA=11
257CONFIG_IRQ_PROG1_INTB=11
258CONFIG_IRQ_PROG2_INTA=11
259CONFIG_IRQ_PROG2_INTB=11
260CONFIG_IRQ_DMA1_WRRD0=8
261CONFIG_IRQ_DMA1_WRRD1=8
262CONFIG_IRQ_DMA2_WRRD0=9
263CONFIG_IRQ_DMA2_WRRD1=9
264CONFIG_IRQ_IMDMA_WRRD0=12
265CONFIG_IRQ_IMDMA_WRRD1=12
266CONFIG_IRQ_WDTIMER=13
267
268#
269# Board customizations
270#
271# CONFIG_CMDLINE_BOOL is not set
272CONFIG_BOOT_LOAD=0x1000
273
274#
275# Clock/PLL Setup
276#
277CONFIG_CLKIN_HZ=12000000
278# CONFIG_BFIN_KERNEL_CLOCK is not set
279CONFIG_MAX_VCO_HZ=600000000
280CONFIG_MIN_VCO_HZ=50000000
281CONFIG_MAX_SCLK_HZ=133333333
282CONFIG_MIN_SCLK_HZ=27000000
283
284#
285# Kernel Timer/Scheduler
286#
287# CONFIG_HZ_100 is not set
288CONFIG_HZ_250=y
289# CONFIG_HZ_300 is not set
290# CONFIG_HZ_1000 is not set
291CONFIG_HZ=250
292CONFIG_SCHED_HRTICK=y
293CONFIG_GENERIC_TIME=y
294CONFIG_GENERIC_CLOCKEVENTS=y
295# CONFIG_TICKSOURCE_GPTMR0 is not set
296CONFIG_TICKSOURCE_CORETMR=y
297CONFIG_CYCLES_CLOCKSOURCE=y
298# CONFIG_GPTMR0_CLOCKSOURCE is not set
299CONFIG_TICK_ONESHOT=y
300# CONFIG_NO_HZ is not set
301CONFIG_HIGH_RES_TIMERS=y
302CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
303
304#
305# Misc
306#
307CONFIG_BFIN_SCRATCH_REG_RETN=y
308# CONFIG_BFIN_SCRATCH_REG_RETE is not set
309# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
310
311#
312# Blackfin Kernel Optimizations
313#
314
315#
316# Memory Optimizations
317#
318CONFIG_I_ENTRY_L1=y
319CONFIG_EXCPT_IRQ_SYSC_L1=y
320CONFIG_DO_IRQ_L1=y
321CONFIG_CORE_TIMER_IRQ_L1=y
322CONFIG_IDLE_L1=y
323CONFIG_SCHEDULE_L1=y
324CONFIG_ARITHMETIC_OPS_L1=y
325CONFIG_ACCESS_OK_L1=y
326CONFIG_MEMSET_L1=y
327CONFIG_MEMCPY_L1=y
328CONFIG_SYS_BFIN_SPINLOCK_L1=y
329# CONFIG_IP_CHECKSUM_L1 is not set
330CONFIG_CACHELINE_ALIGNED_L1=y
331# CONFIG_SYSCALL_TAB_L1 is not set
332# CONFIG_CPLB_SWITCH_TAB_L1 is not set
333CONFIG_APP_STACK_L1=y
334
335#
336# Speed Optimizations
337#
338CONFIG_BFIN_INS_LOWOVERHEAD=y
339CONFIG_RAMKERNEL=y
340# CONFIG_ROMKERNEL is not set
341CONFIG_SELECT_MEMORY_MODEL=y
342CONFIG_FLATMEM_MANUAL=y
343# CONFIG_DISCONTIGMEM_MANUAL is not set
344# CONFIG_SPARSEMEM_MANUAL is not set
345CONFIG_FLATMEM=y
346CONFIG_FLAT_NODE_MEM_MAP=y
347CONFIG_PAGEFLAGS_EXTENDED=y
348CONFIG_SPLIT_PTLOCK_CPUS=4
349# CONFIG_PHYS_ADDR_T_64BIT is not set
350CONFIG_ZONE_DMA_FLAG=1
351CONFIG_VIRT_TO_BUS=y
352CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
353CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
354CONFIG_BFIN_GPTIMERS=y
355CONFIG_DMA_UNCACHED_4M=y
356# CONFIG_DMA_UNCACHED_2M is not set
357# CONFIG_DMA_UNCACHED_1M is not set
358# CONFIG_DMA_UNCACHED_NONE is not set
359
360#
361# Cache Support
362#
363CONFIG_BFIN_ICACHE=y
364CONFIG_BFIN_EXTMEM_ICACHEABLE=y
365# CONFIG_BFIN_L2_ICACHEABLE is not set
366CONFIG_BFIN_DCACHE=y
367# CONFIG_BFIN_DCACHE_BANKA is not set
368CONFIG_BFIN_EXTMEM_DCACHEABLE=y
369CONFIG_BFIN_EXTMEM_WRITEBACK=y
370# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
371# CONFIG_BFIN_L2_DCACHEABLE is not set
372
373#
374# Memory Protection Unit
375#
376# CONFIG_MPU is not set
377
378#
379# Asynchronous Memory Configuration
380#
381
382#
383# EBIU_AMGCTL Global Control
384#
385CONFIG_C_AMCKEN=y
386CONFIG_C_CDPRIO=y
387CONFIG_C_B0PEN=y
388CONFIG_C_B1PEN=y
389CONFIG_C_B2PEN=y
390# CONFIG_C_B3PEN is not set
391# CONFIG_C_AMBEN is not set
392# CONFIG_C_AMBEN_B0 is not set
393# CONFIG_C_AMBEN_B0_B1 is not set
394# CONFIG_C_AMBEN_B0_B1_B2 is not set
395CONFIG_C_AMBEN_ALL=y
396
397#
398# EBIU_AMBCTL Control
399#
400CONFIG_BANK_0=0x99b2
401CONFIG_BANK_1=0x3350
402CONFIG_BANK_2=0x7BB0
403CONFIG_BANK_3=0xAAC2
404
405#
406# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
407#
408# CONFIG_ARCH_SUPPORTS_MSI is not set
409# CONFIG_PCCARD is not set
410
411#
412# Executable file formats
413#
414CONFIG_BINFMT_ELF_FDPIC=y
415CONFIG_BINFMT_FLAT=y
416CONFIG_BINFMT_ZFLAT=y
417# CONFIG_BINFMT_SHARED_FLAT is not set
418# CONFIG_HAVE_AOUT is not set
419# CONFIG_BINFMT_MISC is not set
420
421#
422# Power management options
423#
424# CONFIG_PM is not set
425CONFIG_ARCH_SUSPEND_POSSIBLE=y
426
427#
428# CPU Frequency scaling
429#
430# CONFIG_CPU_FREQ is not set
431CONFIG_NET=y
432
433#
434# Networking options
435#
436CONFIG_PACKET=y
437# CONFIG_PACKET_MMAP is not set
438CONFIG_UNIX=y
439CONFIG_XFRM=y
440# CONFIG_XFRM_USER is not set
441# CONFIG_XFRM_SUB_POLICY is not set
442# CONFIG_XFRM_MIGRATE is not set
443# CONFIG_XFRM_STATISTICS is not set
444# CONFIG_NET_KEY is not set
445CONFIG_INET=y
446# CONFIG_IP_MULTICAST is not set
447# CONFIG_IP_ADVANCED_ROUTER is not set
448CONFIG_IP_FIB_HASH=y
449CONFIG_IP_PNP=y
450# CONFIG_IP_PNP_DHCP is not set
451# CONFIG_IP_PNP_BOOTP is not set
452# CONFIG_IP_PNP_RARP is not set
453# CONFIG_NET_IPIP is not set
454# CONFIG_NET_IPGRE is not set
455# CONFIG_ARPD is not set
456CONFIG_SYN_COOKIES=y
457# CONFIG_INET_AH is not set
458# CONFIG_INET_ESP is not set
459# CONFIG_INET_IPCOMP is not set
460# CONFIG_INET_XFRM_TUNNEL is not set
461# CONFIG_INET_TUNNEL is not set
462CONFIG_INET_XFRM_MODE_TRANSPORT=y
463CONFIG_INET_XFRM_MODE_TUNNEL=y
464CONFIG_INET_XFRM_MODE_BEET=y
465# CONFIG_INET_LRO is not set
466CONFIG_INET_DIAG=y
467CONFIG_INET_TCP_DIAG=y
468# CONFIG_TCP_CONG_ADVANCED is not set
469CONFIG_TCP_CONG_CUBIC=y
470CONFIG_DEFAULT_TCP_CONG="cubic"
471# CONFIG_TCP_MD5SIG is not set
472# CONFIG_IPV6 is not set
473# CONFIG_NETLABEL is not set
474# CONFIG_NETWORK_SECMARK is not set
475# CONFIG_NETFILTER is not set
476# CONFIG_IP_DCCP is not set
477# CONFIG_IP_SCTP is not set
478# CONFIG_TIPC is not set
479# CONFIG_ATM is not set
480# CONFIG_BRIDGE is not set
481# CONFIG_NET_DSA is not set
482# CONFIG_VLAN_8021Q is not set
483# CONFIG_DECNET is not set
484# CONFIG_LLC2 is not set
485# CONFIG_IPX is not set
486# CONFIG_ATALK is not set
487# CONFIG_X25 is not set
488# CONFIG_LAPB is not set
489# CONFIG_ECONET is not set
490# CONFIG_WAN_ROUTER is not set
491# CONFIG_PHONET is not set
492# CONFIG_IEEE802154 is not set
493# CONFIG_NET_SCHED is not set
494# CONFIG_DCB is not set
495
496#
497# Network testing
498#
499# CONFIG_NET_PKTGEN is not set
500# CONFIG_HAMRADIO is not set
501# CONFIG_CAN is not set
502# CONFIG_IRDA is not set
503# CONFIG_BT is not set
504# CONFIG_AF_RXRPC is not set
505# CONFIG_WIRELESS is not set
506# CONFIG_WIMAX is not set
507# CONFIG_RFKILL is not set
508# CONFIG_NET_9P is not set
509
510#
511# Device Drivers
512#
513
514#
515# Generic Driver Options
516#
517CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
518CONFIG_STANDALONE=y
519CONFIG_PREVENT_FIRMWARE_BUILD=y
520# CONFIG_FW_LOADER is not set
521# CONFIG_DEBUG_DRIVER is not set
522# CONFIG_DEBUG_DEVRES is not set
523# CONFIG_SYS_HYPERVISOR is not set
524# CONFIG_CONNECTOR is not set
525CONFIG_MTD=y
526# CONFIG_MTD_DEBUG is not set
527# CONFIG_MTD_TESTS is not set
528# CONFIG_MTD_CONCAT is not set
529CONFIG_MTD_PARTITIONS=y
530# CONFIG_MTD_REDBOOT_PARTS is not set
531CONFIG_MTD_CMDLINE_PARTS=y
532# CONFIG_MTD_AR7_PARTS is not set
533
534#
535# User Modules And Translation Layers
536#
537CONFIG_MTD_CHAR=y
538CONFIG_MTD_BLKDEVS=y
539CONFIG_MTD_BLOCK=y
540# CONFIG_FTL is not set
541# CONFIG_NFTL is not set
542# CONFIG_INFTL is not set
543# CONFIG_RFD_FTL is not set
544# CONFIG_SSFDC is not set
545# CONFIG_MTD_OOPS is not set
546
547#
548# RAM/ROM/Flash chip drivers
549#
550# CONFIG_MTD_CFI is not set
551# CONFIG_MTD_JEDECPROBE is not set
552CONFIG_MTD_MAP_BANK_WIDTH_1=y
553CONFIG_MTD_MAP_BANK_WIDTH_2=y
554CONFIG_MTD_MAP_BANK_WIDTH_4=y
555# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
556# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
557# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
558CONFIG_MTD_CFI_I1=y
559CONFIG_MTD_CFI_I2=y
560# CONFIG_MTD_CFI_I4 is not set
561# CONFIG_MTD_CFI_I8 is not set
562CONFIG_MTD_RAM=y
563# CONFIG_MTD_ROM is not set
564# CONFIG_MTD_ABSENT is not set
565
566#
567# Mapping drivers for chip access
568#
569# CONFIG_MTD_COMPLEX_MAPPINGS is not set
570# CONFIG_MTD_UCLINUX is not set
571CONFIG_MTD_PLATRAM=y
572
573#
574# Self-contained MTD device drivers
575#
576# CONFIG_MTD_DATAFLASH is not set
577# CONFIG_MTD_M25P80 is not set
578# CONFIG_MTD_SLRAM is not set
579CONFIG_MTD_PHRAM=y
580# CONFIG_MTD_MTDRAM is not set
581CONFIG_MTD_BLOCK2MTD=y
582
583#
584# Disk-On-Chip Device Drivers
585#
586# CONFIG_MTD_DOC2000 is not set
587# CONFIG_MTD_DOC2001 is not set
588# CONFIG_MTD_DOC2001PLUS is not set
589CONFIG_MTD_NAND=y
590CONFIG_MTD_NAND_VERIFY_WRITE=y
591# CONFIG_MTD_NAND_ECC_SMC is not set
592# CONFIG_MTD_NAND_MUSEUM_IDS is not set
593CONFIG_MTD_NAND_IDS=y
594# CONFIG_MTD_NAND_DISKONCHIP is not set
595# CONFIG_MTD_NAND_NANDSIM is not set
596CONFIG_MTD_NAND_PLATFORM=y
597# CONFIG_MTD_ALAUDA is not set
598# CONFIG_MTD_ONENAND is not set
599
600#
601# LPDDR flash memory drivers
602#
603# CONFIG_MTD_LPDDR is not set
604
605#
606# UBI - Unsorted block images
607#
608# CONFIG_MTD_UBI is not set
609# CONFIG_PARPORT is not set
610CONFIG_BLK_DEV=y
611# CONFIG_BLK_DEV_COW_COMMON is not set
612CONFIG_BLK_DEV_LOOP=y
613# CONFIG_BLK_DEV_CRYPTOLOOP is not set
614# CONFIG_BLK_DEV_NBD is not set
615# CONFIG_BLK_DEV_UB is not set
616CONFIG_BLK_DEV_RAM=y
617CONFIG_BLK_DEV_RAM_COUNT=2
618CONFIG_BLK_DEV_RAM_SIZE=16384
619# CONFIG_BLK_DEV_XIP is not set
620# CONFIG_CDROM_PKTCDVD is not set
621# CONFIG_ATA_OVER_ETH is not set
622# CONFIG_BLK_DEV_HD is not set
623# CONFIG_MISC_DEVICES is not set
624CONFIG_HAVE_IDE=y
625# CONFIG_IDE is not set
626
627#
628# SCSI device support
629#
630# CONFIG_RAID_ATTRS is not set
631CONFIG_SCSI=y
632CONFIG_SCSI_DMA=y
633# CONFIG_SCSI_TGT is not set
634# CONFIG_SCSI_NETLINK is not set
635# CONFIG_SCSI_PROC_FS is not set
636
637#
638# SCSI support type (disk, tape, CD-ROM)
639#
640CONFIG_BLK_DEV_SD=y
641# CONFIG_CHR_DEV_ST is not set
642# CONFIG_CHR_DEV_OSST is not set
643# CONFIG_BLK_DEV_SR is not set
644# CONFIG_CHR_DEV_SG is not set
645# CONFIG_CHR_DEV_SCH is not set
646# CONFIG_SCSI_MULTI_LUN is not set
647# CONFIG_SCSI_CONSTANTS is not set
648# CONFIG_SCSI_LOGGING is not set
649# CONFIG_SCSI_SCAN_ASYNC is not set
650CONFIG_SCSI_WAIT_SCAN=y
651
652#
653# SCSI Transports
654#
655# CONFIG_SCSI_SPI_ATTRS is not set
656# CONFIG_SCSI_FC_ATTRS is not set
657# CONFIG_SCSI_ISCSI_ATTRS is not set
658# CONFIG_SCSI_SAS_LIBSAS is not set
659# CONFIG_SCSI_SRP_ATTRS is not set
660# CONFIG_SCSI_LOWLEVEL is not set
661# CONFIG_SCSI_DH is not set
662# CONFIG_SCSI_OSD_INITIATOR is not set
663# CONFIG_ATA is not set
664# CONFIG_MD is not set
665CONFIG_NETDEVICES=y
666# CONFIG_DUMMY is not set
667# CONFIG_BONDING is not set
668# CONFIG_MACVLAN is not set
669# CONFIG_EQUALIZER is not set
670# CONFIG_TUN is not set
671# CONFIG_VETH is not set
672CONFIG_PHYLIB=y
673
674#
675# MII PHY device drivers
676#
677# CONFIG_MARVELL_PHY is not set
678# CONFIG_DAVICOM_PHY is not set
679# CONFIG_QSEMI_PHY is not set
680# CONFIG_LXT_PHY is not set
681# CONFIG_CICADA_PHY is not set
682# CONFIG_VITESSE_PHY is not set
683# CONFIG_SMSC_PHY is not set
684# CONFIG_BROADCOM_PHY is not set
685# CONFIG_ICPLUS_PHY is not set
686# CONFIG_REALTEK_PHY is not set
687# CONFIG_NATIONAL_PHY is not set
688# CONFIG_STE10XP is not set
689# CONFIG_LSI_ET1011C_PHY is not set
690# CONFIG_FIXED_PHY is not set
691# CONFIG_MDIO_BITBANG is not set
692CONFIG_NET_ETHERNET=y
693CONFIG_MII=y
694# CONFIG_SMC91X is not set
695# CONFIG_DM9000 is not set
696# CONFIG_ENC28J60 is not set
697# CONFIG_ETHOC is not set
698CONFIG_SMSC911X=y
699# CONFIG_DNET is not set
700# CONFIG_IBM_NEW_EMAC_ZMII is not set
701# CONFIG_IBM_NEW_EMAC_RGMII is not set
702# CONFIG_IBM_NEW_EMAC_TAH is not set
703# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
704# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
705# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
706# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
707# CONFIG_B44 is not set
708# CONFIG_KS8842 is not set
709# CONFIG_KS8851 is not set
710# CONFIG_NETDEV_1000 is not set
711# CONFIG_NETDEV_10000 is not set
712
713#
714# Wireless LAN
715#
716# CONFIG_WLAN_PRE80211 is not set
717# CONFIG_WLAN_80211 is not set
718
719#
720# Enable WiMAX (Networking options) to see the WiMAX drivers
721#
722
723#
724# USB Network Adapters
725#
726# CONFIG_USB_CATC is not set
727# CONFIG_USB_KAWETH is not set
728# CONFIG_USB_PEGASUS is not set
729# CONFIG_USB_RTL8150 is not set
730# CONFIG_USB_USBNET is not set
731# CONFIG_WAN is not set
732# CONFIG_PPP is not set
733# CONFIG_SLIP is not set
734# CONFIG_NETCONSOLE is not set
735# CONFIG_NETPOLL is not set
736# CONFIG_NET_POLL_CONTROLLER is not set
737# CONFIG_ISDN is not set
738# CONFIG_PHONE is not set
739
740#
741# Input device support
742#
743# CONFIG_INPUT is not set
744
745#
746# Hardware I/O ports
747#
748# CONFIG_SERIO is not set
749# CONFIG_GAMEPORT is not set
750
751#
752# Character devices
753#
754# CONFIG_BFIN_DMA_INTERFACE is not set
755# CONFIG_BFIN_PPI is not set
756# CONFIG_BFIN_PPIFCD is not set
757CONFIG_BFIN_SIMPLE_TIMER=y
758# CONFIG_BFIN_SPI_ADC is not set
759# CONFIG_BFIN_SPORT is not set
760# CONFIG_BFIN_TWI_LCD is not set
761# CONFIG_VT is not set
762# CONFIG_DEVKMEM is not set
763# CONFIG_BFIN_JTAG_COMM is not set
764# CONFIG_SERIAL_NONSTANDARD is not set
765
766#
767# Serial drivers
768#
769# CONFIG_SERIAL_8250 is not set
770
771#
772# Non-8250 serial port support
773#
774# CONFIG_SERIAL_MAX3100 is not set
775CONFIG_SERIAL_BFIN=y
776CONFIG_SERIAL_BFIN_CONSOLE=y
777# CONFIG_SERIAL_BFIN_DMA is not set
778CONFIG_SERIAL_BFIN_PIO=y
779CONFIG_SERIAL_BFIN_UART0=y
780# CONFIG_BFIN_UART0_CTSRTS is not set
781CONFIG_SERIAL_CORE=y
782CONFIG_SERIAL_CORE_CONSOLE=y
783# CONFIG_SERIAL_BFIN_SPORT is not set
784CONFIG_UNIX98_PTYS=y
785# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
786CONFIG_LEGACY_PTYS=y
787CONFIG_LEGACY_PTY_COUNT=256
788
789#
790# CAN, the car bus and industrial fieldbus
791#
792# CONFIG_CAN4LINUX is not set
793# CONFIG_IPMI_HANDLER is not set
794# CONFIG_HW_RANDOM is not set
795# CONFIG_R3964 is not set
796# CONFIG_RAW_DRIVER is not set
797# CONFIG_TCG_TPM is not set
798CONFIG_I2C=y
799CONFIG_I2C_BOARDINFO=y
800CONFIG_I2C_CHARDEV=y
801CONFIG_I2C_HELPER_AUTO=y
802CONFIG_I2C_ALGOPCA=y
803
804#
805# I2C Hardware Bus support
806#
807
808#
809# I2C system bus drivers (mostly embedded / system-on-chip)
810#
811# CONFIG_I2C_GPIO is not set
812# CONFIG_I2C_OCORES is not set
813# CONFIG_I2C_SIMTEC is not set
814
815#
816# External I2C/SMBus adapter drivers
817#
818# CONFIG_I2C_PARPORT_LIGHT is not set
819# CONFIG_I2C_TAOS_EVM is not set
820# CONFIG_I2C_TINY_USB is not set
821
822#
823# Other I2C/SMBus bus drivers
824#
825CONFIG_I2C_PCA_PLATFORM=y
826# CONFIG_I2C_STUB is not set
827
828#
829# Miscellaneous I2C Chip support
830#
831# CONFIG_DS1682 is not set
832# CONFIG_SENSORS_PCA9539 is not set
833# CONFIG_SENSORS_TSL2550 is not set
834# CONFIG_I2C_DEBUG_CORE is not set
835# CONFIG_I2C_DEBUG_ALGO is not set
836# CONFIG_I2C_DEBUG_BUS is not set
837# CONFIG_I2C_DEBUG_CHIP is not set
838CONFIG_SPI=y
839# CONFIG_SPI_DEBUG is not set
840CONFIG_SPI_MASTER=y
841
842#
843# SPI Master Controller Drivers
844#
845CONFIG_SPI_BFIN=y
846# CONFIG_SPI_BFIN_LOCK is not set
847# CONFIG_SPI_BFIN_SPORT is not set
848# CONFIG_SPI_BITBANG is not set
849# CONFIG_SPI_GPIO is not set
850
851#
852# SPI Protocol Masters
853#
854CONFIG_SPI_SPIDEV=y
855# CONFIG_SPI_TLE62X0 is not set
856
857#
858# PPS support
859#
860# CONFIG_PPS is not set
861CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
862CONFIG_GPIOLIB=y
863# CONFIG_DEBUG_GPIO is not set
864CONFIG_GPIO_SYSFS=y
865
866#
867# Memory mapped GPIO expanders:
868#
869
870#
871# I2C GPIO expanders:
872#
873# CONFIG_GPIO_MAX732X is not set
874# CONFIG_GPIO_PCA953X is not set
875CONFIG_GPIO_PCF857X=y
876# CONFIG_GPIO_ADP5588 is not set
877
878#
879# PCI GPIO expanders:
880#
881
882#
883# SPI GPIO expanders:
884#
885# CONFIG_GPIO_MAX7301 is not set
886# CONFIG_GPIO_MCP23S08 is not set
887# CONFIG_W1 is not set
888# CONFIG_POWER_SUPPLY is not set
889CONFIG_HWMON=y
890# CONFIG_HWMON_VID is not set
891# CONFIG_SENSORS_AD7414 is not set
892# CONFIG_SENSORS_AD7418 is not set
893# CONFIG_SENSORS_ADCXX is not set
894# CONFIG_SENSORS_ADM1021 is not set
895# CONFIG_SENSORS_ADM1025 is not set
896# CONFIG_SENSORS_ADM1026 is not set
897# CONFIG_SENSORS_ADM1029 is not set
898# CONFIG_SENSORS_ADM1031 is not set
899# CONFIG_SENSORS_ADM9240 is not set
900# CONFIG_SENSORS_ADT7462 is not set
901# CONFIG_SENSORS_ADT7470 is not set
902# CONFIG_SENSORS_ADT7473 is not set
903# CONFIG_SENSORS_ADT7475 is not set
904# CONFIG_SENSORS_ATXP1 is not set
905# CONFIG_SENSORS_DS1621 is not set
906# CONFIG_SENSORS_F71805F is not set
907# CONFIG_SENSORS_F71882FG is not set
908# CONFIG_SENSORS_F75375S is not set
909# CONFIG_SENSORS_G760A is not set
910# CONFIG_SENSORS_GL518SM is not set
911# CONFIG_SENSORS_GL520SM is not set
912# CONFIG_SENSORS_IT87 is not set
913# CONFIG_SENSORS_LM63 is not set
914# CONFIG_SENSORS_LM70 is not set
915CONFIG_SENSORS_LM75=y
916# CONFIG_SENSORS_LM77 is not set
917# CONFIG_SENSORS_LM78 is not set
918# CONFIG_SENSORS_LM80 is not set
919# CONFIG_SENSORS_LM83 is not set
920# CONFIG_SENSORS_LM85 is not set
921# CONFIG_SENSORS_LM87 is not set
922# CONFIG_SENSORS_LM90 is not set
923# CONFIG_SENSORS_LM92 is not set
924# CONFIG_SENSORS_LM93 is not set
925# CONFIG_SENSORS_LTC4215 is not set
926# CONFIG_SENSORS_LTC4245 is not set
927# CONFIG_SENSORS_LM95241 is not set
928# CONFIG_SENSORS_MAX1111 is not set
929# CONFIG_SENSORS_MAX1619 is not set
930# CONFIG_SENSORS_MAX6650 is not set
931# CONFIG_SENSORS_PC87360 is not set
932# CONFIG_SENSORS_PC87427 is not set
933# CONFIG_SENSORS_PCF8591 is not set
934# CONFIG_SENSORS_SHT15 is not set
935# CONFIG_SENSORS_DME1737 is not set
936# CONFIG_SENSORS_SMSC47M1 is not set
937# CONFIG_SENSORS_SMSC47M192 is not set
938# CONFIG_SENSORS_SMSC47B397 is not set
939# CONFIG_SENSORS_ADS7828 is not set
940# CONFIG_SENSORS_THMC50 is not set
941# CONFIG_SENSORS_TMP401 is not set
942# CONFIG_SENSORS_VT1211 is not set
943# CONFIG_SENSORS_W83781D is not set
944# CONFIG_SENSORS_W83791D is not set
945# CONFIG_SENSORS_W83792D is not set
946# CONFIG_SENSORS_W83793 is not set
947# CONFIG_SENSORS_W83L785TS is not set
948# CONFIG_SENSORS_W83L786NG is not set
949# CONFIG_SENSORS_W83627HF is not set
950# CONFIG_SENSORS_W83627EHF is not set
951# CONFIG_HWMON_DEBUG_CHIP is not set
952# CONFIG_THERMAL is not set
953# CONFIG_THERMAL_HWMON is not set
954CONFIG_WATCHDOG=y
955# CONFIG_WATCHDOG_NOWAYOUT is not set
956
957#
958# Watchdog Device Drivers
959#
960# CONFIG_SOFT_WATCHDOG is not set
961CONFIG_BFIN_WDT=y
962
963#
964# USB-based Watchdog Cards
965#
966# CONFIG_USBPCWATCHDOG is not set
967CONFIG_SSB_POSSIBLE=y
968
969#
970# Sonics Silicon Backplane
971#
972# CONFIG_SSB is not set
973
974#
975# Multifunction device drivers
976#
977# CONFIG_MFD_CORE is not set
978# CONFIG_MFD_SM501 is not set
979# CONFIG_HTC_PASIC3 is not set
980# CONFIG_TPS65010 is not set
981# CONFIG_TWL4030_CORE is not set
982# CONFIG_MFD_TMIO is not set
983# CONFIG_PMIC_DA903X is not set
984# CONFIG_PMIC_ADP5520 is not set
985# CONFIG_MFD_WM8400 is not set
986# CONFIG_MFD_WM8350_I2C is not set
987# CONFIG_MFD_PCF50633 is not set
988# CONFIG_AB3100_CORE is not set
989# CONFIG_EZX_PCAP is not set
990# CONFIG_REGULATOR is not set
991# CONFIG_MEDIA_SUPPORT is not set
992
993#
994# Graphics support
995#
996# CONFIG_VGASTATE is not set
997# CONFIG_VIDEO_OUTPUT_CONTROL is not set
998# CONFIG_FB is not set
999# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1000
1001#
1002# Display device support
1003#
1004# CONFIG_DISPLAY_SUPPORT is not set
1005CONFIG_SOUND=y
1006CONFIG_SOUND_OSS_CORE=y
1007CONFIG_SND=y
1008CONFIG_SND_TIMER=y
1009CONFIG_SND_PCM=y
1010# CONFIG_SND_SEQUENCER is not set
1011CONFIG_SND_OSSEMUL=y
1012CONFIG_SND_MIXER_OSS=y
1013CONFIG_SND_PCM_OSS=y
1014CONFIG_SND_PCM_OSS_PLUGINS=y
1015# CONFIG_SND_HRTIMER is not set
1016# CONFIG_SND_DYNAMIC_MINORS is not set
1017CONFIG_SND_SUPPORT_OLD_API=y
1018CONFIG_SND_VERBOSE_PROCFS=y
1019# CONFIG_SND_VERBOSE_PRINTK is not set
1020# CONFIG_SND_DEBUG is not set
1021# CONFIG_SND_RAWMIDI_SEQ is not set
1022# CONFIG_SND_OPL3_LIB_SEQ is not set
1023# CONFIG_SND_OPL4_LIB_SEQ is not set
1024# CONFIG_SND_SBAWE_SEQ is not set
1025# CONFIG_SND_EMU10K1_SEQ is not set
1026# CONFIG_SND_DRIVERS is not set
1027CONFIG_SND_SPI=y
1028
1029#
1030# ALSA Blackfin devices
1031#
1032# CONFIG_SND_BFIN_AD73322 is not set
1033# CONFIG_SND_USB is not set
1034CONFIG_SND_SOC=y
1035CONFIG_SND_BF5XX_I2S=y
1036# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
1037# CONFIG_SND_BF5XX_SOC_AD73311 is not set
1038# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
1039# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
1040# CONFIG_SND_BF5XX_TDM is not set
1041# CONFIG_SND_BF5XX_AC97 is not set
1042CONFIG_SND_BF5XX_SOC_SPORT=y
1043CONFIG_SND_BF5XX_SPORT_NUM=1
1044CONFIG_SND_SOC_I2C_AND_SPI=y
1045# CONFIG_SND_SOC_ALL_CODECS is not set
1046# CONFIG_SOUND_PRIME is not set
1047CONFIG_USB_SUPPORT=y
1048CONFIG_USB_ARCH_HAS_HCD=y
1049# CONFIG_USB_ARCH_HAS_OHCI is not set
1050# CONFIG_USB_ARCH_HAS_EHCI is not set
1051CONFIG_USB=y
1052# CONFIG_USB_DEBUG is not set
1053CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1054
1055#
1056# Miscellaneous USB options
1057#
1058# CONFIG_USB_DEVICEFS is not set
1059# CONFIG_USB_DEVICE_CLASS is not set
1060# CONFIG_USB_DYNAMIC_MINORS is not set
1061# CONFIG_USB_OTG is not set
1062# CONFIG_USB_OTG_WHITELIST is not set
1063# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1064CONFIG_USB_MON=y
1065# CONFIG_USB_WUSB is not set
1066# CONFIG_USB_WUSB_CBAF is not set
1067
1068#
1069# USB Host Controller Drivers
1070#
1071# CONFIG_USB_C67X00_HCD is not set
1072# CONFIG_USB_OXU210HP_HCD is not set
1073# CONFIG_USB_ISP116X_HCD is not set
1074# CONFIG_USB_ISP1760_HCD is not set
1075# CONFIG_USB_ISP1362_HCD is not set
1076# CONFIG_USB_SL811_HCD is not set
1077# CONFIG_USB_R8A66597_HCD is not set
1078# CONFIG_USB_HWA_HCD is not set
1079
1080#
1081# USB Device Class drivers
1082#
1083# CONFIG_USB_ACM is not set
1084# CONFIG_USB_PRINTER is not set
1085# CONFIG_USB_WDM is not set
1086# CONFIG_USB_TMC is not set
1087
1088#
1089# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1090#
1091
1092#
1093# also be needed; see USB_STORAGE Help for more info
1094#
1095CONFIG_USB_STORAGE=y
1096# CONFIG_USB_STORAGE_DEBUG is not set
1097# CONFIG_USB_STORAGE_DATAFAB is not set
1098# CONFIG_USB_STORAGE_FREECOM is not set
1099# CONFIG_USB_STORAGE_ISD200 is not set
1100# CONFIG_USB_STORAGE_USBAT is not set
1101# CONFIG_USB_STORAGE_SDDR09 is not set
1102# CONFIG_USB_STORAGE_SDDR55 is not set
1103# CONFIG_USB_STORAGE_JUMPSHOT is not set
1104# CONFIG_USB_STORAGE_ALAUDA is not set
1105# CONFIG_USB_STORAGE_KARMA is not set
1106# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1107# CONFIG_USB_LIBUSUAL is not set
1108
1109#
1110# USB Imaging devices
1111#
1112# CONFIG_USB_MDC800 is not set
1113# CONFIG_USB_MICROTEK is not set
1114
1115#
1116# USB port drivers
1117#
1118CONFIG_USB_SERIAL=y
1119# CONFIG_USB_SERIAL_CONSOLE is not set
1120# CONFIG_USB_EZUSB is not set
1121# CONFIG_USB_SERIAL_GENERIC is not set
1122# CONFIG_USB_SERIAL_AIRCABLE is not set
1123# CONFIG_USB_SERIAL_ARK3116 is not set
1124# CONFIG_USB_SERIAL_BELKIN is not set
1125# CONFIG_USB_SERIAL_CH341 is not set
1126# CONFIG_USB_SERIAL_WHITEHEAT is not set
1127# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1128# CONFIG_USB_SERIAL_CP210X is not set
1129# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1130# CONFIG_USB_SERIAL_EMPEG is not set
1131CONFIG_USB_SERIAL_FTDI_SIO=y
1132# CONFIG_USB_SERIAL_FUNSOFT is not set
1133# CONFIG_USB_SERIAL_VISOR is not set
1134# CONFIG_USB_SERIAL_IPAQ is not set
1135# CONFIG_USB_SERIAL_IR is not set
1136# CONFIG_USB_SERIAL_EDGEPORT is not set
1137# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1138# CONFIG_USB_SERIAL_GARMIN is not set
1139# CONFIG_USB_SERIAL_IPW is not set
1140# CONFIG_USB_SERIAL_IUU is not set
1141# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1142# CONFIG_USB_SERIAL_KEYSPAN is not set
1143# CONFIG_USB_SERIAL_KLSI is not set
1144# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1145# CONFIG_USB_SERIAL_MCT_U232 is not set
1146# CONFIG_USB_SERIAL_MOS7720 is not set
1147# CONFIG_USB_SERIAL_MOS7840 is not set
1148# CONFIG_USB_SERIAL_MOTOROLA is not set
1149# CONFIG_USB_SERIAL_NAVMAN is not set
1150CONFIG_USB_SERIAL_PL2303=y
1151# CONFIG_USB_SERIAL_OTI6858 is not set
1152# CONFIG_USB_SERIAL_QUALCOMM is not set
1153# CONFIG_USB_SERIAL_SPCP8X5 is not set
1154# CONFIG_USB_SERIAL_HP4X is not set
1155# CONFIG_USB_SERIAL_SAFE is not set
1156# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1157# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1158# CONFIG_USB_SERIAL_SYMBOL is not set
1159# CONFIG_USB_SERIAL_TI is not set
1160# CONFIG_USB_SERIAL_CYBERJACK is not set
1161# CONFIG_USB_SERIAL_XIRCOM is not set
1162# CONFIG_USB_SERIAL_OPTION is not set
1163# CONFIG_USB_SERIAL_OMNINET is not set
1164# CONFIG_USB_SERIAL_OPTICON is not set
1165# CONFIG_USB_SERIAL_DEBUG is not set
1166
1167#
1168# USB Miscellaneous drivers
1169#
1170# CONFIG_USB_EMI62 is not set
1171# CONFIG_USB_EMI26 is not set
1172# CONFIG_USB_ADUTUX is not set
1173# CONFIG_USB_SEVSEG is not set
1174# CONFIG_USB_RIO500 is not set
1175# CONFIG_USB_LEGOTOWER is not set
1176# CONFIG_USB_LCD is not set
1177# CONFIG_USB_BERRY_CHARGE is not set
1178# CONFIG_USB_LED is not set
1179# CONFIG_USB_CYPRESS_CY7C63 is not set
1180# CONFIG_USB_CYTHERM is not set
1181# CONFIG_USB_IDMOUSE is not set
1182# CONFIG_USB_FTDI_ELAN is not set
1183# CONFIG_USB_APPLEDISPLAY is not set
1184# CONFIG_USB_LD is not set
1185# CONFIG_USB_TRANCEVIBRATOR is not set
1186# CONFIG_USB_IOWARRIOR is not set
1187# CONFIG_USB_TEST is not set
1188# CONFIG_USB_ISIGHTFW is not set
1189# CONFIG_USB_VST is not set
1190# CONFIG_USB_GADGET is not set
1191
1192#
1193# OTG and related infrastructure
1194#
1195# CONFIG_USB_GPIO_VBUS is not set
1196# CONFIG_NOP_USB_XCEIV is not set
1197# CONFIG_MMC is not set
1198# CONFIG_MEMSTICK is not set
1199# CONFIG_NEW_LEDS is not set
1200# CONFIG_ACCESSIBILITY is not set
1201CONFIG_RTC_LIB=y
1202CONFIG_RTC_CLASS=y
1203CONFIG_RTC_HCTOSYS=y
1204CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1205# CONFIG_RTC_DEBUG is not set
1206
1207#
1208# RTC interfaces
1209#
1210CONFIG_RTC_INTF_SYSFS=y
1211CONFIG_RTC_INTF_PROC=y
1212CONFIG_RTC_INTF_DEV=y
1213# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1214# CONFIG_RTC_DRV_TEST is not set
1215
1216#
1217# I2C RTC drivers
1218#
1219CONFIG_RTC_DRV_DS1307=y
1220# CONFIG_RTC_DRV_DS1374 is not set
1221# CONFIG_RTC_DRV_DS1672 is not set
1222# CONFIG_RTC_DRV_MAX6900 is not set
1223# CONFIG_RTC_DRV_RS5C372 is not set
1224# CONFIG_RTC_DRV_ISL1208 is not set
1225# CONFIG_RTC_DRV_X1205 is not set
1226# CONFIG_RTC_DRV_PCF8563 is not set
1227# CONFIG_RTC_DRV_PCF8583 is not set
1228# CONFIG_RTC_DRV_M41T80 is not set
1229# CONFIG_RTC_DRV_S35390A is not set
1230# CONFIG_RTC_DRV_FM3130 is not set
1231# CONFIG_RTC_DRV_RX8581 is not set
1232# CONFIG_RTC_DRV_RX8025 is not set
1233
1234#
1235# SPI RTC drivers
1236#
1237# CONFIG_RTC_DRV_M41T94 is not set
1238# CONFIG_RTC_DRV_DS1305 is not set
1239# CONFIG_RTC_DRV_DS1390 is not set
1240# CONFIG_RTC_DRV_MAX6902 is not set
1241# CONFIG_RTC_DRV_R9701 is not set
1242# CONFIG_RTC_DRV_RS5C348 is not set
1243# CONFIG_RTC_DRV_DS3234 is not set
1244
1245#
1246# Platform RTC drivers
1247#
1248# CONFIG_RTC_DRV_DS1286 is not set
1249# CONFIG_RTC_DRV_DS1511 is not set
1250# CONFIG_RTC_DRV_DS1553 is not set
1251# CONFIG_RTC_DRV_DS1742 is not set
1252# CONFIG_RTC_DRV_STK17TA8 is not set
1253# CONFIG_RTC_DRV_M48T86 is not set
1254# CONFIG_RTC_DRV_M48T35 is not set
1255# CONFIG_RTC_DRV_M48T59 is not set
1256# CONFIG_RTC_DRV_BQ4802 is not set
1257# CONFIG_RTC_DRV_V3020 is not set
1258
1259#
1260# on-CPU RTC drivers
1261#
1262# CONFIG_DMADEVICES is not set
1263# CONFIG_AUXDISPLAY is not set
1264# CONFIG_UIO is not set
1265
1266#
1267# TI VLYNQ
1268#
1269# CONFIG_STAGING is not set
1270
1271#
1272# Firmware Drivers
1273#
1274# CONFIG_FIRMWARE_MEMMAP is not set
1275# CONFIG_SIGMA is not set
1276
1277#
1278# File systems
1279#
1280CONFIG_EXT2_FS=y
1281CONFIG_EXT2_FS_XATTR=y
1282CONFIG_EXT2_FS_POSIX_ACL=y
1283CONFIG_EXT2_FS_SECURITY=y
1284# CONFIG_EXT3_FS is not set
1285# CONFIG_EXT4_FS is not set
1286CONFIG_FS_MBCACHE=y
1287# CONFIG_REISERFS_FS is not set
1288# CONFIG_JFS_FS is not set
1289CONFIG_FS_POSIX_ACL=y
1290# CONFIG_XFS_FS is not set
1291# CONFIG_GFS2_FS is not set
1292# CONFIG_OCFS2_FS is not set
1293# CONFIG_BTRFS_FS is not set
1294CONFIG_FILE_LOCKING=y
1295CONFIG_FSNOTIFY=y
1296# CONFIG_DNOTIFY is not set
1297CONFIG_INOTIFY=y
1298CONFIG_INOTIFY_USER=y
1299# CONFIG_QUOTA is not set
1300# CONFIG_AUTOFS_FS is not set
1301# CONFIG_AUTOFS4_FS is not set
1302# CONFIG_FUSE_FS is not set
1303
1304#
1305# Caches
1306#
1307# CONFIG_FSCACHE is not set
1308
1309#
1310# CD-ROM/DVD Filesystems
1311#
1312# CONFIG_ISO9660_FS is not set
1313# CONFIG_UDF_FS is not set
1314
1315#
1316# DOS/FAT/NT Filesystems
1317#
1318CONFIG_FAT_FS=y
1319CONFIG_MSDOS_FS=y
1320CONFIG_VFAT_FS=y
1321CONFIG_FAT_DEFAULT_CODEPAGE=866
1322CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
1323CONFIG_NTFS_FS=y
1324# CONFIG_NTFS_DEBUG is not set
1325# CONFIG_NTFS_RW is not set
1326
1327#
1328# Pseudo filesystems
1329#
1330CONFIG_PROC_FS=y
1331CONFIG_PROC_SYSCTL=y
1332CONFIG_SYSFS=y
1333# CONFIG_TMPFS is not set
1334# CONFIG_HUGETLB_PAGE is not set
1335CONFIG_CONFIGFS_FS=y
1336CONFIG_MISC_FILESYSTEMS=y
1337# CONFIG_ADFS_FS is not set
1338# CONFIG_AFFS_FS is not set
1339# CONFIG_HFS_FS is not set
1340# CONFIG_HFSPLUS_FS is not set
1341# CONFIG_BEFS_FS is not set
1342# CONFIG_BFS_FS is not set
1343# CONFIG_EFS_FS is not set
1344CONFIG_JFFS2_FS=y
1345CONFIG_JFFS2_FS_DEBUG=0
1346CONFIG_JFFS2_FS_WRITEBUFFER=y
1347# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1348# CONFIG_JFFS2_SUMMARY is not set
1349# CONFIG_JFFS2_FS_XATTR is not set
1350CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1351# CONFIG_JFFS2_ZLIB is not set
1352CONFIG_JFFS2_LZO=y
1353# CONFIG_JFFS2_RTIME is not set
1354# CONFIG_JFFS2_RUBIN is not set
1355# CONFIG_JFFS2_CMODE_NONE is not set
1356# CONFIG_JFFS2_CMODE_PRIORITY is not set
1357# CONFIG_JFFS2_CMODE_SIZE is not set
1358CONFIG_JFFS2_CMODE_FAVOURLZO=y
1359CONFIG_CRAMFS=y
1360# CONFIG_SQUASHFS is not set
1361# CONFIG_VXFS_FS is not set
1362CONFIG_MINIX_FS=y
1363# CONFIG_OMFS_FS is not set
1364# CONFIG_HPFS_FS is not set
1365# CONFIG_QNX4FS_FS is not set
1366# CONFIG_ROMFS_FS is not set
1367# CONFIG_SYSV_FS is not set
1368# CONFIG_UFS_FS is not set
1369# CONFIG_NILFS2_FS is not set
1370CONFIG_NETWORK_FILESYSTEMS=y
1371CONFIG_NFS_FS=y
1372CONFIG_NFS_V3=y
1373# CONFIG_NFS_V3_ACL is not set
1374# CONFIG_NFS_V4 is not set
1375CONFIG_ROOT_NFS=y
1376# CONFIG_NFSD is not set
1377CONFIG_LOCKD=y
1378CONFIG_LOCKD_V4=y
1379CONFIG_NFS_COMMON=y
1380CONFIG_SUNRPC=y
1381# CONFIG_RPCSEC_GSS_KRB5 is not set
1382# CONFIG_RPCSEC_GSS_SPKM3 is not set
1383# CONFIG_SMB_FS is not set
1384# CONFIG_CIFS is not set
1385# CONFIG_NCP_FS is not set
1386# CONFIG_CODA_FS is not set
1387# CONFIG_AFS_FS is not set
1388
1389#
1390# Partition Types
1391#
1392# CONFIG_PARTITION_ADVANCED is not set
1393CONFIG_MSDOS_PARTITION=y
1394CONFIG_NLS=y
1395CONFIG_NLS_DEFAULT="cp1251"
1396# CONFIG_NLS_CODEPAGE_437 is not set
1397# CONFIG_NLS_CODEPAGE_737 is not set
1398# CONFIG_NLS_CODEPAGE_775 is not set
1399# CONFIG_NLS_CODEPAGE_850 is not set
1400# CONFIG_NLS_CODEPAGE_852 is not set
1401# CONFIG_NLS_CODEPAGE_855 is not set
1402# CONFIG_NLS_CODEPAGE_857 is not set
1403# CONFIG_NLS_CODEPAGE_860 is not set
1404# CONFIG_NLS_CODEPAGE_861 is not set
1405# CONFIG_NLS_CODEPAGE_862 is not set
1406# CONFIG_NLS_CODEPAGE_863 is not set
1407# CONFIG_NLS_CODEPAGE_864 is not set
1408# CONFIG_NLS_CODEPAGE_865 is not set
1409CONFIG_NLS_CODEPAGE_866=y
1410# CONFIG_NLS_CODEPAGE_869 is not set
1411# CONFIG_NLS_CODEPAGE_936 is not set
1412# CONFIG_NLS_CODEPAGE_950 is not set
1413# CONFIG_NLS_CODEPAGE_932 is not set
1414# CONFIG_NLS_CODEPAGE_949 is not set
1415# CONFIG_NLS_CODEPAGE_874 is not set
1416# CONFIG_NLS_ISO8859_8 is not set
1417# CONFIG_NLS_CODEPAGE_1250 is not set
1418CONFIG_NLS_CODEPAGE_1251=y
1419# CONFIG_NLS_ASCII is not set
1420# CONFIG_NLS_ISO8859_1 is not set
1421# CONFIG_NLS_ISO8859_2 is not set
1422# CONFIG_NLS_ISO8859_3 is not set
1423# CONFIG_NLS_ISO8859_4 is not set
1424# CONFIG_NLS_ISO8859_5 is not set
1425# CONFIG_NLS_ISO8859_6 is not set
1426# CONFIG_NLS_ISO8859_7 is not set
1427# CONFIG_NLS_ISO8859_9 is not set
1428# CONFIG_NLS_ISO8859_13 is not set
1429# CONFIG_NLS_ISO8859_14 is not set
1430# CONFIG_NLS_ISO8859_15 is not set
1431CONFIG_NLS_KOI8_R=y
1432# CONFIG_NLS_KOI8_U is not set
1433CONFIG_NLS_UTF8=y
1434# CONFIG_DLM is not set
1435
1436#
1437# Kernel hacking
1438#
1439# CONFIG_PRINTK_TIME is not set
1440CONFIG_ENABLE_WARN_DEPRECATED=y
1441CONFIG_ENABLE_MUST_CHECK=y
1442CONFIG_FRAME_WARN=1024
1443# CONFIG_MAGIC_SYSRQ is not set
1444# CONFIG_UNUSED_SYMBOLS is not set
1445CONFIG_DEBUG_FS=y
1446# CONFIG_HEADERS_CHECK is not set
1447CONFIG_DEBUG_SECTION_MISMATCH=y
1448CONFIG_DEBUG_KERNEL=y
1449CONFIG_DEBUG_SHIRQ=y
1450CONFIG_DETECT_SOFTLOCKUP=y
1451# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1452CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1453CONFIG_DETECT_HUNG_TASK=y
1454# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1455CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1456CONFIG_SCHED_DEBUG=y
1457# CONFIG_SCHEDSTATS is not set
1458# CONFIG_TIMER_STATS is not set
1459# CONFIG_DEBUG_OBJECTS is not set
1460# CONFIG_DEBUG_SLAB is not set
1461# CONFIG_DEBUG_SPINLOCK is not set
1462# CONFIG_DEBUG_MUTEXES is not set
1463# CONFIG_DEBUG_LOCK_ALLOC is not set
1464# CONFIG_PROVE_LOCKING is not set
1465# CONFIG_LOCK_STAT is not set
1466# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1467# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1468# CONFIG_DEBUG_KOBJECT is not set
1469# CONFIG_DEBUG_BUGVERBOSE is not set
1470CONFIG_DEBUG_INFO=y
1471# CONFIG_DEBUG_VM is not set
1472# CONFIG_DEBUG_NOMMU_REGIONS is not set
1473# CONFIG_DEBUG_WRITECOUNT is not set
1474# CONFIG_DEBUG_MEMORY_INIT is not set
1475# CONFIG_DEBUG_LIST is not set
1476# CONFIG_DEBUG_SG is not set
1477# CONFIG_DEBUG_NOTIFIERS is not set
1478# CONFIG_FRAME_POINTER is not set
1479# CONFIG_BOOT_PRINTK_DELAY is not set
1480# CONFIG_RCU_TORTURE_TEST is not set
1481# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1482# CONFIG_BACKTRACE_SELF_TEST is not set
1483# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1484# CONFIG_FAULT_INJECTION is not set
1485# CONFIG_PAGE_POISONING is not set
1486CONFIG_HAVE_FUNCTION_TRACER=y
1487CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1488CONFIG_TRACING_SUPPORT=y
1489CONFIG_FTRACE=y
1490# CONFIG_FUNCTION_TRACER is not set
1491# CONFIG_IRQSOFF_TRACER is not set
1492# CONFIG_SCHED_TRACER is not set
1493# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1494# CONFIG_BOOT_TRACER is not set
1495CONFIG_BRANCH_PROFILE_NONE=y
1496# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1497# CONFIG_PROFILE_ALL_BRANCHES is not set
1498# CONFIG_STACK_TRACER is not set
1499# CONFIG_KMEMTRACE is not set
1500# CONFIG_WORKQUEUE_TRACER is not set
1501# CONFIG_BLK_DEV_IO_TRACE is not set
1502# CONFIG_DYNAMIC_DEBUG is not set
1503# CONFIG_SAMPLES is not set
1504CONFIG_HAVE_ARCH_KGDB=y
1505# CONFIG_KGDB is not set
1506# CONFIG_KMEMCHECK is not set
1507# CONFIG_DEBUG_STACKOVERFLOW is not set
1508# CONFIG_DEBUG_STACK_USAGE is not set
1509CONFIG_DEBUG_VERBOSE=y
1510CONFIG_DEBUG_MMRS=y
1511# CONFIG_DEBUG_HWERR is not set
1512# CONFIG_DEBUG_DOUBLEFAULT is not set
1513CONFIG_DEBUG_HUNT_FOR_ZERO=y
1514CONFIG_DEBUG_BFIN_HWTRACE_ON=y
1515CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1516# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
1517# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
1518CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1519# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1520# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1521# CONFIG_EARLY_PRINTK is not set
1522CONFIG_CPLB_INFO=y
1523CONFIG_ACCESS_CHECK=y
1524# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1525
1526#
1527# Security options
1528#
1529# CONFIG_KEYS is not set
1530CONFIG_SECURITY=y
1531# CONFIG_SECURITYFS is not set
1532# CONFIG_SECURITY_NETWORK is not set
1533# CONFIG_SECURITY_PATH is not set
1534# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1535# CONFIG_SECURITY_ROOTPLUG is not set
1536# CONFIG_SECURITY_TOMOYO is not set
1537CONFIG_CRYPTO=y
1538
1539#
1540# Crypto core or helper
1541#
1542# CONFIG_CRYPTO_FIPS is not set
1543# CONFIG_CRYPTO_MANAGER is not set
1544# CONFIG_CRYPTO_MANAGER2 is not set
1545# CONFIG_CRYPTO_GF128MUL is not set
1546# CONFIG_CRYPTO_NULL is not set
1547# CONFIG_CRYPTO_CRYPTD is not set
1548# CONFIG_CRYPTO_AUTHENC is not set
1549# CONFIG_CRYPTO_TEST is not set
1550
1551#
1552# Authenticated Encryption with Associated Data
1553#
1554# CONFIG_CRYPTO_CCM is not set
1555# CONFIG_CRYPTO_GCM is not set
1556# CONFIG_CRYPTO_SEQIV is not set
1557
1558#
1559# Block modes
1560#
1561# CONFIG_CRYPTO_CBC is not set
1562# CONFIG_CRYPTO_CTR is not set
1563# CONFIG_CRYPTO_CTS is not set
1564# CONFIG_CRYPTO_ECB is not set
1565# CONFIG_CRYPTO_LRW is not set
1566# CONFIG_CRYPTO_PCBC is not set
1567# CONFIG_CRYPTO_XTS is not set
1568
1569#
1570# Hash modes
1571#
1572# CONFIG_CRYPTO_HMAC is not set
1573# CONFIG_CRYPTO_XCBC is not set
1574
1575#
1576# Digest
1577#
1578# CONFIG_CRYPTO_CRC32C is not set
1579# CONFIG_CRYPTO_MD4 is not set
1580# CONFIG_CRYPTO_MD5 is not set
1581# CONFIG_CRYPTO_MICHAEL_MIC is not set
1582# CONFIG_CRYPTO_RMD128 is not set
1583# CONFIG_CRYPTO_RMD160 is not set
1584# CONFIG_CRYPTO_RMD256 is not set
1585# CONFIG_CRYPTO_RMD320 is not set
1586# CONFIG_CRYPTO_SHA1 is not set
1587# CONFIG_CRYPTO_SHA256 is not set
1588# CONFIG_CRYPTO_SHA512 is not set
1589# CONFIG_CRYPTO_TGR192 is not set
1590# CONFIG_CRYPTO_WP512 is not set
1591
1592#
1593# Ciphers
1594#
1595# CONFIG_CRYPTO_AES is not set
1596# CONFIG_CRYPTO_ANUBIS is not set
1597# CONFIG_CRYPTO_ARC4 is not set
1598# CONFIG_CRYPTO_BLOWFISH is not set
1599# CONFIG_CRYPTO_CAMELLIA is not set
1600# CONFIG_CRYPTO_CAST5 is not set
1601# CONFIG_CRYPTO_CAST6 is not set
1602# CONFIG_CRYPTO_DES is not set
1603# CONFIG_CRYPTO_FCRYPT is not set
1604# CONFIG_CRYPTO_KHAZAD is not set
1605# CONFIG_CRYPTO_SALSA20 is not set
1606# CONFIG_CRYPTO_SEED is not set
1607# CONFIG_CRYPTO_SERPENT is not set
1608# CONFIG_CRYPTO_TEA is not set
1609# CONFIG_CRYPTO_TWOFISH is not set
1610
1611#
1612# Compression
1613#
1614# CONFIG_CRYPTO_DEFLATE is not set
1615# CONFIG_CRYPTO_ZLIB is not set
1616# CONFIG_CRYPTO_LZO is not set
1617
1618#
1619# Random Number Generation
1620#
1621# CONFIG_CRYPTO_ANSI_CPRNG is not set
1622CONFIG_CRYPTO_HW=y
1623# CONFIG_BINARY_PRINTF is not set
1624
1625#
1626# Library routines
1627#
1628CONFIG_BITREVERSE=y
1629CONFIG_GENERIC_FIND_LAST_BIT=y
1630# CONFIG_CRC_CCITT is not set
1631# CONFIG_CRC16 is not set
1632# CONFIG_CRC_T10DIF is not set
1633# CONFIG_CRC_ITU_T is not set
1634CONFIG_CRC32=y
1635# CONFIG_CRC7 is not set
1636# CONFIG_LIBCRC32C is not set
1637CONFIG_ZLIB_INFLATE=y
1638CONFIG_LZO_COMPRESS=y
1639CONFIG_LZO_DECOMPRESS=y
1640CONFIG_HAS_IOMEM=y
1641CONFIG_HAS_IOPORT=y
1642CONFIG_HAS_DMA=y
1643CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 0313cd1d9824..e3ecdcc3e76b 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,22 +1,29 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28.10 3# Linux kernel version: 2.6.31.5
4# Thu May 21 05:50:01 2009 4# Mon Nov 2 21:59:31 2009
5# 5#
6# CONFIG_MMU is not set 6# CONFIG_MMU is not set
7# CONFIG_FPU is not set 7# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y 10CONFIG_BLACKFIN=y
11CONFIG_GENERIC_CSUM=y
12CONFIG_GENERIC_BUG=y
11CONFIG_ZONE_DMA=y 13CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 14CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 15CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y 16CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y 17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_GPIO=y 19CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14 20CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y 21CONFIG_GENERIC_CALIBRATE_DELAY=y
22CONFIG_LOCKDEP_SUPPORT=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_TRACE_IRQFLAGS_SUPPORT=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 25CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
26CONFIG_CONSTRUCTORS=y
20 27
21# 28#
22# General setup 29# General setup
@@ -26,22 +33,40 @@ CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32 33CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION="" 34CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y 35CONFIG_LOCALVERSION_AUTO=y
36CONFIG_HAVE_KERNEL_GZIP=y
37CONFIG_HAVE_KERNEL_BZIP2=y
38CONFIG_HAVE_KERNEL_LZMA=y
39CONFIG_KERNEL_GZIP=y
40# CONFIG_KERNEL_BZIP2 is not set
41# CONFIG_KERNEL_LZMA is not set
29CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set 44# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set 45# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
34# CONFIG_AUDIT is not set 47# CONFIG_AUDIT is not set
48
49#
50# RCU Subsystem
51#
52CONFIG_CLASSIC_RCU=y
53# CONFIG_TREE_RCU is not set
54# CONFIG_PREEMPT_RCU is not set
55# CONFIG_TREE_RCU_TRACE is not set
56# CONFIG_PREEMPT_RCU_TRACE is not set
35CONFIG_IKCONFIG=y 57CONFIG_IKCONFIG=y
36CONFIG_IKCONFIG_PROC=y 58CONFIG_IKCONFIG_PROC=y
37CONFIG_LOG_BUF_SHIFT=14 59CONFIG_LOG_BUF_SHIFT=14
38# CONFIG_CGROUPS is not set
39# CONFIG_GROUP_SCHED is not set 60# CONFIG_GROUP_SCHED is not set
61# CONFIG_CGROUPS is not set
40# CONFIG_SYSFS_DEPRECATED_V2 is not set 62# CONFIG_SYSFS_DEPRECATED_V2 is not set
41# CONFIG_RELAY is not set 63# CONFIG_RELAY is not set
42# CONFIG_NAMESPACES is not set 64# CONFIG_NAMESPACES is not set
43CONFIG_BLK_DEV_INITRD=y 65CONFIG_BLK_DEV_INITRD=y
44CONFIG_INITRAMFS_SOURCE="" 66CONFIG_INITRAMFS_SOURCE=""
67CONFIG_RD_GZIP=y
68# CONFIG_RD_BZIP2 is not set
69# CONFIG_RD_LZMA is not set
45# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 70# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
46CONFIG_SYSCTL=y 71CONFIG_SYSCTL=y
47CONFIG_ANON_INODES=y 72CONFIG_ANON_INODES=y
@@ -62,17 +87,28 @@ CONFIG_EPOLL=y
62# CONFIG_TIMERFD is not set 87# CONFIG_TIMERFD is not set
63# CONFIG_EVENTFD is not set 88# CONFIG_EVENTFD is not set
64# CONFIG_AIO is not set 89# CONFIG_AIO is not set
90
91#
92# Performance Counters
93#
65CONFIG_VM_EVENT_COUNTERS=y 94CONFIG_VM_EVENT_COUNTERS=y
95# CONFIG_STRIP_ASM_SYMS is not set
66CONFIG_COMPAT_BRK=y 96CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 97CONFIG_SLAB=y
68# CONFIG_SLUB is not set 98# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 99# CONFIG_SLOB is not set
100CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 101# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 102# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 103CONFIG_HAVE_OPROFILE=y
104
105#
106# GCOV-based kernel profiling
107#
108# CONFIG_GCOV_KERNEL is not set
109# CONFIG_SLOW_WORK is not set
73# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 110# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
74CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
75CONFIG_TINY_SHMEM=y
76CONFIG_BASE_SMALL=0 112CONFIG_BASE_SMALL=0
77CONFIG_MODULES=y 113CONFIG_MODULES=y
78# CONFIG_MODULE_FORCE_LOAD is not set 114# CONFIG_MODULE_FORCE_LOAD is not set
@@ -80,11 +116,8 @@ CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set 116# CONFIG_MODULE_FORCE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set 117# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set 118# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84CONFIG_BLOCK=y 119CONFIG_BLOCK=y
85# CONFIG_LBD is not set 120# CONFIG_LBDAF is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88# CONFIG_BLK_DEV_BSG is not set 121# CONFIG_BLK_DEV_BSG is not set
89# CONFIG_BLK_DEV_INTEGRITY is not set 122# CONFIG_BLK_DEV_INTEGRITY is not set
90 123
@@ -94,13 +127,12 @@ CONFIG_BLOCK=y
94CONFIG_IOSCHED_NOOP=y 127CONFIG_IOSCHED_NOOP=y
95CONFIG_IOSCHED_AS=y 128CONFIG_IOSCHED_AS=y
96# CONFIG_IOSCHED_DEADLINE is not set 129# CONFIG_IOSCHED_DEADLINE is not set
97CONFIG_IOSCHED_CFQ=y 130# CONFIG_IOSCHED_CFQ is not set
98CONFIG_DEFAULT_AS=y 131CONFIG_DEFAULT_AS=y
99# CONFIG_DEFAULT_DEADLINE is not set 132# CONFIG_DEFAULT_DEADLINE is not set
100# CONFIG_DEFAULT_CFQ is not set 133# CONFIG_DEFAULT_CFQ is not set
101# CONFIG_DEFAULT_NOOP is not set 134# CONFIG_DEFAULT_NOOP is not set
102CONFIG_DEFAULT_IOSCHED="anticipatory" 135CONFIG_DEFAULT_IOSCHED="anticipatory"
103CONFIG_CLASSIC_RCU=y
104# CONFIG_PREEMPT_NONE is not set 136# CONFIG_PREEMPT_NONE is not set
105CONFIG_PREEMPT_VOLUNTARY=y 137CONFIG_PREEMPT_VOLUNTARY=y
106# CONFIG_PREEMPT is not set 138# CONFIG_PREEMPT is not set
@@ -170,6 +202,7 @@ CONFIG_IRQ_SPI_ERROR=7
170CONFIG_BFIN561_EZKIT=y 202CONFIG_BFIN561_EZKIT=y
171# CONFIG_BFIN561_TEPLA is not set 203# CONFIG_BFIN561_TEPLA is not set
172# CONFIG_BFIN561_BLUETECHNIX_CM is not set 204# CONFIG_BFIN561_BLUETECHNIX_CM is not set
205# CONFIG_BFIN561_ACVILON is not set
173 206
174# 207#
175# BF561 Specific Configuration 208# BF561 Specific Configuration
@@ -317,10 +350,11 @@ CONFIG_FLATMEM=y
317CONFIG_FLAT_NODE_MEM_MAP=y 350CONFIG_FLAT_NODE_MEM_MAP=y
318CONFIG_PAGEFLAGS_EXTENDED=y 351CONFIG_PAGEFLAGS_EXTENDED=y
319CONFIG_SPLIT_PTLOCK_CPUS=4 352CONFIG_SPLIT_PTLOCK_CPUS=4
320# CONFIG_RESOURCES_64BIT is not set
321# CONFIG_PHYS_ADDR_T_64BIT is not set 353# CONFIG_PHYS_ADDR_T_64BIT is not set
322CONFIG_ZONE_DMA_FLAG=1 354CONFIG_ZONE_DMA_FLAG=1
323CONFIG_VIRT_TO_BUS=y 355CONFIG_VIRT_TO_BUS=y
356CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
357CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
324CONFIG_BFIN_GPTIMERS=m 358CONFIG_BFIN_GPTIMERS=m
325# CONFIG_DMA_UNCACHED_4M is not set 359# CONFIG_DMA_UNCACHED_4M is not set
326# CONFIG_DMA_UNCACHED_2M is not set 360# CONFIG_DMA_UNCACHED_2M is not set
@@ -331,14 +365,13 @@ CONFIG_DMA_UNCACHED_1M=y
331# Cache Support 365# Cache Support
332# 366#
333CONFIG_BFIN_ICACHE=y 367CONFIG_BFIN_ICACHE=y
334# CONFIG_BFIN_ICACHE_LOCK is not set 368CONFIG_BFIN_EXTMEM_ICACHEABLE=y
369# CONFIG_BFIN_L2_ICACHEABLE is not set
335CONFIG_BFIN_DCACHE=y 370CONFIG_BFIN_DCACHE=y
336# CONFIG_BFIN_DCACHE_BANKA is not set 371# CONFIG_BFIN_DCACHE_BANKA is not set
337CONFIG_BFIN_EXTMEM_ICACHEABLE=y
338CONFIG_BFIN_EXTMEM_DCACHEABLE=y 372CONFIG_BFIN_EXTMEM_DCACHEABLE=y
339CONFIG_BFIN_EXTMEM_WRITEBACK=y 373CONFIG_BFIN_EXTMEM_WRITEBACK=y
340# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 374# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
341# CONFIG_BFIN_L2_ICACHEABLE is not set
342# CONFIG_BFIN_L2_DCACHEABLE is not set 375# CONFIG_BFIN_L2_DCACHEABLE is not set
343 376
344# 377#
@@ -347,7 +380,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
347# CONFIG_MPU is not set 380# CONFIG_MPU is not set
348 381
349# 382#
350# Asynchonous Memory Configuration 383# Asynchronous Memory Configuration
351# 384#
352 385
353# 386#
@@ -407,11 +440,6 @@ CONFIG_NET=y
407CONFIG_PACKET=y 440CONFIG_PACKET=y
408# CONFIG_PACKET_MMAP is not set 441# CONFIG_PACKET_MMAP is not set
409CONFIG_UNIX=y 442CONFIG_UNIX=y
410CONFIG_XFRM=y
411# CONFIG_XFRM_USER is not set
412# CONFIG_XFRM_SUB_POLICY is not set
413# CONFIG_XFRM_MIGRATE is not set
414# CONFIG_XFRM_STATISTICS is not set
415# CONFIG_NET_KEY is not set 443# CONFIG_NET_KEY is not set
416CONFIG_INET=y 444CONFIG_INET=y
417# CONFIG_IP_MULTICAST is not set 445# CONFIG_IP_MULTICAST is not set
@@ -435,13 +463,11 @@ CONFIG_IP_PNP=y
435# CONFIG_INET_XFRM_MODE_BEET is not set 463# CONFIG_INET_XFRM_MODE_BEET is not set
436# CONFIG_INET_LRO is not set 464# CONFIG_INET_LRO is not set
437# CONFIG_INET_DIAG is not set 465# CONFIG_INET_DIAG is not set
438CONFIG_INET_TCP_DIAG=y
439# CONFIG_TCP_CONG_ADVANCED is not set 466# CONFIG_TCP_CONG_ADVANCED is not set
440CONFIG_TCP_CONG_CUBIC=y 467CONFIG_TCP_CONG_CUBIC=y
441CONFIG_DEFAULT_TCP_CONG="cubic" 468CONFIG_DEFAULT_TCP_CONG="cubic"
442# CONFIG_TCP_MD5SIG is not set 469# CONFIG_TCP_MD5SIG is not set
443# CONFIG_IPV6 is not set 470# CONFIG_IPV6 is not set
444# CONFIG_NETLABEL is not set
445# CONFIG_NETWORK_SECMARK is not set 471# CONFIG_NETWORK_SECMARK is not set
446# CONFIG_NETFILTER is not set 472# CONFIG_NETFILTER is not set
447# CONFIG_IP_DCCP is not set 473# CONFIG_IP_DCCP is not set
@@ -459,7 +485,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
459# CONFIG_LAPB is not set 485# CONFIG_LAPB is not set
460# CONFIG_ECONET is not set 486# CONFIG_ECONET is not set
461# CONFIG_WAN_ROUTER is not set 487# CONFIG_WAN_ROUTER is not set
488# CONFIG_PHONET is not set
489# CONFIG_IEEE802154 is not set
462# CONFIG_NET_SCHED is not set 490# CONFIG_NET_SCHED is not set
491# CONFIG_DCB is not set
463 492
464# 493#
465# Network testing 494# Network testing
@@ -503,13 +532,8 @@ CONFIG_IRTTY_SIR=m
503# 532#
504# CONFIG_BT is not set 533# CONFIG_BT is not set
505# CONFIG_AF_RXRPC is not set 534# CONFIG_AF_RXRPC is not set
506# CONFIG_PHONET is not set 535# CONFIG_WIRELESS is not set
507CONFIG_WIRELESS=y 536# CONFIG_WIMAX is not set
508# CONFIG_CFG80211 is not set
509CONFIG_WIRELESS_OLD_REGULATORY=y
510# CONFIG_WIRELESS_EXT is not set
511# CONFIG_MAC80211 is not set
512# CONFIG_IEEE80211 is not set
513# CONFIG_RFKILL is not set 537# CONFIG_RFKILL is not set
514# CONFIG_NET_9P is not set 538# CONFIG_NET_9P is not set
515 539
@@ -530,6 +554,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
530# CONFIG_CONNECTOR is not set 554# CONFIG_CONNECTOR is not set
531CONFIG_MTD=y 555CONFIG_MTD=y
532# CONFIG_MTD_DEBUG is not set 556# CONFIG_MTD_DEBUG is not set
557# CONFIG_MTD_TESTS is not set
533# CONFIG_MTD_CONCAT is not set 558# CONFIG_MTD_CONCAT is not set
534CONFIG_MTD_PARTITIONS=y 559CONFIG_MTD_PARTITIONS=y
535# CONFIG_MTD_REDBOOT_PARTS is not set 560# CONFIG_MTD_REDBOOT_PARTS is not set
@@ -603,6 +628,11 @@ CONFIG_MTD_PHYSMAP=m
603# CONFIG_MTD_ONENAND is not set 628# CONFIG_MTD_ONENAND is not set
604 629
605# 630#
631# LPDDR flash memory drivers
632#
633# CONFIG_MTD_LPDDR is not set
634
635#
606# UBI - Unsorted block images 636# UBI - Unsorted block images
607# 637#
608# CONFIG_MTD_UBI is not set 638# CONFIG_MTD_UBI is not set
@@ -619,9 +649,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
619# CONFIG_ATA_OVER_ETH is not set 649# CONFIG_ATA_OVER_ETH is not set
620# CONFIG_BLK_DEV_HD is not set 650# CONFIG_BLK_DEV_HD is not set
621CONFIG_MISC_DEVICES=y 651CONFIG_MISC_DEVICES=y
622# CONFIG_EEPROM_93CX6 is not set
623# CONFIG_ENCLOSURE_SERVICES is not set 652# CONFIG_ENCLOSURE_SERVICES is not set
624# CONFIG_C2PORT is not set 653# CONFIG_C2PORT is not set
654
655#
656# EEPROM support
657#
658# CONFIG_EEPROM_AT25 is not set
659# CONFIG_EEPROM_93CX6 is not set
625CONFIG_HAVE_IDE=y 660CONFIG_HAVE_IDE=y
626# CONFIG_IDE is not set 661# CONFIG_IDE is not set
627 662
@@ -645,9 +680,11 @@ CONFIG_NETDEVICES=y
645CONFIG_NET_ETHERNET=y 680CONFIG_NET_ETHERNET=y
646CONFIG_MII=y 681CONFIG_MII=y
647CONFIG_SMC91X=y 682CONFIG_SMC91X=y
648# CONFIG_SMSC911X is not set
649# CONFIG_DM9000 is not set 683# CONFIG_DM9000 is not set
650# CONFIG_ENC28J60 is not set 684# CONFIG_ENC28J60 is not set
685# CONFIG_ETHOC is not set
686# CONFIG_SMSC911X is not set
687# CONFIG_DNET is not set
651# CONFIG_IBM_NEW_EMAC_ZMII is not set 688# CONFIG_IBM_NEW_EMAC_ZMII is not set
652# CONFIG_IBM_NEW_EMAC_RGMII is not set 689# CONFIG_IBM_NEW_EMAC_RGMII is not set
653# CONFIG_IBM_NEW_EMAC_TAH is not set 690# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -656,6 +693,8 @@ CONFIG_SMC91X=y
656# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set 693# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
657# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set 694# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
658# CONFIG_B44 is not set 695# CONFIG_B44 is not set
696# CONFIG_KS8842 is not set
697# CONFIG_KS8851 is not set
659# CONFIG_NETDEV_1000 is not set 698# CONFIG_NETDEV_1000 is not set
660# CONFIG_NETDEV_10000 is not set 699# CONFIG_NETDEV_10000 is not set
661 700
@@ -664,7 +703,10 @@ CONFIG_SMC91X=y
664# 703#
665# CONFIG_WLAN_PRE80211 is not set 704# CONFIG_WLAN_PRE80211 is not set
666# CONFIG_WLAN_80211 is not set 705# CONFIG_WLAN_80211 is not set
667# CONFIG_IWLWIFI_LEDS is not set 706
707#
708# Enable WiMAX (Networking options) to see the WiMAX drivers
709#
668# CONFIG_WAN is not set 710# CONFIG_WAN is not set
669# CONFIG_PPP is not set 711# CONFIG_PPP is not set
670# CONFIG_SLIP is not set 712# CONFIG_SLIP is not set
@@ -708,15 +750,12 @@ CONFIG_INPUT_EVDEV=m
708# 750#
709# Character devices 751# Character devices
710# 752#
711# CONFIG_AD9960 is not set
712CONFIG_BFIN_DMA_INTERFACE=m 753CONFIG_BFIN_DMA_INTERFACE=m
713# CONFIG_BFIN_PPI is not set 754# CONFIG_BFIN_PPI is not set
714# CONFIG_BFIN_PPIFCD is not set 755# CONFIG_BFIN_PPIFCD is not set
715# CONFIG_BFIN_SIMPLE_TIMER is not set 756# CONFIG_BFIN_SIMPLE_TIMER is not set
716# CONFIG_BFIN_SPI_ADC is not set 757# CONFIG_BFIN_SPI_ADC is not set
717# CONFIG_BFIN_SPORT is not set 758# CONFIG_BFIN_SPORT is not set
718# CONFIG_BFIN_TIMER_LATENCY is not set
719CONFIG_SIMPLE_GPIO=m
720# CONFIG_VT is not set 759# CONFIG_VT is not set
721# CONFIG_DEVKMEM is not set 760# CONFIG_DEVKMEM is not set
722CONFIG_BFIN_JTAG_COMM=m 761CONFIG_BFIN_JTAG_COMM=m
@@ -730,6 +769,7 @@ CONFIG_BFIN_JTAG_COMM=m
730# 769#
731# Non-8250 serial port support 770# Non-8250 serial port support
732# 771#
772# CONFIG_SERIAL_MAX3100 is not set
733CONFIG_SERIAL_BFIN=y 773CONFIG_SERIAL_BFIN=y
734CONFIG_SERIAL_BFIN_CONSOLE=y 774CONFIG_SERIAL_BFIN_CONSOLE=y
735CONFIG_SERIAL_BFIN_DMA=y 775CONFIG_SERIAL_BFIN_DMA=y
@@ -740,6 +780,7 @@ CONFIG_SERIAL_CORE=y
740CONFIG_SERIAL_CORE_CONSOLE=y 780CONFIG_SERIAL_CORE_CONSOLE=y
741# CONFIG_SERIAL_BFIN_SPORT is not set 781# CONFIG_SERIAL_BFIN_SPORT is not set
742CONFIG_UNIX98_PTYS=y 782CONFIG_UNIX98_PTYS=y
783# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
743# CONFIG_LEGACY_PTYS is not set 784# CONFIG_LEGACY_PTYS is not set
744 785
745# 786#
@@ -763,13 +804,18 @@ CONFIG_SPI_BFIN=y
763# CONFIG_SPI_BFIN_LOCK is not set 804# CONFIG_SPI_BFIN_LOCK is not set
764# CONFIG_SPI_BFIN_SPORT is not set 805# CONFIG_SPI_BFIN_SPORT is not set
765# CONFIG_SPI_BITBANG is not set 806# CONFIG_SPI_BITBANG is not set
807# CONFIG_SPI_GPIO is not set
766 808
767# 809#
768# SPI Protocol Masters 810# SPI Protocol Masters
769# 811#
770# CONFIG_EEPROM_AT25 is not set
771# CONFIG_SPI_SPIDEV is not set 812# CONFIG_SPI_SPIDEV is not set
772# CONFIG_SPI_TLE62X0 is not set 813# CONFIG_SPI_TLE62X0 is not set
814
815#
816# PPS support
817#
818# CONFIG_PPS is not set
773CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 819CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
774CONFIG_GPIOLIB=y 820CONFIG_GPIOLIB=y
775# CONFIG_DEBUG_GPIO is not set 821# CONFIG_DEBUG_GPIO is not set
@@ -782,9 +828,6 @@ CONFIG_GPIO_SYSFS=y
782# 828#
783# I2C GPIO expanders: 829# I2C GPIO expanders:
784# 830#
785# CONFIG_GPIO_MAX732X is not set
786# CONFIG_GPIO_PCA953X is not set
787# CONFIG_GPIO_PCF857X is not set
788 831
789# 832#
790# PCI GPIO expanders: 833# PCI GPIO expanders:
@@ -822,23 +865,9 @@ CONFIG_SSB_POSSIBLE=y
822# CONFIG_MFD_SM501 is not set 865# CONFIG_MFD_SM501 is not set
823# CONFIG_HTC_PASIC3 is not set 866# CONFIG_HTC_PASIC3 is not set
824# CONFIG_MFD_TMIO is not set 867# CONFIG_MFD_TMIO is not set
868# CONFIG_EZX_PCAP is not set
825# CONFIG_REGULATOR is not set 869# CONFIG_REGULATOR is not set
826 870# CONFIG_MEDIA_SUPPORT is not set
827#
828# Multimedia devices
829#
830
831#
832# Multimedia core support
833#
834# CONFIG_VIDEO_DEV is not set
835# CONFIG_DVB_CORE is not set
836# CONFIG_VIDEO_MEDIA is not set
837
838#
839# Multimedia drivers
840#
841# CONFIG_DAB is not set
842 871
843# 872#
844# Graphics support 873# Graphics support
@@ -862,7 +891,6 @@ CONFIG_HID=m
862# 891#
863# Special HID drivers 892# Special HID drivers
864# 893#
865CONFIG_HID_COMPAT=y
866# CONFIG_USB_SUPPORT is not set 894# CONFIG_USB_SUPPORT is not set
867# CONFIG_MMC is not set 895# CONFIG_MMC is not set
868# CONFIG_MEMSTICK is not set 896# CONFIG_MEMSTICK is not set
@@ -870,10 +898,20 @@ CONFIG_HID_COMPAT=y
870# CONFIG_ACCESSIBILITY is not set 898# CONFIG_ACCESSIBILITY is not set
871# CONFIG_RTC_CLASS is not set 899# CONFIG_RTC_CLASS is not set
872# CONFIG_DMADEVICES is not set 900# CONFIG_DMADEVICES is not set
901# CONFIG_AUXDISPLAY is not set
873# CONFIG_UIO is not set 902# CONFIG_UIO is not set
903
904#
905# TI VLYNQ
906#
874# CONFIG_STAGING is not set 907# CONFIG_STAGING is not set
875 908
876# 909#
910# Firmware Drivers
911#
912# CONFIG_FIRMWARE_MEMMAP is not set
913
914#
877# File systems 915# File systems
878# 916#
879# CONFIG_EXT2_FS is not set 917# CONFIG_EXT2_FS is not set
@@ -882,9 +920,11 @@ CONFIG_HID_COMPAT=y
882# CONFIG_REISERFS_FS is not set 920# CONFIG_REISERFS_FS is not set
883# CONFIG_JFS_FS is not set 921# CONFIG_JFS_FS is not set
884# CONFIG_FS_POSIX_ACL is not set 922# CONFIG_FS_POSIX_ACL is not set
885CONFIG_FILE_LOCKING=y
886# CONFIG_XFS_FS is not set 923# CONFIG_XFS_FS is not set
887# CONFIG_OCFS2_FS is not set 924# CONFIG_OCFS2_FS is not set
925# CONFIG_BTRFS_FS is not set
926CONFIG_FILE_LOCKING=y
927CONFIG_FSNOTIFY=y
888# CONFIG_DNOTIFY is not set 928# CONFIG_DNOTIFY is not set
889CONFIG_INOTIFY=y 929CONFIG_INOTIFY=y
890CONFIG_INOTIFY_USER=y 930CONFIG_INOTIFY_USER=y
@@ -894,6 +934,11 @@ CONFIG_INOTIFY_USER=y
894# CONFIG_FUSE_FS is not set 934# CONFIG_FUSE_FS is not set
895 935
896# 936#
937# Caches
938#
939# CONFIG_FSCACHE is not set
940
941#
897# CD-ROM/DVD Filesystems 942# CD-ROM/DVD Filesystems
898# 943#
899# CONFIG_ISO9660_FS is not set 944# CONFIG_ISO9660_FS is not set
@@ -915,10 +960,7 @@ CONFIG_SYSFS=y
915# CONFIG_TMPFS is not set 960# CONFIG_TMPFS is not set
916# CONFIG_HUGETLB_PAGE is not set 961# CONFIG_HUGETLB_PAGE is not set
917# CONFIG_CONFIGFS_FS is not set 962# CONFIG_CONFIGFS_FS is not set
918 963CONFIG_MISC_FILESYSTEMS=y
919#
920# Miscellaneous filesystems
921#
922# CONFIG_ADFS_FS is not set 964# CONFIG_ADFS_FS is not set
923# CONFIG_AFFS_FS is not set 965# CONFIG_AFFS_FS is not set
924# CONFIG_HFS_FS is not set 966# CONFIG_HFS_FS is not set
@@ -937,17 +979,8 @@ CONFIG_JFFS2_ZLIB=y
937# CONFIG_JFFS2_LZO is not set 979# CONFIG_JFFS2_LZO is not set
938CONFIG_JFFS2_RTIME=y 980CONFIG_JFFS2_RTIME=y
939# CONFIG_JFFS2_RUBIN is not set 981# CONFIG_JFFS2_RUBIN is not set
940CONFIG_YAFFS_FS=m
941CONFIG_YAFFS_YAFFS1=y
942# CONFIG_YAFFS_9BYTE_TAGS is not set
943# CONFIG_YAFFS_DOES_ECC is not set
944CONFIG_YAFFS_YAFFS2=y
945CONFIG_YAFFS_AUTO_YAFFS2=y
946# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
947# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
948# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
949CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
950# CONFIG_CRAMFS is not set 982# CONFIG_CRAMFS is not set
983# CONFIG_SQUASHFS is not set
951# CONFIG_VXFS_FS is not set 984# CONFIG_VXFS_FS is not set
952# CONFIG_MINIX_FS is not set 985# CONFIG_MINIX_FS is not set
953# CONFIG_OMFS_FS is not set 986# CONFIG_OMFS_FS is not set
@@ -956,6 +989,7 @@ CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
956# CONFIG_ROMFS_FS is not set 989# CONFIG_ROMFS_FS is not set
957# CONFIG_SYSV_FS is not set 990# CONFIG_SYSV_FS is not set
958# CONFIG_UFS_FS is not set 991# CONFIG_UFS_FS is not set
992# CONFIG_NILFS2_FS is not set
959CONFIG_NETWORK_FILESYSTEMS=y 993CONFIG_NETWORK_FILESYSTEMS=y
960CONFIG_NFS_FS=m 994CONFIG_NFS_FS=m
961CONFIG_NFS_V3=y 995CONFIG_NFS_V3=y
@@ -966,7 +1000,6 @@ CONFIG_LOCKD=m
966CONFIG_LOCKD_V4=y 1000CONFIG_LOCKD_V4=y
967CONFIG_NFS_COMMON=y 1001CONFIG_NFS_COMMON=y
968CONFIG_SUNRPC=m 1002CONFIG_SUNRPC=m
969# CONFIG_SUNRPC_REGISTER_V4 is not set
970# CONFIG_RPCSEC_GSS_KRB5 is not set 1003# CONFIG_RPCSEC_GSS_KRB5 is not set
971# CONFIG_RPCSEC_GSS_SPKM3 is not set 1004# CONFIG_RPCSEC_GSS_SPKM3 is not set
972CONFIG_SMB_FS=m 1005CONFIG_SMB_FS=m
@@ -1034,11 +1067,15 @@ CONFIG_FRAME_WARN=1024
1034# CONFIG_UNUSED_SYMBOLS is not set 1067# CONFIG_UNUSED_SYMBOLS is not set
1035CONFIG_DEBUG_FS=y 1068CONFIG_DEBUG_FS=y
1036# CONFIG_HEADERS_CHECK is not set 1069# CONFIG_HEADERS_CHECK is not set
1070CONFIG_DEBUG_SECTION_MISMATCH=y
1037CONFIG_DEBUG_KERNEL=y 1071CONFIG_DEBUG_KERNEL=y
1038CONFIG_DEBUG_SHIRQ=y 1072CONFIG_DEBUG_SHIRQ=y
1039CONFIG_DETECT_SOFTLOCKUP=y 1073CONFIG_DETECT_SOFTLOCKUP=y
1040# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1074# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1041CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1075CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1076CONFIG_DETECT_HUNG_TASK=y
1077# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1078CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1042CONFIG_SCHED_DEBUG=y 1079CONFIG_SCHED_DEBUG=y
1043# CONFIG_SCHEDSTATS is not set 1080# CONFIG_SCHEDSTATS is not set
1044# CONFIG_TIMER_STATS is not set 1081# CONFIG_TIMER_STATS is not set
@@ -1046,16 +1083,21 @@ CONFIG_SCHED_DEBUG=y
1046# CONFIG_DEBUG_SLAB is not set 1083# CONFIG_DEBUG_SLAB is not set
1047# CONFIG_DEBUG_SPINLOCK is not set 1084# CONFIG_DEBUG_SPINLOCK is not set
1048# CONFIG_DEBUG_MUTEXES is not set 1085# CONFIG_DEBUG_MUTEXES is not set
1086# CONFIG_DEBUG_LOCK_ALLOC is not set
1087# CONFIG_PROVE_LOCKING is not set
1088# CONFIG_LOCK_STAT is not set
1049# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1089# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1050# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1090# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1051# CONFIG_DEBUG_KOBJECT is not set 1091# CONFIG_DEBUG_KOBJECT is not set
1052CONFIG_DEBUG_BUGVERBOSE=y 1092CONFIG_DEBUG_BUGVERBOSE=y
1053CONFIG_DEBUG_INFO=y 1093CONFIG_DEBUG_INFO=y
1054# CONFIG_DEBUG_VM is not set 1094# CONFIG_DEBUG_VM is not set
1095# CONFIG_DEBUG_NOMMU_REGIONS is not set
1055# CONFIG_DEBUG_WRITECOUNT is not set 1096# CONFIG_DEBUG_WRITECOUNT is not set
1056# CONFIG_DEBUG_MEMORY_INIT is not set 1097# CONFIG_DEBUG_MEMORY_INIT is not set
1057# CONFIG_DEBUG_LIST is not set 1098# CONFIG_DEBUG_LIST is not set
1058# CONFIG_DEBUG_SG is not set 1099# CONFIG_DEBUG_SG is not set
1100# CONFIG_DEBUG_NOTIFIERS is not set
1059# CONFIG_FRAME_POINTER is not set 1101# CONFIG_FRAME_POINTER is not set
1060# CONFIG_BOOT_PRINTK_DELAY is not set 1102# CONFIG_BOOT_PRINTK_DELAY is not set
1061# CONFIG_RCU_TORTURE_TEST is not set 1103# CONFIG_RCU_TORTURE_TEST is not set
@@ -1063,17 +1105,19 @@ CONFIG_DEBUG_INFO=y
1063# CONFIG_BACKTRACE_SELF_TEST is not set 1105# CONFIG_BACKTRACE_SELF_TEST is not set
1064# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1106# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1065# CONFIG_FAULT_INJECTION is not set 1107# CONFIG_FAULT_INJECTION is not set
1066 1108# CONFIG_PAGE_POISONING is not set
1067# 1109CONFIG_HAVE_FUNCTION_TRACER=y
1068# Tracers 1110CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1069# 1111CONFIG_TRACING_SUPPORT=y
1070# CONFIG_SCHED_TRACER is not set 1112# CONFIG_FTRACE is not set
1071# CONFIG_CONTEXT_SWITCH_TRACER is not set 1113# CONFIG_BRANCH_PROFILE_NONE is not set
1072# CONFIG_BOOT_TRACER is not set 1114# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1073# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1115# CONFIG_PROFILE_ALL_BRANCHES is not set
1116# CONFIG_DYNAMIC_DEBUG is not set
1074# CONFIG_SAMPLES is not set 1117# CONFIG_SAMPLES is not set
1075CONFIG_HAVE_ARCH_KGDB=y 1118CONFIG_HAVE_ARCH_KGDB=y
1076# CONFIG_KGDB is not set 1119# CONFIG_KGDB is not set
1120# CONFIG_KMEMCHECK is not set
1077# CONFIG_DEBUG_STACKOVERFLOW is not set 1121# CONFIG_DEBUG_STACKOVERFLOW is not set
1078# CONFIG_DEBUG_STACK_USAGE is not set 1122# CONFIG_DEBUG_STACK_USAGE is not set
1079CONFIG_DEBUG_VERBOSE=y 1123CONFIG_DEBUG_VERBOSE=y
@@ -1095,16 +1139,15 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y
1095CONFIG_EARLY_PRINTK=y 1139CONFIG_EARLY_PRINTK=y
1096CONFIG_CPLB_INFO=y 1140CONFIG_CPLB_INFO=y
1097CONFIG_ACCESS_CHECK=y 1141CONFIG_ACCESS_CHECK=y
1142# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1098 1143
1099# 1144#
1100# Security options 1145# Security options
1101# 1146#
1102# CONFIG_KEYS is not set 1147# CONFIG_KEYS is not set
1103CONFIG_SECURITY=y 1148# CONFIG_SECURITY is not set
1104# CONFIG_SECURITYFS is not set 1149# CONFIG_SECURITYFS is not set
1105# CONFIG_SECURITY_NETWORK is not set
1106# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1150# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1107CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1108CONFIG_CRYPTO=y 1151CONFIG_CRYPTO=y
1109 1152
1110# 1153#
@@ -1183,6 +1226,7 @@ CONFIG_CRYPTO=y
1183# Compression 1226# Compression
1184# 1227#
1185# CONFIG_CRYPTO_DEFLATE is not set 1228# CONFIG_CRYPTO_DEFLATE is not set
1229# CONFIG_CRYPTO_ZLIB is not set
1186# CONFIG_CRYPTO_LZO is not set 1230# CONFIG_CRYPTO_LZO is not set
1187 1231
1188# 1232#
@@ -1190,11 +1234,13 @@ CONFIG_CRYPTO=y
1190# 1234#
1191# CONFIG_CRYPTO_ANSI_CPRNG is not set 1235# CONFIG_CRYPTO_ANSI_CPRNG is not set
1192CONFIG_CRYPTO_HW=y 1236CONFIG_CRYPTO_HW=y
1237# CONFIG_BINARY_PRINTF is not set
1193 1238
1194# 1239#
1195# Library routines 1240# Library routines
1196# 1241#
1197CONFIG_BITREVERSE=y 1242CONFIG_BITREVERSE=y
1243CONFIG_GENERIC_FIND_LAST_BIT=y
1198CONFIG_CRC_CCITT=m 1244CONFIG_CRC_CCITT=m
1199# CONFIG_CRC16 is not set 1245# CONFIG_CRC16 is not set
1200# CONFIG_CRC_T10DIF is not set 1246# CONFIG_CRC_T10DIF is not set
@@ -1204,6 +1250,8 @@ CONFIG_CRC32=y
1204# CONFIG_LIBCRC32C is not set 1250# CONFIG_LIBCRC32C is not set
1205CONFIG_ZLIB_INFLATE=y 1251CONFIG_ZLIB_INFLATE=y
1206CONFIG_ZLIB_DEFLATE=m 1252CONFIG_ZLIB_DEFLATE=m
1253CONFIG_DECOMPRESS_GZIP=y
1207CONFIG_HAS_IOMEM=y 1254CONFIG_HAS_IOMEM=y
1208CONFIG_HAS_IOPORT=y 1255CONFIG_HAS_IOPORT=y
1209CONFIG_HAS_DMA=y 1256CONFIG_HAS_DMA=y
1257CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 5d944ffd4ab0..9e65d885ec0b 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -66,6 +66,7 @@ CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_SLAB=y 66CONFIG_SLAB=y
67# CONFIG_SLUB is not set 67# CONFIG_SLUB is not set
68# CONFIG_SLOB is not set 68# CONFIG_SLOB is not set
69CONFIG_MMAP_ALLOW_UNINITIALIZED=y
69# CONFIG_PROFILING is not set 70# CONFIG_PROFILING is not set
70# CONFIG_MARKERS is not set 71# CONFIG_MARKERS is not set
71CONFIG_HAVE_OPROFILE=y 72CONFIG_HAVE_OPROFILE=y
@@ -275,6 +276,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
275# CONFIG_RESOURCES_64BIT is not set 276# CONFIG_RESOURCES_64BIT is not set
276CONFIG_ZONE_DMA_FLAG=1 277CONFIG_ZONE_DMA_FLAG=1
277CONFIG_VIRT_TO_BUS=y 278CONFIG_VIRT_TO_BUS=y
279CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
278CONFIG_BFIN_GPTIMERS=y 280CONFIG_BFIN_GPTIMERS=y
279# CONFIG_DMA_UNCACHED_4M is not set 281# CONFIG_DMA_UNCACHED_4M is not set
280# CONFIG_DMA_UNCACHED_2M is not set 282# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 648a31d01bf4..4432150d89e3 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -1,12 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28 3# Linux kernel version: 2.6.30.5
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
10CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
@@ -15,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
15CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
16CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
17CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
19 23
20# 24#
@@ -25,55 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
25CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
26CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
27CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
28CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
29CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
30# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
31# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
32# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
33# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
34CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
35CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
36CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
37# CONFIG_CGROUPS is not set
38# CONFIG_GROUP_SCHED is not set 56# CONFIG_GROUP_SCHED is not set
39CONFIG_SYSFS_DEPRECATED=y 57# CONFIG_CGROUPS is not set
40CONFIG_SYSFS_DEPRECATED_V2=y 58# CONFIG_SYSFS_DEPRECATED_V2 is not set
41# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
42# CONFIG_NAMESPACES is not set 60# CONFIG_NAMESPACES is not set
43CONFIG_BLK_DEV_INITRD=y 61CONFIG_BLK_DEV_INITRD=y
44CONFIG_INITRAMFS_SOURCE="" 62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
45# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
46# CONFIG_SYSCTL is not set 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
47CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
48CONFIG_UID16=y 70CONFIG_UID16=y
49# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
50CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
51# CONFIG_KALLSYMS_ALL is not set
52# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
53CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
54CONFIG_PRINTK=y 76CONFIG_PRINTK=y
55CONFIG_BUG=y 77CONFIG_BUG=y
56# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
57CONFIG_COMPAT_BRK=y
58CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
59# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
60CONFIG_ANON_INODES=y
61CONFIG_EPOLL=y 81CONFIG_EPOLL=y
62CONFIG_SIGNALFD=y 82CONFIG_SIGNALFD=y
63CONFIG_TIMERFD=y 83CONFIG_TIMERFD=y
64CONFIG_EVENTFD=y 84CONFIG_EVENTFD=y
65# CONFIG_AIO is not set 85# CONFIG_AIO is not set
66CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
87CONFIG_COMPAT_BRK=y
67CONFIG_SLAB=y 88CONFIG_SLAB=y
68# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set 93# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
73# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
74CONFIG_SLABINFO=y 97CONFIG_SLABINFO=y
75CONFIG_RT_MUTEXES=y
76CONFIG_TINY_SHMEM=y
77CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
78CONFIG_MODULES=y 99CONFIG_MODULES=y
79# CONFIG_MODULE_FORCE_LOAD is not set 100# CONFIG_MODULE_FORCE_LOAD is not set
@@ -81,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
81# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
82# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
83# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
84CONFIG_KMOD=y
85CONFIG_BLOCK=y 105CONFIG_BLOCK=y
86# CONFIG_LBD is not set 106# CONFIG_LBD is not set
87# CONFIG_BLK_DEV_IO_TRACE is not set
88# CONFIG_LSF is not set
89# CONFIG_BLK_DEV_BSG is not set 107# CONFIG_BLK_DEV_BSG is not set
90# CONFIG_BLK_DEV_INTEGRITY is not set 108# CONFIG_BLK_DEV_INTEGRITY is not set
91 109
@@ -101,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
101CONFIG_DEFAULT_CFQ=y 119CONFIG_DEFAULT_CFQ=y
102# CONFIG_DEFAULT_NOOP is not set 120# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="cfq" 121CONFIG_DEFAULT_IOSCHED="cfq"
104CONFIG_CLASSIC_RCU=y
105# CONFIG_PREEMPT_NONE is not set 122# CONFIG_PREEMPT_NONE is not set
106CONFIG_PREEMPT_VOLUNTARY=y 123CONFIG_PREEMPT_VOLUNTARY=y
107# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
@@ -265,7 +282,10 @@ CONFIG_HZ=250
265# CONFIG_SCHED_HRTICK is not set 282# CONFIG_SCHED_HRTICK is not set
266CONFIG_GENERIC_TIME=y 283CONFIG_GENERIC_TIME=y
267CONFIG_GENERIC_CLOCKEVENTS=y 284CONFIG_GENERIC_CLOCKEVENTS=y
285# CONFIG_TICKSOURCE_GPTMR0 is not set
286CONFIG_TICKSOURCE_CORETMR=y
268# CONFIG_CYCLES_CLOCKSOURCE is not set 287# CONFIG_CYCLES_CLOCKSOURCE is not set
288# CONFIG_GPTMR0_CLOCKSOURCE is not set
269# CONFIG_NO_HZ is not set 289# CONFIG_NO_HZ is not set
270# CONFIG_HIGH_RES_TIMERS is not set 290# CONFIG_HIGH_RES_TIMERS is not set
271CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 291CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -315,10 +335,12 @@ CONFIG_FLATMEM=y
315CONFIG_FLAT_NODE_MEM_MAP=y 335CONFIG_FLAT_NODE_MEM_MAP=y
316CONFIG_PAGEFLAGS_EXTENDED=y 336CONFIG_PAGEFLAGS_EXTENDED=y
317CONFIG_SPLIT_PTLOCK_CPUS=4 337CONFIG_SPLIT_PTLOCK_CPUS=4
318# CONFIG_RESOURCES_64BIT is not set
319# CONFIG_PHYS_ADDR_T_64BIT is not set 338# CONFIG_PHYS_ADDR_T_64BIT is not set
320CONFIG_ZONE_DMA_FLAG=1 339CONFIG_ZONE_DMA_FLAG=1
321CONFIG_VIRT_TO_BUS=y 340CONFIG_VIRT_TO_BUS=y
341CONFIG_UNEVICTABLE_LRU=y
342CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
343CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
322CONFIG_BFIN_GPTIMERS=y 344CONFIG_BFIN_GPTIMERS=y
323# CONFIG_DMA_UNCACHED_4M is not set 345# CONFIG_DMA_UNCACHED_4M is not set
324# CONFIG_DMA_UNCACHED_2M is not set 346# CONFIG_DMA_UNCACHED_2M is not set
@@ -329,10 +351,9 @@ CONFIG_DMA_UNCACHED_1M=y
329# Cache Support 351# Cache Support
330# 352#
331CONFIG_BFIN_ICACHE=y 353CONFIG_BFIN_ICACHE=y
332# CONFIG_BFIN_ICACHE_LOCK is not set 354CONFIG_BFIN_EXTMEM_ICACHEABLE=y
333CONFIG_BFIN_DCACHE=y 355CONFIG_BFIN_DCACHE=y
334# CONFIG_BFIN_DCACHE_BANKA is not set 356# CONFIG_BFIN_DCACHE_BANKA is not set
335CONFIG_BFIN_EXTMEM_ICACHEABLE=y
336CONFIG_BFIN_EXTMEM_DCACHEABLE=y 357CONFIG_BFIN_EXTMEM_DCACHEABLE=y
337CONFIG_BFIN_EXTMEM_WRITEBACK=y 358CONFIG_BFIN_EXTMEM_WRITEBACK=y
338# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 359# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -343,7 +364,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
343# CONFIG_MPU is not set 364# CONFIG_MPU is not set
344 365
345# 366#
346# Asynchonous Memory Configuration 367# Asynchronous Memory Configuration
347# 368#
348 369
349# 370#
@@ -361,7 +382,7 @@ CONFIG_C_AMBEN_ALL=y
361# EBIU_AMBCTL Control 382# EBIU_AMBCTL Control
362# 383#
363CONFIG_BANK_0=0x7BB0 384CONFIG_BANK_0=0x7BB0
364CONFIG_BANK_1=0x5554 385CONFIG_BANK_1=0x7BB0
365CONFIG_BANK_2=0x7BB0 386CONFIG_BANK_2=0x7BB0
366CONFIG_BANK_3=0xFFC0 387CONFIG_BANK_3=0xFFC0
367 388
@@ -386,7 +407,6 @@ CONFIG_BINFMT_ZFLAT=y
386# 407#
387# CONFIG_PM is not set 408# CONFIG_PM is not set
388CONFIG_ARCH_SUSPEND_POSSIBLE=y 409CONFIG_ARCH_SUSPEND_POSSIBLE=y
389# CONFIG_PM_WAKEUP_BY_GPIO is not set
390 410
391# 411#
392# CPU Frequency scaling 412# CPU Frequency scaling
@@ -400,11 +420,6 @@ CONFIG_NET=y
400CONFIG_PACKET=y 420CONFIG_PACKET=y
401# CONFIG_PACKET_MMAP is not set 421# CONFIG_PACKET_MMAP is not set
402CONFIG_UNIX=y 422CONFIG_UNIX=y
403CONFIG_XFRM=y
404# CONFIG_XFRM_USER is not set
405# CONFIG_XFRM_SUB_POLICY is not set
406# CONFIG_XFRM_MIGRATE is not set
407# CONFIG_XFRM_STATISTICS is not set
408# CONFIG_NET_KEY is not set 423# CONFIG_NET_KEY is not set
409CONFIG_INET=y 424CONFIG_INET=y
410# CONFIG_IP_MULTICAST is not set 425# CONFIG_IP_MULTICAST is not set
@@ -428,7 +443,6 @@ CONFIG_IP_PNP=y
428# CONFIG_INET_XFRM_MODE_BEET is not set 443# CONFIG_INET_XFRM_MODE_BEET is not set
429# CONFIG_INET_LRO is not set 444# CONFIG_INET_LRO is not set
430# CONFIG_INET_DIAG is not set 445# CONFIG_INET_DIAG is not set
431CONFIG_INET_TCP_DIAG=y
432# CONFIG_TCP_CONG_ADVANCED is not set 446# CONFIG_TCP_CONG_ADVANCED is not set
433CONFIG_TCP_CONG_CUBIC=y 447CONFIG_TCP_CONG_CUBIC=y
434CONFIG_DEFAULT_TCP_CONG="cubic" 448CONFIG_DEFAULT_TCP_CONG="cubic"
@@ -452,7 +466,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
452# CONFIG_LAPB is not set 466# CONFIG_LAPB is not set
453# CONFIG_ECONET is not set 467# CONFIG_ECONET is not set
454# CONFIG_WAN_ROUTER is not set 468# CONFIG_WAN_ROUTER is not set
469# CONFIG_PHONET is not set
455# CONFIG_NET_SCHED is not set 470# CONFIG_NET_SCHED is not set
471# CONFIG_DCB is not set
456 472
457# 473#
458# Network testing 474# Network testing
@@ -463,13 +479,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
463# CONFIG_IRDA is not set 479# CONFIG_IRDA is not set
464# CONFIG_BT is not set 480# CONFIG_BT is not set
465# CONFIG_AF_RXRPC is not set 481# CONFIG_AF_RXRPC is not set
466# CONFIG_PHONET is not set 482# CONFIG_WIRELESS is not set
467CONFIG_WIRELESS=y 483# CONFIG_WIMAX is not set
468# CONFIG_CFG80211 is not set
469CONFIG_WIRELESS_OLD_REGULATORY=y
470# CONFIG_WIRELESS_EXT is not set
471# CONFIG_MAC80211 is not set
472# CONFIG_IEEE80211 is not set
473# CONFIG_RFKILL is not set 484# CONFIG_RFKILL is not set
474# CONFIG_NET_9P is not set 485# CONFIG_NET_9P is not set
475 486
@@ -484,22 +495,21 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
484CONFIG_STANDALONE=y 495CONFIG_STANDALONE=y
485CONFIG_PREVENT_FIRMWARE_BUILD=y 496CONFIG_PREVENT_FIRMWARE_BUILD=y
486# CONFIG_FW_LOADER is not set 497# CONFIG_FW_LOADER is not set
487# CONFIG_DEBUG_DRIVER is not set
488# CONFIG_DEBUG_DEVRES is not set
489# CONFIG_SYS_HYPERVISOR is not set 498# CONFIG_SYS_HYPERVISOR is not set
490# CONFIG_CONNECTOR is not set 499# CONFIG_CONNECTOR is not set
491CONFIG_MTD=y 500CONFIG_MTD=y
492# CONFIG_MTD_DEBUG is not set 501# CONFIG_MTD_DEBUG is not set
502# CONFIG_MTD_TESTS is not set
493# CONFIG_MTD_CONCAT is not set 503# CONFIG_MTD_CONCAT is not set
494CONFIG_MTD_PARTITIONS=y 504CONFIG_MTD_PARTITIONS=y
495# CONFIG_MTD_REDBOOT_PARTS is not set 505# CONFIG_MTD_REDBOOT_PARTS is not set
496# CONFIG_MTD_CMDLINE_PARTS is not set 506CONFIG_MTD_CMDLINE_PARTS=y
497# CONFIG_MTD_AR7_PARTS is not set 507# CONFIG_MTD_AR7_PARTS is not set
498 508
499# 509#
500# User Modules And Translation Layers 510# User Modules And Translation Layers
501# 511#
502CONFIG_MTD_CHAR=m 512CONFIG_MTD_CHAR=y
503CONFIG_MTD_BLKDEVS=y 513CONFIG_MTD_BLKDEVS=y
504CONFIG_MTD_BLOCK=y 514CONFIG_MTD_BLOCK=y
505# CONFIG_FTL is not set 515# CONFIG_FTL is not set
@@ -512,9 +522,9 @@ CONFIG_MTD_BLOCK=y
512# 522#
513# RAM/ROM/Flash chip drivers 523# RAM/ROM/Flash chip drivers
514# 524#
515# CONFIG_MTD_CFI is not set 525CONFIG_MTD_CFI=y
516CONFIG_MTD_JEDECPROBE=m 526# CONFIG_MTD_JEDECPROBE is not set
517CONFIG_MTD_GEN_PROBE=m 527CONFIG_MTD_GEN_PROBE=y
518# CONFIG_MTD_CFI_ADV_OPTIONS is not set 528# CONFIG_MTD_CFI_ADV_OPTIONS is not set
519CONFIG_MTD_MAP_BANK_WIDTH_1=y 529CONFIG_MTD_MAP_BANK_WIDTH_1=y
520CONFIG_MTD_MAP_BANK_WIDTH_2=y 530CONFIG_MTD_MAP_BANK_WIDTH_2=y
@@ -526,9 +536,11 @@ CONFIG_MTD_CFI_I1=y
526CONFIG_MTD_CFI_I2=y 536CONFIG_MTD_CFI_I2=y
527# CONFIG_MTD_CFI_I4 is not set 537# CONFIG_MTD_CFI_I4 is not set
528# CONFIG_MTD_CFI_I8 is not set 538# CONFIG_MTD_CFI_I8 is not set
529# CONFIG_MTD_CFI_INTELEXT is not set 539CONFIG_MTD_CFI_INTELEXT=y
530# CONFIG_MTD_CFI_AMDSTD is not set 540# CONFIG_MTD_CFI_AMDSTD is not set
531# CONFIG_MTD_CFI_STAA is not set 541# CONFIG_MTD_CFI_STAA is not set
542# CONFIG_MTD_PSD4256G is not set
543CONFIG_MTD_CFI_UTIL=y
532CONFIG_MTD_RAM=y 544CONFIG_MTD_RAM=y
533CONFIG_MTD_ROM=m 545CONFIG_MTD_ROM=m
534# CONFIG_MTD_ABSENT is not set 546# CONFIG_MTD_ABSENT is not set
@@ -538,7 +550,7 @@ CONFIG_MTD_ROM=m
538# 550#
539CONFIG_MTD_COMPLEX_MAPPINGS=y 551CONFIG_MTD_COMPLEX_MAPPINGS=y
540# CONFIG_MTD_PHYSMAP is not set 552# CONFIG_MTD_PHYSMAP is not set
541# CONFIG_MTD_GPIO_ADDR is not set 553CONFIG_MTD_GPIO_ADDR=y
542# CONFIG_MTD_UCLINUX is not set 554# CONFIG_MTD_UCLINUX is not set
543# CONFIG_MTD_PLATRAM is not set 555# CONFIG_MTD_PLATRAM is not set
544 556
@@ -562,6 +574,11 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
562# CONFIG_MTD_ONENAND is not set 574# CONFIG_MTD_ONENAND is not set
563 575
564# 576#
577# LPDDR flash memory drivers
578#
579# CONFIG_MTD_LPDDR is not set
580
581#
565# UBI - Unsorted block images 582# UBI - Unsorted block images
566# 583#
567# CONFIG_MTD_UBI is not set 584# CONFIG_MTD_UBI is not set
@@ -586,12 +603,46 @@ CONFIG_HAVE_IDE=y
586# SCSI device support 603# SCSI device support
587# 604#
588# CONFIG_RAID_ATTRS is not set 605# CONFIG_RAID_ATTRS is not set
589# CONFIG_SCSI is not set 606CONFIG_SCSI=y
590# CONFIG_SCSI_DMA is not set 607CONFIG_SCSI_DMA=y
608# CONFIG_SCSI_TGT is not set
591# CONFIG_SCSI_NETLINK is not set 609# CONFIG_SCSI_NETLINK is not set
610CONFIG_SCSI_PROC_FS=y
611
612#
613# SCSI support type (disk, tape, CD-ROM)
614#
615CONFIG_BLK_DEV_SD=y
616# CONFIG_CHR_DEV_ST is not set
617# CONFIG_CHR_DEV_OSST is not set
618# CONFIG_BLK_DEV_SR is not set
619# CONFIG_CHR_DEV_SG is not set
620# CONFIG_CHR_DEV_SCH is not set
621
622#
623# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
624#
625# CONFIG_SCSI_MULTI_LUN is not set
626# CONFIG_SCSI_CONSTANTS is not set
627# CONFIG_SCSI_LOGGING is not set
628# CONFIG_SCSI_SCAN_ASYNC is not set
629CONFIG_SCSI_WAIT_SCAN=m
630
631#
632# SCSI Transports
633#
634# CONFIG_SCSI_SPI_ATTRS is not set
635# CONFIG_SCSI_FC_ATTRS is not set
636# CONFIG_SCSI_ISCSI_ATTRS is not set
637# CONFIG_SCSI_SAS_LIBSAS is not set
638# CONFIG_SCSI_SRP_ATTRS is not set
639# CONFIG_SCSI_LOWLEVEL is not set
640# CONFIG_SCSI_DH is not set
641# CONFIG_SCSI_OSD_INITIATOR is not set
592# CONFIG_ATA is not set 642# CONFIG_ATA is not set
593# CONFIG_MD is not set 643# CONFIG_MD is not set
594CONFIG_NETDEVICES=y 644CONFIG_NETDEVICES=y
645CONFIG_COMPAT_NET_DEV_OPS=y
595# CONFIG_DUMMY is not set 646# CONFIG_DUMMY is not set
596# CONFIG_BONDING is not set 647# CONFIG_BONDING is not set
597# CONFIG_MACVLAN is not set 648# CONFIG_MACVLAN is not set
@@ -613,6 +664,9 @@ CONFIG_PHYLIB=y
613# CONFIG_BROADCOM_PHY is not set 664# CONFIG_BROADCOM_PHY is not set
614# CONFIG_ICPLUS_PHY is not set 665# CONFIG_ICPLUS_PHY is not set
615# CONFIG_REALTEK_PHY is not set 666# CONFIG_REALTEK_PHY is not set
667# CONFIG_NATIONAL_PHY is not set
668# CONFIG_STE10XP is not set
669# CONFIG_LSI_ET1011C_PHY is not set
616# CONFIG_FIXED_PHY is not set 670# CONFIG_FIXED_PHY is not set
617# CONFIG_MDIO_BITBANG is not set 671# CONFIG_MDIO_BITBANG is not set
618CONFIG_NET_ETHERNET=y 672CONFIG_NET_ETHERNET=y
@@ -623,9 +677,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
623CONFIG_BFIN_RX_DESC_NUM=20 677CONFIG_BFIN_RX_DESC_NUM=20
624CONFIG_BFIN_MAC_RMII=y 678CONFIG_BFIN_MAC_RMII=y
625# CONFIG_SMC91X is not set 679# CONFIG_SMC91X is not set
626# CONFIG_SMSC911X is not set
627# CONFIG_DM9000 is not set 680# CONFIG_DM9000 is not set
628# CONFIG_ENC28J60 is not set 681# CONFIG_ENC28J60 is not set
682# CONFIG_ETHOC is not set
683# CONFIG_SMSC911X is not set
684# CONFIG_DNET is not set
629# CONFIG_IBM_NEW_EMAC_ZMII is not set 685# CONFIG_IBM_NEW_EMAC_ZMII is not set
630# CONFIG_IBM_NEW_EMAC_RGMII is not set 686# CONFIG_IBM_NEW_EMAC_RGMII is not set
631# CONFIG_IBM_NEW_EMAC_TAH is not set 687# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -633,6 +689,7 @@ CONFIG_BFIN_MAC_RMII=y
633# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set 689# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
634# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set 690# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
635# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set 691# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
692# CONFIG_B44 is not set
636# CONFIG_NETDEV_1000 is not set 693# CONFIG_NETDEV_1000 is not set
637# CONFIG_NETDEV_10000 is not set 694# CONFIG_NETDEV_10000 is not set
638 695
@@ -641,7 +698,10 @@ CONFIG_BFIN_MAC_RMII=y
641# 698#
642# CONFIG_WLAN_PRE80211 is not set 699# CONFIG_WLAN_PRE80211 is not set
643# CONFIG_WLAN_80211 is not set 700# CONFIG_WLAN_80211 is not set
644# CONFIG_IWLWIFI_LEDS is not set 701
702#
703# Enable WiMAX (Networking options) to see the WiMAX drivers
704#
645 705
646# 706#
647# USB Network Adapters 707# USB Network Adapters
@@ -674,17 +734,13 @@ CONFIG_BFIN_MAC_RMII=y
674# 734#
675# Character devices 735# Character devices
676# 736#
677# CONFIG_AD9960 is not set 737CONFIG_BFIN_DMA_INTERFACE=m
678# CONFIG_SPI_ADC_BF533 is not set 738# CONFIG_BFIN_PPI is not set
679# CONFIG_BF5xx_PPIFCD is not set 739# CONFIG_BFIN_PPIFCD is not set
680# CONFIG_BFIN_SIMPLE_TIMER is not set 740# CONFIG_BFIN_SIMPLE_TIMER is not set
681# CONFIG_BF5xx_PPI is not set 741# CONFIG_BFIN_SPI_ADC is not set
682# CONFIG_BF5xx_EPPI is not set
683# CONFIG_BFIN_SPORT is not set 742# CONFIG_BFIN_SPORT is not set
684# CONFIG_BFIN_TIMER_LATENCY is not set 743# CONFIG_BFIN_TWI_LCD is not set
685# CONFIG_TWI_LCD is not set
686CONFIG_BFIN_DMA_INTERFACE=m
687CONFIG_SIMPLE_GPIO=m
688# CONFIG_VT is not set 744# CONFIG_VT is not set
689# CONFIG_DEVKMEM is not set 745# CONFIG_DEVKMEM is not set
690# CONFIG_BFIN_JTAG_COMM is not set 746# CONFIG_BFIN_JTAG_COMM is not set
@@ -698,6 +754,7 @@ CONFIG_SIMPLE_GPIO=m
698# 754#
699# Non-8250 serial port support 755# Non-8250 serial port support
700# 756#
757# CONFIG_SERIAL_MAX3100 is not set
701CONFIG_SERIAL_BFIN=y 758CONFIG_SERIAL_BFIN=y
702CONFIG_SERIAL_BFIN_CONSOLE=y 759CONFIG_SERIAL_BFIN_CONSOLE=y
703CONFIG_SERIAL_BFIN_DMA=y 760CONFIG_SERIAL_BFIN_DMA=y
@@ -710,6 +767,7 @@ CONFIG_SERIAL_CORE=y
710CONFIG_SERIAL_CORE_CONSOLE=y 767CONFIG_SERIAL_CORE_CONSOLE=y
711# CONFIG_SERIAL_BFIN_SPORT is not set 768# CONFIG_SERIAL_BFIN_SPORT is not set
712CONFIG_UNIX98_PTYS=y 769CONFIG_UNIX98_PTYS=y
770# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
713# CONFIG_LEGACY_PTYS is not set 771# CONFIG_LEGACY_PTYS is not set
714CONFIG_BFIN_OTP=y 772CONFIG_BFIN_OTP=y
715# CONFIG_BFIN_OTP_WRITE_ENABLE is not set 773# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
@@ -758,13 +816,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
758# Miscellaneous I2C Chip support 816# Miscellaneous I2C Chip support
759# 817#
760# CONFIG_DS1682 is not set 818# CONFIG_DS1682 is not set
761# CONFIG_AT24 is not set
762# CONFIG_SENSORS_AD5252 is not set
763# CONFIG_SENSORS_EEPROM is not set
764# CONFIG_SENSORS_PCF8574 is not set 819# CONFIG_SENSORS_PCF8574 is not set
765# CONFIG_PCF8575 is not set 820# CONFIG_PCF8575 is not set
766# CONFIG_SENSORS_PCA9539 is not set 821# CONFIG_SENSORS_PCA9539 is not set
767# CONFIG_SENSORS_PCF8591 is not set
768# CONFIG_SENSORS_MAX6875 is not set 822# CONFIG_SENSORS_MAX6875 is not set
769# CONFIG_SENSORS_TSL2550 is not set 823# CONFIG_SENSORS_TSL2550 is not set
770# CONFIG_I2C_DEBUG_CORE is not set 824# CONFIG_I2C_DEBUG_CORE is not set
@@ -772,7 +826,6 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
772# CONFIG_I2C_DEBUG_BUS is not set 826# CONFIG_I2C_DEBUG_BUS is not set
773# CONFIG_I2C_DEBUG_CHIP is not set 827# CONFIG_I2C_DEBUG_CHIP is not set
774CONFIG_SPI=y 828CONFIG_SPI=y
775# CONFIG_SPI_DEBUG is not set
776CONFIG_SPI_MASTER=y 829CONFIG_SPI_MASTER=y
777 830
778# 831#
@@ -780,17 +833,17 @@ CONFIG_SPI_MASTER=y
780# 833#
781CONFIG_SPI_BFIN=y 834CONFIG_SPI_BFIN=y
782# CONFIG_SPI_BFIN_LOCK is not set 835# CONFIG_SPI_BFIN_LOCK is not set
836# CONFIG_SPI_BFIN_SPORT is not set
783# CONFIG_SPI_BITBANG is not set 837# CONFIG_SPI_BITBANG is not set
838# CONFIG_SPI_GPIO is not set
784 839
785# 840#
786# SPI Protocol Masters 841# SPI Protocol Masters
787# 842#
788# CONFIG_SPI_AT25 is not set
789# CONFIG_SPI_SPIDEV is not set 843# CONFIG_SPI_SPIDEV is not set
790# CONFIG_SPI_TLE62X0 is not set 844# CONFIG_SPI_TLE62X0 is not set
791CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 845CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
792CONFIG_GPIOLIB=y 846CONFIG_GPIOLIB=y
793# CONFIG_DEBUG_GPIO is not set
794CONFIG_GPIO_SYSFS=y 847CONFIG_GPIO_SYSFS=y
795 848
796# 849#
@@ -803,6 +856,7 @@ CONFIG_GPIO_SYSFS=y
803# CONFIG_GPIO_MAX732X is not set 856# CONFIG_GPIO_MAX732X is not set
804# CONFIG_GPIO_PCA953X is not set 857# CONFIG_GPIO_PCA953X is not set
805# CONFIG_GPIO_PCF857X is not set 858# CONFIG_GPIO_PCF857X is not set
859# CONFIG_GPIO_ADP5588 is not set
806 860
807# 861#
808# PCI GPIO expanders: 862# PCI GPIO expanders:
@@ -829,11 +883,13 @@ CONFIG_HWMON=y
829# CONFIG_SENSORS_ADT7462 is not set 883# CONFIG_SENSORS_ADT7462 is not set
830# CONFIG_SENSORS_ADT7470 is not set 884# CONFIG_SENSORS_ADT7470 is not set
831# CONFIG_SENSORS_ADT7473 is not set 885# CONFIG_SENSORS_ADT7473 is not set
886# CONFIG_SENSORS_ADT7475 is not set
832# CONFIG_SENSORS_ATXP1 is not set 887# CONFIG_SENSORS_ATXP1 is not set
833# CONFIG_SENSORS_DS1621 is not set 888# CONFIG_SENSORS_DS1621 is not set
834# CONFIG_SENSORS_F71805F is not set 889# CONFIG_SENSORS_F71805F is not set
835# CONFIG_SENSORS_F71882FG is not set 890# CONFIG_SENSORS_F71882FG is not set
836# CONFIG_SENSORS_F75375S is not set 891# CONFIG_SENSORS_F75375S is not set
892# CONFIG_SENSORS_G760A is not set
837# CONFIG_SENSORS_GL518SM is not set 893# CONFIG_SENSORS_GL518SM is not set
838# CONFIG_SENSORS_GL520SM is not set 894# CONFIG_SENSORS_GL520SM is not set
839# CONFIG_SENSORS_IT87 is not set 895# CONFIG_SENSORS_IT87 is not set
@@ -849,11 +905,16 @@ CONFIG_HWMON=y
849# CONFIG_SENSORS_LM90 is not set 905# CONFIG_SENSORS_LM90 is not set
850# CONFIG_SENSORS_LM92 is not set 906# CONFIG_SENSORS_LM92 is not set
851# CONFIG_SENSORS_LM93 is not set 907# CONFIG_SENSORS_LM93 is not set
908# CONFIG_SENSORS_LTC4215 is not set
909# CONFIG_SENSORS_LTC4245 is not set
910# CONFIG_SENSORS_LM95241 is not set
852# CONFIG_SENSORS_MAX1111 is not set 911# CONFIG_SENSORS_MAX1111 is not set
853# CONFIG_SENSORS_MAX1619 is not set 912# CONFIG_SENSORS_MAX1619 is not set
854# CONFIG_SENSORS_MAX6650 is not set 913# CONFIG_SENSORS_MAX6650 is not set
855# CONFIG_SENSORS_PC87360 is not set 914# CONFIG_SENSORS_PC87360 is not set
856# CONFIG_SENSORS_PC87427 is not set 915# CONFIG_SENSORS_PC87427 is not set
916# CONFIG_SENSORS_PCF8591 is not set
917# CONFIG_SENSORS_SHT15 is not set
857# CONFIG_SENSORS_DME1737 is not set 918# CONFIG_SENSORS_DME1737 is not set
858# CONFIG_SENSORS_SMSC47M1 is not set 919# CONFIG_SENSORS_SMSC47M1 is not set
859# CONFIG_SENSORS_SMSC47M192 is not set 920# CONFIG_SENSORS_SMSC47M192 is not set
@@ -885,6 +946,12 @@ CONFIG_BFIN_WDT=y
885# USB-based Watchdog Cards 946# USB-based Watchdog Cards
886# 947#
887# CONFIG_USBPCWATCHDOG is not set 948# CONFIG_USBPCWATCHDOG is not set
949CONFIG_SSB_POSSIBLE=y
950
951#
952# Sonics Silicon Backplane
953#
954# CONFIG_SSB is not set
888 955
889# 956#
890# Multifunction device drivers 957# Multifunction device drivers
@@ -892,10 +959,14 @@ CONFIG_BFIN_WDT=y
892# CONFIG_MFD_CORE is not set 959# CONFIG_MFD_CORE is not set
893# CONFIG_MFD_SM501 is not set 960# CONFIG_MFD_SM501 is not set
894# CONFIG_HTC_PASIC3 is not set 961# CONFIG_HTC_PASIC3 is not set
962# CONFIG_TPS65010 is not set
963# CONFIG_TWL4030_CORE is not set
895# CONFIG_MFD_TMIO is not set 964# CONFIG_MFD_TMIO is not set
896# CONFIG_PMIC_DA903X is not set 965# CONFIG_PMIC_DA903X is not set
966# CONFIG_PMIC_ADP5520 is not set
897# CONFIG_MFD_WM8400 is not set 967# CONFIG_MFD_WM8400 is not set
898# CONFIG_MFD_WM8350_I2C is not set 968# CONFIG_MFD_WM8350_I2C is not set
969# CONFIG_MFD_PCF50633 is not set
899# CONFIG_REGULATOR is not set 970# CONFIG_REGULATOR is not set
900 971
901# 972#
@@ -931,20 +1002,20 @@ CONFIG_USB_SUPPORT=y
931CONFIG_USB_ARCH_HAS_HCD=y 1002CONFIG_USB_ARCH_HAS_HCD=y
932# CONFIG_USB_ARCH_HAS_OHCI is not set 1003# CONFIG_USB_ARCH_HAS_OHCI is not set
933# CONFIG_USB_ARCH_HAS_EHCI is not set 1004# CONFIG_USB_ARCH_HAS_EHCI is not set
934CONFIG_USB=y 1005CONFIG_USB=m
935# CONFIG_USB_DEBUG is not set 1006# CONFIG_USB_DEBUG is not set
936# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set 1007CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
937 1008
938# 1009#
939# Miscellaneous USB options 1010# Miscellaneous USB options
940# 1011#
941# CONFIG_USB_DEVICEFS is not set 1012CONFIG_USB_DEVICEFS=y
942CONFIG_USB_DEVICE_CLASS=y 1013# CONFIG_USB_DEVICE_CLASS is not set
943# CONFIG_USB_DYNAMIC_MINORS is not set 1014# CONFIG_USB_DYNAMIC_MINORS is not set
944# CONFIG_USB_OTG is not set 1015# CONFIG_USB_OTG is not set
945# CONFIG_USB_OTG_WHITELIST is not set 1016# CONFIG_USB_OTG_WHITELIST is not set
946CONFIG_USB_OTG_BLACKLIST_HUB=y 1017CONFIG_USB_OTG_BLACKLIST_HUB=y
947CONFIG_USB_MON=y 1018CONFIG_USB_MON=m
948# CONFIG_USB_WUSB is not set 1019# CONFIG_USB_WUSB is not set
949# CONFIG_USB_WUSB_CBAF is not set 1020# CONFIG_USB_WUSB_CBAF is not set
950 1021
@@ -952,24 +1023,24 @@ CONFIG_USB_MON=y
952# USB Host Controller Drivers 1023# USB Host Controller Drivers
953# 1024#
954# CONFIG_USB_C67X00_HCD is not set 1025# CONFIG_USB_C67X00_HCD is not set
1026# CONFIG_USB_OXU210HP_HCD is not set
955# CONFIG_USB_ISP116X_HCD is not set 1027# CONFIG_USB_ISP116X_HCD is not set
956# CONFIG_USB_ISP1760_HCD is not set 1028# CONFIG_USB_ISP1760_HCD is not set
957# CONFIG_USB_ISP1362_HCD is not set 1029# CONFIG_USB_ISP1362_HCD is not set
958# CONFIG_USB_SL811_HCD is not set 1030# CONFIG_USB_SL811_HCD is not set
959# CONFIG_USB_R8A66597_HCD is not set 1031# CONFIG_USB_R8A66597_HCD is not set
960# CONFIG_USB_HWA_HCD is not set 1032# CONFIG_USB_HWA_HCD is not set
961CONFIG_USB_MUSB_HDRC=y 1033CONFIG_USB_MUSB_HDRC=m
962CONFIG_USB_MUSB_SOC=y 1034CONFIG_USB_MUSB_SOC=y
963 1035
964# 1036#
965# Blackfin high speed USB Support 1037# Blackfin high speed USB Support
966# 1038#
967CONFIG_USB_MUSB_HOST=y 1039# CONFIG_USB_MUSB_HOST is not set
968# CONFIG_USB_MUSB_PERIPHERAL is not set 1040CONFIG_USB_MUSB_PERIPHERAL=y
969# CONFIG_USB_MUSB_OTG is not set 1041# CONFIG_USB_MUSB_OTG is not set
970CONFIG_USB_MUSB_HDRC_HCD=y 1042CONFIG_USB_GADGET_MUSB_HDRC=y
971CONFIG_MUSB_PIO_ONLY=y 1043CONFIG_MUSB_PIO_ONLY=y
972CONFIG_MUSB_DMA_POLL=y
973# CONFIG_USB_MUSB_DEBUG is not set 1044# CONFIG_USB_MUSB_DEBUG is not set
974 1045
975# 1046#
@@ -981,18 +1052,31 @@ CONFIG_MUSB_DMA_POLL=y
981# CONFIG_USB_TMC is not set 1052# CONFIG_USB_TMC is not set
982 1053
983# 1054#
984# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 1055# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
985# 1056#
986 1057
987# 1058#
988# see USB_STORAGE Help for more information 1059# also be needed; see USB_STORAGE Help for more info
989# 1060#
1061CONFIG_USB_STORAGE=m
1062# CONFIG_USB_STORAGE_DEBUG is not set
1063# CONFIG_USB_STORAGE_DATAFAB is not set
1064# CONFIG_USB_STORAGE_FREECOM is not set
1065# CONFIG_USB_STORAGE_ISD200 is not set
1066# CONFIG_USB_STORAGE_USBAT is not set
1067# CONFIG_USB_STORAGE_SDDR09 is not set
1068# CONFIG_USB_STORAGE_SDDR55 is not set
1069# CONFIG_USB_STORAGE_JUMPSHOT is not set
1070# CONFIG_USB_STORAGE_ALAUDA is not set
1071# CONFIG_USB_STORAGE_KARMA is not set
1072# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
990# CONFIG_USB_LIBUSUAL is not set 1073# CONFIG_USB_LIBUSUAL is not set
991 1074
992# 1075#
993# USB Imaging devices 1076# USB Imaging devices
994# 1077#
995# CONFIG_USB_MDC800 is not set 1078# CONFIG_USB_MDC800 is not set
1079# CONFIG_USB_MICROTEK is not set
996 1080
997# 1081#
998# USB port drivers 1082# USB port drivers
@@ -1013,7 +1097,6 @@ CONFIG_MUSB_DMA_POLL=y
1013# CONFIG_USB_LED is not set 1097# CONFIG_USB_LED is not set
1014# CONFIG_USB_CYPRESS_CY7C63 is not set 1098# CONFIG_USB_CYPRESS_CY7C63 is not set
1015# CONFIG_USB_CYTHERM is not set 1099# CONFIG_USB_CYTHERM is not set
1016# CONFIG_USB_PHIDGET is not set
1017# CONFIG_USB_IDMOUSE is not set 1100# CONFIG_USB_IDMOUSE is not set
1018# CONFIG_USB_FTDI_ELAN is not set 1101# CONFIG_USB_FTDI_ELAN is not set
1019# CONFIG_USB_APPLEDISPLAY is not set 1102# CONFIG_USB_APPLEDISPLAY is not set
@@ -1021,9 +1104,50 @@ CONFIG_MUSB_DMA_POLL=y
1021# CONFIG_USB_LD is not set 1104# CONFIG_USB_LD is not set
1022# CONFIG_USB_TRANCEVIBRATOR is not set 1105# CONFIG_USB_TRANCEVIBRATOR is not set
1023# CONFIG_USB_IOWARRIOR is not set 1106# CONFIG_USB_IOWARRIOR is not set
1107# CONFIG_USB_TEST is not set
1024# CONFIG_USB_ISIGHTFW is not set 1108# CONFIG_USB_ISIGHTFW is not set
1025# CONFIG_USB_VST is not set 1109# CONFIG_USB_VST is not set
1026# CONFIG_USB_GADGET is not set 1110CONFIG_USB_GADGET=m
1111# CONFIG_USB_GADGET_DEBUG_FILES is not set
1112# CONFIG_USB_GADGET_DEBUG_FS is not set
1113CONFIG_USB_GADGET_VBUS_DRAW=2
1114CONFIG_USB_GADGET_SELECTED=y
1115# CONFIG_USB_GADGET_AT91 is not set
1116# CONFIG_USB_GADGET_ATMEL_USBA is not set
1117# CONFIG_USB_GADGET_FSL_USB2 is not set
1118# CONFIG_USB_GADGET_LH7A40X is not set
1119# CONFIG_USB_GADGET_OMAP is not set
1120# CONFIG_USB_GADGET_PXA25X is not set
1121# CONFIG_USB_GADGET_PXA27X is not set
1122# CONFIG_USB_GADGET_S3C2410 is not set
1123# CONFIG_USB_GADGET_IMX is not set
1124# CONFIG_USB_GADGET_M66592 is not set
1125# CONFIG_USB_GADGET_AMD5536UDC is not set
1126# CONFIG_USB_GADGET_FSL_QE is not set
1127# CONFIG_USB_GADGET_CI13XXX is not set
1128# CONFIG_USB_GADGET_NET2272 is not set
1129# CONFIG_USB_GADGET_NET2280 is not set
1130# CONFIG_USB_GADGET_GOKU is not set
1131# CONFIG_USB_GADGET_DUMMY_HCD is not set
1132CONFIG_USB_GADGET_DUALSPEED=y
1133# CONFIG_USB_ZERO is not set
1134# CONFIG_USB_AUDIO is not set
1135CONFIG_USB_ETH=m
1136CONFIG_USB_ETH_RNDIS=y
1137# CONFIG_USB_GADGETFS is not set
1138CONFIG_USB_FILE_STORAGE=m
1139# CONFIG_USB_FILE_STORAGE_TEST is not set
1140CONFIG_USB_G_SERIAL=m
1141# CONFIG_USB_MIDI_GADGET is not set
1142CONFIG_USB_G_PRINTER=m
1143# CONFIG_USB_CDC_COMPOSITE is not set
1144
1145#
1146# OTG and related infrastructure
1147#
1148CONFIG_USB_OTG_UTILS=y
1149# CONFIG_USB_GPIO_VBUS is not set
1150# CONFIG_NOP_USB_XCEIV is not set
1027# CONFIG_MMC is not set 1151# CONFIG_MMC is not set
1028# CONFIG_MEMSTICK is not set 1152# CONFIG_MEMSTICK is not set
1029# CONFIG_NEW_LEDS is not set 1153# CONFIG_NEW_LEDS is not set
@@ -1090,6 +1214,7 @@ CONFIG_RTC_INTF_DEV=y
1090# 1214#
1091CONFIG_RTC_DRV_BFIN=y 1215CONFIG_RTC_DRV_BFIN=y
1092# CONFIG_DMADEVICES is not set 1216# CONFIG_DMADEVICES is not set
1217# CONFIG_AUXDISPLAY is not set
1093# CONFIG_UIO is not set 1218# CONFIG_UIO is not set
1094# CONFIG_STAGING is not set 1219# CONFIG_STAGING is not set
1095 1220
@@ -1102,9 +1227,10 @@ CONFIG_RTC_DRV_BFIN=y
1102# CONFIG_REISERFS_FS is not set 1227# CONFIG_REISERFS_FS is not set
1103# CONFIG_JFS_FS is not set 1228# CONFIG_JFS_FS is not set
1104# CONFIG_FS_POSIX_ACL is not set 1229# CONFIG_FS_POSIX_ACL is not set
1105CONFIG_FILE_LOCKING=y
1106# CONFIG_XFS_FS is not set 1230# CONFIG_XFS_FS is not set
1107# CONFIG_OCFS2_FS is not set 1231# CONFIG_OCFS2_FS is not set
1232# CONFIG_BTRFS_FS is not set
1233CONFIG_FILE_LOCKING=y
1108# CONFIG_DNOTIFY is not set 1234# CONFIG_DNOTIFY is not set
1109CONFIG_INOTIFY=y 1235CONFIG_INOTIFY=y
1110CONFIG_INOTIFY_USER=y 1236CONFIG_INOTIFY_USER=y
@@ -1114,6 +1240,11 @@ CONFIG_INOTIFY_USER=y
1114# CONFIG_FUSE_FS is not set 1240# CONFIG_FUSE_FS is not set
1115 1241
1116# 1242#
1243# Caches
1244#
1245# CONFIG_FSCACHE is not set
1246
1247#
1117# CD-ROM/DVD Filesystems 1248# CD-ROM/DVD Filesystems
1118# 1249#
1119# CONFIG_ISO9660_FS is not set 1250# CONFIG_ISO9660_FS is not set
@@ -1122,8 +1253,11 @@ CONFIG_INOTIFY_USER=y
1122# 1253#
1123# DOS/FAT/NT Filesystems 1254# DOS/FAT/NT Filesystems
1124# 1255#
1125# CONFIG_MSDOS_FS is not set 1256CONFIG_FAT_FS=y
1126# CONFIG_VFAT_FS is not set 1257CONFIG_MSDOS_FS=y
1258CONFIG_VFAT_FS=y
1259CONFIG_FAT_DEFAULT_CODEPAGE=437
1260CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1127# CONFIG_NTFS_FS is not set 1261# CONFIG_NTFS_FS is not set
1128 1262
1129# 1263#
@@ -1135,10 +1269,7 @@ CONFIG_SYSFS=y
1135# CONFIG_TMPFS is not set 1269# CONFIG_TMPFS is not set
1136# CONFIG_HUGETLB_PAGE is not set 1270# CONFIG_HUGETLB_PAGE is not set
1137# CONFIG_CONFIGFS_FS is not set 1271# CONFIG_CONFIGFS_FS is not set
1138 1272CONFIG_MISC_FILESYSTEMS=y
1139#
1140# Miscellaneous filesystems
1141#
1142# CONFIG_ADFS_FS is not set 1273# CONFIG_ADFS_FS is not set
1143# CONFIG_AFFS_FS is not set 1274# CONFIG_AFFS_FS is not set
1144# CONFIG_HFS_FS is not set 1275# CONFIG_HFS_FS is not set
@@ -1146,9 +1277,19 @@ CONFIG_SYSFS=y
1146# CONFIG_BEFS_FS is not set 1277# CONFIG_BEFS_FS is not set
1147# CONFIG_BFS_FS is not set 1278# CONFIG_BFS_FS is not set
1148# CONFIG_EFS_FS is not set 1279# CONFIG_EFS_FS is not set
1149# CONFIG_YAFFS_FS is not set 1280CONFIG_JFFS2_FS=y
1150# CONFIG_JFFS2_FS is not set 1281CONFIG_JFFS2_FS_DEBUG=0
1282CONFIG_JFFS2_FS_WRITEBUFFER=y
1283# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1284# CONFIG_JFFS2_SUMMARY is not set
1285# CONFIG_JFFS2_FS_XATTR is not set
1286# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1287CONFIG_JFFS2_ZLIB=y
1288# CONFIG_JFFS2_LZO is not set
1289CONFIG_JFFS2_RTIME=y
1290# CONFIG_JFFS2_RUBIN is not set
1151# CONFIG_CRAMFS is not set 1291# CONFIG_CRAMFS is not set
1292# CONFIG_SQUASHFS is not set
1152# CONFIG_VXFS_FS is not set 1293# CONFIG_VXFS_FS is not set
1153# CONFIG_MINIX_FS is not set 1294# CONFIG_MINIX_FS is not set
1154# CONFIG_OMFS_FS is not set 1295# CONFIG_OMFS_FS is not set
@@ -1157,6 +1298,7 @@ CONFIG_SYSFS=y
1157# CONFIG_ROMFS_FS is not set 1298# CONFIG_ROMFS_FS is not set
1158# CONFIG_SYSV_FS is not set 1299# CONFIG_SYSV_FS is not set
1159# CONFIG_UFS_FS is not set 1300# CONFIG_UFS_FS is not set
1301# CONFIG_NILFS2_FS is not set
1160CONFIG_NETWORK_FILESYSTEMS=y 1302CONFIG_NETWORK_FILESYSTEMS=y
1161CONFIG_NFS_FS=m 1303CONFIG_NFS_FS=m
1162CONFIG_NFS_V3=y 1304CONFIG_NFS_V3=y
@@ -1167,7 +1309,6 @@ CONFIG_LOCKD=m
1167CONFIG_LOCKD_V4=y 1309CONFIG_LOCKD_V4=y
1168CONFIG_NFS_COMMON=y 1310CONFIG_NFS_COMMON=y
1169CONFIG_SUNRPC=m 1311CONFIG_SUNRPC=m
1170# CONFIG_SUNRPC_REGISTER_V4 is not set
1171# CONFIG_RPCSEC_GSS_KRB5 is not set 1312# CONFIG_RPCSEC_GSS_KRB5 is not set
1172# CONFIG_RPCSEC_GSS_SPKM3 is not set 1313# CONFIG_RPCSEC_GSS_SPKM3 is not set
1173CONFIG_SMB_FS=m 1314CONFIG_SMB_FS=m
@@ -1182,9 +1323,9 @@ CONFIG_SMB_FS=m
1182# 1323#
1183# CONFIG_PARTITION_ADVANCED is not set 1324# CONFIG_PARTITION_ADVANCED is not set
1184CONFIG_MSDOS_PARTITION=y 1325CONFIG_MSDOS_PARTITION=y
1185CONFIG_NLS=m 1326CONFIG_NLS=y
1186CONFIG_NLS_DEFAULT="iso8859-1" 1327CONFIG_NLS_DEFAULT="iso8859-1"
1187# CONFIG_NLS_CODEPAGE_437 is not set 1328CONFIG_NLS_CODEPAGE_437=y
1188# CONFIG_NLS_CODEPAGE_737 is not set 1329# CONFIG_NLS_CODEPAGE_737 is not set
1189# CONFIG_NLS_CODEPAGE_775 is not set 1330# CONFIG_NLS_CODEPAGE_775 is not set
1190# CONFIG_NLS_CODEPAGE_850 is not set 1331# CONFIG_NLS_CODEPAGE_850 is not set
@@ -1208,7 +1349,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1208# CONFIG_NLS_CODEPAGE_1250 is not set 1349# CONFIG_NLS_CODEPAGE_1250 is not set
1209# CONFIG_NLS_CODEPAGE_1251 is not set 1350# CONFIG_NLS_CODEPAGE_1251 is not set
1210# CONFIG_NLS_ASCII is not set 1351# CONFIG_NLS_ASCII is not set
1211# CONFIG_NLS_ISO8859_1 is not set 1352CONFIG_NLS_ISO8859_1=y
1212# CONFIG_NLS_ISO8859_2 is not set 1353# CONFIG_NLS_ISO8859_2 is not set
1213# CONFIG_NLS_ISO8859_3 is not set 1354# CONFIG_NLS_ISO8859_3 is not set
1214# CONFIG_NLS_ISO8859_4 is not set 1355# CONFIG_NLS_ISO8859_4 is not set
@@ -1235,55 +1376,34 @@ CONFIG_FRAME_WARN=1024
1235# CONFIG_UNUSED_SYMBOLS is not set 1376# CONFIG_UNUSED_SYMBOLS is not set
1236CONFIG_DEBUG_FS=y 1377CONFIG_DEBUG_FS=y
1237# CONFIG_HEADERS_CHECK is not set 1378# CONFIG_HEADERS_CHECK is not set
1238CONFIG_DEBUG_KERNEL=y 1379CONFIG_DEBUG_SECTION_MISMATCH=y
1239# CONFIG_DEBUG_SHIRQ is not set 1380# CONFIG_DEBUG_KERNEL is not set
1240CONFIG_DETECT_SOFTLOCKUP=y 1381# CONFIG_DEBUG_BUGVERBOSE is not set
1241# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1242CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1243# CONFIG_SCHED_DEBUG is not set
1244# CONFIG_SCHEDSTATS is not set
1245# CONFIG_TIMER_STATS is not set
1246# CONFIG_DEBUG_OBJECTS is not set
1247# CONFIG_DEBUG_SLAB is not set
1248# CONFIG_DEBUG_RT_MUTEXES is not set
1249# CONFIG_RT_MUTEX_TESTER is not set
1250# CONFIG_DEBUG_SPINLOCK is not set
1251# CONFIG_DEBUG_MUTEXES is not set
1252# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1253# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1254# CONFIG_DEBUG_KOBJECT is not set
1255CONFIG_DEBUG_BUGVERBOSE=y
1256# CONFIG_DEBUG_INFO is not set
1257# CONFIG_DEBUG_VM is not set
1258# CONFIG_DEBUG_WRITECOUNT is not set
1259# CONFIG_DEBUG_MEMORY_INIT is not set 1382# CONFIG_DEBUG_MEMORY_INIT is not set
1260# CONFIG_DEBUG_LIST is not set
1261# CONFIG_DEBUG_SG is not set
1262# CONFIG_FRAME_POINTER is not set
1263# CONFIG_BOOT_PRINTK_DELAY is not set
1264# CONFIG_RCU_TORTURE_TEST is not set
1265# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1383# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1266# CONFIG_BACKTRACE_SELF_TEST is not set 1384CONFIG_HAVE_FUNCTION_TRACER=y
1267# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1385CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1268# CONFIG_FAULT_INJECTION is not set 1386CONFIG_TRACING_SUPPORT=y
1269# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1270 1387
1271# 1388#
1272# Tracers 1389# Tracers
1273# 1390#
1391# CONFIG_FUNCTION_TRACER is not set
1392# CONFIG_IRQSOFF_TRACER is not set
1274# CONFIG_SCHED_TRACER is not set 1393# CONFIG_SCHED_TRACER is not set
1275# CONFIG_CONTEXT_SWITCH_TRACER is not set 1394# CONFIG_CONTEXT_SWITCH_TRACER is not set
1395# CONFIG_EVENT_TRACER is not set
1276# CONFIG_BOOT_TRACER is not set 1396# CONFIG_BOOT_TRACER is not set
1277# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1397# CONFIG_TRACE_BRANCH_PROFILING is not set
1398# CONFIG_STACK_TRACER is not set
1399# CONFIG_KMEMTRACE is not set
1400# CONFIG_WORKQUEUE_TRACER is not set
1401# CONFIG_BLK_DEV_IO_TRACE is not set
1402# CONFIG_DYNAMIC_DEBUG is not set
1278# CONFIG_SAMPLES is not set 1403# CONFIG_SAMPLES is not set
1279CONFIG_HAVE_ARCH_KGDB=y 1404CONFIG_HAVE_ARCH_KGDB=y
1280# CONFIG_KGDB is not set
1281# CONFIG_DEBUG_STACKOVERFLOW is not set
1282# CONFIG_DEBUG_STACK_USAGE is not set
1283# CONFIG_KGDB_TESTCASE is not set
1284CONFIG_DEBUG_VERBOSE=y 1405CONFIG_DEBUG_VERBOSE=y
1285CONFIG_DEBUG_MMRS=y 1406# CONFIG_DEBUG_MMRS is not set
1286# CONFIG_DEBUG_HWERR is not set
1287# CONFIG_DEBUG_DOUBLEFAULT is not set 1407# CONFIG_DEBUG_DOUBLEFAULT is not set
1288CONFIG_DEBUG_HUNT_FOR_ZERO=y 1408CONFIG_DEBUG_HUNT_FOR_ZERO=y
1289CONFIG_DEBUG_BFIN_HWTRACE_ON=y 1409CONFIG_DEBUG_BFIN_HWTRACE_ON=y
@@ -1293,9 +1413,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1293CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1413CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1294# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1414# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1295# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1415# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1296# CONFIG_EARLY_PRINTK is not set 1416CONFIG_EARLY_PRINTK=y
1297# CONFIG_CPLB_INFO is not set 1417# CONFIG_CPLB_INFO is not set
1298CONFIG_ACCESS_CHECK=y 1418CONFIG_ACCESS_CHECK=y
1419# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1299 1420
1300# 1421#
1301# Security options 1422# Security options
@@ -1304,9 +1425,9 @@ CONFIG_ACCESS_CHECK=y
1304CONFIG_SECURITY=y 1425CONFIG_SECURITY=y
1305# CONFIG_SECURITYFS is not set 1426# CONFIG_SECURITYFS is not set
1306# CONFIG_SECURITY_NETWORK is not set 1427# CONFIG_SECURITY_NETWORK is not set
1428# CONFIG_SECURITY_PATH is not set
1307# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1429# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1308# CONFIG_SECURITY_ROOTPLUG is not set 1430# CONFIG_SECURITY_TOMOYO is not set
1309CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1310CONFIG_CRYPTO=y 1431CONFIG_CRYPTO=y
1311 1432
1312# 1433#
@@ -1385,6 +1506,7 @@ CONFIG_CRYPTO=y
1385# Compression 1506# Compression
1386# 1507#
1387# CONFIG_CRYPTO_DEFLATE is not set 1508# CONFIG_CRYPTO_DEFLATE is not set
1509# CONFIG_CRYPTO_ZLIB is not set
1388# CONFIG_CRYPTO_LZO is not set 1510# CONFIG_CRYPTO_LZO is not set
1389 1511
1390# 1512#
@@ -1392,20 +1514,24 @@ CONFIG_CRYPTO=y
1392# 1514#
1393# CONFIG_CRYPTO_ANSI_CPRNG is not set 1515# CONFIG_CRYPTO_ANSI_CPRNG is not set
1394CONFIG_CRYPTO_HW=y 1516CONFIG_CRYPTO_HW=y
1517# CONFIG_BINARY_PRINTF is not set
1395 1518
1396# 1519#
1397# Library routines 1520# Library routines
1398# 1521#
1399CONFIG_BITREVERSE=y 1522CONFIG_BITREVERSE=y
1523CONFIG_GENERIC_FIND_LAST_BIT=y
1400CONFIG_CRC_CCITT=m 1524CONFIG_CRC_CCITT=m
1401# CONFIG_CRC16 is not set 1525# CONFIG_CRC16 is not set
1402# CONFIG_CRC_T10DIF is not set 1526# CONFIG_CRC_T10DIF is not set
1403# CONFIG_CRC_ITU_T is not set 1527CONFIG_CRC_ITU_T=y
1404CONFIG_CRC32=y 1528CONFIG_CRC32=y
1405# CONFIG_CRC7 is not set 1529CONFIG_CRC7=y
1406# CONFIG_LIBCRC32C is not set 1530# CONFIG_LIBCRC32C is not set
1407CONFIG_ZLIB_INFLATE=y 1531CONFIG_ZLIB_INFLATE=y
1408CONFIG_PLIST=y 1532CONFIG_ZLIB_DEFLATE=y
1533CONFIG_DECOMPRESS_LZMA=y
1409CONFIG_HAS_IOMEM=y 1534CONFIG_HAS_IOMEM=y
1410CONFIG_HAS_IOPORT=y 1535CONFIG_HAS_IOPORT=y
1411CONFIG_HAS_DMA=y 1536CONFIG_HAS_DMA=y
1537CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index ae665b93b875..df56639ab2f2 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -1,94 +1,110 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.16 3# Linux kernel version: 2.6.30.5
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
10CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
11CONFIG_SEMAPHORE_SLEEPERS=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y 14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y 15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_TIME=y
17CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
18CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
19CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
20CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
21 23
22# 24#
23# Code maturity level options 25# General setup
24# 26#
25CONFIG_EXPERIMENTAL=y 27CONFIG_EXPERIMENTAL=y
26CONFIG_BROKEN_ON_SMP=y 28CONFIG_BROKEN_ON_SMP=y
27CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
28
29#
30# General setup
31#
32CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
33CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
34CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
35# CONFIG_IPC_NS is not set
36CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
37# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
38# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
39# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
40# CONFIG_UTS_NS is not set
41# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
42CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
43CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
44CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
45# CONFIG_SYSFS_DEPRECATED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
58# CONFIG_SYSFS_DEPRECATED_V2 is not set
46# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
47# CONFIG_BLK_DEV_INITRD is not set 60# CONFIG_NAMESPACES is not set
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 61CONFIG_BLK_DEV_INITRD=y
49# CONFIG_SYSCTL is not set 62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
66CONFIG_CC_OPTIMIZE_FOR_SIZE=y
67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
50CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
51# CONFIG_UID16 is not set 70# CONFIG_UID16 is not set
52# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
53CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
55# CONFIG_HOTPLUG is not set 74# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y
56CONFIG_PRINTK=y 76CONFIG_PRINTK=y
57CONFIG_BUG=y 77CONFIG_BUG=y
58# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
59CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
60# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y 81CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y 82CONFIG_SIGNALFD=y
83CONFIG_TIMERFD=y
64CONFIG_EVENTFD=y 84CONFIG_EVENTFD=y
85CONFIG_AIO=y
65CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 87CONFIG_COMPAT_BRK=y
67# CONFIG_NP2 is not set
68CONFIG_SLAB=y 88CONFIG_SLAB=y
69# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
70# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
71CONFIG_RT_MUTEXES=y 91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
72CONFIG_TINY_SHMEM=y 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
97CONFIG_SLABINFO=y
73CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
74
75#
76# Loadable module support
77#
78CONFIG_MODULES=y 99CONFIG_MODULES=y
79CONFIG_MODULE_UNLOAD=y 100# CONFIG_MODULE_FORCE_LOAD is not set
80# CONFIG_MODULE_FORCE_UNLOAD is not set 101# CONFIG_MODULE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set 102# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set 103# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84
85#
86# Block layer
87#
88CONFIG_BLOCK=y 104CONFIG_BLOCK=y
89# CONFIG_LBD is not set 105# CONFIG_LBD is not set
90# CONFIG_BLK_DEV_IO_TRACE is not set 106# CONFIG_BLK_DEV_BSG is not set
91# CONFIG_LSF is not set 107# CONFIG_BLK_DEV_INTEGRITY is not set
92 108
93# 109#
94# IO Schedulers 110# IO Schedulers
@@ -96,7 +112,7 @@ CONFIG_BLOCK=y
96CONFIG_IOSCHED_NOOP=y 112CONFIG_IOSCHED_NOOP=y
97# CONFIG_IOSCHED_AS is not set 113# CONFIG_IOSCHED_AS is not set
98# CONFIG_IOSCHED_DEADLINE is not set 114# CONFIG_IOSCHED_DEADLINE is not set
99CONFIG_IOSCHED_CFQ=y 115# CONFIG_IOSCHED_CFQ is not set
100# CONFIG_DEFAULT_AS is not set 116# CONFIG_DEFAULT_AS is not set
101# CONFIG_DEFAULT_DEADLINE is not set 117# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set 118# CONFIG_DEFAULT_CFQ is not set
@@ -105,6 +121,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
105CONFIG_PREEMPT_NONE=y 121CONFIG_PREEMPT_NONE=y
106# CONFIG_PREEMPT_VOLUNTARY is not set 122# CONFIG_PREEMPT_VOLUNTARY is not set
107# CONFIG_PREEMPT is not set 123# CONFIG_PREEMPT is not set
124# CONFIG_FREEZER is not set
108 125
109# 126#
110# Blackfin Processor Options 127# Blackfin Processor Options
@@ -113,6 +130,10 @@ CONFIG_PREEMPT_NONE=y
113# 130#
114# Processor and Board Settings 131# Processor and Board Settings
115# 132#
133# CONFIG_BF512 is not set
134# CONFIG_BF514 is not set
135# CONFIG_BF516 is not set
136# CONFIG_BF518 is not set
116# CONFIG_BF522 is not set 137# CONFIG_BF522 is not set
117# CONFIG_BF523 is not set 138# CONFIG_BF523 is not set
118# CONFIG_BF524 is not set 139# CONFIG_BF524 is not set
@@ -125,28 +146,38 @@ CONFIG_BF533=y
125# CONFIG_BF534 is not set 146# CONFIG_BF534 is not set
126# CONFIG_BF536 is not set 147# CONFIG_BF536 is not set
127# CONFIG_BF537 is not set 148# CONFIG_BF537 is not set
149# CONFIG_BF538 is not set
150# CONFIG_BF539 is not set
128# CONFIG_BF542 is not set 151# CONFIG_BF542 is not set
152# CONFIG_BF542M is not set
129# CONFIG_BF544 is not set 153# CONFIG_BF544 is not set
154# CONFIG_BF544M is not set
130# CONFIG_BF547 is not set 155# CONFIG_BF547 is not set
156# CONFIG_BF547M is not set
131# CONFIG_BF548 is not set 157# CONFIG_BF548 is not set
158# CONFIG_BF548M is not set
132# CONFIG_BF549 is not set 159# CONFIG_BF549 is not set
160# CONFIG_BF549M is not set
133# CONFIG_BF561 is not set 161# CONFIG_BF561 is not set
162CONFIG_BF_REV_MIN=3
163CONFIG_BF_REV_MAX=6
134# CONFIG_BF_REV_0_0 is not set 164# CONFIG_BF_REV_0_0 is not set
135# CONFIG_BF_REV_0_1 is not set 165# CONFIG_BF_REV_0_1 is not set
136# CONFIG_BF_REV_0_2 is not set 166# CONFIG_BF_REV_0_2 is not set
137CONFIG_BF_REV_0_3=y 167CONFIG_BF_REV_0_3=y
138# CONFIG_BF_REV_0_4 is not set 168# CONFIG_BF_REV_0_4 is not set
139# CONFIG_BF_REV_0_5 is not set 169# CONFIG_BF_REV_0_5 is not set
170# CONFIG_BF_REV_0_6 is not set
140# CONFIG_BF_REV_ANY is not set 171# CONFIG_BF_REV_ANY is not set
141# CONFIG_BF_REV_NONE is not set 172# CONFIG_BF_REV_NONE is not set
142CONFIG_BF53x=y 173CONFIG_BF53x=y
143CONFIG_BFIN_SINGLE_CORE=y
144CONFIG_MEM_MT48LC16M16A2TG_75=y 174CONFIG_MEM_MT48LC16M16A2TG_75=y
145# CONFIG_BFIN533_EZKIT is not set 175# CONFIG_BFIN533_EZKIT is not set
146# CONFIG_BFIN533_STAMP is not set 176# CONFIG_BFIN533_STAMP is not set
177# CONFIG_BLACKSTAMP is not set
147CONFIG_BFIN533_BLUETECHNIX_CM=y 178CONFIG_BFIN533_BLUETECHNIX_CM=y
148# CONFIG_H8606_HVSISTEMAS is not set 179# CONFIG_H8606_HVSISTEMAS is not set
149# CONFIG_GENERIC_BF533_BOARD is not set 180# CONFIG_BFIN532_IP0X is not set
150 181
151# 182#
152# BF533/2/1 Specific Configuration 183# BF533/2/1 Specific Configuration
@@ -188,6 +219,7 @@ CONFIG_WDTIMER=13
188# Board customizations 219# Board customizations
189# 220#
190# CONFIG_CMDLINE_BOOL is not set 221# CONFIG_CMDLINE_BOOL is not set
222CONFIG_BOOT_LOAD=0x1000
191 223
192# 224#
193# Clock/PLL Setup 225# Clock/PLL Setup
@@ -207,13 +239,20 @@ CONFIG_HZ_250=y
207# CONFIG_HZ_300 is not set 239# CONFIG_HZ_300 is not set
208# CONFIG_HZ_1000 is not set 240# CONFIG_HZ_1000 is not set
209CONFIG_HZ=250 241CONFIG_HZ=250
242# CONFIG_SCHED_HRTICK is not set
243CONFIG_GENERIC_TIME=y
244CONFIG_GENERIC_CLOCKEVENTS=y
245# CONFIG_TICKSOURCE_GPTMR0 is not set
246CONFIG_TICKSOURCE_CORETMR=y
247# CONFIG_CYCLES_CLOCKSOURCE is not set
248# CONFIG_GPTMR0_CLOCKSOURCE is not set
249# CONFIG_NO_HZ is not set
250# CONFIG_HIGH_RES_TIMERS is not set
251CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
210 252
211# 253#
212# Memory Setup 254# Misc
213# 255#
214CONFIG_MAX_MEM_SIZE=32
215CONFIG_MEM_ADD_WIDTH=9
216CONFIG_BOOT_LOAD=0x1000
217CONFIG_BFIN_SCRATCH_REG_RETN=y 256CONFIG_BFIN_SCRATCH_REG_RETN=y
218# CONFIG_BFIN_SCRATCH_REG_RETE is not set 257# CONFIG_BFIN_SCRATCH_REG_RETE is not set
219# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set 258# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -240,6 +279,12 @@ CONFIG_IP_CHECKSUM_L1=y
240CONFIG_CACHELINE_ALIGNED_L1=y 279CONFIG_CACHELINE_ALIGNED_L1=y
241CONFIG_SYSCALL_TAB_L1=y 280CONFIG_SYSCALL_TAB_L1=y
242CONFIG_CPLB_SWITCH_TAB_L1=y 281CONFIG_CPLB_SWITCH_TAB_L1=y
282CONFIG_APP_STACK_L1=y
283
284#
285# Speed Optimizations
286#
287CONFIG_BFIN_INS_LOWOVERHEAD=y
243CONFIG_RAMKERNEL=y 288CONFIG_RAMKERNEL=y
244# CONFIG_ROMKERNEL is not set 289# CONFIG_ROMKERNEL is not set
245CONFIG_SELECT_MEMORY_MODEL=y 290CONFIG_SELECT_MEMORY_MODEL=y
@@ -248,12 +293,16 @@ CONFIG_FLATMEM_MANUAL=y
248# CONFIG_SPARSEMEM_MANUAL is not set 293# CONFIG_SPARSEMEM_MANUAL is not set
249CONFIG_FLATMEM=y 294CONFIG_FLATMEM=y
250CONFIG_FLAT_NODE_MEM_MAP=y 295CONFIG_FLAT_NODE_MEM_MAP=y
251# CONFIG_SPARSEMEM_STATIC is not set 296CONFIG_PAGEFLAGS_EXTENDED=y
252CONFIG_SPLIT_PTLOCK_CPUS=4 297CONFIG_SPLIT_PTLOCK_CPUS=4
253# CONFIG_RESOURCES_64BIT is not set 298# CONFIG_PHYS_ADDR_T_64BIT is not set
254CONFIG_ZONE_DMA_FLAG=1 299CONFIG_ZONE_DMA_FLAG=1
255CONFIG_LARGE_ALLOCS=y 300CONFIG_VIRT_TO_BUS=y
301CONFIG_UNEVICTABLE_LRU=y
302CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
303CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
256# CONFIG_BFIN_GPTIMERS is not set 304# CONFIG_BFIN_GPTIMERS is not set
305# CONFIG_DMA_UNCACHED_4M is not set
257# CONFIG_DMA_UNCACHED_2M is not set 306# CONFIG_DMA_UNCACHED_2M is not set
258CONFIG_DMA_UNCACHED_1M=y 307CONFIG_DMA_UNCACHED_1M=y
259# CONFIG_DMA_UNCACHED_NONE is not set 308# CONFIG_DMA_UNCACHED_NONE is not set
@@ -262,10 +311,9 @@ CONFIG_DMA_UNCACHED_1M=y
262# Cache Support 311# Cache Support
263# 312#
264CONFIG_BFIN_ICACHE=y 313CONFIG_BFIN_ICACHE=y
265# CONFIG_BFIN_ICACHE_LOCK is not set 314CONFIG_BFIN_EXTMEM_ICACHEABLE=y
266CONFIG_BFIN_DCACHE=y 315CONFIG_BFIN_DCACHE=y
267# CONFIG_BFIN_DCACHE_BANKA is not set 316# CONFIG_BFIN_DCACHE_BANKA is not set
268CONFIG_BFIN_EXTMEM_ICACHEABLE=y
269CONFIG_BFIN_EXTMEM_DCACHEABLE=y 317CONFIG_BFIN_EXTMEM_DCACHEABLE=y
270CONFIG_BFIN_EXTMEM_WRITEBACK=y 318CONFIG_BFIN_EXTMEM_WRITEBACK=y
271# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 319# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -276,7 +324,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
276# CONFIG_MPU is not set 324# CONFIG_MPU is not set
277 325
278# 326#
279# Asynchonous Memory Configuration 327# Asynchronous Memory Configuration
280# 328#
281 329
282# 330#
@@ -301,12 +349,8 @@ CONFIG_BANK_3=0xFFC2
301# 349#
302# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 350# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
303# 351#
304# CONFIG_PCI is not set
305# CONFIG_ARCH_SUPPORTS_MSI is not set 352# CONFIG_ARCH_SUPPORTS_MSI is not set
306 353# CONFIG_PCCARD is not set
307#
308# PCCARD (PCMCIA/CardBus) support
309#
310 354
311# 355#
312# Executable file formats 356# Executable file formats
@@ -315,22 +359,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
315CONFIG_BINFMT_FLAT=y 359CONFIG_BINFMT_FLAT=y
316CONFIG_BINFMT_ZFLAT=y 360CONFIG_BINFMT_ZFLAT=y
317CONFIG_BINFMT_SHARED_FLAT=y 361CONFIG_BINFMT_SHARED_FLAT=y
362# CONFIG_HAVE_AOUT is not set
318# CONFIG_BINFMT_MISC is not set 363# CONFIG_BINFMT_MISC is not set
319 364
320# 365#
321# Power management options 366# Power management options
322# 367#
323# CONFIG_PM is not set 368# CONFIG_PM is not set
324# CONFIG_PM_WAKEUP_BY_GPIO is not set 369CONFIG_ARCH_SUSPEND_POSSIBLE=y
325 370
326# 371#
327# CPU Frequency scaling 372# CPU Frequency scaling
328# 373#
329# CONFIG_CPU_FREQ is not set 374# CONFIG_CPU_FREQ is not set
330
331#
332# Networking
333#
334CONFIG_NET=y 375CONFIG_NET=y
335 376
336# 377#
@@ -339,45 +380,13 @@ CONFIG_NET=y
339CONFIG_PACKET=y 380CONFIG_PACKET=y
340# CONFIG_PACKET_MMAP is not set 381# CONFIG_PACKET_MMAP is not set
341CONFIG_UNIX=y 382CONFIG_UNIX=y
342CONFIG_XFRM=y
343# CONFIG_XFRM_USER is not set
344# CONFIG_XFRM_SUB_POLICY is not set
345# CONFIG_XFRM_MIGRATE is not set
346# CONFIG_NET_KEY is not set 383# CONFIG_NET_KEY is not set
347CONFIG_INET=y 384# CONFIG_INET is not set
348# CONFIG_IP_MULTICAST is not set
349# CONFIG_IP_ADVANCED_ROUTER is not set
350CONFIG_IP_FIB_HASH=y
351# CONFIG_IP_PNP is not set
352# CONFIG_NET_IPIP is not set
353# CONFIG_NET_IPGRE is not set
354# CONFIG_ARPD is not set
355# CONFIG_SYN_COOKIES is not set
356# CONFIG_INET_AH is not set
357# CONFIG_INET_ESP is not set
358# CONFIG_INET_IPCOMP is not set
359# CONFIG_INET_XFRM_TUNNEL is not set
360# CONFIG_INET_TUNNEL is not set
361# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
362# CONFIG_INET_XFRM_MODE_TUNNEL is not set
363# CONFIG_INET_XFRM_MODE_BEET is not set
364# CONFIG_INET_DIAG is not set
365CONFIG_INET_TCP_DIAG=y
366# CONFIG_TCP_CONG_ADVANCED is not set
367CONFIG_TCP_CONG_CUBIC=y
368CONFIG_DEFAULT_TCP_CONG="cubic"
369# CONFIG_TCP_MD5SIG is not set
370# CONFIG_IPV6 is not set
371# CONFIG_INET6_XFRM_TUNNEL is not set
372# CONFIG_INET6_TUNNEL is not set
373# CONFIG_NETLABEL is not set
374# CONFIG_NETWORK_SECMARK is not set 385# CONFIG_NETWORK_SECMARK is not set
375# CONFIG_NETFILTER is not set 386# CONFIG_NETFILTER is not set
376# CONFIG_IP_DCCP is not set
377# CONFIG_IP_SCTP is not set
378# CONFIG_TIPC is not set
379# CONFIG_ATM is not set 387# CONFIG_ATM is not set
380# CONFIG_BRIDGE is not set 388# CONFIG_BRIDGE is not set
389# CONFIG_NET_DSA is not set
381# CONFIG_VLAN_8021Q is not set 390# CONFIG_VLAN_8021Q is not set
382# CONFIG_DECNET is not set 391# CONFIG_DECNET is not set
383# CONFIG_LLC2 is not set 392# CONFIG_LLC2 is not set
@@ -385,31 +394,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
385# CONFIG_ATALK is not set 394# CONFIG_ATALK is not set
386# CONFIG_X25 is not set 395# CONFIG_X25 is not set
387# CONFIG_LAPB is not set 396# CONFIG_LAPB is not set
388# CONFIG_ECONET is not set
389# CONFIG_WAN_ROUTER is not set 397# CONFIG_WAN_ROUTER is not set
390 398# CONFIG_PHONET is not set
391#
392# QoS and/or fair queueing
393#
394# CONFIG_NET_SCHED is not set 399# CONFIG_NET_SCHED is not set
400# CONFIG_DCB is not set
395 401
396# 402#
397# Network testing 403# Network testing
398# 404#
399# CONFIG_NET_PKTGEN is not set 405# CONFIG_NET_PKTGEN is not set
400# CONFIG_HAMRADIO is not set 406# CONFIG_HAMRADIO is not set
407# CONFIG_CAN is not set
401# CONFIG_IRDA is not set 408# CONFIG_IRDA is not set
402# CONFIG_BT is not set 409# CONFIG_BT is not set
403# CONFIG_AF_RXRPC is not set 410# CONFIG_WIRELESS is not set
404 411# CONFIG_WIMAX is not set
405#
406# Wireless
407#
408# CONFIG_CFG80211 is not set
409# CONFIG_WIRELESS_EXT is not set
410# CONFIG_MAC80211 is not set
411# CONFIG_IEEE80211 is not set
412# CONFIG_RFKILL is not set 412# CONFIG_RFKILL is not set
413# CONFIG_NET_9P is not set
413 414
414# 415#
415# Device Drivers 416# Device Drivers
@@ -418,20 +419,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
418# 419#
419# Generic Driver Options 420# Generic Driver Options
420# 421#
422CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
421CONFIG_STANDALONE=y 423CONFIG_STANDALONE=y
422CONFIG_PREVENT_FIRMWARE_BUILD=y 424CONFIG_PREVENT_FIRMWARE_BUILD=y
425CONFIG_FW_LOADER=y
426CONFIG_FIRMWARE_IN_KERNEL=y
427CONFIG_EXTRA_FIRMWARE=""
423# CONFIG_SYS_HYPERVISOR is not set 428# CONFIG_SYS_HYPERVISOR is not set
424
425#
426# Connector - unified userspace <-> kernelspace linker
427#
428# CONFIG_CONNECTOR is not set 429# CONFIG_CONNECTOR is not set
429CONFIG_MTD=y 430CONFIG_MTD=y
430# CONFIG_MTD_DEBUG is not set 431# CONFIG_MTD_DEBUG is not set
432# CONFIG_MTD_TESTS is not set
431# CONFIG_MTD_CONCAT is not set 433# CONFIG_MTD_CONCAT is not set
432CONFIG_MTD_PARTITIONS=y 434CONFIG_MTD_PARTITIONS=y
433# CONFIG_MTD_REDBOOT_PARTS is not set 435# CONFIG_MTD_REDBOOT_PARTS is not set
434# CONFIG_MTD_CMDLINE_PARTS is not set 436CONFIG_MTD_CMDLINE_PARTS=y
437# CONFIG_MTD_AR7_PARTS is not set
435 438
436# 439#
437# User Modules And Translation Layers 440# User Modules And Translation Layers
@@ -444,12 +447,15 @@ CONFIG_MTD_BLOCK=y
444# CONFIG_INFTL is not set 447# CONFIG_INFTL is not set
445# CONFIG_RFD_FTL is not set 448# CONFIG_RFD_FTL is not set
446# CONFIG_SSFDC is not set 449# CONFIG_SSFDC is not set
450# CONFIG_MTD_OOPS is not set
447 451
448# 452#
449# RAM/ROM/Flash chip drivers 453# RAM/ROM/Flash chip drivers
450# 454#
451# CONFIG_MTD_CFI is not set 455CONFIG_MTD_CFI=y
452# CONFIG_MTD_JEDECPROBE is not set 456# CONFIG_MTD_JEDECPROBE is not set
457CONFIG_MTD_GEN_PROBE=y
458# CONFIG_MTD_CFI_ADV_OPTIONS is not set
453CONFIG_MTD_MAP_BANK_WIDTH_1=y 459CONFIG_MTD_MAP_BANK_WIDTH_1=y
454CONFIG_MTD_MAP_BANK_WIDTH_2=y 460CONFIG_MTD_MAP_BANK_WIDTH_2=y
455CONFIG_MTD_MAP_BANK_WIDTH_4=y 461CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -460,6 +466,11 @@ CONFIG_MTD_CFI_I1=y
460CONFIG_MTD_CFI_I2=y 466CONFIG_MTD_CFI_I2=y
461# CONFIG_MTD_CFI_I4 is not set 467# CONFIG_MTD_CFI_I4 is not set
462# CONFIG_MTD_CFI_I8 is not set 468# CONFIG_MTD_CFI_I8 is not set
469CONFIG_MTD_CFI_INTELEXT=y
470# CONFIG_MTD_CFI_AMDSTD is not set
471# CONFIG_MTD_CFI_STAA is not set
472# CONFIG_MTD_PSD4256G is not set
473CONFIG_MTD_CFI_UTIL=y
463CONFIG_MTD_RAM=y 474CONFIG_MTD_RAM=y
464# CONFIG_MTD_ROM is not set 475# CONFIG_MTD_ROM is not set
465# CONFIG_MTD_ABSENT is not set 476# CONFIG_MTD_ABSENT is not set
@@ -468,12 +479,16 @@ CONFIG_MTD_RAM=y
468# Mapping drivers for chip access 479# Mapping drivers for chip access
469# 480#
470# CONFIG_MTD_COMPLEX_MAPPINGS is not set 481# CONFIG_MTD_COMPLEX_MAPPINGS is not set
471CONFIG_MTD_UCLINUX=y 482CONFIG_MTD_PHYSMAP=y
483# CONFIG_MTD_PHYSMAP_COMPAT is not set
484# CONFIG_MTD_UCLINUX is not set
472# CONFIG_MTD_PLATRAM is not set 485# CONFIG_MTD_PLATRAM is not set
473 486
474# 487#
475# Self-contained MTD device drivers 488# Self-contained MTD device drivers
476# 489#
490# CONFIG_MTD_DATAFLASH is not set
491# CONFIG_MTD_M25P80 is not set
477# CONFIG_MTD_SLRAM is not set 492# CONFIG_MTD_SLRAM is not set
478# CONFIG_MTD_PHRAM is not set 493# CONFIG_MTD_PHRAM is not set
479# CONFIG_MTD_MTDRAM is not set 494# CONFIG_MTD_MTDRAM is not set
@@ -489,36 +504,25 @@ CONFIG_MTD_UCLINUX=y
489# CONFIG_MTD_ONENAND is not set 504# CONFIG_MTD_ONENAND is not set
490 505
491# 506#
492# UBI - Unsorted block images 507# LPDDR flash memory drivers
493# 508#
494# CONFIG_MTD_UBI is not set 509# CONFIG_MTD_LPDDR is not set
495 510
496# 511#
497# Parallel port support 512# UBI - Unsorted block images
498# 513#
514# CONFIG_MTD_UBI is not set
499# CONFIG_PARPORT is not set 515# CONFIG_PARPORT is not set
500 516CONFIG_BLK_DEV=y
501#
502# Plug and Play support
503#
504# CONFIG_PNPACPI is not set
505
506#
507# Block devices
508#
509# CONFIG_BLK_DEV_COW_COMMON is not set 517# CONFIG_BLK_DEV_COW_COMMON is not set
510# CONFIG_BLK_DEV_LOOP is not set 518# CONFIG_BLK_DEV_LOOP is not set
511# CONFIG_BLK_DEV_NBD is not set 519# CONFIG_BLK_DEV_NBD is not set
512CONFIG_BLK_DEV_RAM=y 520# CONFIG_BLK_DEV_RAM is not set
513CONFIG_BLK_DEV_RAM_COUNT=16
514CONFIG_BLK_DEV_RAM_SIZE=4096
515CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
516# CONFIG_CDROM_PKTCDVD is not set 521# CONFIG_CDROM_PKTCDVD is not set
517# CONFIG_ATA_OVER_ETH is not set 522# CONFIG_ATA_OVER_ETH is not set
518 523# CONFIG_BLK_DEV_HD is not set
519# 524# CONFIG_MISC_DEVICES is not set
520# Misc devices 525CONFIG_HAVE_IDE=y
521#
522# CONFIG_IDE is not set 526# CONFIG_IDE is not set
523 527
524# 528#
@@ -526,34 +530,19 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
526# 530#
527# CONFIG_RAID_ATTRS is not set 531# CONFIG_RAID_ATTRS is not set
528# CONFIG_SCSI is not set 532# CONFIG_SCSI is not set
533# CONFIG_SCSI_DMA is not set
529# CONFIG_SCSI_NETLINK is not set 534# CONFIG_SCSI_NETLINK is not set
530# CONFIG_ATA is not set 535# CONFIG_ATA is not set
531
532#
533# Multi-device support (RAID and LVM)
534#
535# CONFIG_MD is not set 536# CONFIG_MD is not set
536
537#
538# Network device support
539#
540CONFIG_NETDEVICES=y 537CONFIG_NETDEVICES=y
538CONFIG_COMPAT_NET_DEV_OPS=y
541# CONFIG_DUMMY is not set 539# CONFIG_DUMMY is not set
542# CONFIG_BONDING is not set 540# CONFIG_MACVLAN is not set
543# CONFIG_EQUALIZER is not set 541# CONFIG_EQUALIZER is not set
544# CONFIG_TUN is not set 542# CONFIG_TUN is not set
545# CONFIG_PHYLIB is not set 543# CONFIG_VETH is not set
546 544# CONFIG_NET_ETHERNET is not set
547#
548# Ethernet (10 or 100Mbit)
549#
550CONFIG_NET_ETHERNET=y
551CONFIG_MII=y
552CONFIG_SMC91X=y
553# CONFIG_SMSC911X is not set
554# CONFIG_DM9000 is not set
555# CONFIG_NETDEV_1000 is not set 545# CONFIG_NETDEV_1000 is not set
556# CONFIG_AX88180 is not set
557# CONFIG_NETDEV_10000 is not set 546# CONFIG_NETDEV_10000 is not set
558 547
559# 548#
@@ -561,22 +550,17 @@ CONFIG_SMC91X=y
561# 550#
562# CONFIG_WLAN_PRE80211 is not set 551# CONFIG_WLAN_PRE80211 is not set
563# CONFIG_WLAN_80211 is not set 552# CONFIG_WLAN_80211 is not set
553
554#
555# Enable WiMAX (Networking options) to see the WiMAX drivers
556#
564# CONFIG_WAN is not set 557# CONFIG_WAN is not set
565# CONFIG_PPP is not set 558# CONFIG_PPP is not set
566# CONFIG_SLIP is not set 559# CONFIG_SLIP is not set
567# CONFIG_SHAPER is not set
568# CONFIG_NETCONSOLE is not set 560# CONFIG_NETCONSOLE is not set
569# CONFIG_NETPOLL is not set 561# CONFIG_NETPOLL is not set
570# CONFIG_NET_POLL_CONTROLLER is not set 562# CONFIG_NET_POLL_CONTROLLER is not set
571
572#
573# ISDN subsystem
574#
575# CONFIG_ISDN is not set 563# CONFIG_ISDN is not set
576
577#
578# Telephony Support
579#
580# CONFIG_PHONE is not set 564# CONFIG_PHONE is not set
581 565
582# 566#
@@ -593,16 +577,15 @@ CONFIG_SMC91X=y
593# 577#
594# Character devices 578# Character devices
595# 579#
596# CONFIG_AD9960 is not set 580# CONFIG_BFIN_DMA_INTERFACE is not set
597# CONFIG_SPI_ADC_BF533 is not set 581# CONFIG_BFIN_PPI is not set
598# CONFIG_BF5xx_PFLAGS is not set 582# CONFIG_BFIN_PPIFCD is not set
599# CONFIG_BF5xx_PPIFCD is not set
600# CONFIG_BFIN_SIMPLE_TIMER is not set 583# CONFIG_BFIN_SIMPLE_TIMER is not set
601# CONFIG_BF5xx_PPI is not set 584# CONFIG_BFIN_SPI_ADC is not set
602CONFIG_BFIN_SPORT=y 585# CONFIG_BFIN_SPORT is not set
603# CONFIG_BFIN_TIMER_LATENCY is not set
604# CONFIG_VT is not set 586# CONFIG_VT is not set
605# CONFIG_DEVKMEM is not set 587# CONFIG_DEVKMEM is not set
588# CONFIG_BFIN_JTAG_COMM is not set
606# CONFIG_SERIAL_NONSTANDARD is not set 589# CONFIG_SERIAL_NONSTANDARD is not set
607 590
608# 591#
@@ -613,6 +596,7 @@ CONFIG_BFIN_SPORT=y
613# 596#
614# Non-8250 serial port support 597# Non-8250 serial port support
615# 598#
599# CONFIG_SERIAL_MAX3100 is not set
616CONFIG_SERIAL_BFIN=y 600CONFIG_SERIAL_BFIN=y
617CONFIG_SERIAL_BFIN_CONSOLE=y 601CONFIG_SERIAL_BFIN_CONSOLE=y
618CONFIG_SERIAL_BFIN_DMA=y 602CONFIG_SERIAL_BFIN_DMA=y
@@ -623,176 +607,141 @@ CONFIG_SERIAL_CORE=y
623CONFIG_SERIAL_CORE_CONSOLE=y 607CONFIG_SERIAL_CORE_CONSOLE=y
624# CONFIG_SERIAL_BFIN_SPORT is not set 608# CONFIG_SERIAL_BFIN_SPORT is not set
625CONFIG_UNIX98_PTYS=y 609CONFIG_UNIX98_PTYS=y
610# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
626# CONFIG_LEGACY_PTYS is not set 611# CONFIG_LEGACY_PTYS is not set
627 612
628# 613#
629# CAN, the car bus and industrial fieldbus 614# CAN, the car bus and industrial fieldbus
630# 615#
631# CONFIG_CAN4LINUX is not set 616# CONFIG_CAN4LINUX is not set
632
633#
634# IPMI
635#
636# CONFIG_IPMI_HANDLER is not set 617# CONFIG_IPMI_HANDLER is not set
637# CONFIG_WATCHDOG is not set
638# CONFIG_HW_RANDOM is not set 618# CONFIG_HW_RANDOM is not set
639# CONFIG_GEN_RTC is not set
640# CONFIG_R3964 is not set 619# CONFIG_R3964 is not set
641# CONFIG_RAW_DRIVER is not set 620# CONFIG_RAW_DRIVER is not set
642
643#
644# TPM devices
645#
646# CONFIG_TCG_TPM is not set 621# CONFIG_TCG_TPM is not set
647# CONFIG_I2C is not set 622# CONFIG_I2C is not set
648 623CONFIG_SPI=y
649CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 624CONFIG_SPI_MASTER=y
650CONFIG_GPIOLIB=y
651CONFIG_GPIO_SYSFS=y
652 625
653# 626#
654# SPI support 627# SPI Master Controller Drivers
655# 628#
656# CONFIG_SPI is not set 629CONFIG_SPI_BFIN=y
657# CONFIG_SPI_MASTER is not set 630# CONFIG_SPI_BFIN_LOCK is not set
631# CONFIG_SPI_BFIN_SPORT is not set
632# CONFIG_SPI_BITBANG is not set
633# CONFIG_SPI_GPIO is not set
658 634
659# 635#
660# Dallas's 1-wire bus 636# SPI Protocol Masters
661# 637#
638# CONFIG_SPI_SPIDEV is not set
639# CONFIG_SPI_TLE62X0 is not set
640CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
641# CONFIG_GPIOLIB is not set
662# CONFIG_W1 is not set 642# CONFIG_W1 is not set
663CONFIG_HWMON=y 643# CONFIG_POWER_SUPPLY is not set
664# CONFIG_HWMON_VID is not set 644# CONFIG_HWMON is not set
665# CONFIG_SENSORS_ABITUGURU is not set 645# CONFIG_THERMAL is not set
666# CONFIG_SENSORS_F71805F is not set 646# CONFIG_THERMAL_HWMON is not set
667# CONFIG_SENSORS_PC87427 is not set 647# CONFIG_WATCHDOG is not set
668# CONFIG_SENSORS_SMSC47M1 is not set 648CONFIG_SSB_POSSIBLE=y
669# CONFIG_SENSORS_SMSC47B397 is not set 649
670# CONFIG_SENSORS_VT1211 is not set 650#
671# CONFIG_SENSORS_W83627HF is not set 651# Sonics Silicon Backplane
672# CONFIG_HWMON_DEBUG_CHIP is not set 652#
653# CONFIG_SSB is not set
673 654
674# 655#
675# Multifunction device drivers 656# Multifunction device drivers
676# 657#
658# CONFIG_MFD_CORE is not set
677# CONFIG_MFD_SM501 is not set 659# CONFIG_MFD_SM501 is not set
660# CONFIG_HTC_PASIC3 is not set
661# CONFIG_MFD_TMIO is not set
662# CONFIG_REGULATOR is not set
678 663
679# 664#
680# Multimedia devices 665# Multimedia devices
681# 666#
667
668#
669# Multimedia core support
670#
682# CONFIG_VIDEO_DEV is not set 671# CONFIG_VIDEO_DEV is not set
683# CONFIG_DVB_CORE is not set 672# CONFIG_VIDEO_MEDIA is not set
684# CONFIG_DAB is not set
685 673
686# 674#
687# Graphics support 675# Multimedia drivers
688# 676#
689# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 677# CONFIG_DAB is not set
690 678
691# 679#
692# Display device support 680# Graphics support
693# 681#
694# CONFIG_DISPLAY_SUPPORT is not set
695# CONFIG_VGASTATE is not set 682# CONFIG_VGASTATE is not set
683# CONFIG_VIDEO_OUTPUT_CONTROL is not set
696# CONFIG_FB is not set 684# CONFIG_FB is not set
685# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
697 686
698# 687#
699# Sound 688# Display device support
700# 689#
690# CONFIG_DISPLAY_SUPPORT is not set
701# CONFIG_SOUND is not set 691# CONFIG_SOUND is not set
692# CONFIG_USB_SUPPORT is not set
693CONFIG_MMC=y
694# CONFIG_MMC_DEBUG is not set
695# CONFIG_MMC_UNSAFE_RESUME is not set
702 696
703# 697#
704# USB support 698# MMC/SD/SDIO Card Drivers
705# 699#
706CONFIG_USB_ARCH_HAS_HCD=y 700CONFIG_MMC_BLOCK=y
707# CONFIG_USB_ARCH_HAS_OHCI is not set 701# CONFIG_MMC_BLOCK_BOUNCE is not set
708# CONFIG_USB_ARCH_HAS_EHCI is not set 702# CONFIG_SDIO_UART is not set
709# CONFIG_USB is not set 703# CONFIG_MMC_TEST is not set
710 704
711# 705#
712# Enable Host or Gadget support to see Inventra options 706# MMC/SD/SDIO Host Controller Drivers
713#
714
715#
716# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
717#
718
719#
720# USB Gadget Support
721#
722# CONFIG_USB_GADGET is not set
723# CONFIG_MMC is not set
724
725#
726# LED devices
727# 707#
708# CONFIG_MMC_SDHCI is not set
709CONFIG_MMC_SPI=m
710# CONFIG_MEMSTICK is not set
728# CONFIG_NEW_LEDS is not set 711# CONFIG_NEW_LEDS is not set
729 712# CONFIG_ACCESSIBILITY is not set
730#
731# LED drivers
732#
733
734#
735# LED Triggers
736#
737
738#
739# InfiniBand support
740#
741
742#
743# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
744#
745
746#
747# Real Time Clock
748#
749# CONFIG_RTC_CLASS is not set 713# CONFIG_RTC_CLASS is not set
750 714# CONFIG_DMADEVICES is not set
751# 715# CONFIG_AUXDISPLAY is not set
752# DMA Engine support 716# CONFIG_UIO is not set
753# 717# CONFIG_STAGING is not set
754# CONFIG_DMA_ENGINE is not set
755
756#
757# DMA Clients
758#
759
760#
761# DMA Devices
762#
763
764#
765# PBX support
766#
767# CONFIG_PBX is not set
768 718
769# 719#
770# File systems 720# File systems
771# 721#
772CONFIG_EXT2_FS=y 722# CONFIG_EXT2_FS is not set
773CONFIG_EXT2_FS_XATTR=y
774# CONFIG_EXT2_FS_POSIX_ACL is not set
775# CONFIG_EXT2_FS_SECURITY is not set
776# CONFIG_EXT3_FS is not set 723# CONFIG_EXT3_FS is not set
777# CONFIG_EXT4DEV_FS is not set 724# CONFIG_EXT4_FS is not set
778CONFIG_FS_MBCACHE=y
779# CONFIG_REISERFS_FS is not set 725# CONFIG_REISERFS_FS is not set
780# CONFIG_JFS_FS is not set 726# CONFIG_JFS_FS is not set
781# CONFIG_FS_POSIX_ACL is not set 727# CONFIG_FS_POSIX_ACL is not set
782# CONFIG_XFS_FS is not set 728# CONFIG_XFS_FS is not set
783# CONFIG_GFS2_FS is not set
784# CONFIG_OCFS2_FS is not set 729# CONFIG_OCFS2_FS is not set
785# CONFIG_MINIX_FS is not set 730# CONFIG_BTRFS_FS is not set
786# CONFIG_ROMFS_FS is not set 731CONFIG_FILE_LOCKING=y
787CONFIG_INOTIFY=y
788CONFIG_INOTIFY_USER=y
789# CONFIG_QUOTA is not set
790# CONFIG_DNOTIFY is not set 732# CONFIG_DNOTIFY is not set
733# CONFIG_INOTIFY is not set
734# CONFIG_QUOTA is not set
791# CONFIG_AUTOFS_FS is not set 735# CONFIG_AUTOFS_FS is not set
792# CONFIG_AUTOFS4_FS is not set 736# CONFIG_AUTOFS4_FS is not set
793# CONFIG_FUSE_FS is not set 737# CONFIG_FUSE_FS is not set
794 738
795# 739#
740# Caches
741#
742# CONFIG_FSCACHE is not set
743
744#
796# CD-ROM/DVD Filesystems 745# CD-ROM/DVD Filesystems
797# 746#
798# CONFIG_ISO9660_FS is not set 747# CONFIG_ISO9660_FS is not set
@@ -801,8 +750,11 @@ CONFIG_INOTIFY_USER=y
801# 750#
802# DOS/FAT/NT Filesystems 751# DOS/FAT/NT Filesystems
803# 752#
753CONFIG_FAT_FS=y
804# CONFIG_MSDOS_FS is not set 754# CONFIG_MSDOS_FS is not set
805# CONFIG_VFAT_FS is not set 755CONFIG_VFAT_FS=y
756CONFIG_FAT_DEFAULT_CODEPAGE=437
757CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
806# CONFIG_NTFS_FS is not set 758# CONFIG_NTFS_FS is not set
807 759
808# 760#
@@ -813,12 +765,8 @@ CONFIG_PROC_SYSCTL=y
813CONFIG_SYSFS=y 765CONFIG_SYSFS=y
814# CONFIG_TMPFS is not set 766# CONFIG_TMPFS is not set
815# CONFIG_HUGETLB_PAGE is not set 767# CONFIG_HUGETLB_PAGE is not set
816CONFIG_RAMFS=y
817# CONFIG_CONFIGFS_FS is not set 768# CONFIG_CONFIGFS_FS is not set
818 769CONFIG_MISC_FILESYSTEMS=y
819#
820# Miscellaneous filesystems
821#
822# CONFIG_ADFS_FS is not set 770# CONFIG_ADFS_FS is not set
823# CONFIG_AFFS_FS is not set 771# CONFIG_AFFS_FS is not set
824# CONFIG_HFS_FS is not set 772# CONFIG_HFS_FS is not set
@@ -826,60 +774,106 @@ CONFIG_RAMFS=y
826# CONFIG_BEFS_FS is not set 774# CONFIG_BEFS_FS is not set
827# CONFIG_BFS_FS is not set 775# CONFIG_BFS_FS is not set
828# CONFIG_EFS_FS is not set 776# CONFIG_EFS_FS is not set
829# CONFIG_YAFFS_FS is not set
830# CONFIG_JFFS2_FS is not set 777# CONFIG_JFFS2_FS is not set
831# CONFIG_CRAMFS is not set 778# CONFIG_CRAMFS is not set
779# CONFIG_SQUASHFS is not set
832# CONFIG_VXFS_FS is not set 780# CONFIG_VXFS_FS is not set
781# CONFIG_MINIX_FS is not set
782# CONFIG_OMFS_FS is not set
833# CONFIG_HPFS_FS is not set 783# CONFIG_HPFS_FS is not set
834# CONFIG_QNX4FS_FS is not set 784# CONFIG_QNX4FS_FS is not set
785# CONFIG_ROMFS_FS is not set
835# CONFIG_SYSV_FS is not set 786# CONFIG_SYSV_FS is not set
836# CONFIG_UFS_FS is not set 787# CONFIG_UFS_FS is not set
837 788# CONFIG_NILFS2_FS is not set
838# 789# CONFIG_NETWORK_FILESYSTEMS is not set
839# Network File Systems
840#
841# CONFIG_NFS_FS is not set
842# CONFIG_NFSD is not set
843# CONFIG_SMB_FS is not set
844# CONFIG_CIFS is not set
845# CONFIG_NCP_FS is not set
846# CONFIG_CODA_FS is not set
847# CONFIG_AFS_FS is not set
848# CONFIG_9P_FS is not set
849 790
850# 791#
851# Partition Types 792# Partition Types
852# 793#
853# CONFIG_PARTITION_ADVANCED is not set 794# CONFIG_PARTITION_ADVANCED is not set
854CONFIG_MSDOS_PARTITION=y 795CONFIG_MSDOS_PARTITION=y
855 796CONFIG_NLS=y
856# 797CONFIG_NLS_DEFAULT="iso8859-1"
857# Native Language Support 798CONFIG_NLS_CODEPAGE_437=y
858# 799# CONFIG_NLS_CODEPAGE_737 is not set
859# CONFIG_NLS is not set 800# CONFIG_NLS_CODEPAGE_775 is not set
860 801# CONFIG_NLS_CODEPAGE_850 is not set
861# 802# CONFIG_NLS_CODEPAGE_852 is not set
862# Distributed Lock Manager 803# CONFIG_NLS_CODEPAGE_855 is not set
863# 804# CONFIG_NLS_CODEPAGE_857 is not set
864# CONFIG_DLM is not set 805# CONFIG_NLS_CODEPAGE_860 is not set
865 806# CONFIG_NLS_CODEPAGE_861 is not set
866# 807# CONFIG_NLS_CODEPAGE_862 is not set
867# Profiling support 808# CONFIG_NLS_CODEPAGE_863 is not set
868# 809# CONFIG_NLS_CODEPAGE_864 is not set
869# CONFIG_PROFILING is not set 810# CONFIG_NLS_CODEPAGE_865 is not set
811# CONFIG_NLS_CODEPAGE_866 is not set
812# CONFIG_NLS_CODEPAGE_869 is not set
813# CONFIG_NLS_CODEPAGE_936 is not set
814# CONFIG_NLS_CODEPAGE_950 is not set
815# CONFIG_NLS_CODEPAGE_932 is not set
816# CONFIG_NLS_CODEPAGE_949 is not set
817# CONFIG_NLS_CODEPAGE_874 is not set
818# CONFIG_NLS_ISO8859_8 is not set
819# CONFIG_NLS_CODEPAGE_1250 is not set
820# CONFIG_NLS_CODEPAGE_1251 is not set
821# CONFIG_NLS_ASCII is not set
822CONFIG_NLS_ISO8859_1=y
823# CONFIG_NLS_ISO8859_2 is not set
824# CONFIG_NLS_ISO8859_3 is not set
825# CONFIG_NLS_ISO8859_4 is not set
826# CONFIG_NLS_ISO8859_5 is not set
827# CONFIG_NLS_ISO8859_6 is not set
828# CONFIG_NLS_ISO8859_7 is not set
829# CONFIG_NLS_ISO8859_9 is not set
830# CONFIG_NLS_ISO8859_13 is not set
831# CONFIG_NLS_ISO8859_14 is not set
832# CONFIG_NLS_ISO8859_15 is not set
833# CONFIG_NLS_KOI8_R is not set
834# CONFIG_NLS_KOI8_U is not set
835# CONFIG_NLS_UTF8 is not set
870 836
871# 837#
872# Kernel hacking 838# Kernel hacking
873# 839#
874# CONFIG_PRINTK_TIME is not set 840# CONFIG_PRINTK_TIME is not set
841CONFIG_ENABLE_WARN_DEPRECATED=y
875CONFIG_ENABLE_MUST_CHECK=y 842CONFIG_ENABLE_MUST_CHECK=y
843CONFIG_FRAME_WARN=1024
876# CONFIG_MAGIC_SYSRQ is not set 844# CONFIG_MAGIC_SYSRQ is not set
877# CONFIG_UNUSED_SYMBOLS is not set 845# CONFIG_UNUSED_SYMBOLS is not set
878CONFIG_DEBUG_FS=y 846CONFIG_DEBUG_FS=y
879# CONFIG_HEADERS_CHECK is not set 847# CONFIG_HEADERS_CHECK is not set
848CONFIG_DEBUG_SECTION_MISMATCH=y
880# CONFIG_DEBUG_KERNEL is not set 849# CONFIG_DEBUG_KERNEL is not set
881CONFIG_DEBUG_BUGVERBOSE=y 850# CONFIG_DEBUG_BUGVERBOSE is not set
851# CONFIG_DEBUG_MEMORY_INIT is not set
852# CONFIG_RCU_CPU_STALL_DETECTOR is not set
853CONFIG_HAVE_FUNCTION_TRACER=y
854CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
855CONFIG_TRACING_SUPPORT=y
856
857#
858# Tracers
859#
860# CONFIG_FUNCTION_TRACER is not set
861# CONFIG_IRQSOFF_TRACER is not set
862# CONFIG_SCHED_TRACER is not set
863# CONFIG_CONTEXT_SWITCH_TRACER is not set
864# CONFIG_EVENT_TRACER is not set
865# CONFIG_BOOT_TRACER is not set
866# CONFIG_TRACE_BRANCH_PROFILING is not set
867# CONFIG_STACK_TRACER is not set
868# CONFIG_KMEMTRACE is not set
869# CONFIG_WORKQUEUE_TRACER is not set
870# CONFIG_BLK_DEV_IO_TRACE is not set
871# CONFIG_DYNAMIC_DEBUG is not set
872# CONFIG_SAMPLES is not set
873CONFIG_HAVE_ARCH_KGDB=y
874CONFIG_DEBUG_VERBOSE=y
882CONFIG_DEBUG_MMRS=y 875CONFIG_DEBUG_MMRS=y
876# CONFIG_DEBUG_DOUBLEFAULT is not set
883CONFIG_DEBUG_HUNT_FOR_ZERO=y 877CONFIG_DEBUG_HUNT_FOR_ZERO=y
884CONFIG_DEBUG_BFIN_HWTRACE_ON=y 878CONFIG_DEBUG_BFIN_HWTRACE_ON=y
885CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y 879CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -888,34 +882,39 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
888CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 882CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
889# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 883# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
890# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 884# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
891# CONFIG_EARLY_PRINTK is not set 885CONFIG_EARLY_PRINTK=y
892CONFIG_CPLB_INFO=y 886CONFIG_CPLB_INFO=y
893CONFIG_ACCESS_CHECK=y 887CONFIG_ACCESS_CHECK=y
888# CONFIG_BFIN_ISRAM_SELF_TEST is not set
894 889
895# 890#
896# Security options 891# Security options
897# 892#
898# CONFIG_KEYS is not set 893# CONFIG_KEYS is not set
899CONFIG_SECURITY=y 894CONFIG_SECURITY=y
895# CONFIG_SECURITYFS is not set
900# CONFIG_SECURITY_NETWORK is not set 896# CONFIG_SECURITY_NETWORK is not set
901CONFIG_SECURITY_CAPABILITIES=y 897# CONFIG_SECURITY_PATH is not set
902 898# CONFIG_SECURITY_FILE_CAPABILITIES is not set
903# 899# CONFIG_SECURITY_TOMOYO is not set
904# Cryptographic options
905#
906# CONFIG_CRYPTO is not set 900# CONFIG_CRYPTO is not set
901# CONFIG_BINARY_PRINTF is not set
907 902
908# 903#
909# Library routines 904# Library routines
910# 905#
911CONFIG_BITREVERSE=y 906CONFIG_BITREVERSE=y
912CONFIG_CRC_CCITT=m 907CONFIG_GENERIC_FIND_LAST_BIT=y
908CONFIG_CRC_CCITT=y
913# CONFIG_CRC16 is not set 909# CONFIG_CRC16 is not set
914# CONFIG_CRC_ITU_T is not set 910# CONFIG_CRC_T10DIF is not set
911CONFIG_CRC_ITU_T=y
915CONFIG_CRC32=y 912CONFIG_CRC32=y
913CONFIG_CRC7=y
916# CONFIG_LIBCRC32C is not set 914# CONFIG_LIBCRC32C is not set
917CONFIG_ZLIB_INFLATE=y 915CONFIG_ZLIB_INFLATE=y
918CONFIG_PLIST=y 916CONFIG_DECOMPRESS_LZMA=y
919CONFIG_HAS_IOMEM=y 917CONFIG_HAS_IOMEM=y
920CONFIG_HAS_IOPORT=y 918CONFIG_HAS_IOPORT=y
921CONFIG_HAS_DMA=y 919CONFIG_HAS_DMA=y
920CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index d74b6f4db35d..22e565c51d66 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -1,13 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28.10 3# Linux kernel version: 2.6.30.5
4# Wed Jun 3 06:27:41 2009
5# 4#
6# CONFIG_MMU is not set 5# CONFIG_MMU is not set
7# CONFIG_FPU is not set 6# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20 23
21# 24#
@@ -26,21 +29,40 @@ CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
29CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
34# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
35CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
36CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
37CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
38# CONFIG_CGROUPS is not set
39# CONFIG_GROUP_SCHED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
40# CONFIG_SYSFS_DEPRECATED_V2 is not set 58# CONFIG_SYSFS_DEPRECATED_V2 is not set
41# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
42# CONFIG_NAMESPACES is not set 60# CONFIG_NAMESPACES is not set
43# CONFIG_BLK_DEV_INITRD is not set 61CONFIG_BLK_DEV_INITRD=y
62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
44# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
45CONFIG_SYSCTL=y 67CONFIG_SYSCTL=y
46CONFIG_ANON_INODES=y 68CONFIG_ANON_INODES=y
@@ -49,7 +71,8 @@ CONFIG_EMBEDDED=y
49# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
50CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
51# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
52# CONFIG_HOTPLUG is not set 74# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y
53CONFIG_PRINTK=y 76CONFIG_PRINTK=y
54CONFIG_BUG=y 77CONFIG_BUG=y
55# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
@@ -65,12 +88,13 @@ CONFIG_COMPAT_BRK=y
65CONFIG_SLAB=y 88CONFIG_SLAB=y
66# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
67# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
68# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
69# CONFIG_MARKERS is not set 93# CONFIG_MARKERS is not set
70CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
71# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
72CONFIG_SLABINFO=y 97CONFIG_SLABINFO=y
73CONFIG_TINY_SHMEM=y
74CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
75CONFIG_MODULES=y 99CONFIG_MODULES=y
76# CONFIG_MODULE_FORCE_LOAD is not set 100# CONFIG_MODULE_FORCE_LOAD is not set
@@ -78,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
78# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
79# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
80# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
81CONFIG_KMOD=y
82CONFIG_BLOCK=y 105CONFIG_BLOCK=y
83# CONFIG_LBD is not set 106# CONFIG_LBD is not set
84# CONFIG_BLK_DEV_IO_TRACE is not set
85# CONFIG_LSF is not set
86# CONFIG_BLK_DEV_BSG is not set 107# CONFIG_BLK_DEV_BSG is not set
87# CONFIG_BLK_DEV_INTEGRITY is not set 108# CONFIG_BLK_DEV_INTEGRITY is not set
88 109
@@ -98,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
98# CONFIG_DEFAULT_CFQ is not set 119# CONFIG_DEFAULT_CFQ is not set
99CONFIG_DEFAULT_NOOP=y 120CONFIG_DEFAULT_NOOP=y
100CONFIG_DEFAULT_IOSCHED="noop" 121CONFIG_DEFAULT_IOSCHED="noop"
101CONFIG_CLASSIC_RCU=y
102CONFIG_PREEMPT_NONE=y 122CONFIG_PREEMPT_NONE=y
103# CONFIG_PREEMPT_VOLUNTARY is not set 123# CONFIG_PREEMPT_VOLUNTARY is not set
104# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
@@ -181,7 +201,8 @@ CONFIG_IRQ_MEM_DMA1=13
181CONFIG_IRQ_WATCH=13 201CONFIG_IRQ_WATCH=13
182CONFIG_IRQ_SPI=10 202CONFIG_IRQ_SPI=10
183# CONFIG_BFIN537_STAMP is not set 203# CONFIG_BFIN537_STAMP is not set
184CONFIG_BFIN537_BLUETECHNIX_CM=y 204CONFIG_BFIN537_BLUETECHNIX_CM_E=y
205# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
185# CONFIG_BFIN537_BLUETECHNIX_TCM is not set 206# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
186# CONFIG_PNAV10 is not set 207# CONFIG_PNAV10 is not set
187# CONFIG_CAMSIG_MINOTAUR is not set 208# CONFIG_CAMSIG_MINOTAUR is not set
@@ -283,10 +304,12 @@ CONFIG_FLATMEM=y
283CONFIG_FLAT_NODE_MEM_MAP=y 304CONFIG_FLAT_NODE_MEM_MAP=y
284CONFIG_PAGEFLAGS_EXTENDED=y 305CONFIG_PAGEFLAGS_EXTENDED=y
285CONFIG_SPLIT_PTLOCK_CPUS=4 306CONFIG_SPLIT_PTLOCK_CPUS=4
286# CONFIG_RESOURCES_64BIT is not set
287# CONFIG_PHYS_ADDR_T_64BIT is not set 307# CONFIG_PHYS_ADDR_T_64BIT is not set
288CONFIG_ZONE_DMA_FLAG=1 308CONFIG_ZONE_DMA_FLAG=1
289CONFIG_VIRT_TO_BUS=y 309CONFIG_VIRT_TO_BUS=y
310CONFIG_UNEVICTABLE_LRU=y
311CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
312CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
290# CONFIG_BFIN_GPTIMERS is not set 313# CONFIG_BFIN_GPTIMERS is not set
291# CONFIG_DMA_UNCACHED_4M is not set 314# CONFIG_DMA_UNCACHED_4M is not set
292# CONFIG_DMA_UNCACHED_2M is not set 315# CONFIG_DMA_UNCACHED_2M is not set
@@ -297,10 +320,9 @@ CONFIG_DMA_UNCACHED_1M=y
297# Cache Support 320# Cache Support
298# 321#
299CONFIG_BFIN_ICACHE=y 322CONFIG_BFIN_ICACHE=y
300# CONFIG_BFIN_ICACHE_LOCK is not set 323CONFIG_BFIN_EXTMEM_ICACHEABLE=y
301CONFIG_BFIN_DCACHE=y 324CONFIG_BFIN_DCACHE=y
302# CONFIG_BFIN_DCACHE_BANKA is not set 325# CONFIG_BFIN_DCACHE_BANKA is not set
303CONFIG_BFIN_EXTMEM_ICACHEABLE=y
304CONFIG_BFIN_EXTMEM_DCACHEABLE=y 326CONFIG_BFIN_EXTMEM_DCACHEABLE=y
305CONFIG_BFIN_EXTMEM_WRITEBACK=y 327CONFIG_BFIN_EXTMEM_WRITEBACK=y
306# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 328# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -311,7 +333,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
311# CONFIG_MPU is not set 333# CONFIG_MPU is not set
312 334
313# 335#
314# Asynchonous Memory Configuration 336# Asynchronous Memory Configuration
315# 337#
316 338
317# 339#
@@ -337,6 +359,7 @@ CONFIG_BANK_3=0xFFC2
337# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 359# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
338# 360#
339# CONFIG_ARCH_SUPPORTS_MSI is not set 361# CONFIG_ARCH_SUPPORTS_MSI is not set
362# CONFIG_PCCARD is not set
340 363
341# 364#
342# Executable file formats 365# Executable file formats
@@ -366,11 +389,6 @@ CONFIG_NET=y
366CONFIG_PACKET=y 389CONFIG_PACKET=y
367# CONFIG_PACKET_MMAP is not set 390# CONFIG_PACKET_MMAP is not set
368CONFIG_UNIX=y 391CONFIG_UNIX=y
369CONFIG_XFRM=y
370# CONFIG_XFRM_USER is not set
371# CONFIG_XFRM_SUB_POLICY is not set
372# CONFIG_XFRM_MIGRATE is not set
373# CONFIG_XFRM_STATISTICS is not set
374# CONFIG_NET_KEY is not set 392# CONFIG_NET_KEY is not set
375CONFIG_INET=y 393CONFIG_INET=y
376# CONFIG_IP_MULTICAST is not set 394# CONFIG_IP_MULTICAST is not set
@@ -394,7 +412,6 @@ CONFIG_IP_PNP=y
394# CONFIG_INET_XFRM_MODE_BEET is not set 412# CONFIG_INET_XFRM_MODE_BEET is not set
395# CONFIG_INET_LRO is not set 413# CONFIG_INET_LRO is not set
396# CONFIG_INET_DIAG is not set 414# CONFIG_INET_DIAG is not set
397CONFIG_INET_TCP_DIAG=y
398# CONFIG_TCP_CONG_ADVANCED is not set 415# CONFIG_TCP_CONG_ADVANCED is not set
399CONFIG_TCP_CONG_CUBIC=y 416CONFIG_TCP_CONG_CUBIC=y
400CONFIG_DEFAULT_TCP_CONG="cubic" 417CONFIG_DEFAULT_TCP_CONG="cubic"
@@ -418,7 +435,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
418# CONFIG_LAPB is not set 435# CONFIG_LAPB is not set
419# CONFIG_ECONET is not set 436# CONFIG_ECONET is not set
420# CONFIG_WAN_ROUTER is not set 437# CONFIG_WAN_ROUTER is not set
438# CONFIG_PHONET is not set
421# CONFIG_NET_SCHED is not set 439# CONFIG_NET_SCHED is not set
440# CONFIG_DCB is not set
422 441
423# 442#
424# Network testing 443# Network testing
@@ -429,8 +448,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
429# CONFIG_IRDA is not set 448# CONFIG_IRDA is not set
430# CONFIG_BT is not set 449# CONFIG_BT is not set
431# CONFIG_AF_RXRPC is not set 450# CONFIG_AF_RXRPC is not set
432# CONFIG_PHONET is not set
433# CONFIG_WIRELESS is not set 451# CONFIG_WIRELESS is not set
452# CONFIG_WIMAX is not set
434# CONFIG_RFKILL is not set 453# CONFIG_RFKILL is not set
435# CONFIG_NET_9P is not set 454# CONFIG_NET_9P is not set
436 455
@@ -441,16 +460,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
441# 460#
442# Generic Driver Options 461# Generic Driver Options
443# 462#
463CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
444CONFIG_STANDALONE=y 464CONFIG_STANDALONE=y
445CONFIG_PREVENT_FIRMWARE_BUILD=y 465CONFIG_PREVENT_FIRMWARE_BUILD=y
466CONFIG_FW_LOADER=y
467CONFIG_FIRMWARE_IN_KERNEL=y
468CONFIG_EXTRA_FIRMWARE=""
446# CONFIG_SYS_HYPERVISOR is not set 469# CONFIG_SYS_HYPERVISOR is not set
447# CONFIG_CONNECTOR is not set 470# CONFIG_CONNECTOR is not set
448CONFIG_MTD=y 471CONFIG_MTD=y
449# CONFIG_MTD_DEBUG is not set 472# CONFIG_MTD_DEBUG is not set
473# CONFIG_MTD_TESTS is not set
450# CONFIG_MTD_CONCAT is not set 474# CONFIG_MTD_CONCAT is not set
451CONFIG_MTD_PARTITIONS=y 475CONFIG_MTD_PARTITIONS=y
452# CONFIG_MTD_REDBOOT_PARTS is not set 476# CONFIG_MTD_REDBOOT_PARTS is not set
453# CONFIG_MTD_CMDLINE_PARTS is not set 477CONFIG_MTD_CMDLINE_PARTS=y
454# CONFIG_MTD_AR7_PARTS is not set 478# CONFIG_MTD_AR7_PARTS is not set
455 479
456# 480#
@@ -486,22 +510,26 @@ CONFIG_MTD_CFI_I2=y
486CONFIG_MTD_CFI_INTELEXT=y 510CONFIG_MTD_CFI_INTELEXT=y
487# CONFIG_MTD_CFI_AMDSTD is not set 511# CONFIG_MTD_CFI_AMDSTD is not set
488# CONFIG_MTD_CFI_STAA is not set 512# CONFIG_MTD_CFI_STAA is not set
513# CONFIG_MTD_PSD4256G is not set
489CONFIG_MTD_CFI_UTIL=y 514CONFIG_MTD_CFI_UTIL=y
490CONFIG_MTD_RAM=y 515CONFIG_MTD_RAM=y
491# CONFIG_MTD_ROM is not set 516CONFIG_MTD_ROM=m
492# CONFIG_MTD_ABSENT is not set 517# CONFIG_MTD_ABSENT is not set
493 518
494# 519#
495# Mapping drivers for chip access 520# Mapping drivers for chip access
496# 521#
497CONFIG_MTD_COMPLEX_MAPPINGS=y 522CONFIG_MTD_COMPLEX_MAPPINGS=y
523# CONFIG_MTD_PHYSMAP is not set
498CONFIG_MTD_GPIO_ADDR=y 524CONFIG_MTD_GPIO_ADDR=y
499CONFIG_MTD_UCLINUX=y 525# CONFIG_MTD_UCLINUX is not set
500# CONFIG_MTD_PLATRAM is not set 526# CONFIG_MTD_PLATRAM is not set
501 527
502# 528#
503# Self-contained MTD device drivers 529# Self-contained MTD device drivers
504# 530#
531# CONFIG_MTD_DATAFLASH is not set
532# CONFIG_MTD_M25P80 is not set
505# CONFIG_MTD_SLRAM is not set 533# CONFIG_MTD_SLRAM is not set
506# CONFIG_MTD_PHRAM is not set 534# CONFIG_MTD_PHRAM is not set
507# CONFIG_MTD_MTDRAM is not set 535# CONFIG_MTD_MTDRAM is not set
@@ -517,6 +545,11 @@ CONFIG_MTD_UCLINUX=y
517# CONFIG_MTD_ONENAND is not set 545# CONFIG_MTD_ONENAND is not set
518 546
519# 547#
548# LPDDR flash memory drivers
549#
550# CONFIG_MTD_LPDDR is not set
551
552#
520# UBI - Unsorted block images 553# UBI - Unsorted block images
521# 554#
522# CONFIG_MTD_UBI is not set 555# CONFIG_MTD_UBI is not set
@@ -533,9 +566,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
533# CONFIG_ATA_OVER_ETH is not set 566# CONFIG_ATA_OVER_ETH is not set
534# CONFIG_BLK_DEV_HD is not set 567# CONFIG_BLK_DEV_HD is not set
535CONFIG_MISC_DEVICES=y 568CONFIG_MISC_DEVICES=y
536# CONFIG_EEPROM_93CX6 is not set
537# CONFIG_ENCLOSURE_SERVICES is not set 569# CONFIG_ENCLOSURE_SERVICES is not set
538# CONFIG_C2PORT is not set 570# CONFIG_C2PORT is not set
571
572#
573# EEPROM support
574#
575# CONFIG_EEPROM_AT25 is not set
576# CONFIG_EEPROM_93CX6 is not set
539CONFIG_HAVE_IDE=y 577CONFIG_HAVE_IDE=y
540# CONFIG_IDE is not set 578# CONFIG_IDE is not set
541 579
@@ -549,6 +587,7 @@ CONFIG_HAVE_IDE=y
549# CONFIG_ATA is not set 587# CONFIG_ATA is not set
550# CONFIG_MD is not set 588# CONFIG_MD is not set
551CONFIG_NETDEVICES=y 589CONFIG_NETDEVICES=y
590CONFIG_COMPAT_NET_DEV_OPS=y
552# CONFIG_DUMMY is not set 591# CONFIG_DUMMY is not set
553# CONFIG_BONDING is not set 592# CONFIG_BONDING is not set
554# CONFIG_MACVLAN is not set 593# CONFIG_MACVLAN is not set
@@ -570,6 +609,9 @@ CONFIG_PHYLIB=y
570# CONFIG_BROADCOM_PHY is not set 609# CONFIG_BROADCOM_PHY is not set
571# CONFIG_ICPLUS_PHY is not set 610# CONFIG_ICPLUS_PHY is not set
572# CONFIG_REALTEK_PHY is not set 611# CONFIG_REALTEK_PHY is not set
612# CONFIG_NATIONAL_PHY is not set
613# CONFIG_STE10XP is not set
614# CONFIG_LSI_ET1011C_PHY is not set
573# CONFIG_FIXED_PHY is not set 615# CONFIG_FIXED_PHY is not set
574# CONFIG_MDIO_BITBANG is not set 616# CONFIG_MDIO_BITBANG is not set
575CONFIG_NET_ETHERNET=y 617CONFIG_NET_ETHERNET=y
@@ -580,8 +622,11 @@ CONFIG_BFIN_TX_DESC_NUM=10
580CONFIG_BFIN_RX_DESC_NUM=20 622CONFIG_BFIN_RX_DESC_NUM=20
581# CONFIG_BFIN_MAC_RMII is not set 623# CONFIG_BFIN_MAC_RMII is not set
582# CONFIG_SMC91X is not set 624# CONFIG_SMC91X is not set
583# CONFIG_SMSC911X is not set
584# CONFIG_DM9000 is not set 625# CONFIG_DM9000 is not set
626# CONFIG_ENC28J60 is not set
627# CONFIG_ETHOC is not set
628# CONFIG_SMSC911X is not set
629# CONFIG_DNET is not set
585# CONFIG_IBM_NEW_EMAC_ZMII is not set 630# CONFIG_IBM_NEW_EMAC_ZMII is not set
586# CONFIG_IBM_NEW_EMAC_RGMII is not set 631# CONFIG_IBM_NEW_EMAC_RGMII is not set
587# CONFIG_IBM_NEW_EMAC_TAH is not set 632# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -598,7 +643,10 @@ CONFIG_BFIN_RX_DESC_NUM=20
598# 643#
599# CONFIG_WLAN_PRE80211 is not set 644# CONFIG_WLAN_PRE80211 is not set
600# CONFIG_WLAN_80211 is not set 645# CONFIG_WLAN_80211 is not set
601# CONFIG_IWLWIFI_LEDS is not set 646
647#
648# Enable WiMAX (Networking options) to see the WiMAX drivers
649#
602# CONFIG_WAN is not set 650# CONFIG_WAN is not set
603# CONFIG_PPP is not set 651# CONFIG_PPP is not set
604# CONFIG_SLIP is not set 652# CONFIG_SLIP is not set
@@ -622,15 +670,12 @@ CONFIG_BFIN_RX_DESC_NUM=20
622# 670#
623# Character devices 671# Character devices
624# 672#
625# CONFIG_AD9960 is not set
626CONFIG_BFIN_DMA_INTERFACE=m 673CONFIG_BFIN_DMA_INTERFACE=m
627# CONFIG_BFIN_PPI is not set 674# CONFIG_BFIN_PPI is not set
628# CONFIG_BFIN_PPIFCD is not set 675# CONFIG_BFIN_PPIFCD is not set
629# CONFIG_BFIN_SIMPLE_TIMER is not set 676# CONFIG_BFIN_SIMPLE_TIMER is not set
630# CONFIG_BFIN_SPI_ADC is not set 677# CONFIG_BFIN_SPI_ADC is not set
631CONFIG_BFIN_SPORT=y 678CONFIG_BFIN_SPORT=y
632# CONFIG_BFIN_TIMER_LATENCY is not set
633# CONFIG_SIMPLE_GPIO is not set
634# CONFIG_VT is not set 679# CONFIG_VT is not set
635# CONFIG_DEVKMEM is not set 680# CONFIG_DEVKMEM is not set
636# CONFIG_BFIN_JTAG_COMM is not set 681# CONFIG_BFIN_JTAG_COMM is not set
@@ -644,6 +689,7 @@ CONFIG_BFIN_SPORT=y
644# 689#
645# Non-8250 serial port support 690# Non-8250 serial port support
646# 691#
692# CONFIG_SERIAL_MAX3100 is not set
647CONFIG_SERIAL_BFIN=y 693CONFIG_SERIAL_BFIN=y
648CONFIG_SERIAL_BFIN_CONSOLE=y 694CONFIG_SERIAL_BFIN_CONSOLE=y
649CONFIG_SERIAL_BFIN_DMA=y 695CONFIG_SERIAL_BFIN_DMA=y
@@ -656,6 +702,7 @@ CONFIG_SERIAL_CORE=y
656CONFIG_SERIAL_CORE_CONSOLE=y 702CONFIG_SERIAL_CORE_CONSOLE=y
657# CONFIG_SERIAL_BFIN_SPORT is not set 703# CONFIG_SERIAL_BFIN_SPORT is not set
658CONFIG_UNIX98_PTYS=y 704CONFIG_UNIX98_PTYS=y
705# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
659# CONFIG_LEGACY_PTYS is not set 706# CONFIG_LEGACY_PTYS is not set
660 707
661# 708#
@@ -668,7 +715,23 @@ CONFIG_UNIX98_PTYS=y
668# CONFIG_RAW_DRIVER is not set 715# CONFIG_RAW_DRIVER is not set
669# CONFIG_TCG_TPM is not set 716# CONFIG_TCG_TPM is not set
670# CONFIG_I2C is not set 717# CONFIG_I2C is not set
671# CONFIG_SPI is not set 718CONFIG_SPI=y
719CONFIG_SPI_MASTER=y
720
721#
722# SPI Master Controller Drivers
723#
724CONFIG_SPI_BFIN=y
725# CONFIG_SPI_BFIN_LOCK is not set
726# CONFIG_SPI_BFIN_SPORT is not set
727# CONFIG_SPI_BITBANG is not set
728# CONFIG_SPI_GPIO is not set
729
730#
731# SPI Protocol Masters
732#
733# CONFIG_SPI_SPIDEV is not set
734# CONFIG_SPI_TLE62X0 is not set
672CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 735CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
673CONFIG_GPIOLIB=y 736CONFIG_GPIOLIB=y
674CONFIG_GPIO_SYSFS=y 737CONFIG_GPIO_SYSFS=y
@@ -688,15 +751,21 @@ CONFIG_GPIO_SYSFS=y
688# 751#
689# SPI GPIO expanders: 752# SPI GPIO expanders:
690# 753#
754# CONFIG_GPIO_MAX7301 is not set
755# CONFIG_GPIO_MCP23S08 is not set
691# CONFIG_W1 is not set 756# CONFIG_W1 is not set
692# CONFIG_POWER_SUPPLY is not set 757# CONFIG_POWER_SUPPLY is not set
693CONFIG_HWMON=y 758CONFIG_HWMON=y
694# CONFIG_HWMON_VID is not set 759# CONFIG_HWMON_VID is not set
760# CONFIG_SENSORS_ADCXX is not set
695# CONFIG_SENSORS_F71805F is not set 761# CONFIG_SENSORS_F71805F is not set
696# CONFIG_SENSORS_F71882FG is not set 762# CONFIG_SENSORS_F71882FG is not set
697# CONFIG_SENSORS_IT87 is not set 763# CONFIG_SENSORS_IT87 is not set
764# CONFIG_SENSORS_LM70 is not set
765# CONFIG_SENSORS_MAX1111 is not set
698# CONFIG_SENSORS_PC87360 is not set 766# CONFIG_SENSORS_PC87360 is not set
699# CONFIG_SENSORS_PC87427 is not set 767# CONFIG_SENSORS_PC87427 is not set
768# CONFIG_SENSORS_SHT15 is not set
700# CONFIG_SENSORS_SMSC47M1 is not set 769# CONFIG_SENSORS_SMSC47M1 is not set
701# CONFIG_SENSORS_SMSC47B397 is not set 770# CONFIG_SENSORS_SMSC47B397 is not set
702# CONFIG_SENSORS_VT1211 is not set 771# CONFIG_SENSORS_VT1211 is not set
@@ -758,21 +827,74 @@ CONFIG_USB_ARCH_HAS_HCD=y
758# CONFIG_USB is not set 827# CONFIG_USB is not set
759# CONFIG_USB_OTG_WHITELIST is not set 828# CONFIG_USB_OTG_WHITELIST is not set
760# CONFIG_USB_OTG_BLACKLIST_HUB is not set 829# CONFIG_USB_OTG_BLACKLIST_HUB is not set
761 830# CONFIG_USB_GADGET_MUSB_HDRC is not set
762# 831
763# Enable Host or Gadget support to see Inventra options 832#
764# 833# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
765 834#
766# 835CONFIG_USB_GADGET=m
767# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 836# CONFIG_USB_GADGET_DEBUG_FILES is not set
768# 837# CONFIG_USB_GADGET_DEBUG_FS is not set
769# CONFIG_USB_GADGET is not set 838CONFIG_USB_GADGET_VBUS_DRAW=2
770# CONFIG_MMC is not set 839CONFIG_USB_GADGET_SELECTED=y
840# CONFIG_USB_GADGET_AT91 is not set
841# CONFIG_USB_GADGET_ATMEL_USBA is not set
842# CONFIG_USB_GADGET_FSL_USB2 is not set
843# CONFIG_USB_GADGET_LH7A40X is not set
844# CONFIG_USB_GADGET_OMAP is not set
845# CONFIG_USB_GADGET_PXA25X is not set
846# CONFIG_USB_GADGET_PXA27X is not set
847# CONFIG_USB_GADGET_S3C2410 is not set
848# CONFIG_USB_GADGET_IMX is not set
849# CONFIG_USB_GADGET_M66592 is not set
850# CONFIG_USB_GADGET_AMD5536UDC is not set
851# CONFIG_USB_GADGET_FSL_QE is not set
852# CONFIG_USB_GADGET_CI13XXX is not set
853CONFIG_USB_GADGET_NET2272=y
854CONFIG_USB_NET2272=m
855# CONFIG_USB_GADGET_NET2280 is not set
856# CONFIG_USB_GADGET_GOKU is not set
857# CONFIG_USB_GADGET_DUMMY_HCD is not set
858CONFIG_USB_GADGET_DUALSPEED=y
859# CONFIG_USB_ZERO is not set
860# CONFIG_USB_AUDIO is not set
861CONFIG_USB_ETH=m
862CONFIG_USB_ETH_RNDIS=y
863# CONFIG_USB_GADGETFS is not set
864# CONFIG_USB_FILE_STORAGE is not set
865# CONFIG_USB_G_SERIAL is not set
866# CONFIG_USB_MIDI_GADGET is not set
867# CONFIG_USB_G_PRINTER is not set
868# CONFIG_USB_CDC_COMPOSITE is not set
869
870#
871# OTG and related infrastructure
872#
873# CONFIG_USB_GPIO_VBUS is not set
874# CONFIG_NOP_USB_XCEIV is not set
875CONFIG_MMC=y
876# CONFIG_MMC_DEBUG is not set
877# CONFIG_MMC_UNSAFE_RESUME is not set
878
879#
880# MMC/SD/SDIO Card Drivers
881#
882CONFIG_MMC_BLOCK=y
883# CONFIG_MMC_BLOCK_BOUNCE is not set
884# CONFIG_SDIO_UART is not set
885# CONFIG_MMC_TEST is not set
886
887#
888# MMC/SD/SDIO Host Controller Drivers
889#
890# CONFIG_MMC_SDHCI is not set
891CONFIG_MMC_SPI=m
771# CONFIG_MEMSTICK is not set 892# CONFIG_MEMSTICK is not set
772# CONFIG_NEW_LEDS is not set 893# CONFIG_NEW_LEDS is not set
773# CONFIG_ACCESSIBILITY is not set 894# CONFIG_ACCESSIBILITY is not set
774# CONFIG_RTC_CLASS is not set 895# CONFIG_RTC_CLASS is not set
775# CONFIG_DMADEVICES is not set 896# CONFIG_DMADEVICES is not set
897# CONFIG_AUXDISPLAY is not set
776# CONFIG_UIO is not set 898# CONFIG_UIO is not set
777# CONFIG_STAGING is not set 899# CONFIG_STAGING is not set
778 900
@@ -789,9 +911,10 @@ CONFIG_FS_MBCACHE=y
789# CONFIG_REISERFS_FS is not set 911# CONFIG_REISERFS_FS is not set
790# CONFIG_JFS_FS is not set 912# CONFIG_JFS_FS is not set
791# CONFIG_FS_POSIX_ACL is not set 913# CONFIG_FS_POSIX_ACL is not set
792CONFIG_FILE_LOCKING=y
793# CONFIG_XFS_FS is not set 914# CONFIG_XFS_FS is not set
794# CONFIG_OCFS2_FS is not set 915# CONFIG_OCFS2_FS is not set
916# CONFIG_BTRFS_FS is not set
917CONFIG_FILE_LOCKING=y
795# CONFIG_DNOTIFY is not set 918# CONFIG_DNOTIFY is not set
796CONFIG_INOTIFY=y 919CONFIG_INOTIFY=y
797CONFIG_INOTIFY_USER=y 920CONFIG_INOTIFY_USER=y
@@ -801,6 +924,11 @@ CONFIG_INOTIFY_USER=y
801# CONFIG_FUSE_FS is not set 924# CONFIG_FUSE_FS is not set
802 925
803# 926#
927# Caches
928#
929# CONFIG_FSCACHE is not set
930
931#
804# CD-ROM/DVD Filesystems 932# CD-ROM/DVD Filesystems
805# 933#
806# CONFIG_ISO9660_FS is not set 934# CONFIG_ISO9660_FS is not set
@@ -809,8 +937,11 @@ CONFIG_INOTIFY_USER=y
809# 937#
810# DOS/FAT/NT Filesystems 938# DOS/FAT/NT Filesystems
811# 939#
812# CONFIG_MSDOS_FS is not set 940CONFIG_FAT_FS=y
813# CONFIG_VFAT_FS is not set 941CONFIG_MSDOS_FS=y
942CONFIG_VFAT_FS=y
943CONFIG_FAT_DEFAULT_CODEPAGE=437
944CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
814# CONFIG_NTFS_FS is not set 945# CONFIG_NTFS_FS is not set
815 946
816# 947#
@@ -822,10 +953,7 @@ CONFIG_SYSFS=y
822# CONFIG_TMPFS is not set 953# CONFIG_TMPFS is not set
823# CONFIG_HUGETLB_PAGE is not set 954# CONFIG_HUGETLB_PAGE is not set
824# CONFIG_CONFIGFS_FS is not set 955# CONFIG_CONFIGFS_FS is not set
825 956CONFIG_MISC_FILESYSTEMS=y
826#
827# Miscellaneous filesystems
828#
829# CONFIG_ADFS_FS is not set 957# CONFIG_ADFS_FS is not set
830# CONFIG_AFFS_FS is not set 958# CONFIG_AFFS_FS is not set
831# CONFIG_HFS_FS is not set 959# CONFIG_HFS_FS is not set
@@ -833,9 +961,19 @@ CONFIG_SYSFS=y
833# CONFIG_BEFS_FS is not set 961# CONFIG_BEFS_FS is not set
834# CONFIG_BFS_FS is not set 962# CONFIG_BFS_FS is not set
835# CONFIG_EFS_FS is not set 963# CONFIG_EFS_FS is not set
836# CONFIG_JFFS2_FS is not set 964CONFIG_JFFS2_FS=y
837# CONFIG_YAFFS_FS is not set 965CONFIG_JFFS2_FS_DEBUG=0
966CONFIG_JFFS2_FS_WRITEBUFFER=y
967# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
968# CONFIG_JFFS2_SUMMARY is not set
969# CONFIG_JFFS2_FS_XATTR is not set
970# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
971CONFIG_JFFS2_ZLIB=y
972# CONFIG_JFFS2_LZO is not set
973CONFIG_JFFS2_RTIME=y
974# CONFIG_JFFS2_RUBIN is not set
838# CONFIG_CRAMFS is not set 975# CONFIG_CRAMFS is not set
976# CONFIG_SQUASHFS is not set
839# CONFIG_VXFS_FS is not set 977# CONFIG_VXFS_FS is not set
840# CONFIG_MINIX_FS is not set 978# CONFIG_MINIX_FS is not set
841# CONFIG_OMFS_FS is not set 979# CONFIG_OMFS_FS is not set
@@ -844,14 +982,70 @@ CONFIG_SYSFS=y
844# CONFIG_ROMFS_FS is not set 982# CONFIG_ROMFS_FS is not set
845# CONFIG_SYSV_FS is not set 983# CONFIG_SYSV_FS is not set
846# CONFIG_UFS_FS is not set 984# CONFIG_UFS_FS is not set
847# CONFIG_NETWORK_FILESYSTEMS is not set 985# CONFIG_NILFS2_FS is not set
986CONFIG_NETWORK_FILESYSTEMS=y
987CONFIG_NFS_FS=m
988CONFIG_NFS_V3=y
989# CONFIG_NFS_V3_ACL is not set
990# CONFIG_NFS_V4 is not set
991# CONFIG_NFSD is not set
992CONFIG_LOCKD=m
993CONFIG_LOCKD_V4=y
994CONFIG_NFS_COMMON=y
995CONFIG_SUNRPC=m
996# CONFIG_RPCSEC_GSS_KRB5 is not set
997# CONFIG_RPCSEC_GSS_SPKM3 is not set
998# CONFIG_SMB_FS is not set
999# CONFIG_CIFS is not set
1000# CONFIG_NCP_FS is not set
1001# CONFIG_CODA_FS is not set
1002# CONFIG_AFS_FS is not set
848 1003
849# 1004#
850# Partition Types 1005# Partition Types
851# 1006#
852# CONFIG_PARTITION_ADVANCED is not set 1007# CONFIG_PARTITION_ADVANCED is not set
853CONFIG_MSDOS_PARTITION=y 1008CONFIG_MSDOS_PARTITION=y
854# CONFIG_NLS is not set 1009CONFIG_NLS=y
1010CONFIG_NLS_DEFAULT="iso8859-1"
1011CONFIG_NLS_CODEPAGE_437=y
1012# CONFIG_NLS_CODEPAGE_737 is not set
1013# CONFIG_NLS_CODEPAGE_775 is not set
1014# CONFIG_NLS_CODEPAGE_850 is not set
1015# CONFIG_NLS_CODEPAGE_852 is not set
1016# CONFIG_NLS_CODEPAGE_855 is not set
1017# CONFIG_NLS_CODEPAGE_857 is not set
1018# CONFIG_NLS_CODEPAGE_860 is not set
1019# CONFIG_NLS_CODEPAGE_861 is not set
1020# CONFIG_NLS_CODEPAGE_862 is not set
1021# CONFIG_NLS_CODEPAGE_863 is not set
1022# CONFIG_NLS_CODEPAGE_864 is not set
1023# CONFIG_NLS_CODEPAGE_865 is not set
1024# CONFIG_NLS_CODEPAGE_866 is not set
1025# CONFIG_NLS_CODEPAGE_869 is not set
1026# CONFIG_NLS_CODEPAGE_936 is not set
1027# CONFIG_NLS_CODEPAGE_950 is not set
1028# CONFIG_NLS_CODEPAGE_932 is not set
1029# CONFIG_NLS_CODEPAGE_949 is not set
1030# CONFIG_NLS_CODEPAGE_874 is not set
1031# CONFIG_NLS_ISO8859_8 is not set
1032# CONFIG_NLS_CODEPAGE_1250 is not set
1033# CONFIG_NLS_CODEPAGE_1251 is not set
1034# CONFIG_NLS_ASCII is not set
1035CONFIG_NLS_ISO8859_1=y
1036# CONFIG_NLS_ISO8859_2 is not set
1037# CONFIG_NLS_ISO8859_3 is not set
1038# CONFIG_NLS_ISO8859_4 is not set
1039# CONFIG_NLS_ISO8859_5 is not set
1040# CONFIG_NLS_ISO8859_6 is not set
1041# CONFIG_NLS_ISO8859_7 is not set
1042# CONFIG_NLS_ISO8859_9 is not set
1043# CONFIG_NLS_ISO8859_13 is not set
1044# CONFIG_NLS_ISO8859_14 is not set
1045# CONFIG_NLS_ISO8859_15 is not set
1046# CONFIG_NLS_KOI8_R is not set
1047# CONFIG_NLS_KOI8_U is not set
1048# CONFIG_NLS_UTF8 is not set
855# CONFIG_DLM is not set 1049# CONFIG_DLM is not set
856 1050
857# 1051#
@@ -867,14 +1061,28 @@ CONFIG_DEBUG_FS=y
867# CONFIG_HEADERS_CHECK is not set 1061# CONFIG_HEADERS_CHECK is not set
868CONFIG_DEBUG_SECTION_MISMATCH=y 1062CONFIG_DEBUG_SECTION_MISMATCH=y
869# CONFIG_DEBUG_KERNEL is not set 1063# CONFIG_DEBUG_KERNEL is not set
870CONFIG_DEBUG_BUGVERBOSE=y 1064# CONFIG_DEBUG_BUGVERBOSE is not set
871# CONFIG_DEBUG_MEMORY_INIT is not set 1065# CONFIG_DEBUG_MEMORY_INIT is not set
872# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1066# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1067CONFIG_HAVE_FUNCTION_TRACER=y
1068CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1069CONFIG_TRACING_SUPPORT=y
873 1070
874# 1071#
875# Tracers 1072# Tracers
876# 1073#
877# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1074# CONFIG_FUNCTION_TRACER is not set
1075# CONFIG_IRQSOFF_TRACER is not set
1076# CONFIG_SCHED_TRACER is not set
1077# CONFIG_CONTEXT_SWITCH_TRACER is not set
1078# CONFIG_EVENT_TRACER is not set
1079# CONFIG_BOOT_TRACER is not set
1080# CONFIG_TRACE_BRANCH_PROFILING is not set
1081# CONFIG_STACK_TRACER is not set
1082# CONFIG_KMEMTRACE is not set
1083# CONFIG_WORKQUEUE_TRACER is not set
1084# CONFIG_BLK_DEV_IO_TRACE is not set
1085# CONFIG_DYNAMIC_DEBUG is not set
878# CONFIG_SAMPLES is not set 1086# CONFIG_SAMPLES is not set
879CONFIG_HAVE_ARCH_KGDB=y 1087CONFIG_HAVE_ARCH_KGDB=y
880CONFIG_DEBUG_VERBOSE=y 1088CONFIG_DEBUG_VERBOSE=y
@@ -888,9 +1096,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
888CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1096CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
889# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1097# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
890# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1098# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
891# CONFIG_EARLY_PRINTK is not set 1099CONFIG_EARLY_PRINTK=y
892CONFIG_CPLB_INFO=y 1100CONFIG_CPLB_INFO=y
893CONFIG_ACCESS_CHECK=y 1101CONFIG_ACCESS_CHECK=y
1102# CONFIG_BFIN_ISRAM_SELF_TEST is not set
894 1103
895# 1104#
896# Security options 1105# Security options
@@ -899,8 +1108,9 @@ CONFIG_ACCESS_CHECK=y
899CONFIG_SECURITY=y 1108CONFIG_SECURITY=y
900# CONFIG_SECURITYFS is not set 1109# CONFIG_SECURITYFS is not set
901# CONFIG_SECURITY_NETWORK is not set 1110# CONFIG_SECURITY_NETWORK is not set
1111# CONFIG_SECURITY_PATH is not set
902# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1112# CONFIG_SECURITY_FILE_CAPABILITIES is not set
903CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 1113# CONFIG_SECURITY_TOMOYO is not set
904CONFIG_CRYPTO=y 1114CONFIG_CRYPTO=y
905 1115
906# 1116#
@@ -979,6 +1189,7 @@ CONFIG_CRYPTO=y
979# Compression 1189# Compression
980# 1190#
981# CONFIG_CRYPTO_DEFLATE is not set 1191# CONFIG_CRYPTO_DEFLATE is not set
1192# CONFIG_CRYPTO_ZLIB is not set
982# CONFIG_CRYPTO_LZO is not set 1193# CONFIG_CRYPTO_LZO is not set
983 1194
984# 1195#
@@ -986,19 +1197,24 @@ CONFIG_CRYPTO=y
986# 1197#
987# CONFIG_CRYPTO_ANSI_CPRNG is not set 1198# CONFIG_CRYPTO_ANSI_CPRNG is not set
988CONFIG_CRYPTO_HW=y 1199CONFIG_CRYPTO_HW=y
1200# CONFIG_BINARY_PRINTF is not set
989 1201
990# 1202#
991# Library routines 1203# Library routines
992# 1204#
993CONFIG_BITREVERSE=y 1205CONFIG_BITREVERSE=y
1206CONFIG_GENERIC_FIND_LAST_BIT=y
994CONFIG_CRC_CCITT=m 1207CONFIG_CRC_CCITT=m
995# CONFIG_CRC16 is not set 1208# CONFIG_CRC16 is not set
996# CONFIG_CRC_T10DIF is not set 1209# CONFIG_CRC_T10DIF is not set
997# CONFIG_CRC_ITU_T is not set 1210CONFIG_CRC_ITU_T=y
998CONFIG_CRC32=y 1211CONFIG_CRC32=y
999# CONFIG_CRC7 is not set 1212CONFIG_CRC7=y
1000# CONFIG_LIBCRC32C is not set 1213# CONFIG_LIBCRC32C is not set
1001CONFIG_ZLIB_INFLATE=y 1214CONFIG_ZLIB_INFLATE=y
1215CONFIG_ZLIB_DEFLATE=y
1216CONFIG_DECOMPRESS_LZMA=y
1002CONFIG_HAS_IOMEM=y 1217CONFIG_HAS_IOMEM=y
1003CONFIG_HAS_IOPORT=y 1218CONFIG_HAS_IOPORT=y
1004CONFIG_HAS_DMA=y 1219CONFIG_HAS_DMA=y
1220CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index 7fc8dfa1719f..efcc90d2f345 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -1,94 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.16 3# Linux kernel version: 2.6.30.5
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
10CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
11CONFIG_SEMAPHORE_SLEEPERS=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y 14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y 15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_TIME=y
17CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
18CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
19CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
20CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
21 23
22# 24#
23# Code maturity level options 25# General setup
24# 26#
25CONFIG_EXPERIMENTAL=y 27CONFIG_EXPERIMENTAL=y
26CONFIG_BROKEN_ON_SMP=y 28CONFIG_BROKEN_ON_SMP=y
27CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
28
29#
30# General setup
31#
32CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
33CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
34CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
35# CONFIG_IPC_NS is not set
36CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
37# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
38# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
39# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
40# CONFIG_UTS_NS is not set
41# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
42CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
43CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
44CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
45# CONFIG_SYSFS_DEPRECATED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
58# CONFIG_SYSFS_DEPRECATED_V2 is not set
46# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
47# CONFIG_BLK_DEV_INITRD is not set 60# CONFIG_NAMESPACES is not set
61CONFIG_BLK_DEV_INITRD=y
62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
49# CONFIG_SYSCTL is not set 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
50CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
51# CONFIG_UID16 is not set 70# CONFIG_UID16 is not set
52# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
53CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
55# CONFIG_HOTPLUG is not set 74# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y
56CONFIG_PRINTK=y 76CONFIG_PRINTK=y
57CONFIG_BUG=y 77CONFIG_BUG=y
58# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
59CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
60# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y 81CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y 82CONFIG_SIGNALFD=y
83CONFIG_TIMERFD=y
64CONFIG_EVENTFD=y 84CONFIG_EVENTFD=y
85CONFIG_AIO=y
65CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 87CONFIG_COMPAT_BRK=y
67# CONFIG_NP2 is not set
68CONFIG_SLAB=y 88CONFIG_SLAB=y
69# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
70# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
71CONFIG_RT_MUTEXES=y 91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
72CONFIG_TINY_SHMEM=y 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
97CONFIG_SLABINFO=y
73CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
74
75#
76# Loadable module support
77#
78CONFIG_MODULES=y 99CONFIG_MODULES=y
100# CONFIG_MODULE_FORCE_LOAD is not set
79CONFIG_MODULE_UNLOAD=y 101CONFIG_MODULE_UNLOAD=y
80# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
81# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
82# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
83CONFIG_KMOD=y
84
85#
86# Block layer
87#
88CONFIG_BLOCK=y 105CONFIG_BLOCK=y
89# CONFIG_LBD is not set 106# CONFIG_LBD is not set
90# CONFIG_BLK_DEV_IO_TRACE is not set 107# CONFIG_BLK_DEV_BSG is not set
91# CONFIG_LSF is not set 108# CONFIG_BLK_DEV_INTEGRITY is not set
92 109
93# 110#
94# IO Schedulers 111# IO Schedulers
@@ -105,6 +122,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
105CONFIG_PREEMPT_NONE=y 122CONFIG_PREEMPT_NONE=y
106# CONFIG_PREEMPT_VOLUNTARY is not set 123# CONFIG_PREEMPT_VOLUNTARY is not set
107# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
125# CONFIG_FREEZER is not set
108 126
109# 127#
110# Blackfin Processor Options 128# Blackfin Processor Options
@@ -113,6 +131,10 @@ CONFIG_PREEMPT_NONE=y
113# 131#
114# Processor and Board Settings 132# Processor and Board Settings
115# 133#
134# CONFIG_BF512 is not set
135# CONFIG_BF514 is not set
136# CONFIG_BF516 is not set
137# CONFIG_BF518 is not set
116# CONFIG_BF522 is not set 138# CONFIG_BF522 is not set
117# CONFIG_BF523 is not set 139# CONFIG_BF523 is not set
118# CONFIG_BF524 is not set 140# CONFIG_BF524 is not set
@@ -125,22 +147,31 @@ CONFIG_PREEMPT_NONE=y
125# CONFIG_BF534 is not set 147# CONFIG_BF534 is not set
126# CONFIG_BF536 is not set 148# CONFIG_BF536 is not set
127CONFIG_BF537=y 149CONFIG_BF537=y
150# CONFIG_BF538 is not set
151# CONFIG_BF539 is not set
128# CONFIG_BF542 is not set 152# CONFIG_BF542 is not set
153# CONFIG_BF542M is not set
129# CONFIG_BF544 is not set 154# CONFIG_BF544 is not set
155# CONFIG_BF544M is not set
130# CONFIG_BF547 is not set 156# CONFIG_BF547 is not set
157# CONFIG_BF547M is not set
131# CONFIG_BF548 is not set 158# CONFIG_BF548 is not set
159# CONFIG_BF548M is not set
132# CONFIG_BF549 is not set 160# CONFIG_BF549 is not set
161# CONFIG_BF549M is not set
133# CONFIG_BF561 is not set 162# CONFIG_BF561 is not set
163CONFIG_BF_REV_MIN=2
164CONFIG_BF_REV_MAX=3
134# CONFIG_BF_REV_0_0 is not set 165# CONFIG_BF_REV_0_0 is not set
135# CONFIG_BF_REV_0_1 is not set 166# CONFIG_BF_REV_0_1 is not set
136CONFIG_BF_REV_0_2=y 167CONFIG_BF_REV_0_2=y
137# CONFIG_BF_REV_0_3 is not set 168# CONFIG_BF_REV_0_3 is not set
138# CONFIG_BF_REV_0_4 is not set 169# CONFIG_BF_REV_0_4 is not set
139# CONFIG_BF_REV_0_5 is not set 170# CONFIG_BF_REV_0_5 is not set
171# CONFIG_BF_REV_0_6 is not set
140# CONFIG_BF_REV_ANY is not set 172# CONFIG_BF_REV_ANY is not set
141# CONFIG_BF_REV_NONE is not set 173# CONFIG_BF_REV_NONE is not set
142CONFIG_BF53x=y 174CONFIG_BF53x=y
143CONFIG_BFIN_SINGLE_CORE=y
144CONFIG_MEM_MT48LC16M16A2TG_75=y 175CONFIG_MEM_MT48LC16M16A2TG_75=y
145CONFIG_IRQ_PLL_WAKEUP=7 176CONFIG_IRQ_PLL_WAKEUP=7
146CONFIG_IRQ_RTC=8 177CONFIG_IRQ_RTC=8
@@ -150,7 +181,6 @@ CONFIG_IRQ_SPORT0_TX=9
150CONFIG_IRQ_SPORT1_RX=9 181CONFIG_IRQ_SPORT1_RX=9
151CONFIG_IRQ_SPORT1_TX=9 182CONFIG_IRQ_SPORT1_TX=9
152CONFIG_IRQ_TWI=10 183CONFIG_IRQ_TWI=10
153CONFIG_IRQ_SPI=10
154CONFIG_IRQ_UART0_RX=10 184CONFIG_IRQ_UART0_RX=10
155CONFIG_IRQ_UART0_TX=10 185CONFIG_IRQ_UART0_TX=10
156CONFIG_IRQ_UART1_RX=10 186CONFIG_IRQ_UART1_RX=10
@@ -169,11 +199,13 @@ CONFIG_IRQ_PORTG_INTB=12
169CONFIG_IRQ_MEM_DMA0=13 199CONFIG_IRQ_MEM_DMA0=13
170CONFIG_IRQ_MEM_DMA1=13 200CONFIG_IRQ_MEM_DMA1=13
171CONFIG_IRQ_WATCH=13 201CONFIG_IRQ_WATCH=13
202CONFIG_IRQ_SPI=10
172# CONFIG_BFIN537_STAMP is not set 203# CONFIG_BFIN537_STAMP is not set
173CONFIG_BFIN537_BLUETECHNIX_CM=y 204# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set
205CONFIG_BFIN537_BLUETECHNIX_CM_U=y
206# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
174# CONFIG_PNAV10 is not set 207# CONFIG_PNAV10 is not set
175# CONFIG_CAMSIG_MINOTAUR is not set 208# CONFIG_CAMSIG_MINOTAUR is not set
176# CONFIG_GENERIC_BF537_BOARD is not set
177 209
178# 210#
179# BF537 Specific Configuration 211# BF537 Specific Configuration
@@ -196,6 +228,7 @@ CONFIG_IRQ_PROG_INTA=12
196# Board customizations 228# Board customizations
197# 229#
198# CONFIG_CMDLINE_BOOL is not set 230# CONFIG_CMDLINE_BOOL is not set
231CONFIG_BOOT_LOAD=0x1000
199 232
200# 233#
201# Clock/PLL Setup 234# Clock/PLL Setup
@@ -215,13 +248,20 @@ CONFIG_HZ_250=y
215# CONFIG_HZ_300 is not set 248# CONFIG_HZ_300 is not set
216# CONFIG_HZ_1000 is not set 249# CONFIG_HZ_1000 is not set
217CONFIG_HZ=250 250CONFIG_HZ=250
251# CONFIG_SCHED_HRTICK is not set
252CONFIG_GENERIC_TIME=y
253CONFIG_GENERIC_CLOCKEVENTS=y
254# CONFIG_TICKSOURCE_GPTMR0 is not set
255CONFIG_TICKSOURCE_CORETMR=y
256# CONFIG_CYCLES_CLOCKSOURCE is not set
257# CONFIG_GPTMR0_CLOCKSOURCE is not set
258# CONFIG_NO_HZ is not set
259# CONFIG_HIGH_RES_TIMERS is not set
260CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
218 261
219# 262#
220# Memory Setup 263# Misc
221# 264#
222CONFIG_MAX_MEM_SIZE=32
223CONFIG_MEM_ADD_WIDTH=9
224CONFIG_BOOT_LOAD=0x1000
225CONFIG_BFIN_SCRATCH_REG_RETN=y 265CONFIG_BFIN_SCRATCH_REG_RETN=y
226# CONFIG_BFIN_SCRATCH_REG_RETE is not set 266# CONFIG_BFIN_SCRATCH_REG_RETE is not set
227# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set 267# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -248,6 +288,12 @@ CONFIG_IP_CHECKSUM_L1=y
248CONFIG_CACHELINE_ALIGNED_L1=y 288CONFIG_CACHELINE_ALIGNED_L1=y
249CONFIG_SYSCALL_TAB_L1=y 289CONFIG_SYSCALL_TAB_L1=y
250CONFIG_CPLB_SWITCH_TAB_L1=y 290CONFIG_CPLB_SWITCH_TAB_L1=y
291CONFIG_APP_STACK_L1=y
292
293#
294# Speed Optimizations
295#
296CONFIG_BFIN_INS_LOWOVERHEAD=y
251CONFIG_RAMKERNEL=y 297CONFIG_RAMKERNEL=y
252# CONFIG_ROMKERNEL is not set 298# CONFIG_ROMKERNEL is not set
253CONFIG_SELECT_MEMORY_MODEL=y 299CONFIG_SELECT_MEMORY_MODEL=y
@@ -256,12 +302,16 @@ CONFIG_FLATMEM_MANUAL=y
256# CONFIG_SPARSEMEM_MANUAL is not set 302# CONFIG_SPARSEMEM_MANUAL is not set
257CONFIG_FLATMEM=y 303CONFIG_FLATMEM=y
258CONFIG_FLAT_NODE_MEM_MAP=y 304CONFIG_FLAT_NODE_MEM_MAP=y
259# CONFIG_SPARSEMEM_STATIC is not set 305CONFIG_PAGEFLAGS_EXTENDED=y
260CONFIG_SPLIT_PTLOCK_CPUS=4 306CONFIG_SPLIT_PTLOCK_CPUS=4
261# CONFIG_RESOURCES_64BIT is not set 307# CONFIG_PHYS_ADDR_T_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1 308CONFIG_ZONE_DMA_FLAG=1
263CONFIG_LARGE_ALLOCS=y 309CONFIG_VIRT_TO_BUS=y
310CONFIG_UNEVICTABLE_LRU=y
311CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
312CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
264# CONFIG_BFIN_GPTIMERS is not set 313# CONFIG_BFIN_GPTIMERS is not set
314# CONFIG_DMA_UNCACHED_4M is not set
265# CONFIG_DMA_UNCACHED_2M is not set 315# CONFIG_DMA_UNCACHED_2M is not set
266CONFIG_DMA_UNCACHED_1M=y 316CONFIG_DMA_UNCACHED_1M=y
267# CONFIG_DMA_UNCACHED_NONE is not set 317# CONFIG_DMA_UNCACHED_NONE is not set
@@ -270,10 +320,9 @@ CONFIG_DMA_UNCACHED_1M=y
270# Cache Support 320# Cache Support
271# 321#
272CONFIG_BFIN_ICACHE=y 322CONFIG_BFIN_ICACHE=y
273# CONFIG_BFIN_ICACHE_LOCK is not set 323CONFIG_BFIN_EXTMEM_ICACHEABLE=y
274CONFIG_BFIN_DCACHE=y 324CONFIG_BFIN_DCACHE=y
275# CONFIG_BFIN_DCACHE_BANKA is not set 325# CONFIG_BFIN_DCACHE_BANKA is not set
276CONFIG_BFIN_EXTMEM_ICACHEABLE=y
277CONFIG_BFIN_EXTMEM_DCACHEABLE=y 326CONFIG_BFIN_EXTMEM_DCACHEABLE=y
278CONFIG_BFIN_EXTMEM_WRITEBACK=y 327CONFIG_BFIN_EXTMEM_WRITEBACK=y
279# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 328# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -284,7 +333,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
284# CONFIG_MPU is not set 333# CONFIG_MPU is not set
285 334
286# 335#
287# Asynchonous Memory Configuration 336# Asynchronous Memory Configuration
288# 337#
289 338
290# 339#
@@ -309,12 +358,8 @@ CONFIG_BANK_3=0xFFC2
309# 358#
310# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 359# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
311# 360#
312# CONFIG_PCI is not set
313# CONFIG_ARCH_SUPPORTS_MSI is not set 361# CONFIG_ARCH_SUPPORTS_MSI is not set
314 362# CONFIG_PCCARD is not set
315#
316# PCCARD (PCMCIA/CardBus) support
317#
318 363
319# 364#
320# Executable file formats 365# Executable file formats
@@ -323,22 +368,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
323CONFIG_BINFMT_FLAT=y 368CONFIG_BINFMT_FLAT=y
324CONFIG_BINFMT_ZFLAT=y 369CONFIG_BINFMT_ZFLAT=y
325CONFIG_BINFMT_SHARED_FLAT=y 370CONFIG_BINFMT_SHARED_FLAT=y
371# CONFIG_HAVE_AOUT is not set
326# CONFIG_BINFMT_MISC is not set 372# CONFIG_BINFMT_MISC is not set
327 373
328# 374#
329# Power management options 375# Power management options
330# 376#
331# CONFIG_PM is not set 377# CONFIG_PM is not set
332# CONFIG_PM_WAKEUP_BY_GPIO is not set 378CONFIG_ARCH_SUSPEND_POSSIBLE=y
333 379
334# 380#
335# CPU Frequency scaling 381# CPU Frequency scaling
336# 382#
337# CONFIG_CPU_FREQ is not set 383# CONFIG_CPU_FREQ is not set
338
339#
340# Networking
341#
342CONFIG_NET=y 384CONFIG_NET=y
343 385
344# 386#
@@ -347,10 +389,6 @@ CONFIG_NET=y
347CONFIG_PACKET=y 389CONFIG_PACKET=y
348# CONFIG_PACKET_MMAP is not set 390# CONFIG_PACKET_MMAP is not set
349CONFIG_UNIX=y 391CONFIG_UNIX=y
350CONFIG_XFRM=y
351# CONFIG_XFRM_USER is not set
352# CONFIG_XFRM_SUB_POLICY is not set
353# CONFIG_XFRM_MIGRATE is not set
354# CONFIG_NET_KEY is not set 392# CONFIG_NET_KEY is not set
355CONFIG_INET=y 393CONFIG_INET=y
356# CONFIG_IP_MULTICAST is not set 394# CONFIG_IP_MULTICAST is not set
@@ -369,15 +407,13 @@ CONFIG_IP_FIB_HASH=y
369# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 407# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
370# CONFIG_INET_XFRM_MODE_TUNNEL is not set 408# CONFIG_INET_XFRM_MODE_TUNNEL is not set
371# CONFIG_INET_XFRM_MODE_BEET is not set 409# CONFIG_INET_XFRM_MODE_BEET is not set
410CONFIG_INET_LRO=y
372# CONFIG_INET_DIAG is not set 411# CONFIG_INET_DIAG is not set
373CONFIG_INET_TCP_DIAG=y
374# CONFIG_TCP_CONG_ADVANCED is not set 412# CONFIG_TCP_CONG_ADVANCED is not set
375CONFIG_TCP_CONG_CUBIC=y 413CONFIG_TCP_CONG_CUBIC=y
376CONFIG_DEFAULT_TCP_CONG="cubic" 414CONFIG_DEFAULT_TCP_CONG="cubic"
377# CONFIG_TCP_MD5SIG is not set 415# CONFIG_TCP_MD5SIG is not set
378# CONFIG_IPV6 is not set 416# CONFIG_IPV6 is not set
379# CONFIG_INET6_XFRM_TUNNEL is not set
380# CONFIG_INET6_TUNNEL is not set
381# CONFIG_NETLABEL is not set 417# CONFIG_NETLABEL is not set
382# CONFIG_NETWORK_SECMARK is not set 418# CONFIG_NETWORK_SECMARK is not set
383# CONFIG_NETFILTER is not set 419# CONFIG_NETFILTER is not set
@@ -386,6 +422,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
386# CONFIG_TIPC is not set 422# CONFIG_TIPC is not set
387# CONFIG_ATM is not set 423# CONFIG_ATM is not set
388# CONFIG_BRIDGE is not set 424# CONFIG_BRIDGE is not set
425# CONFIG_NET_DSA is not set
389# CONFIG_VLAN_8021Q is not set 426# CONFIG_VLAN_8021Q is not set
390# CONFIG_DECNET is not set 427# CONFIG_DECNET is not set
391# CONFIG_LLC2 is not set 428# CONFIG_LLC2 is not set
@@ -395,29 +432,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
395# CONFIG_LAPB is not set 432# CONFIG_LAPB is not set
396# CONFIG_ECONET is not set 433# CONFIG_ECONET is not set
397# CONFIG_WAN_ROUTER is not set 434# CONFIG_WAN_ROUTER is not set
398 435# CONFIG_PHONET is not set
399#
400# QoS and/or fair queueing
401#
402# CONFIG_NET_SCHED is not set 436# CONFIG_NET_SCHED is not set
437# CONFIG_DCB is not set
403 438
404# 439#
405# Network testing 440# Network testing
406# 441#
407# CONFIG_NET_PKTGEN is not set 442# CONFIG_NET_PKTGEN is not set
408# CONFIG_HAMRADIO is not set 443# CONFIG_HAMRADIO is not set
444# CONFIG_CAN is not set
409# CONFIG_IRDA is not set 445# CONFIG_IRDA is not set
410# CONFIG_BT is not set 446# CONFIG_BT is not set
411# CONFIG_AF_RXRPC is not set 447# CONFIG_AF_RXRPC is not set
412 448# CONFIG_WIRELESS is not set
413# 449# CONFIG_WIMAX is not set
414# Wireless
415#
416# CONFIG_CFG80211 is not set
417# CONFIG_WIRELESS_EXT is not set
418# CONFIG_MAC80211 is not set
419# CONFIG_IEEE80211 is not set
420# CONFIG_RFKILL is not set 450# CONFIG_RFKILL is not set
451# CONFIG_NET_9P is not set
421 452
422# 453#
423# Device Drivers 454# Device Drivers
@@ -426,20 +457,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
426# 457#
427# Generic Driver Options 458# Generic Driver Options
428# 459#
460CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
429CONFIG_STANDALONE=y 461CONFIG_STANDALONE=y
430CONFIG_PREVENT_FIRMWARE_BUILD=y 462CONFIG_PREVENT_FIRMWARE_BUILD=y
463CONFIG_FW_LOADER=y
464CONFIG_FIRMWARE_IN_KERNEL=y
465CONFIG_EXTRA_FIRMWARE=""
431# CONFIG_SYS_HYPERVISOR is not set 466# CONFIG_SYS_HYPERVISOR is not set
432
433#
434# Connector - unified userspace <-> kernelspace linker
435#
436# CONFIG_CONNECTOR is not set 467# CONFIG_CONNECTOR is not set
437CONFIG_MTD=y 468CONFIG_MTD=y
438# CONFIG_MTD_DEBUG is not set 469# CONFIG_MTD_DEBUG is not set
470# CONFIG_MTD_TESTS is not set
439# CONFIG_MTD_CONCAT is not set 471# CONFIG_MTD_CONCAT is not set
440CONFIG_MTD_PARTITIONS=y 472CONFIG_MTD_PARTITIONS=y
441# CONFIG_MTD_REDBOOT_PARTS is not set 473# CONFIG_MTD_REDBOOT_PARTS is not set
442# CONFIG_MTD_CMDLINE_PARTS is not set 474CONFIG_MTD_CMDLINE_PARTS=y
475# CONFIG_MTD_AR7_PARTS is not set
443 476
444# 477#
445# User Modules And Translation Layers 478# User Modules And Translation Layers
@@ -452,12 +485,15 @@ CONFIG_MTD_BLOCK=y
452# CONFIG_INFTL is not set 485# CONFIG_INFTL is not set
453# CONFIG_RFD_FTL is not set 486# CONFIG_RFD_FTL is not set
454# CONFIG_SSFDC is not set 487# CONFIG_SSFDC is not set
488# CONFIG_MTD_OOPS is not set
455 489
456# 490#
457# RAM/ROM/Flash chip drivers 491# RAM/ROM/Flash chip drivers
458# 492#
459# CONFIG_MTD_CFI is not set 493CONFIG_MTD_CFI=y
460# CONFIG_MTD_JEDECPROBE is not set 494# CONFIG_MTD_JEDECPROBE is not set
495CONFIG_MTD_GEN_PROBE=y
496# CONFIG_MTD_CFI_ADV_OPTIONS is not set
461CONFIG_MTD_MAP_BANK_WIDTH_1=y 497CONFIG_MTD_MAP_BANK_WIDTH_1=y
462CONFIG_MTD_MAP_BANK_WIDTH_2=y 498CONFIG_MTD_MAP_BANK_WIDTH_2=y
463CONFIG_MTD_MAP_BANK_WIDTH_4=y 499CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -468,20 +504,29 @@ CONFIG_MTD_CFI_I1=y
468CONFIG_MTD_CFI_I2=y 504CONFIG_MTD_CFI_I2=y
469# CONFIG_MTD_CFI_I4 is not set 505# CONFIG_MTD_CFI_I4 is not set
470# CONFIG_MTD_CFI_I8 is not set 506# CONFIG_MTD_CFI_I8 is not set
507CONFIG_MTD_CFI_INTELEXT=y
508# CONFIG_MTD_CFI_AMDSTD is not set
509# CONFIG_MTD_CFI_STAA is not set
510# CONFIG_MTD_PSD4256G is not set
511CONFIG_MTD_CFI_UTIL=y
471CONFIG_MTD_RAM=y 512CONFIG_MTD_RAM=y
472# CONFIG_MTD_ROM is not set 513CONFIG_MTD_ROM=m
473# CONFIG_MTD_ABSENT is not set 514# CONFIG_MTD_ABSENT is not set
474 515
475# 516#
476# Mapping drivers for chip access 517# Mapping drivers for chip access
477# 518#
478# CONFIG_MTD_COMPLEX_MAPPINGS is not set 519CONFIG_MTD_COMPLEX_MAPPINGS=y
479CONFIG_MTD_UCLINUX=y 520# CONFIG_MTD_PHYSMAP is not set
521CONFIG_MTD_GPIO_ADDR=y
522# CONFIG_MTD_UCLINUX is not set
480# CONFIG_MTD_PLATRAM is not set 523# CONFIG_MTD_PLATRAM is not set
481 524
482# 525#
483# Self-contained MTD device drivers 526# Self-contained MTD device drivers
484# 527#
528# CONFIG_MTD_DATAFLASH is not set
529# CONFIG_MTD_M25P80 is not set
485# CONFIG_MTD_SLRAM is not set 530# CONFIG_MTD_SLRAM is not set
486# CONFIG_MTD_PHRAM is not set 531# CONFIG_MTD_PHRAM is not set
487# CONFIG_MTD_MTDRAM is not set 532# CONFIG_MTD_MTDRAM is not set
@@ -497,36 +542,36 @@ CONFIG_MTD_UCLINUX=y
497# CONFIG_MTD_ONENAND is not set 542# CONFIG_MTD_ONENAND is not set
498 543
499# 544#
500# UBI - Unsorted block images 545# LPDDR flash memory drivers
501# 546#
502# CONFIG_MTD_UBI is not set 547# CONFIG_MTD_LPDDR is not set
503 548
504# 549#
505# Parallel port support 550# UBI - Unsorted block images
506# 551#
552# CONFIG_MTD_UBI is not set
507# CONFIG_PARPORT is not set 553# CONFIG_PARPORT is not set
508 554CONFIG_BLK_DEV=y
509#
510# Plug and Play support
511#
512# CONFIG_PNPACPI is not set
513
514#
515# Block devices
516#
517# CONFIG_BLK_DEV_COW_COMMON is not set 555# CONFIG_BLK_DEV_COW_COMMON is not set
518# CONFIG_BLK_DEV_LOOP is not set 556# CONFIG_BLK_DEV_LOOP is not set
519# CONFIG_BLK_DEV_NBD is not set 557# CONFIG_BLK_DEV_NBD is not set
520CONFIG_BLK_DEV_RAM=y 558CONFIG_BLK_DEV_RAM=y
521CONFIG_BLK_DEV_RAM_COUNT=16 559CONFIG_BLK_DEV_RAM_COUNT=16
522CONFIG_BLK_DEV_RAM_SIZE=4096 560CONFIG_BLK_DEV_RAM_SIZE=4096
523CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 561# CONFIG_BLK_DEV_XIP is not set
524# CONFIG_CDROM_PKTCDVD is not set 562# CONFIG_CDROM_PKTCDVD is not set
525# CONFIG_ATA_OVER_ETH is not set 563# CONFIG_ATA_OVER_ETH is not set
564# CONFIG_BLK_DEV_HD is not set
565CONFIG_MISC_DEVICES=y
566# CONFIG_ENCLOSURE_SERVICES is not set
567# CONFIG_C2PORT is not set
526 568
527# 569#
528# Misc devices 570# EEPROM support
529# 571#
572# CONFIG_EEPROM_AT25 is not set
573# CONFIG_EEPROM_93CX6 is not set
574CONFIG_HAVE_IDE=y
530# CONFIG_IDE is not set 575# CONFIG_IDE is not set
531 576
532# 577#
@@ -534,35 +579,20 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
534# 579#
535# CONFIG_RAID_ATTRS is not set 580# CONFIG_RAID_ATTRS is not set
536# CONFIG_SCSI is not set 581# CONFIG_SCSI is not set
582# CONFIG_SCSI_DMA is not set
537# CONFIG_SCSI_NETLINK is not set 583# CONFIG_SCSI_NETLINK is not set
538# CONFIG_ATA is not set 584# CONFIG_ATA is not set
539
540#
541# Multi-device support (RAID and LVM)
542#
543# CONFIG_MD is not set 585# CONFIG_MD is not set
544
545#
546# Network device support
547#
548CONFIG_NETDEVICES=y 586CONFIG_NETDEVICES=y
587CONFIG_COMPAT_NET_DEV_OPS=y
549# CONFIG_DUMMY is not set 588# CONFIG_DUMMY is not set
550# CONFIG_BONDING is not set 589# CONFIG_BONDING is not set
590# CONFIG_MACVLAN is not set
551# CONFIG_EQUALIZER is not set 591# CONFIG_EQUALIZER is not set
552# CONFIG_TUN is not set 592# CONFIG_TUN is not set
553# CONFIG_PHYLIB is not set 593# CONFIG_VETH is not set
554 594# CONFIG_NET_ETHERNET is not set
555#
556# Ethernet (10 or 100Mbit)
557#
558CONFIG_NET_ETHERNET=y
559CONFIG_MII=y
560CONFIG_SMC91X=y
561# CONFIG_BFIN_MAC is not set
562# CONFIG_SMSC911X is not set
563# CONFIG_DM9000 is not set
564# CONFIG_NETDEV_1000 is not set 595# CONFIG_NETDEV_1000 is not set
565# CONFIG_AX88180 is not set
566# CONFIG_NETDEV_10000 is not set 596# CONFIG_NETDEV_10000 is not set
567 597
568# 598#
@@ -570,22 +600,17 @@ CONFIG_SMC91X=y
570# 600#
571# CONFIG_WLAN_PRE80211 is not set 601# CONFIG_WLAN_PRE80211 is not set
572# CONFIG_WLAN_80211 is not set 602# CONFIG_WLAN_80211 is not set
603
604#
605# Enable WiMAX (Networking options) to see the WiMAX drivers
606#
573# CONFIG_WAN is not set 607# CONFIG_WAN is not set
574# CONFIG_PPP is not set 608# CONFIG_PPP is not set
575# CONFIG_SLIP is not set 609# CONFIG_SLIP is not set
576# CONFIG_SHAPER is not set
577# CONFIG_NETCONSOLE is not set 610# CONFIG_NETCONSOLE is not set
578# CONFIG_NETPOLL is not set 611# CONFIG_NETPOLL is not set
579# CONFIG_NET_POLL_CONTROLLER is not set 612# CONFIG_NET_POLL_CONTROLLER is not set
580
581#
582# ISDN subsystem
583#
584# CONFIG_ISDN is not set 613# CONFIG_ISDN is not set
585
586#
587# Telephony Support
588#
589# CONFIG_PHONE is not set 614# CONFIG_PHONE is not set
590 615
591# 616#
@@ -602,16 +627,15 @@ CONFIG_SMC91X=y
602# 627#
603# Character devices 628# Character devices
604# 629#
605# CONFIG_AD9960 is not set 630CONFIG_BFIN_DMA_INTERFACE=m
606# CONFIG_SPI_ADC_BF533 is not set 631# CONFIG_BFIN_PPI is not set
607# CONFIG_BF5xx_PFLAGS is not set 632# CONFIG_BFIN_PPIFCD is not set
608# CONFIG_BF5xx_PPIFCD is not set
609# CONFIG_BFIN_SIMPLE_TIMER is not set 633# CONFIG_BFIN_SIMPLE_TIMER is not set
610# CONFIG_BF5xx_PPI is not set 634# CONFIG_BFIN_SPI_ADC is not set
611CONFIG_BFIN_SPORT=y 635CONFIG_BFIN_SPORT=y
612# CONFIG_BFIN_TIMER_LATENCY is not set
613# CONFIG_VT is not set 636# CONFIG_VT is not set
614# CONFIG_DEVKMEM is not set 637# CONFIG_DEVKMEM is not set
638# CONFIG_BFIN_JTAG_COMM is not set
615# CONFIG_SERIAL_NONSTANDARD is not set 639# CONFIG_SERIAL_NONSTANDARD is not set
616 640
617# 641#
@@ -622,6 +646,7 @@ CONFIG_BFIN_SPORT=y
622# 646#
623# Non-8250 serial port support 647# Non-8250 serial port support
624# 648#
649# CONFIG_SERIAL_MAX3100 is not set
625CONFIG_SERIAL_BFIN=y 650CONFIG_SERIAL_BFIN=y
626CONFIG_SERIAL_BFIN_CONSOLE=y 651CONFIG_SERIAL_BFIN_CONSOLE=y
627CONFIG_SERIAL_BFIN_DMA=y 652CONFIG_SERIAL_BFIN_DMA=y
@@ -634,165 +659,201 @@ CONFIG_SERIAL_CORE=y
634CONFIG_SERIAL_CORE_CONSOLE=y 659CONFIG_SERIAL_CORE_CONSOLE=y
635# CONFIG_SERIAL_BFIN_SPORT is not set 660# CONFIG_SERIAL_BFIN_SPORT is not set
636CONFIG_UNIX98_PTYS=y 661CONFIG_UNIX98_PTYS=y
662# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
637# CONFIG_LEGACY_PTYS is not set 663# CONFIG_LEGACY_PTYS is not set
638 664
639# 665#
640# CAN, the car bus and industrial fieldbus 666# CAN, the car bus and industrial fieldbus
641# 667#
642# CONFIG_CAN4LINUX is not set 668# CONFIG_CAN4LINUX is not set
643
644#
645# IPMI
646#
647# CONFIG_IPMI_HANDLER is not set 669# CONFIG_IPMI_HANDLER is not set
648# CONFIG_WATCHDOG is not set
649# CONFIG_HW_RANDOM is not set 670# CONFIG_HW_RANDOM is not set
650# CONFIG_GEN_RTC is not set
651# CONFIG_R3964 is not set 671# CONFIG_R3964 is not set
652# CONFIG_RAW_DRIVER is not set 672# CONFIG_RAW_DRIVER is not set
673# CONFIG_TCG_TPM is not set
674# CONFIG_I2C is not set
675CONFIG_SPI=y
676CONFIG_SPI_MASTER=y
653 677
654# 678#
655# TPM devices 679# SPI Master Controller Drivers
656# 680#
657# CONFIG_TCG_TPM is not set 681CONFIG_SPI_BFIN=y
658# CONFIG_I2C is not set 682# CONFIG_SPI_BFIN_LOCK is not set
683# CONFIG_SPI_BFIN_SPORT is not set
684# CONFIG_SPI_BITBANG is not set
685# CONFIG_SPI_GPIO is not set
659 686
687#
688# SPI Protocol Masters
689#
690# CONFIG_SPI_SPIDEV is not set
691# CONFIG_SPI_TLE62X0 is not set
660CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 692CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
661CONFIG_GPIOLIB=y 693CONFIG_GPIOLIB=y
662CONFIG_GPIO_SYSFS=y 694CONFIG_GPIO_SYSFS=y
663 695
664# 696#
665# SPI support 697# Memory mapped GPIO expanders:
698#
699
700#
701# I2C GPIO expanders:
666# 702#
667# CONFIG_SPI is not set
668# CONFIG_SPI_MASTER is not set
669 703
670# 704#
671# Dallas's 1-wire bus 705# PCI GPIO expanders:
672# 706#
707
708#
709# SPI GPIO expanders:
710#
711# CONFIG_GPIO_MAX7301 is not set
712# CONFIG_GPIO_MCP23S08 is not set
673# CONFIG_W1 is not set 713# CONFIG_W1 is not set
714# CONFIG_POWER_SUPPLY is not set
674CONFIG_HWMON=y 715CONFIG_HWMON=y
675# CONFIG_HWMON_VID is not set 716# CONFIG_HWMON_VID is not set
676# CONFIG_SENSORS_ABITUGURU is not set 717# CONFIG_SENSORS_ADCXX is not set
677# CONFIG_SENSORS_F71805F is not set 718# CONFIG_SENSORS_F71805F is not set
719# CONFIG_SENSORS_F71882FG is not set
720# CONFIG_SENSORS_IT87 is not set
721# CONFIG_SENSORS_LM70 is not set
722# CONFIG_SENSORS_MAX1111 is not set
723# CONFIG_SENSORS_PC87360 is not set
678# CONFIG_SENSORS_PC87427 is not set 724# CONFIG_SENSORS_PC87427 is not set
725# CONFIG_SENSORS_SHT15 is not set
679# CONFIG_SENSORS_SMSC47M1 is not set 726# CONFIG_SENSORS_SMSC47M1 is not set
680# CONFIG_SENSORS_SMSC47B397 is not set 727# CONFIG_SENSORS_SMSC47B397 is not set
681# CONFIG_SENSORS_VT1211 is not set 728# CONFIG_SENSORS_VT1211 is not set
682# CONFIG_SENSORS_W83627HF is not set 729# CONFIG_SENSORS_W83627HF is not set
730# CONFIG_SENSORS_W83627EHF is not set
683# CONFIG_HWMON_DEBUG_CHIP is not set 731# CONFIG_HWMON_DEBUG_CHIP is not set
732# CONFIG_THERMAL is not set
733# CONFIG_THERMAL_HWMON is not set
734# CONFIG_WATCHDOG is not set
735CONFIG_SSB_POSSIBLE=y
736
737#
738# Sonics Silicon Backplane
739#
740# CONFIG_SSB is not set
684 741
685# 742#
686# Multifunction device drivers 743# Multifunction device drivers
687# 744#
745# CONFIG_MFD_CORE is not set
688# CONFIG_MFD_SM501 is not set 746# CONFIG_MFD_SM501 is not set
747# CONFIG_HTC_PASIC3 is not set
748# CONFIG_MFD_TMIO is not set
749# CONFIG_REGULATOR is not set
689 750
690# 751#
691# Multimedia devices 752# Multimedia devices
692# 753#
754
755#
756# Multimedia core support
757#
693# CONFIG_VIDEO_DEV is not set 758# CONFIG_VIDEO_DEV is not set
694# CONFIG_DVB_CORE is not set 759# CONFIG_DVB_CORE is not set
695# CONFIG_DAB is not set 760# CONFIG_VIDEO_MEDIA is not set
696 761
697# 762#
698# Graphics support 763# Multimedia drivers
699# 764#
700# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 765# CONFIG_DAB is not set
701 766
702# 767#
703# Display device support 768# Graphics support
704# 769#
705# CONFIG_DISPLAY_SUPPORT is not set
706# CONFIG_VGASTATE is not set 770# CONFIG_VGASTATE is not set
771# CONFIG_VIDEO_OUTPUT_CONTROL is not set
707# CONFIG_FB is not set 772# CONFIG_FB is not set
773# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
708 774
709# 775#
710# Sound 776# Display device support
711# 777#
778# CONFIG_DISPLAY_SUPPORT is not set
712# CONFIG_SOUND is not set 779# CONFIG_SOUND is not set
713 780CONFIG_USB_SUPPORT=y
714#
715# USB support
716#
717CONFIG_USB_ARCH_HAS_HCD=y 781CONFIG_USB_ARCH_HAS_HCD=y
718# CONFIG_USB_ARCH_HAS_OHCI is not set 782# CONFIG_USB_ARCH_HAS_OHCI is not set
719# CONFIG_USB_ARCH_HAS_EHCI is not set 783# CONFIG_USB_ARCH_HAS_EHCI is not set
720# CONFIG_USB is not set 784# CONFIG_USB is not set
721# CONFIG_USB_MUSB_HDRC is not set 785# CONFIG_USB_OTG_WHITELIST is not set
786# CONFIG_USB_OTG_BLACKLIST_HUB is not set
722# CONFIG_USB_GADGET_MUSB_HDRC is not set 787# CONFIG_USB_GADGET_MUSB_HDRC is not set
723 788
724# 789#
725# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 790# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
726#
727
728#
729# USB Gadget Support
730# 791#
731CONFIG_USB_GADGET=y 792CONFIG_USB_GADGET=y
732# CONFIG_USB_GADGET_DEBUG_FILES is not set 793# CONFIG_USB_GADGET_DEBUG_FILES is not set
794# CONFIG_USB_GADGET_DEBUG_FS is not set
795CONFIG_USB_GADGET_VBUS_DRAW=2
733CONFIG_USB_GADGET_SELECTED=y 796CONFIG_USB_GADGET_SELECTED=y
797# CONFIG_USB_GADGET_AT91 is not set
798# CONFIG_USB_GADGET_ATMEL_USBA is not set
734# CONFIG_USB_GADGET_FSL_USB2 is not set 799# CONFIG_USB_GADGET_FSL_USB2 is not set
800# CONFIG_USB_GADGET_LH7A40X is not set
801# CONFIG_USB_GADGET_OMAP is not set
802# CONFIG_USB_GADGET_PXA25X is not set
803# CONFIG_USB_GADGET_PXA27X is not set
804# CONFIG_USB_GADGET_S3C2410 is not set
805# CONFIG_USB_GADGET_IMX is not set
806# CONFIG_USB_GADGET_M66592 is not set
807# CONFIG_USB_GADGET_AMD5536UDC is not set
808# CONFIG_USB_GADGET_FSL_QE is not set
809# CONFIG_USB_GADGET_CI13XXX is not set
735CONFIG_USB_GADGET_NET2272=y 810CONFIG_USB_GADGET_NET2272=y
736CONFIG_USB_NET2272=y 811CONFIG_USB_NET2272=y
737# CONFIG_USB_GADGET_NET2280 is not set 812# CONFIG_USB_GADGET_NET2280 is not set
738# CONFIG_USB_GADGET_PXA2XX is not set
739# CONFIG_USB_GADGET_GOKU is not set 813# CONFIG_USB_GADGET_GOKU is not set
740# CONFIG_USB_GADGET_LH7A40X is not set
741# CONFIG_USB_GADGET_OMAP is not set
742# CONFIG_USB_GADGET_AT91 is not set
743# CONFIG_USB_GADGET_DUMMY_HCD is not set 814# CONFIG_USB_GADGET_DUMMY_HCD is not set
744CONFIG_USB_GADGET_DUALSPEED=y 815CONFIG_USB_GADGET_DUALSPEED=y
745# CONFIG_USB_ZERO is not set 816# CONFIG_USB_ZERO is not set
746# CONFIG_USB_ETH is not set 817# CONFIG_USB_AUDIO is not set
818CONFIG_USB_ETH=y
819CONFIG_USB_ETH_RNDIS=y
747# CONFIG_USB_GADGETFS is not set 820# CONFIG_USB_GADGETFS is not set
748# CONFIG_USB_FILE_STORAGE is not set 821# CONFIG_USB_FILE_STORAGE is not set
749# CONFIG_USB_G_SERIAL is not set 822# CONFIG_USB_G_SERIAL is not set
750# CONFIG_USB_MIDI_GADGET is not set 823# CONFIG_USB_MIDI_GADGET is not set
751# CONFIG_MMC is not set 824# CONFIG_USB_G_PRINTER is not set
752 825# CONFIG_USB_CDC_COMPOSITE is not set
753#
754# LED devices
755#
756# CONFIG_NEW_LEDS is not set
757
758#
759# LED drivers
760#
761
762#
763# LED Triggers
764#
765 826
766# 827#
767# InfiniBand support 828# OTG and related infrastructure
768# 829#
830# CONFIG_USB_GPIO_VBUS is not set
831# CONFIG_NOP_USB_XCEIV is not set
832CONFIG_MMC=y
833# CONFIG_MMC_DEBUG is not set
834# CONFIG_MMC_UNSAFE_RESUME is not set
769 835
770# 836#
771# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 837# MMC/SD/SDIO Card Drivers
772# 838#
839CONFIG_MMC_BLOCK=y
840CONFIG_MMC_BLOCK_BOUNCE=y
841# CONFIG_SDIO_UART is not set
842# CONFIG_MMC_TEST is not set
773 843
774# 844#
775# Real Time Clock 845# MMC/SD/SDIO Host Controller Drivers
776# 846#
847# CONFIG_MMC_SDHCI is not set
848CONFIG_MMC_SPI=m
849# CONFIG_MEMSTICK is not set
850# CONFIG_NEW_LEDS is not set
851# CONFIG_ACCESSIBILITY is not set
777# CONFIG_RTC_CLASS is not set 852# CONFIG_RTC_CLASS is not set
778 853# CONFIG_DMADEVICES is not set
779# 854# CONFIG_AUXDISPLAY is not set
780# DMA Engine support 855# CONFIG_UIO is not set
781# 856# CONFIG_STAGING is not set
782# CONFIG_DMA_ENGINE is not set
783
784#
785# DMA Clients
786#
787
788#
789# DMA Devices
790#
791
792#
793# PBX support
794#
795# CONFIG_PBX is not set
796 857
797# 858#
798# File systems 859# File systems
@@ -802,25 +863,29 @@ CONFIG_EXT2_FS_XATTR=y
802# CONFIG_EXT2_FS_POSIX_ACL is not set 863# CONFIG_EXT2_FS_POSIX_ACL is not set
803# CONFIG_EXT2_FS_SECURITY is not set 864# CONFIG_EXT2_FS_SECURITY is not set
804# CONFIG_EXT3_FS is not set 865# CONFIG_EXT3_FS is not set
805# CONFIG_EXT4DEV_FS is not set 866# CONFIG_EXT4_FS is not set
806CONFIG_FS_MBCACHE=y 867CONFIG_FS_MBCACHE=y
807# CONFIG_REISERFS_FS is not set 868# CONFIG_REISERFS_FS is not set
808# CONFIG_JFS_FS is not set 869# CONFIG_JFS_FS is not set
809# CONFIG_FS_POSIX_ACL is not set 870# CONFIG_FS_POSIX_ACL is not set
810# CONFIG_XFS_FS is not set 871# CONFIG_XFS_FS is not set
811# CONFIG_GFS2_FS is not set
812# CONFIG_OCFS2_FS is not set 872# CONFIG_OCFS2_FS is not set
813# CONFIG_MINIX_FS is not set 873# CONFIG_BTRFS_FS is not set
814# CONFIG_ROMFS_FS is not set 874CONFIG_FILE_LOCKING=y
875# CONFIG_DNOTIFY is not set
815CONFIG_INOTIFY=y 876CONFIG_INOTIFY=y
816CONFIG_INOTIFY_USER=y 877CONFIG_INOTIFY_USER=y
817# CONFIG_QUOTA is not set 878# CONFIG_QUOTA is not set
818# CONFIG_DNOTIFY is not set
819# CONFIG_AUTOFS_FS is not set 879# CONFIG_AUTOFS_FS is not set
820# CONFIG_AUTOFS4_FS is not set 880# CONFIG_AUTOFS4_FS is not set
821# CONFIG_FUSE_FS is not set 881# CONFIG_FUSE_FS is not set
822 882
823# 883#
884# Caches
885#
886# CONFIG_FSCACHE is not set
887
888#
824# CD-ROM/DVD Filesystems 889# CD-ROM/DVD Filesystems
825# 890#
826# CONFIG_ISO9660_FS is not set 891# CONFIG_ISO9660_FS is not set
@@ -829,8 +894,11 @@ CONFIG_INOTIFY_USER=y
829# 894#
830# DOS/FAT/NT Filesystems 895# DOS/FAT/NT Filesystems
831# 896#
832# CONFIG_MSDOS_FS is not set 897CONFIG_FAT_FS=y
833# CONFIG_VFAT_FS is not set 898CONFIG_MSDOS_FS=y
899CONFIG_VFAT_FS=y
900CONFIG_FAT_DEFAULT_CODEPAGE=437
901CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
834# CONFIG_NTFS_FS is not set 902# CONFIG_NTFS_FS is not set
835 903
836# 904#
@@ -841,12 +909,8 @@ CONFIG_PROC_SYSCTL=y
841CONFIG_SYSFS=y 909CONFIG_SYSFS=y
842# CONFIG_TMPFS is not set 910# CONFIG_TMPFS is not set
843# CONFIG_HUGETLB_PAGE is not set 911# CONFIG_HUGETLB_PAGE is not set
844CONFIG_RAMFS=y
845# CONFIG_CONFIGFS_FS is not set 912# CONFIG_CONFIGFS_FS is not set
846 913CONFIG_MISC_FILESYSTEMS=y
847#
848# Miscellaneous filesystems
849#
850# CONFIG_ADFS_FS is not set 914# CONFIG_ADFS_FS is not set
851# CONFIG_AFFS_FS is not set 915# CONFIG_AFFS_FS is not set
852# CONFIG_HFS_FS is not set 916# CONFIG_HFS_FS is not set
@@ -854,18 +918,29 @@ CONFIG_RAMFS=y
854# CONFIG_BEFS_FS is not set 918# CONFIG_BEFS_FS is not set
855# CONFIG_BFS_FS is not set 919# CONFIG_BFS_FS is not set
856# CONFIG_EFS_FS is not set 920# CONFIG_EFS_FS is not set
857# CONFIG_YAFFS_FS is not set 921CONFIG_JFFS2_FS=y
858# CONFIG_JFFS2_FS is not set 922CONFIG_JFFS2_FS_DEBUG=0
923CONFIG_JFFS2_FS_WRITEBUFFER=y
924# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
925# CONFIG_JFFS2_SUMMARY is not set
926# CONFIG_JFFS2_FS_XATTR is not set
927# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
928CONFIG_JFFS2_ZLIB=y
929# CONFIG_JFFS2_LZO is not set
930CONFIG_JFFS2_RTIME=y
931# CONFIG_JFFS2_RUBIN is not set
859# CONFIG_CRAMFS is not set 932# CONFIG_CRAMFS is not set
933# CONFIG_SQUASHFS is not set
860# CONFIG_VXFS_FS is not set 934# CONFIG_VXFS_FS is not set
935# CONFIG_MINIX_FS is not set
936# CONFIG_OMFS_FS is not set
861# CONFIG_HPFS_FS is not set 937# CONFIG_HPFS_FS is not set
862# CONFIG_QNX4FS_FS is not set 938# CONFIG_QNX4FS_FS is not set
939# CONFIG_ROMFS_FS is not set
863# CONFIG_SYSV_FS is not set 940# CONFIG_SYSV_FS is not set
864# CONFIG_UFS_FS is not set 941# CONFIG_UFS_FS is not set
865 942# CONFIG_NILFS2_FS is not set
866# 943CONFIG_NETWORK_FILESYSTEMS=y
867# Network File Systems
868#
869# CONFIG_NFS_FS is not set 944# CONFIG_NFS_FS is not set
870# CONFIG_NFSD is not set 945# CONFIG_NFSD is not set
871# CONFIG_SMB_FS is not set 946# CONFIG_SMB_FS is not set
@@ -873,41 +948,94 @@ CONFIG_RAMFS=y
873# CONFIG_NCP_FS is not set 948# CONFIG_NCP_FS is not set
874# CONFIG_CODA_FS is not set 949# CONFIG_CODA_FS is not set
875# CONFIG_AFS_FS is not set 950# CONFIG_AFS_FS is not set
876# CONFIG_9P_FS is not set
877 951
878# 952#
879# Partition Types 953# Partition Types
880# 954#
881# CONFIG_PARTITION_ADVANCED is not set 955# CONFIG_PARTITION_ADVANCED is not set
882CONFIG_MSDOS_PARTITION=y 956CONFIG_MSDOS_PARTITION=y
883 957CONFIG_NLS=y
884# 958CONFIG_NLS_DEFAULT="iso8859-1"
885# Native Language Support 959CONFIG_NLS_CODEPAGE_437=y
886# 960# CONFIG_NLS_CODEPAGE_737 is not set
887# CONFIG_NLS is not set 961# CONFIG_NLS_CODEPAGE_775 is not set
888 962# CONFIG_NLS_CODEPAGE_850 is not set
889# 963# CONFIG_NLS_CODEPAGE_852 is not set
890# Distributed Lock Manager 964# CONFIG_NLS_CODEPAGE_855 is not set
891# 965# CONFIG_NLS_CODEPAGE_857 is not set
966# CONFIG_NLS_CODEPAGE_860 is not set
967# CONFIG_NLS_CODEPAGE_861 is not set
968# CONFIG_NLS_CODEPAGE_862 is not set
969# CONFIG_NLS_CODEPAGE_863 is not set
970# CONFIG_NLS_CODEPAGE_864 is not set
971# CONFIG_NLS_CODEPAGE_865 is not set
972# CONFIG_NLS_CODEPAGE_866 is not set
973# CONFIG_NLS_CODEPAGE_869 is not set
974# CONFIG_NLS_CODEPAGE_936 is not set
975# CONFIG_NLS_CODEPAGE_950 is not set
976# CONFIG_NLS_CODEPAGE_932 is not set
977# CONFIG_NLS_CODEPAGE_949 is not set
978# CONFIG_NLS_CODEPAGE_874 is not set
979# CONFIG_NLS_ISO8859_8 is not set
980# CONFIG_NLS_CODEPAGE_1250 is not set
981# CONFIG_NLS_CODEPAGE_1251 is not set
982# CONFIG_NLS_ASCII is not set
983CONFIG_NLS_ISO8859_1=y
984# CONFIG_NLS_ISO8859_2 is not set
985# CONFIG_NLS_ISO8859_3 is not set
986# CONFIG_NLS_ISO8859_4 is not set
987# CONFIG_NLS_ISO8859_5 is not set
988# CONFIG_NLS_ISO8859_6 is not set
989# CONFIG_NLS_ISO8859_7 is not set
990# CONFIG_NLS_ISO8859_9 is not set
991# CONFIG_NLS_ISO8859_13 is not set
992# CONFIG_NLS_ISO8859_14 is not set
993# CONFIG_NLS_ISO8859_15 is not set
994# CONFIG_NLS_KOI8_R is not set
995# CONFIG_NLS_KOI8_U is not set
996# CONFIG_NLS_UTF8 is not set
892# CONFIG_DLM is not set 997# CONFIG_DLM is not set
893 998
894# 999#
895# Profiling support
896#
897# CONFIG_PROFILING is not set
898
899#
900# Kernel hacking 1000# Kernel hacking
901# 1001#
902# CONFIG_PRINTK_TIME is not set 1002# CONFIG_PRINTK_TIME is not set
1003CONFIG_ENABLE_WARN_DEPRECATED=y
903CONFIG_ENABLE_MUST_CHECK=y 1004CONFIG_ENABLE_MUST_CHECK=y
1005CONFIG_FRAME_WARN=1024
904# CONFIG_MAGIC_SYSRQ is not set 1006# CONFIG_MAGIC_SYSRQ is not set
905# CONFIG_UNUSED_SYMBOLS is not set 1007# CONFIG_UNUSED_SYMBOLS is not set
906CONFIG_DEBUG_FS=y 1008CONFIG_DEBUG_FS=y
907# CONFIG_HEADERS_CHECK is not set 1009# CONFIG_HEADERS_CHECK is not set
1010CONFIG_DEBUG_SECTION_MISMATCH=y
908# CONFIG_DEBUG_KERNEL is not set 1011# CONFIG_DEBUG_KERNEL is not set
909CONFIG_DEBUG_BUGVERBOSE=y 1012# CONFIG_DEBUG_BUGVERBOSE is not set
1013# CONFIG_DEBUG_MEMORY_INIT is not set
1014# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1015CONFIG_HAVE_FUNCTION_TRACER=y
1016CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1017CONFIG_TRACING_SUPPORT=y
1018
1019#
1020# Tracers
1021#
1022# CONFIG_FUNCTION_TRACER is not set
1023# CONFIG_IRQSOFF_TRACER is not set
1024# CONFIG_SCHED_TRACER is not set
1025# CONFIG_CONTEXT_SWITCH_TRACER is not set
1026# CONFIG_EVENT_TRACER is not set
1027# CONFIG_BOOT_TRACER is not set
1028# CONFIG_TRACE_BRANCH_PROFILING is not set
1029# CONFIG_STACK_TRACER is not set
1030# CONFIG_KMEMTRACE is not set
1031# CONFIG_WORKQUEUE_TRACER is not set
1032# CONFIG_BLK_DEV_IO_TRACE is not set
1033# CONFIG_DYNAMIC_DEBUG is not set
1034# CONFIG_SAMPLES is not set
1035CONFIG_HAVE_ARCH_KGDB=y
1036CONFIG_DEBUG_VERBOSE=y
910CONFIG_DEBUG_MMRS=y 1037CONFIG_DEBUG_MMRS=y
1038# CONFIG_DEBUG_DOUBLEFAULT is not set
911CONFIG_DEBUG_HUNT_FOR_ZERO=y 1039CONFIG_DEBUG_HUNT_FOR_ZERO=y
912CONFIG_DEBUG_BFIN_HWTRACE_ON=y 1040CONFIG_DEBUG_BFIN_HWTRACE_ON=y
913CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y 1041CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -916,34 +1044,40 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
916CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1044CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
917# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1045# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
918# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1046# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
919# CONFIG_EARLY_PRINTK is not set 1047CONFIG_EARLY_PRINTK=y
920CONFIG_CPLB_INFO=y 1048CONFIG_CPLB_INFO=y
921CONFIG_ACCESS_CHECK=y 1049CONFIG_ACCESS_CHECK=y
1050# CONFIG_BFIN_ISRAM_SELF_TEST is not set
922 1051
923# 1052#
924# Security options 1053# Security options
925# 1054#
926# CONFIG_KEYS is not set 1055# CONFIG_KEYS is not set
927CONFIG_SECURITY=y 1056CONFIG_SECURITY=y
1057# CONFIG_SECURITYFS is not set
928# CONFIG_SECURITY_NETWORK is not set 1058# CONFIG_SECURITY_NETWORK is not set
929CONFIG_SECURITY_CAPABILITIES=y 1059# CONFIG_SECURITY_PATH is not set
930 1060# CONFIG_SECURITY_FILE_CAPABILITIES is not set
931# 1061# CONFIG_SECURITY_TOMOYO is not set
932# Cryptographic options
933#
934# CONFIG_CRYPTO is not set 1062# CONFIG_CRYPTO is not set
1063# CONFIG_BINARY_PRINTF is not set
935 1064
936# 1065#
937# Library routines 1066# Library routines
938# 1067#
939CONFIG_BITREVERSE=y 1068CONFIG_BITREVERSE=y
1069CONFIG_GENERIC_FIND_LAST_BIT=y
940CONFIG_CRC_CCITT=m 1070CONFIG_CRC_CCITT=m
941# CONFIG_CRC16 is not set 1071# CONFIG_CRC16 is not set
942# CONFIG_CRC_ITU_T is not set 1072# CONFIG_CRC_T10DIF is not set
1073CONFIG_CRC_ITU_T=y
943CONFIG_CRC32=y 1074CONFIG_CRC32=y
1075CONFIG_CRC7=y
944# CONFIG_LIBCRC32C is not set 1076# CONFIG_LIBCRC32C is not set
945CONFIG_ZLIB_INFLATE=y 1077CONFIG_ZLIB_INFLATE=y
946CONFIG_PLIST=y 1078CONFIG_ZLIB_DEFLATE=y
1079CONFIG_DECOMPRESS_LZMA=y
947CONFIG_HAS_IOMEM=y 1080CONFIG_HAS_IOMEM=y
948CONFIG_HAS_IOPORT=y 1081CONFIG_HAS_IOPORT=y
949CONFIG_HAS_DMA=y 1082CONFIG_HAS_DMA=y
1083CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index acca4e51a45a..7f579cf51127 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -1,14 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24.4 3# Linux kernel version: 2.6.30.5
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
10CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
11CONFIG_SEMAPHORE_SLEEPERS=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y 14CONFIG_GENERIC_HARDIRQS=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20 23
21# 24#
@@ -26,79 +29,100 @@ CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
29CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
34# CONFIG_USER_NS is not set
35# CONFIG_PID_NS is not set
36# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
37CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
38CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
39CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
56# CONFIG_GROUP_SCHED is not set
40# CONFIG_CGROUPS is not set 57# CONFIG_CGROUPS is not set
41CONFIG_FAIR_GROUP_SCHED=y 58# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_FAIR_USER_SCHED=y
43# CONFIG_FAIR_CGROUP_SCHED is not set
44# CONFIG_SYSFS_DEPRECATED is not set
45# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
60# CONFIG_NAMESPACES is not set
46CONFIG_BLK_DEV_INITRD=y 61CONFIG_BLK_DEV_INITRD=y
47CONFIG_INITRAMFS_SOURCE="" 62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
49# CONFIG_SYSCTL is not set 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
50CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
51CONFIG_UID16=y 70# CONFIG_UID16 is not set
52# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
53CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
55CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
56CONFIG_PRINTK=y 76CONFIG_PRINTK=y
57CONFIG_BUG=y 77CONFIG_BUG=y
58# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
59CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
60# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y 81CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y 82CONFIG_SIGNALFD=y
83CONFIG_TIMERFD=y
64CONFIG_EVENTFD=y 84CONFIG_EVENTFD=y
85CONFIG_AIO=y
65CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 87CONFIG_COMPAT_BRK=y
67# CONFIG_NP2 is not set
68CONFIG_SLAB=y 88CONFIG_SLAB=y
69# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
70# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
71CONFIG_SLABINFO=y 97CONFIG_SLABINFO=y
72CONFIG_RT_MUTEXES=y
73CONFIG_TINY_SHMEM=y
74CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
75CONFIG_MODULES=y 99CONFIG_MODULES=y
100# CONFIG_MODULE_FORCE_LOAD is not set
76CONFIG_MODULE_UNLOAD=y 101CONFIG_MODULE_UNLOAD=y
77# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
78# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
79# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
80CONFIG_KMOD=y
81CONFIG_BLOCK=y 105CONFIG_BLOCK=y
82# CONFIG_LBD is not set 106# CONFIG_LBD is not set
83# CONFIG_BLK_DEV_IO_TRACE is not set
84# CONFIG_LSF is not set
85# CONFIG_BLK_DEV_BSG is not set 107# CONFIG_BLK_DEV_BSG is not set
108# CONFIG_BLK_DEV_INTEGRITY is not set
86 109
87# 110#
88# IO Schedulers 111# IO Schedulers
89# 112#
90CONFIG_IOSCHED_NOOP=y 113CONFIG_IOSCHED_NOOP=y
91CONFIG_IOSCHED_AS=y 114# CONFIG_IOSCHED_AS is not set
92# CONFIG_IOSCHED_DEADLINE is not set 115# CONFIG_IOSCHED_DEADLINE is not set
93CONFIG_IOSCHED_CFQ=y 116CONFIG_IOSCHED_CFQ=y
94CONFIG_DEFAULT_AS=y 117# CONFIG_DEFAULT_AS is not set
95# CONFIG_DEFAULT_DEADLINE is not set 118# CONFIG_DEFAULT_DEADLINE is not set
96# CONFIG_DEFAULT_CFQ is not set 119# CONFIG_DEFAULT_CFQ is not set
97# CONFIG_DEFAULT_NOOP is not set 120CONFIG_DEFAULT_NOOP=y
98CONFIG_DEFAULT_IOSCHED="anticipatory" 121CONFIG_DEFAULT_IOSCHED="noop"
99# CONFIG_PREEMPT_NONE is not set 122CONFIG_PREEMPT_NONE=y
100CONFIG_PREEMPT_VOLUNTARY=y 123# CONFIG_PREEMPT_VOLUNTARY is not set
101# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
125# CONFIG_FREEZER is not set
102 126
103# 127#
104# Blackfin Processor Options 128# Blackfin Processor Options
@@ -107,6 +131,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
107# 131#
108# Processor and Board Settings 132# Processor and Board Settings
109# 133#
134# CONFIG_BF512 is not set
135# CONFIG_BF514 is not set
136# CONFIG_BF516 is not set
137# CONFIG_BF518 is not set
110# CONFIG_BF522 is not set 138# CONFIG_BF522 is not set
111# CONFIG_BF523 is not set 139# CONFIG_BF523 is not set
112# CONFIG_BF524 is not set 140# CONFIG_BF524 is not set
@@ -119,19 +147,29 @@ CONFIG_PREEMPT_VOLUNTARY=y
119# CONFIG_BF534 is not set 147# CONFIG_BF534 is not set
120# CONFIG_BF536 is not set 148# CONFIG_BF536 is not set
121# CONFIG_BF537 is not set 149# CONFIG_BF537 is not set
150# CONFIG_BF538 is not set
151# CONFIG_BF539 is not set
122# CONFIG_BF542 is not set 152# CONFIG_BF542 is not set
153# CONFIG_BF542M is not set
123# CONFIG_BF544 is not set 154# CONFIG_BF544 is not set
155# CONFIG_BF544M is not set
124# CONFIG_BF547 is not set 156# CONFIG_BF547 is not set
125CONFIG_BF548=y 157# CONFIG_BF547M is not set
158CONFIG_BF548_std=y
159# CONFIG_BF548M is not set
126# CONFIG_BF549 is not set 160# CONFIG_BF549 is not set
161# CONFIG_BF549M is not set
127# CONFIG_BF561 is not set 162# CONFIG_BF561 is not set
163CONFIG_BF_REV_MIN=0
164CONFIG_BF_REV_MAX=2
128# CONFIG_BF_REV_0_0 is not set 165# CONFIG_BF_REV_0_0 is not set
129# CONFIG_BF_REV_0_1 is not set 166# CONFIG_BF_REV_0_1 is not set
130CONFIG_BF_REV_0_2=y 167# CONFIG_BF_REV_0_2 is not set
131# CONFIG_BF_REV_0_3 is not set 168# CONFIG_BF_REV_0_3 is not set
132# CONFIG_BF_REV_0_4 is not set 169# CONFIG_BF_REV_0_4 is not set
133# CONFIG_BF_REV_0_5 is not set 170# CONFIG_BF_REV_0_5 is not set
134# CONFIG_BF_REV_ANY is not set 171# CONFIG_BF_REV_0_6 is not set
172CONFIG_BF_REV_ANY=y
135# CONFIG_BF_REV_NONE is not set 173# CONFIG_BF_REV_NONE is not set
136CONFIG_BF54x=y 174CONFIG_BF54x=y
137CONFIG_IRQ_PLL_WAKEUP=7 175CONFIG_IRQ_PLL_WAKEUP=7
@@ -140,15 +178,12 @@ CONFIG_IRQ_SPORT0_RX=9
140CONFIG_IRQ_SPORT0_TX=9 178CONFIG_IRQ_SPORT0_TX=9
141CONFIG_IRQ_SPORT1_RX=9 179CONFIG_IRQ_SPORT1_RX=9
142CONFIG_IRQ_SPORT1_TX=9 180CONFIG_IRQ_SPORT1_TX=9
181CONFIG_IRQ_SPI0=10
143CONFIG_IRQ_UART0_RX=10 182CONFIG_IRQ_UART0_RX=10
144CONFIG_IRQ_UART0_TX=10 183CONFIG_IRQ_UART0_TX=10
145CONFIG_IRQ_UART1_RX=10 184CONFIG_IRQ_UART1_RX=10
146CONFIG_IRQ_UART1_TX=10 185CONFIG_IRQ_UART1_TX=10
147CONFIG_IRQ_CNT=8 186CONFIG_IRQ_CNT=8
148CONFIG_IRQ_USB_INT0=11
149CONFIG_IRQ_USB_INT1=11
150CONFIG_IRQ_USB_INT2=11
151CONFIG_IRQ_USB_DMA=11
152CONFIG_IRQ_TIMER0=11 187CONFIG_IRQ_TIMER0=11
153CONFIG_IRQ_TIMER1=11 188CONFIG_IRQ_TIMER1=11
154CONFIG_IRQ_TIMER2=11 189CONFIG_IRQ_TIMER2=11
@@ -157,9 +192,21 @@ CONFIG_IRQ_TIMER4=11
157CONFIG_IRQ_TIMER5=11 192CONFIG_IRQ_TIMER5=11
158CONFIG_IRQ_TIMER6=11 193CONFIG_IRQ_TIMER6=11
159CONFIG_IRQ_TIMER7=11 194CONFIG_IRQ_TIMER7=11
195CONFIG_IRQ_USB_INT0=11
196CONFIG_IRQ_USB_INT1=11
197CONFIG_IRQ_USB_INT2=11
198CONFIG_IRQ_USB_DMA=11
160CONFIG_IRQ_TIMER8=11 199CONFIG_IRQ_TIMER8=11
161CONFIG_IRQ_TIMER9=11 200CONFIG_IRQ_TIMER9=11
162CONFIG_IRQ_TIMER10=11 201CONFIG_IRQ_TIMER10=11
202CONFIG_IRQ_SPORT2_RX=9
203CONFIG_IRQ_SPORT2_TX=9
204CONFIG_IRQ_SPORT3_RX=9
205CONFIG_IRQ_SPORT3_TX=9
206CONFIG_IRQ_SPI1=10
207CONFIG_IRQ_SPI2=10
208CONFIG_IRQ_TWI0=11
209CONFIG_IRQ_TWI1=11
163# CONFIG_BFIN548_EZKIT is not set 210# CONFIG_BFIN548_EZKIT is not set
164CONFIG_BFIN548_BLUETECHNIX_CM=y 211CONFIG_BFIN548_BLUETECHNIX_CM=y
165 212
@@ -167,6 +214,7 @@ CONFIG_BFIN548_BLUETECHNIX_CM=y
167# BF548 Specific Configuration 214# BF548 Specific Configuration
168# 215#
169# CONFIG_DEB_DMA_URGENT is not set 216# CONFIG_DEB_DMA_URGENT is not set
217# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set
170 218
171# 219#
172# Interrupt Priority Assignment 220# Interrupt Priority Assignment
@@ -182,7 +230,6 @@ CONFIG_IRQ_SPORT1_ERR=7
182CONFIG_IRQ_SPI0_ERR=7 230CONFIG_IRQ_SPI0_ERR=7
183CONFIG_IRQ_UART0_ERR=7 231CONFIG_IRQ_UART0_ERR=7
184CONFIG_IRQ_EPPI0=8 232CONFIG_IRQ_EPPI0=8
185CONFIG_IRQ_SPI0=10
186CONFIG_IRQ_PINT0=12 233CONFIG_IRQ_PINT0=12
187CONFIG_IRQ_PINT1=12 234CONFIG_IRQ_PINT1=12
188CONFIG_IRQ_MDMAS0=13 235CONFIG_IRQ_MDMAS0=13
@@ -197,18 +244,10 @@ CONFIG_IRQ_SPI2_ERR=7
197CONFIG_IRQ_UART1_ERR=7 244CONFIG_IRQ_UART1_ERR=7
198CONFIG_IRQ_UART2_ERR=7 245CONFIG_IRQ_UART2_ERR=7
199CONFIG_IRQ_CAN0_ERR=7 246CONFIG_IRQ_CAN0_ERR=7
200CONFIG_IRQ_SPORT2_RX=9
201CONFIG_IRQ_SPORT2_TX=9
202CONFIG_IRQ_SPORT3_RX=9
203CONFIG_IRQ_SPORT3_TX=9
204CONFIG_IRQ_EPPI1=9 247CONFIG_IRQ_EPPI1=9
205CONFIG_IRQ_EPPI2=9 248CONFIG_IRQ_EPPI2=9
206CONFIG_IRQ_SPI1=10
207CONFIG_IRQ_SPI2=10
208CONFIG_IRQ_ATAPI_RX=10 249CONFIG_IRQ_ATAPI_RX=10
209CONFIG_IRQ_ATAPI_TX=10 250CONFIG_IRQ_ATAPI_TX=10
210CONFIG_IRQ_TWI0=11
211CONFIG_IRQ_TWI1=11
212CONFIG_IRQ_CAN0_RX=11 251CONFIG_IRQ_CAN0_RX=11
213CONFIG_IRQ_CAN0_TX=11 252CONFIG_IRQ_CAN0_TX=11
214CONFIG_IRQ_MDMAS2=13 253CONFIG_IRQ_MDMAS2=13
@@ -255,6 +294,7 @@ CONFIG_PINT3_ASSIGN=0x02020303
255# Board customizations 294# Board customizations
256# 295#
257# CONFIG_CMDLINE_BOOL is not set 296# CONFIG_CMDLINE_BOOL is not set
297CONFIG_BOOT_LOAD=0x1000
258 298
259# 299#
260# Clock/PLL Setup 300# Clock/PLL Setup
@@ -274,16 +314,12 @@ CONFIG_HZ_250=y
274# CONFIG_HZ_300 is not set 314# CONFIG_HZ_300 is not set
275# CONFIG_HZ_1000 is not set 315# CONFIG_HZ_1000 is not set
276CONFIG_HZ=250 316CONFIG_HZ=250
317# CONFIG_SCHED_HRTICK is not set
277# CONFIG_GENERIC_TIME is not set 318# CONFIG_GENERIC_TIME is not set
278# CONFIG_TICK_ONESHOT is not set
279 319
280# 320#
281# Memory Setup 321# Misc
282# 322#
283CONFIG_MAX_MEM_SIZE=64
284# CONFIG_MEM_MT46V32M16_6T is not set
285CONFIG_MEM_MT46V32M16_5B=y
286CONFIG_BOOT_LOAD=0x1000
287CONFIG_BFIN_SCRATCH_REG_RETN=y 323CONFIG_BFIN_SCRATCH_REG_RETN=y
288# CONFIG_BFIN_SCRATCH_REG_RETE is not set 324# CONFIG_BFIN_SCRATCH_REG_RETE is not set
289# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set 325# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -310,6 +346,12 @@ CONFIG_ACCESS_OK_L1=y
310CONFIG_CACHELINE_ALIGNED_L1=y 346CONFIG_CACHELINE_ALIGNED_L1=y
311# CONFIG_SYSCALL_TAB_L1 is not set 347# CONFIG_SYSCALL_TAB_L1 is not set
312# CONFIG_CPLB_SWITCH_TAB_L1 is not set 348# CONFIG_CPLB_SWITCH_TAB_L1 is not set
349CONFIG_APP_STACK_L1=y
350
351#
352# Speed Optimizations
353#
354CONFIG_BFIN_INS_LOWOVERHEAD=y
313CONFIG_RAMKERNEL=y 355CONFIG_RAMKERNEL=y
314# CONFIG_ROMKERNEL is not set 356# CONFIG_ROMKERNEL is not set
315CONFIG_SELECT_MEMORY_MODEL=y 357CONFIG_SELECT_MEMORY_MODEL=y
@@ -318,13 +360,16 @@ CONFIG_FLATMEM_MANUAL=y
318# CONFIG_SPARSEMEM_MANUAL is not set 360# CONFIG_SPARSEMEM_MANUAL is not set
319CONFIG_FLATMEM=y 361CONFIG_FLATMEM=y
320CONFIG_FLAT_NODE_MEM_MAP=y 362CONFIG_FLAT_NODE_MEM_MAP=y
321# CONFIG_SPARSEMEM_STATIC is not set 363CONFIG_PAGEFLAGS_EXTENDED=y
322# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
323CONFIG_SPLIT_PTLOCK_CPUS=4 364CONFIG_SPLIT_PTLOCK_CPUS=4
324# CONFIG_RESOURCES_64BIT is not set 365# CONFIG_PHYS_ADDR_T_64BIT is not set
325CONFIG_ZONE_DMA_FLAG=1 366CONFIG_ZONE_DMA_FLAG=1
326CONFIG_VIRT_TO_BUS=y 367CONFIG_VIRT_TO_BUS=y
368CONFIG_UNEVICTABLE_LRU=y
369CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
370CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
327# CONFIG_BFIN_GPTIMERS is not set 371# CONFIG_BFIN_GPTIMERS is not set
372# CONFIG_DMA_UNCACHED_4M is not set
328# CONFIG_DMA_UNCACHED_2M is not set 373# CONFIG_DMA_UNCACHED_2M is not set
329CONFIG_DMA_UNCACHED_1M=y 374CONFIG_DMA_UNCACHED_1M=y
330# CONFIG_DMA_UNCACHED_NONE is not set 375# CONFIG_DMA_UNCACHED_NONE is not set
@@ -333,14 +378,13 @@ CONFIG_DMA_UNCACHED_1M=y
333# Cache Support 378# Cache Support
334# 379#
335CONFIG_BFIN_ICACHE=y 380CONFIG_BFIN_ICACHE=y
336# CONFIG_BFIN_ICACHE_LOCK is not set 381CONFIG_BFIN_EXTMEM_ICACHEABLE=y
382# CONFIG_BFIN_L2_ICACHEABLE is not set
337CONFIG_BFIN_DCACHE=y 383CONFIG_BFIN_DCACHE=y
338# CONFIG_BFIN_DCACHE_BANKA is not set 384# CONFIG_BFIN_DCACHE_BANKA is not set
339CONFIG_BFIN_EXTMEM_ICACHEABLE=y
340CONFIG_BFIN_EXTMEM_DCACHEABLE=y 385CONFIG_BFIN_EXTMEM_DCACHEABLE=y
341CONFIG_BFIN_EXTMEM_WRITEBACK=y 386# CONFIG_BFIN_EXTMEM_WRITEBACK
342# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 387CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
343# CONFIG_BFIN_L2_ICACHEABLE is not set
344# CONFIG_BFIN_L2_DCACHEABLE is not set 388# CONFIG_BFIN_L2_DCACHEABLE is not set
345 389
346# 390#
@@ -349,7 +393,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
349# CONFIG_MPU is not set 393# CONFIG_MPU is not set
350 394
351# 395#
352# Asynchonous Memory Configuration 396# Asynchronous Memory Configuration
353# 397#
354 398
355# 399#
@@ -369,7 +413,7 @@ CONFIG_C_AMBEN_ALL=y
369CONFIG_BANK_0=0x7BB0 413CONFIG_BANK_0=0x7BB0
370CONFIG_BANK_1=0x5554 414CONFIG_BANK_1=0x5554
371CONFIG_BANK_2=0x7BB0 415CONFIG_BANK_2=0x7BB0
372CONFIG_BANK_3=0x99B2 416CONFIG_BANK_3=0x99B3
373CONFIG_EBIU_MBSCTLVAL=0x0 417CONFIG_EBIU_MBSCTLVAL=0x0
374CONFIG_EBIU_MODEVAL=0x1 418CONFIG_EBIU_MODEVAL=0x1
375CONFIG_EBIU_FCTLVAL=0x6 419CONFIG_EBIU_FCTLVAL=0x6
@@ -377,7 +421,6 @@ CONFIG_EBIU_FCTLVAL=0x6
377# 421#
378# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 422# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
379# 423#
380# CONFIG_PCI is not set
381# CONFIG_ARCH_SUPPORTS_MSI is not set 424# CONFIG_ARCH_SUPPORTS_MSI is not set
382# CONFIG_PCCARD is not set 425# CONFIG_PCCARD is not set
383 426
@@ -388,23 +431,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
388CONFIG_BINFMT_FLAT=y 431CONFIG_BINFMT_FLAT=y
389CONFIG_BINFMT_ZFLAT=y 432CONFIG_BINFMT_ZFLAT=y
390# CONFIG_BINFMT_SHARED_FLAT is not set 433# CONFIG_BINFMT_SHARED_FLAT is not set
434# CONFIG_HAVE_AOUT is not set
391# CONFIG_BINFMT_MISC is not set 435# CONFIG_BINFMT_MISC is not set
392 436
393# 437#
394# Power management options 438# Power management options
395# 439#
396# CONFIG_PM is not set 440# CONFIG_PM is not set
397CONFIG_SUSPEND_UP_POSSIBLE=y 441CONFIG_ARCH_SUSPEND_POSSIBLE=y
398# CONFIG_PM_WAKEUP_BY_GPIO is not set
399 442
400# 443#
401# CPU Frequency scaling 444# CPU Frequency scaling
402# 445#
403# CONFIG_CPU_FREQ is not set 446# CONFIG_CPU_FREQ is not set
404
405#
406# Networking
407#
408CONFIG_NET=y 447CONFIG_NET=y
409 448
410# 449#
@@ -417,6 +456,7 @@ CONFIG_XFRM=y
417# CONFIG_XFRM_USER is not set 456# CONFIG_XFRM_USER is not set
418# CONFIG_XFRM_SUB_POLICY is not set 457# CONFIG_XFRM_SUB_POLICY is not set
419# CONFIG_XFRM_MIGRATE is not set 458# CONFIG_XFRM_MIGRATE is not set
459# CONFIG_XFRM_STATISTICS is not set
420# CONFIG_NET_KEY is not set 460# CONFIG_NET_KEY is not set
421CONFIG_INET=y 461CONFIG_INET=y
422# CONFIG_IP_MULTICAST is not set 462# CONFIG_IP_MULTICAST is not set
@@ -435,19 +475,16 @@ CONFIG_IP_PNP=y
435# CONFIG_INET_IPCOMP is not set 475# CONFIG_INET_IPCOMP is not set
436# CONFIG_INET_XFRM_TUNNEL is not set 476# CONFIG_INET_XFRM_TUNNEL is not set
437# CONFIG_INET_TUNNEL is not set 477# CONFIG_INET_TUNNEL is not set
438# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 478CONFIG_INET_XFRM_MODE_TRANSPORT=m
439# CONFIG_INET_XFRM_MODE_TUNNEL is not set 479CONFIG_INET_XFRM_MODE_TUNNEL=m
440# CONFIG_INET_XFRM_MODE_BEET is not set 480CONFIG_INET_XFRM_MODE_BEET=m
441# CONFIG_INET_LRO is not set 481# CONFIG_INET_LRO is not set
442# CONFIG_INET_DIAG is not set 482# CONFIG_INET_DIAG is not set
443CONFIG_INET_TCP_DIAG=y
444# CONFIG_TCP_CONG_ADVANCED is not set 483# CONFIG_TCP_CONG_ADVANCED is not set
445CONFIG_TCP_CONG_CUBIC=y 484CONFIG_TCP_CONG_CUBIC=y
446CONFIG_DEFAULT_TCP_CONG="cubic" 485CONFIG_DEFAULT_TCP_CONG="cubic"
447# CONFIG_TCP_MD5SIG is not set 486# CONFIG_TCP_MD5SIG is not set
448# CONFIG_IPV6 is not set 487# CONFIG_IPV6 is not set
449# CONFIG_INET6_XFRM_TUNNEL is not set
450# CONFIG_INET6_TUNNEL is not set
451# CONFIG_NETLABEL is not set 488# CONFIG_NETLABEL is not set
452# CONFIG_NETWORK_SECMARK is not set 489# CONFIG_NETWORK_SECMARK is not set
453# CONFIG_NETFILTER is not set 490# CONFIG_NETFILTER is not set
@@ -456,6 +493,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
456# CONFIG_TIPC is not set 493# CONFIG_TIPC is not set
457# CONFIG_ATM is not set 494# CONFIG_ATM is not set
458# CONFIG_BRIDGE is not set 495# CONFIG_BRIDGE is not set
496# CONFIG_NET_DSA is not set
459# CONFIG_VLAN_8021Q is not set 497# CONFIG_VLAN_8021Q is not set
460# CONFIG_DECNET is not set 498# CONFIG_DECNET is not set
461# CONFIG_LLC2 is not set 499# CONFIG_LLC2 is not set
@@ -465,24 +503,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
465# CONFIG_LAPB is not set 503# CONFIG_LAPB is not set
466# CONFIG_ECONET is not set 504# CONFIG_ECONET is not set
467# CONFIG_WAN_ROUTER is not set 505# CONFIG_WAN_ROUTER is not set
506# CONFIG_PHONET is not set
468# CONFIG_NET_SCHED is not set 507# CONFIG_NET_SCHED is not set
508# CONFIG_DCB is not set
469 509
470# 510#
471# Network testing 511# Network testing
472# 512#
473# CONFIG_NET_PKTGEN is not set 513# CONFIG_NET_PKTGEN is not set
474# CONFIG_HAMRADIO is not set 514# CONFIG_HAMRADIO is not set
515# CONFIG_CAN is not set
475# CONFIG_IRDA is not set 516# CONFIG_IRDA is not set
476# CONFIG_BT is not set 517# CONFIG_BT is not set
477# CONFIG_AF_RXRPC is not set 518# CONFIG_AF_RXRPC is not set
478 519# CONFIG_WIRELESS is not set
479# 520# CONFIG_WIMAX is not set
480# Wireless
481#
482# CONFIG_CFG80211 is not set
483# CONFIG_WIRELESS_EXT is not set
484# CONFIG_MAC80211 is not set
485# CONFIG_IEEE80211 is not set
486# CONFIG_RFKILL is not set 521# CONFIG_RFKILL is not set
487# CONFIG_NET_9P is not set 522# CONFIG_NET_9P is not set
488 523
@@ -501,10 +536,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
501# CONFIG_CONNECTOR is not set 536# CONFIG_CONNECTOR is not set
502CONFIG_MTD=y 537CONFIG_MTD=y
503# CONFIG_MTD_DEBUG is not set 538# CONFIG_MTD_DEBUG is not set
539# CONFIG_MTD_TESTS is not set
504# CONFIG_MTD_CONCAT is not set 540# CONFIG_MTD_CONCAT is not set
505CONFIG_MTD_PARTITIONS=y 541CONFIG_MTD_PARTITIONS=y
506# CONFIG_MTD_REDBOOT_PARTS is not set 542# CONFIG_MTD_REDBOOT_PARTS is not set
507CONFIG_MTD_CMDLINE_PARTS=y 543CONFIG_MTD_CMDLINE_PARTS=y
544# CONFIG_MTD_AR7_PARTS is not set
508 545
509# 546#
510# User Modules And Translation Layers 547# User Modules And Translation Layers
@@ -539,6 +576,7 @@ CONFIG_MTD_CFI_I2=y
539CONFIG_MTD_CFI_INTELEXT=y 576CONFIG_MTD_CFI_INTELEXT=y
540# CONFIG_MTD_CFI_AMDSTD is not set 577# CONFIG_MTD_CFI_AMDSTD is not set
541# CONFIG_MTD_CFI_STAA is not set 578# CONFIG_MTD_CFI_STAA is not set
579# CONFIG_MTD_PSD4256G is not set
542CONFIG_MTD_CFI_UTIL=y 580CONFIG_MTD_CFI_UTIL=y
543CONFIG_MTD_RAM=y 581CONFIG_MTD_RAM=y
544# CONFIG_MTD_ROM is not set 582# CONFIG_MTD_ROM is not set
@@ -549,9 +587,8 @@ CONFIG_MTD_RAM=y
549# 587#
550CONFIG_MTD_COMPLEX_MAPPINGS=y 588CONFIG_MTD_COMPLEX_MAPPINGS=y
551CONFIG_MTD_PHYSMAP=y 589CONFIG_MTD_PHYSMAP=y
552CONFIG_MTD_PHYSMAP_START=0x20000000 590# CONFIG_MTD_PHYSMAP_COMPAT is not set
553CONFIG_MTD_PHYSMAP_LEN=0 591# CONFIG_MTD_GPIO_ADDR is not set
554CONFIG_MTD_PHYSMAP_BANKWIDTH=2
555# CONFIG_MTD_UCLINUX is not set 592# CONFIG_MTD_UCLINUX is not set
556# CONFIG_MTD_PLATRAM is not set 593# CONFIG_MTD_PLATRAM is not set
557 594
@@ -575,6 +612,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
575# CONFIG_MTD_ONENAND is not set 612# CONFIG_MTD_ONENAND is not set
576 613
577# 614#
615# LPDDR flash memory drivers
616#
617# CONFIG_MTD_LPDDR is not set
618
619#
578# UBI - Unsorted block images 620# UBI - Unsorted block images
579# 621#
580# CONFIG_MTD_UBI is not set 622# CONFIG_MTD_UBI is not set
@@ -587,31 +629,31 @@ CONFIG_BLK_DEV=y
587CONFIG_BLK_DEV_RAM=y 629CONFIG_BLK_DEV_RAM=y
588CONFIG_BLK_DEV_RAM_COUNT=16 630CONFIG_BLK_DEV_RAM_COUNT=16
589CONFIG_BLK_DEV_RAM_SIZE=4096 631CONFIG_BLK_DEV_RAM_SIZE=4096
590CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 632# CONFIG_BLK_DEV_XIP is not set
591# CONFIG_CDROM_PKTCDVD is not set 633# CONFIG_CDROM_PKTCDVD is not set
592# CONFIG_ATA_OVER_ETH is not set 634# CONFIG_ATA_OVER_ETH is not set
593CONFIG_MISC_DEVICES=y 635# CONFIG_BLK_DEV_HD is not set
594# CONFIG_EEPROM_93CX6 is not set 636# CONFIG_MISC_DEVICES is not set
637CONFIG_HAVE_IDE=y
595# CONFIG_IDE is not set 638# CONFIG_IDE is not set
596 639
597# 640#
598# SCSI device support 641# SCSI device support
599# 642#
600# CONFIG_RAID_ATTRS is not set 643# CONFIG_RAID_ATTRS is not set
601CONFIG_SCSI=y 644CONFIG_SCSI=m
602CONFIG_SCSI_DMA=y 645CONFIG_SCSI_DMA=y
603# CONFIG_SCSI_TGT is not set 646# CONFIG_SCSI_TGT is not set
604# CONFIG_SCSI_NETLINK is not set 647# CONFIG_SCSI_NETLINK is not set
605# CONFIG_SCSI_PROC_FS is not set 648CONFIG_SCSI_PROC_FS=y
606 649
607# 650#
608# SCSI support type (disk, tape, CD-ROM) 651# SCSI support type (disk, tape, CD-ROM)
609# 652#
610CONFIG_BLK_DEV_SD=y 653CONFIG_BLK_DEV_SD=m
611# CONFIG_CHR_DEV_ST is not set 654# CONFIG_CHR_DEV_ST is not set
612# CONFIG_CHR_DEV_OSST is not set 655# CONFIG_CHR_DEV_OSST is not set
613CONFIG_BLK_DEV_SR=y 656# CONFIG_BLK_DEV_SR is not set
614# CONFIG_BLK_DEV_SR_VENDOR is not set
615# CONFIG_CHR_DEV_SG is not set 657# CONFIG_CHR_DEV_SG is not set
616# CONFIG_CHR_DEV_SCH is not set 658# CONFIG_CHR_DEV_SCH is not set
617 659
@@ -632,29 +674,54 @@ CONFIG_SCSI_WAIT_SCAN=m
632# CONFIG_SCSI_ISCSI_ATTRS is not set 674# CONFIG_SCSI_ISCSI_ATTRS is not set
633# CONFIG_SCSI_SAS_LIBSAS is not set 675# CONFIG_SCSI_SAS_LIBSAS is not set
634# CONFIG_SCSI_SRP_ATTRS is not set 676# CONFIG_SCSI_SRP_ATTRS is not set
635CONFIG_SCSI_LOWLEVEL=y 677# CONFIG_SCSI_LOWLEVEL is not set
636# CONFIG_ISCSI_TCP is not set 678# CONFIG_SCSI_DH is not set
637# CONFIG_SCSI_DEBUG is not set 679# CONFIG_SCSI_OSD_INITIATOR is not set
638# CONFIG_ATA is not set 680# CONFIG_ATA is not set
639# CONFIG_MD is not set 681# CONFIG_MD is not set
640CONFIG_NETDEVICES=y 682CONFIG_NETDEVICES=y
641# CONFIG_NETDEVICES_MULTIQUEUE is not set 683CONFIG_COMPAT_NET_DEV_OPS=y
642# CONFIG_DUMMY is not set 684# CONFIG_DUMMY is not set
643# CONFIG_BONDING is not set 685# CONFIG_BONDING is not set
644# CONFIG_MACVLAN is not set 686# CONFIG_MACVLAN is not set
645# CONFIG_EQUALIZER is not set 687# CONFIG_EQUALIZER is not set
646# CONFIG_TUN is not set 688# CONFIG_TUN is not set
647# CONFIG_VETH is not set 689# CONFIG_VETH is not set
648# CONFIG_PHYLIB is not set 690CONFIG_PHYLIB=y
691
692#
693# MII PHY device drivers
694#
695# CONFIG_MARVELL_PHY is not set
696# CONFIG_DAVICOM_PHY is not set
697# CONFIG_QSEMI_PHY is not set
698# CONFIG_LXT_PHY is not set
699# CONFIG_CICADA_PHY is not set
700# CONFIG_VITESSE_PHY is not set
701# CONFIG_SMSC_PHY is not set
702# CONFIG_BROADCOM_PHY is not set
703# CONFIG_ICPLUS_PHY is not set
704# CONFIG_REALTEK_PHY is not set
705# CONFIG_NATIONAL_PHY is not set
706# CONFIG_STE10XP is not set
707# CONFIG_LSI_ET1011C_PHY is not set
708# CONFIG_FIXED_PHY is not set
709# CONFIG_MDIO_BITBANG is not set
649CONFIG_NET_ETHERNET=y 710CONFIG_NET_ETHERNET=y
650CONFIG_MII=y 711CONFIG_MII=y
651# CONFIG_SMC91X is not set 712# CONFIG_SMC91X is not set
652CONFIG_SMSC911X=y
653# CONFIG_DM9000 is not set 713# CONFIG_DM9000 is not set
714# CONFIG_ENC28J60 is not set
715# CONFIG_ETHOC is not set
716CONFIG_SMSC911X=y
717# CONFIG_DNET is not set
654# CONFIG_IBM_NEW_EMAC_ZMII is not set 718# CONFIG_IBM_NEW_EMAC_ZMII is not set
655# CONFIG_IBM_NEW_EMAC_RGMII is not set 719# CONFIG_IBM_NEW_EMAC_RGMII is not set
656# CONFIG_IBM_NEW_EMAC_TAH is not set 720# CONFIG_IBM_NEW_EMAC_TAH is not set
657# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 721# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
722# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
723# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
724# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
658# CONFIG_B44 is not set 725# CONFIG_B44 is not set
659# CONFIG_NETDEV_1000 is not set 726# CONFIG_NETDEV_1000 is not set
660# CONFIG_NETDEV_10000 is not set 727# CONFIG_NETDEV_10000 is not set
@@ -666,6 +733,10 @@ CONFIG_SMSC911X=y
666# CONFIG_WLAN_80211 is not set 733# CONFIG_WLAN_80211 is not set
667 734
668# 735#
736# Enable WiMAX (Networking options) to see the WiMAX drivers
737#
738
739#
669# USB Network Adapters 740# USB Network Adapters
670# 741#
671# CONFIG_USB_CATC is not set 742# CONFIG_USB_CATC is not set
@@ -676,7 +747,6 @@ CONFIG_SMSC911X=y
676# CONFIG_WAN is not set 747# CONFIG_WAN is not set
677# CONFIG_PPP is not set 748# CONFIG_PPP is not set
678# CONFIG_SLIP is not set 749# CONFIG_SLIP is not set
679# CONFIG_SHAPER is not set
680# CONFIG_NETCONSOLE is not set 750# CONFIG_NETCONSOLE is not set
681# CONFIG_NETPOLL is not set 751# CONFIG_NETPOLL is not set
682# CONFIG_NET_POLL_CONTROLLER is not set 752# CONFIG_NET_POLL_CONTROLLER is not set
@@ -711,6 +781,7 @@ CONFIG_INPUT_KEYBOARD=y
711# CONFIG_KEYBOARD_GPIO is not set 781# CONFIG_KEYBOARD_GPIO is not set
712# CONFIG_KEYBOARD_BFIN is not set 782# CONFIG_KEYBOARD_BFIN is not set
713# CONFIG_KEYBOARD_OPENCORES is not set 783# CONFIG_KEYBOARD_OPENCORES is not set
784# CONFIG_KEYBOARD_ADP5588 is not set
714# CONFIG_INPUT_MOUSE is not set 785# CONFIG_INPUT_MOUSE is not set
715# CONFIG_INPUT_JOYSTICK is not set 786# CONFIG_INPUT_JOYSTICK is not set
716# CONFIG_INPUT_TABLET is not set 787# CONFIG_INPUT_TABLET is not set
@@ -726,19 +797,16 @@ CONFIG_INPUT_KEYBOARD=y
726# 797#
727# Character devices 798# Character devices
728# 799#
729# CONFIG_AD9960 is not set 800CONFIG_BFIN_DMA_INTERFACE=m
730# CONFIG_SPI_ADC_BF533 is not set 801# CONFIG_BFIN_PPI is not set
731# CONFIG_BF5xx_PPIFCD is not set 802# CONFIG_BFIN_PPIFCD is not set
732# CONFIG_BFIN_SIMPLE_TIMER is not set 803# CONFIG_BFIN_SIMPLE_TIMER is not set
733# CONFIG_BF5xx_PPI is not set 804# CONFIG_BFIN_SPI_ADC is not set
734CONFIG_BFIN_OTP=y
735# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
736# CONFIG_BFIN_SPORT is not set 805# CONFIG_BFIN_SPORT is not set
737# CONFIG_BFIN_TIMER_LATENCY is not set 806# CONFIG_BFIN_TWI_LCD is not set
738# CONFIG_TWI_LCD is not set
739# CONFIG_SIMPLE_GPIO is not set
740# CONFIG_VT is not set 807# CONFIG_VT is not set
741# CONFIG_DEVKMEM is not set 808CONFIG_DEVKMEM=y
809# CONFIG_BFIN_JTAG_COMM is not set
742# CONFIG_SERIAL_NONSTANDARD is not set 810# CONFIG_SERIAL_NONSTANDARD is not set
743 811
744# 812#
@@ -749,10 +817,11 @@ CONFIG_BFIN_OTP=y
749# 817#
750# Non-8250 serial port support 818# Non-8250 serial port support
751# 819#
820# CONFIG_SERIAL_MAX3100 is not set
752CONFIG_SERIAL_BFIN=y 821CONFIG_SERIAL_BFIN=y
753CONFIG_SERIAL_BFIN_CONSOLE=y 822CONFIG_SERIAL_BFIN_CONSOLE=y
754CONFIG_SERIAL_BFIN_DMA=y 823# CONFIG_SERIAL_BFIN_DMA is not set
755# CONFIG_SERIAL_BFIN_PIO is not set 824CONFIG_SERIAL_BFIN_PIO=y
756# CONFIG_SERIAL_BFIN_UART0 is not set 825# CONFIG_SERIAL_BFIN_UART0 is not set
757CONFIG_SERIAL_BFIN_UART1=y 826CONFIG_SERIAL_BFIN_UART1=y
758# CONFIG_BFIN_UART1_CTSRTS is not set 827# CONFIG_BFIN_UART1_CTSRTS is not set
@@ -762,7 +831,10 @@ CONFIG_SERIAL_CORE=y
762CONFIG_SERIAL_CORE_CONSOLE=y 831CONFIG_SERIAL_CORE_CONSOLE=y
763# CONFIG_SERIAL_BFIN_SPORT is not set 832# CONFIG_SERIAL_BFIN_SPORT is not set
764CONFIG_UNIX98_PTYS=y 833CONFIG_UNIX98_PTYS=y
834# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
765# CONFIG_LEGACY_PTYS is not set 835# CONFIG_LEGACY_PTYS is not set
836CONFIG_BFIN_OTP=y
837# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
766 838
767# 839#
768# CAN, the car bus and industrial fieldbus 840# CAN, the car bus and industrial fieldbus
@@ -770,61 +842,53 @@ CONFIG_UNIX98_PTYS=y
770# CONFIG_CAN4LINUX is not set 842# CONFIG_CAN4LINUX is not set
771# CONFIG_IPMI_HANDLER is not set 843# CONFIG_IPMI_HANDLER is not set
772# CONFIG_HW_RANDOM is not set 844# CONFIG_HW_RANDOM is not set
773# CONFIG_GEN_RTC is not set
774# CONFIG_R3964 is not set 845# CONFIG_R3964 is not set
775# CONFIG_RAW_DRIVER is not set 846# CONFIG_RAW_DRIVER is not set
776# CONFIG_TCG_TPM is not set 847# CONFIG_TCG_TPM is not set
777CONFIG_I2C=y 848CONFIG_I2C=y
778CONFIG_I2C_BOARDINFO=y 849CONFIG_I2C_BOARDINFO=y
779CONFIG_I2C_CHARDEV=y 850CONFIG_I2C_CHARDEV=y
851CONFIG_I2C_HELPER_AUTO=y
780 852
781# 853#
782# I2C Algorithms 854# I2C Hardware Bus support
783# 855#
784# CONFIG_I2C_ALGOBIT is not set
785# CONFIG_I2C_ALGOPCF is not set
786# CONFIG_I2C_ALGOPCA is not set
787 856
788# 857#
789# I2C Hardware Bus support 858# I2C system bus drivers (mostly embedded / system-on-chip)
790# 859#
791CONFIG_I2C_BLACKFIN_TWI=y 860CONFIG_I2C_BLACKFIN_TWI=y
792CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 861CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
793# CONFIG_I2C_GPIO is not set 862# CONFIG_I2C_GPIO is not set
794# CONFIG_I2C_OCORES is not set 863# CONFIG_I2C_OCORES is not set
795# CONFIG_I2C_PARPORT_LIGHT is not set
796# CONFIG_I2C_SIMTEC is not set 864# CONFIG_I2C_SIMTEC is not set
865
866#
867# External I2C/SMBus adapter drivers
868#
869# CONFIG_I2C_PARPORT_LIGHT is not set
797# CONFIG_I2C_TAOS_EVM is not set 870# CONFIG_I2C_TAOS_EVM is not set
798# CONFIG_I2C_STUB is not set
799# CONFIG_I2C_TINY_USB is not set 871# CONFIG_I2C_TINY_USB is not set
800 872
801# 873#
874# Other I2C/SMBus bus drivers
875#
876# CONFIG_I2C_PCA_PLATFORM is not set
877# CONFIG_I2C_STUB is not set
878
879#
802# Miscellaneous I2C Chip support 880# Miscellaneous I2C Chip support
803# 881#
804# CONFIG_SENSORS_DS1337 is not set
805# CONFIG_SENSORS_DS1374 is not set
806# CONFIG_DS1682 is not set 882# CONFIG_DS1682 is not set
807# CONFIG_SENSORS_AD5252 is not set
808# CONFIG_EEPROM_LEGACY is not set
809# CONFIG_SENSORS_PCF8574 is not set 883# CONFIG_SENSORS_PCF8574 is not set
810# CONFIG_SENSORS_PCF8575 is not set 884# CONFIG_PCF8575 is not set
811# CONFIG_SENSORS_PCA9543 is not set
812# CONFIG_SENSORS_PCA9539 is not set 885# CONFIG_SENSORS_PCA9539 is not set
813# CONFIG_SENSORS_PCF8591 is not set
814# CONFIG_SENSORS_MAX6875 is not set 886# CONFIG_SENSORS_MAX6875 is not set
815# CONFIG_SENSORS_TSL2550 is not set 887# CONFIG_SENSORS_TSL2550 is not set
816# CONFIG_I2C_DEBUG_CORE is not set 888# CONFIG_I2C_DEBUG_CORE is not set
817# CONFIG_I2C_DEBUG_ALGO is not set 889# CONFIG_I2C_DEBUG_ALGO is not set
818# CONFIG_I2C_DEBUG_BUS is not set 890# CONFIG_I2C_DEBUG_BUS is not set
819# CONFIG_I2C_DEBUG_CHIP is not set 891# CONFIG_I2C_DEBUG_CHIP is not set
820
821CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
822CONFIG_GPIOLIB=y
823CONFIG_GPIO_SYSFS=y
824
825#
826# SPI support
827#
828CONFIG_SPI=y 892CONFIG_SPI=y
829CONFIG_SPI_MASTER=y 893CONFIG_SPI_MASTER=y
830 894
@@ -832,64 +896,23 @@ CONFIG_SPI_MASTER=y
832# SPI Master Controller Drivers 896# SPI Master Controller Drivers
833# 897#
834CONFIG_SPI_BFIN=y 898CONFIG_SPI_BFIN=y
899# CONFIG_SPI_BFIN_LOCK is not set
900# CONFIG_SPI_BFIN_SPORT is not set
835# CONFIG_SPI_BITBANG is not set 901# CONFIG_SPI_BITBANG is not set
902# CONFIG_SPI_GPIO is not set
836 903
837# 904#
838# SPI Protocol Masters 905# SPI Protocol Masters
839# 906#
840# CONFIG_EEPROM_AT25 is not set
841# CONFIG_SPI_SPIDEV is not set 907# CONFIG_SPI_SPIDEV is not set
842# CONFIG_SPI_TLE62X0 is not set 908# CONFIG_SPI_TLE62X0 is not set
909CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
910# CONFIG_GPIOLIB is not set
843# CONFIG_W1 is not set 911# CONFIG_W1 is not set
844# CONFIG_POWER_SUPPLY is not set 912# CONFIG_POWER_SUPPLY is not set
845CONFIG_HWMON=y 913# CONFIG_HWMON is not set
846# CONFIG_HWMON_VID is not set 914# CONFIG_THERMAL is not set
847# CONFIG_SENSORS_AD7418 is not set 915# CONFIG_THERMAL_HWMON is not set
848# CONFIG_SENSORS_ADM1021 is not set
849# CONFIG_SENSORS_ADM1025 is not set
850# CONFIG_SENSORS_ADM1026 is not set
851# CONFIG_SENSORS_ADM1029 is not set
852# CONFIG_SENSORS_ADM1031 is not set
853# CONFIG_SENSORS_ADM9240 is not set
854# CONFIG_SENSORS_ADT7470 is not set
855# CONFIG_SENSORS_ATXP1 is not set
856# CONFIG_SENSORS_DS1621 is not set
857# CONFIG_SENSORS_F71805F is not set
858# CONFIG_SENSORS_F71882FG is not set
859# CONFIG_SENSORS_F75375S is not set
860# CONFIG_SENSORS_GL518SM is not set
861# CONFIG_SENSORS_GL520SM is not set
862# CONFIG_SENSORS_IT87 is not set
863# CONFIG_SENSORS_LM63 is not set
864# CONFIG_SENSORS_LM70 is not set
865# CONFIG_SENSORS_LM75 is not set
866# CONFIG_SENSORS_LM77 is not set
867# CONFIG_SENSORS_LM78 is not set
868# CONFIG_SENSORS_LM80 is not set
869# CONFIG_SENSORS_LM83 is not set
870# CONFIG_SENSORS_LM85 is not set
871# CONFIG_SENSORS_LM87 is not set
872# CONFIG_SENSORS_LM90 is not set
873# CONFIG_SENSORS_LM92 is not set
874# CONFIG_SENSORS_LM93 is not set
875# CONFIG_SENSORS_MAX1619 is not set
876# CONFIG_SENSORS_MAX6650 is not set
877# CONFIG_SENSORS_PC87360 is not set
878# CONFIG_SENSORS_PC87427 is not set
879# CONFIG_SENSORS_DME1737 is not set
880# CONFIG_SENSORS_SMSC47M1 is not set
881# CONFIG_SENSORS_SMSC47M192 is not set
882# CONFIG_SENSORS_SMSC47B397 is not set
883# CONFIG_SENSORS_THMC50 is not set
884# CONFIG_SENSORS_VT1211 is not set
885# CONFIG_SENSORS_W83781D is not set
886# CONFIG_SENSORS_W83791D is not set
887# CONFIG_SENSORS_W83792D is not set
888# CONFIG_SENSORS_W83793 is not set
889# CONFIG_SENSORS_W83L785TS is not set
890# CONFIG_SENSORS_W83627HF is not set
891# CONFIG_SENSORS_W83627EHF is not set
892# CONFIG_HWMON_DEBUG_CHIP is not set
893CONFIG_WATCHDOG=y 916CONFIG_WATCHDOG=y
894# CONFIG_WATCHDOG_NOWAYOUT is not set 917# CONFIG_WATCHDOG_NOWAYOUT is not set
895 918
@@ -903,25 +926,43 @@ CONFIG_BFIN_WDT=y
903# USB-based Watchdog Cards 926# USB-based Watchdog Cards
904# 927#
905# CONFIG_USBPCWATCHDOG is not set 928# CONFIG_USBPCWATCHDOG is not set
929CONFIG_SSB_POSSIBLE=y
906 930
907# 931#
908# Sonics Silicon Backplane 932# Sonics Silicon Backplane
909# 933#
910CONFIG_SSB_POSSIBLE=y
911# CONFIG_SSB is not set 934# CONFIG_SSB is not set
912 935
913# 936#
914# Multifunction device drivers 937# Multifunction device drivers
915# 938#
939# CONFIG_MFD_CORE is not set
916# CONFIG_MFD_SM501 is not set 940# CONFIG_MFD_SM501 is not set
941# CONFIG_HTC_PASIC3 is not set
942# CONFIG_TWL4030_CORE is not set
943# CONFIG_MFD_TMIO is not set
944# CONFIG_PMIC_DA903X is not set
945# CONFIG_PMIC_ADP5520 is not set
946# CONFIG_MFD_WM8400 is not set
947# CONFIG_MFD_WM8350_I2C is not set
948# CONFIG_MFD_PCF50633 is not set
949# CONFIG_REGULATOR is not set
917 950
918# 951#
919# Multimedia devices 952# Multimedia devices
920# 953#
954
955#
956# Multimedia core support
957#
921# CONFIG_VIDEO_DEV is not set 958# CONFIG_VIDEO_DEV is not set
922# CONFIG_DVB_CORE is not set 959# CONFIG_DVB_CORE is not set
960# CONFIG_VIDEO_MEDIA is not set
961
962#
963# Multimedia drivers
964#
923# CONFIG_DAB is not set 965# CONFIG_DAB is not set
924# CONFIG_USB_DABUSB is not set
925 966
926# 967#
927# Graphics support 968# Graphics support
@@ -935,80 +976,75 @@ CONFIG_SSB_POSSIBLE=y
935# Display device support 976# Display device support
936# 977#
937# CONFIG_DISPLAY_SUPPORT is not set 978# CONFIG_DISPLAY_SUPPORT is not set
938
939#
940# Sound
941#
942# CONFIG_SOUND is not set 979# CONFIG_SOUND is not set
943CONFIG_HID_SUPPORT=y 980# CONFIG_HID_SUPPORT is not set
944CONFIG_HID=y
945# CONFIG_HID_DEBUG is not set
946# CONFIG_HIDRAW is not set
947
948#
949# USB Input Devices
950#
951CONFIG_USB_HID=y
952# CONFIG_USB_HIDINPUT_POWERBOOK is not set
953# CONFIG_HID_FF is not set
954# CONFIG_USB_HIDDEV is not set
955CONFIG_USB_SUPPORT=y 981CONFIG_USB_SUPPORT=y
956CONFIG_USB_ARCH_HAS_HCD=y 982CONFIG_USB_ARCH_HAS_HCD=y
957# CONFIG_USB_ARCH_HAS_OHCI is not set 983# CONFIG_USB_ARCH_HAS_OHCI is not set
958# CONFIG_USB_ARCH_HAS_EHCI is not set 984# CONFIG_USB_ARCH_HAS_EHCI is not set
959CONFIG_USB=y 985CONFIG_USB=m
960# CONFIG_USB_DEBUG is not set 986# CONFIG_USB_DEBUG is not set
987# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
961 988
962# 989#
963# Miscellaneous USB options 990# Miscellaneous USB options
964# 991#
965# CONFIG_USB_DEVICEFS is not set 992CONFIG_USB_DEVICEFS=y
966CONFIG_USB_DEVICE_CLASS=y 993# CONFIG_USB_DEVICE_CLASS is not set
967# CONFIG_USB_DYNAMIC_MINORS is not set 994# CONFIG_USB_DYNAMIC_MINORS is not set
968# CONFIG_USB_OTG is not set 995# CONFIG_USB_OTG is not set
996# CONFIG_USB_OTG_WHITELIST is not set
997# CONFIG_USB_OTG_BLACKLIST_HUB is not set
998CONFIG_USB_MON=m
999# CONFIG_USB_WUSB is not set
1000# CONFIG_USB_WUSB_CBAF is not set
969 1001
970# 1002#
971# USB Host Controller Drivers 1003# USB Host Controller Drivers
972# 1004#
1005# CONFIG_USB_C67X00_HCD is not set
1006# CONFIG_USB_OXU210HP_HCD is not set
973# CONFIG_USB_ISP116X_HCD is not set 1007# CONFIG_USB_ISP116X_HCD is not set
974# CONFIG_USB_ISP1362_HCD is not set
975# CONFIG_USB_ISP1760_HCD is not set 1008# CONFIG_USB_ISP1760_HCD is not set
1009# CONFIG_USB_ISP1362_HCD is not set
976# CONFIG_USB_SL811_HCD is not set 1010# CONFIG_USB_SL811_HCD is not set
977# CONFIG_USB_R8A66597_HCD is not set 1011# CONFIG_USB_R8A66597_HCD is not set
978CONFIG_USB_MUSB_HDRC=y 1012# CONFIG_USB_HWA_HCD is not set
1013CONFIG_USB_MUSB_HDRC=m
979CONFIG_USB_MUSB_SOC=y 1014CONFIG_USB_MUSB_SOC=y
980 1015
981# 1016#
982# Blackfin BF54x, BF525 and BF527 high speed USB support 1017# Blackfin high speed USB Support
983# 1018#
984CONFIG_USB_MUSB_HOST=y 1019# CONFIG_USB_MUSB_HOST is not set
985# CONFIG_USB_MUSB_PERIPHERAL is not set 1020CONFIG_USB_MUSB_PERIPHERAL=y
986# CONFIG_USB_MUSB_OTG is not set 1021# CONFIG_USB_MUSB_OTG is not set
987CONFIG_USB_MUSB_HDRC_HCD=y 1022CONFIG_USB_GADGET_MUSB_HDRC=y
988# CONFIG_MUSB_PIO_ONLY is not set 1023# CONFIG_MUSB_PIO_ONLY is not set
989# CONFIG_USB_INVENTRA_DMA is not set 1024CONFIG_USB_INVENTRA_DMA=y
990# CONFIG_USB_TI_CPPI_DMA is not set 1025# CONFIG_USB_TI_CPPI_DMA is not set
991CONFIG_USB_MUSB_LOGLEVEL=0 1026# CONFIG_USB_MUSB_DEBUG is not set
992 1027
993# 1028#
994# USB Device Class drivers 1029# USB Device Class drivers
995# 1030#
996# CONFIG_USB_ACM is not set 1031# CONFIG_USB_ACM is not set
997# CONFIG_USB_PRINTER is not set 1032# CONFIG_USB_PRINTER is not set
1033# CONFIG_USB_WDM is not set
1034# CONFIG_USB_TMC is not set
998 1035
999# 1036#
1000# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1037# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1001# 1038#
1002 1039
1003# 1040#
1004# may also be needed; see USB_STORAGE Help for more information 1041# also be needed; see USB_STORAGE Help for more info
1005# 1042#
1006CONFIG_USB_STORAGE=y 1043CONFIG_USB_STORAGE=m
1007# CONFIG_USB_STORAGE_DEBUG is not set 1044# CONFIG_USB_STORAGE_DEBUG is not set
1008# CONFIG_USB_STORAGE_DATAFAB is not set 1045# CONFIG_USB_STORAGE_DATAFAB is not set
1009# CONFIG_USB_STORAGE_FREECOM is not set 1046# CONFIG_USB_STORAGE_FREECOM is not set
1010# CONFIG_USB_STORAGE_ISD200 is not set 1047# CONFIG_USB_STORAGE_ISD200 is not set
1011# CONFIG_USB_STORAGE_DPCM is not set
1012# CONFIG_USB_STORAGE_USBAT is not set 1048# CONFIG_USB_STORAGE_USBAT is not set
1013# CONFIG_USB_STORAGE_SDDR09 is not set 1049# CONFIG_USB_STORAGE_SDDR09 is not set
1014# CONFIG_USB_STORAGE_SDDR55 is not set 1050# CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1016,6 +1052,7 @@ CONFIG_USB_STORAGE=y
1016# CONFIG_USB_STORAGE_ALAUDA is not set 1052# CONFIG_USB_STORAGE_ALAUDA is not set
1017# CONFIG_USB_STORAGE_ONETOUCH is not set 1053# CONFIG_USB_STORAGE_ONETOUCH is not set
1018# CONFIG_USB_STORAGE_KARMA is not set 1054# CONFIG_USB_STORAGE_KARMA is not set
1055# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1019# CONFIG_USB_LIBUSUAL is not set 1056# CONFIG_USB_LIBUSUAL is not set
1020 1057
1021# 1058#
@@ -1023,15 +1060,10 @@ CONFIG_USB_STORAGE=y
1023# 1060#
1024# CONFIG_USB_MDC800 is not set 1061# CONFIG_USB_MDC800 is not set
1025# CONFIG_USB_MICROTEK is not set 1062# CONFIG_USB_MICROTEK is not set
1026CONFIG_USB_MON=y
1027 1063
1028# 1064#
1029# USB port drivers 1065# USB port drivers
1030# 1066#
1031
1032#
1033# USB Serial Converter support
1034#
1035# CONFIG_USB_SERIAL is not set 1067# CONFIG_USB_SERIAL is not set
1036 1068
1037# 1069#
@@ -1040,7 +1072,7 @@ CONFIG_USB_MON=y
1040# CONFIG_USB_EMI62 is not set 1072# CONFIG_USB_EMI62 is not set
1041# CONFIG_USB_EMI26 is not set 1073# CONFIG_USB_EMI26 is not set
1042# CONFIG_USB_ADUTUX is not set 1074# CONFIG_USB_ADUTUX is not set
1043# CONFIG_USB_AUERSWALD is not set 1075# CONFIG_USB_SEVSEG is not set
1044# CONFIG_USB_RIO500 is not set 1076# CONFIG_USB_RIO500 is not set
1045# CONFIG_USB_LEGOTOWER is not set 1077# CONFIG_USB_LEGOTOWER is not set
1046# CONFIG_USB_LCD is not set 1078# CONFIG_USB_LCD is not set
@@ -1048,7 +1080,6 @@ CONFIG_USB_MON=y
1048# CONFIG_USB_LED is not set 1080# CONFIG_USB_LED is not set
1049# CONFIG_USB_CYPRESS_CY7C63 is not set 1081# CONFIG_USB_CYPRESS_CY7C63 is not set
1050# CONFIG_USB_CYTHERM is not set 1082# CONFIG_USB_CYTHERM is not set
1051# CONFIG_USB_PHIDGET is not set
1052# CONFIG_USB_IDMOUSE is not set 1083# CONFIG_USB_IDMOUSE is not set
1053# CONFIG_USB_FTDI_ELAN is not set 1084# CONFIG_USB_FTDI_ELAN is not set
1054# CONFIG_USB_APPLEDISPLAY is not set 1085# CONFIG_USB_APPLEDISPLAY is not set
@@ -1056,38 +1087,75 @@ CONFIG_USB_MON=y
1056# CONFIG_USB_LD is not set 1087# CONFIG_USB_LD is not set
1057# CONFIG_USB_TRANCEVIBRATOR is not set 1088# CONFIG_USB_TRANCEVIBRATOR is not set
1058# CONFIG_USB_IOWARRIOR is not set 1089# CONFIG_USB_IOWARRIOR is not set
1059 1090# CONFIG_USB_TEST is not set
1060# 1091# CONFIG_USB_ISIGHTFW is not set
1061# USB DSL modem support 1092# CONFIG_USB_VST is not set
1062# 1093CONFIG_USB_GADGET=m
1063 1094# CONFIG_USB_GADGET_DEBUG_FILES is not set
1064# 1095# CONFIG_USB_GADGET_DEBUG_FS is not set
1065# USB Gadget Support 1096CONFIG_USB_GADGET_VBUS_DRAW=2
1066# 1097CONFIG_USB_GADGET_SELECTED=y
1067# CONFIG_USB_GADGET is not set 1098# CONFIG_USB_GADGET_AT91 is not set
1068CONFIG_MMC=y 1099# CONFIG_USB_GADGET_ATMEL_USBA is not set
1100# CONFIG_USB_GADGET_FSL_USB2 is not set
1101# CONFIG_USB_GADGET_LH7A40X is not set
1102# CONFIG_USB_GADGET_OMAP is not set
1103# CONFIG_USB_GADGET_PXA25X is not set
1104# CONFIG_USB_GADGET_PXA27X is not set
1105# CONFIG_USB_GADGET_S3C2410 is not set
1106# CONFIG_USB_GADGET_IMX is not set
1107# CONFIG_USB_GADGET_M66592 is not set
1108# CONFIG_USB_GADGET_AMD5536UDC is not set
1109# CONFIG_USB_GADGET_FSL_QE is not set
1110# CONFIG_USB_GADGET_CI13XXX is not set
1111# CONFIG_USB_GADGET_NET2272 is not set
1112# CONFIG_USB_GADGET_NET2280 is not set
1113# CONFIG_USB_GADGET_GOKU is not set
1114# CONFIG_USB_GADGET_DUMMY_HCD is not set
1115CONFIG_USB_GADGET_DUALSPEED=y
1116CONFIG_USB_ZERO=m
1117# CONFIG_USB_AUDIO is not set
1118CONFIG_USB_ETH=m
1119# CONFIG_USB_ETH_RNDIS is not set
1120CONFIG_USB_GADGETFS=m
1121CONFIG_USB_FILE_STORAGE=m
1122# CONFIG_USB_FILE_STORAGE_TEST is not set
1123CONFIG_USB_G_SERIAL=m
1124# CONFIG_USB_MIDI_GADGET is not set
1125CONFIG_USB_G_PRINTER=m
1126# CONFIG_USB_CDC_COMPOSITE is not set
1127
1128#
1129# OTG and related infrastructure
1130#
1131CONFIG_USB_OTG_UTILS=y
1132# CONFIG_USB_GPIO_VBUS is not set
1133# CONFIG_NOP_USB_XCEIV is not set
1134CONFIG_MMC=m
1069# CONFIG_MMC_DEBUG is not set 1135# CONFIG_MMC_DEBUG is not set
1070# CONFIG_MMC_UNSAFE_RESUME is not set 1136# CONFIG_MMC_UNSAFE_RESUME is not set
1071 1137
1072# 1138#
1073# MMC/SD Card Drivers 1139# MMC/SD/SDIO Card Drivers
1074# 1140#
1075CONFIG_MMC_BLOCK=y 1141CONFIG_MMC_BLOCK=m
1076CONFIG_MMC_BLOCK_BOUNCE=y 1142CONFIG_MMC_BLOCK_BOUNCE=y
1077# CONFIG_SDIO_UART is not set 1143# CONFIG_SDIO_UART is not set
1144# CONFIG_MMC_TEST is not set
1078 1145
1079# 1146#
1080# MMC/SD Host Controller Drivers 1147# MMC/SD/SDIO Host Controller Drivers
1081# 1148#
1082CONFIG_SDH_BFIN=y 1149# CONFIG_MMC_SDHCI is not set
1150CONFIG_SDH_BFIN=m
1151# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set
1152# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set
1083# CONFIG_MMC_SPI is not set 1153# CONFIG_MMC_SPI is not set
1084# CONFIG_SPI_MMC is not set 1154# CONFIG_MEMSTICK is not set
1085# CONFIG_NEW_LEDS is not set 1155# CONFIG_NEW_LEDS is not set
1086CONFIG_RTC_LIB=y 1156# CONFIG_ACCESSIBILITY is not set
1087CONFIG_RTC_CLASS=y 1157CONFIG_RTC_LIB=m
1088CONFIG_RTC_HCTOSYS=y 1158CONFIG_RTC_CLASS=m
1089CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1090# CONFIG_RTC_DEBUG is not set
1091 1159
1092# 1160#
1093# RTC interfaces 1161# RTC interfaces
@@ -1111,66 +1179,74 @@ CONFIG_RTC_INTF_DEV=y
1111# CONFIG_RTC_DRV_PCF8563 is not set 1179# CONFIG_RTC_DRV_PCF8563 is not set
1112# CONFIG_RTC_DRV_PCF8583 is not set 1180# CONFIG_RTC_DRV_PCF8583 is not set
1113# CONFIG_RTC_DRV_M41T80 is not set 1181# CONFIG_RTC_DRV_M41T80 is not set
1182# CONFIG_RTC_DRV_S35390A is not set
1183# CONFIG_RTC_DRV_FM3130 is not set
1184# CONFIG_RTC_DRV_RX8581 is not set
1114 1185
1115# 1186#
1116# SPI RTC drivers 1187# SPI RTC drivers
1117# 1188#
1118# CONFIG_RTC_DRV_RS5C348 is not set 1189# CONFIG_RTC_DRV_M41T94 is not set
1190# CONFIG_RTC_DRV_DS1305 is not set
1191# CONFIG_RTC_DRV_DS1390 is not set
1119# CONFIG_RTC_DRV_MAX6902 is not set 1192# CONFIG_RTC_DRV_MAX6902 is not set
1193# CONFIG_RTC_DRV_R9701 is not set
1194# CONFIG_RTC_DRV_RS5C348 is not set
1195# CONFIG_RTC_DRV_DS3234 is not set
1120 1196
1121# 1197#
1122# Platform RTC drivers 1198# Platform RTC drivers
1123# 1199#
1200# CONFIG_RTC_DRV_DS1286 is not set
1201# CONFIG_RTC_DRV_DS1511 is not set
1124# CONFIG_RTC_DRV_DS1553 is not set 1202# CONFIG_RTC_DRV_DS1553 is not set
1125# CONFIG_RTC_DRV_STK17TA8 is not set
1126# CONFIG_RTC_DRV_DS1742 is not set 1203# CONFIG_RTC_DRV_DS1742 is not set
1204# CONFIG_RTC_DRV_STK17TA8 is not set
1127# CONFIG_RTC_DRV_M48T86 is not set 1205# CONFIG_RTC_DRV_M48T86 is not set
1206# CONFIG_RTC_DRV_M48T35 is not set
1128# CONFIG_RTC_DRV_M48T59 is not set 1207# CONFIG_RTC_DRV_M48T59 is not set
1208# CONFIG_RTC_DRV_BQ4802 is not set
1129# CONFIG_RTC_DRV_V3020 is not set 1209# CONFIG_RTC_DRV_V3020 is not set
1130 1210
1131# 1211#
1132# on-CPU RTC drivers 1212# on-CPU RTC drivers
1133# 1213#
1134CONFIG_RTC_DRV_BFIN=y 1214CONFIG_RTC_DRV_BFIN=m
1135 1215# CONFIG_DMADEVICES is not set
1136# 1216# CONFIG_AUXDISPLAY is not set
1137# Userspace I/O
1138#
1139# CONFIG_UIO is not set 1217# CONFIG_UIO is not set
1140 1218# CONFIG_STAGING is not set
1141#
1142# PBX support
1143#
1144# CONFIG_PBX is not set
1145 1219
1146# 1220#
1147# File systems 1221# File systems
1148# 1222#
1149# CONFIG_EXT2_FS is not set 1223CONFIG_EXT2_FS=m
1224# CONFIG_EXT2_FS_XATTR is not set
1150# CONFIG_EXT3_FS is not set 1225# CONFIG_EXT3_FS is not set
1151# CONFIG_EXT4DEV_FS is not set 1226# CONFIG_EXT4_FS is not set
1152# CONFIG_REISERFS_FS is not set 1227# CONFIG_REISERFS_FS is not set
1153# CONFIG_JFS_FS is not set 1228# CONFIG_JFS_FS is not set
1154# CONFIG_FS_POSIX_ACL is not set 1229# CONFIG_FS_POSIX_ACL is not set
1155# CONFIG_XFS_FS is not set 1230# CONFIG_XFS_FS is not set
1156# CONFIG_GFS2_FS is not set
1157# CONFIG_OCFS2_FS is not set 1231# CONFIG_OCFS2_FS is not set
1158# CONFIG_MINIX_FS is not set 1232# CONFIG_BTRFS_FS is not set
1159# CONFIG_ROMFS_FS is not set 1233CONFIG_FILE_LOCKING=y
1160CONFIG_INOTIFY=y
1161CONFIG_INOTIFY_USER=y
1162# CONFIG_QUOTA is not set
1163# CONFIG_DNOTIFY is not set 1234# CONFIG_DNOTIFY is not set
1235# CONFIG_INOTIFY is not set
1236# CONFIG_QUOTA is not set
1164# CONFIG_AUTOFS_FS is not set 1237# CONFIG_AUTOFS_FS is not set
1165# CONFIG_AUTOFS4_FS is not set 1238# CONFIG_AUTOFS4_FS is not set
1166# CONFIG_FUSE_FS is not set 1239# CONFIG_FUSE_FS is not set
1167 1240
1168# 1241#
1242# Caches
1243#
1244# CONFIG_FSCACHE is not set
1245
1246#
1169# CD-ROM/DVD Filesystems 1247# CD-ROM/DVD Filesystems
1170# 1248#
1171CONFIG_ISO9660_FS=m 1249# CONFIG_ISO9660_FS is not set
1172CONFIG_JOLIET=y
1173CONFIG_ZISOFS=y
1174# CONFIG_UDF_FS is not set 1250# CONFIG_UDF_FS is not set
1175 1251
1176# 1252#
@@ -1194,10 +1270,7 @@ CONFIG_SYSFS=y
1194# CONFIG_TMPFS is not set 1270# CONFIG_TMPFS is not set
1195# CONFIG_HUGETLB_PAGE is not set 1271# CONFIG_HUGETLB_PAGE is not set
1196# CONFIG_CONFIGFS_FS is not set 1272# CONFIG_CONFIGFS_FS is not set
1197 1273CONFIG_MISC_FILESYSTEMS=y
1198#
1199# Miscellaneous filesystems
1200#
1201# CONFIG_ADFS_FS is not set 1274# CONFIG_ADFS_FS is not set
1202# CONFIG_AFFS_FS is not set 1275# CONFIG_AFFS_FS is not set
1203# CONFIG_HFS_FS is not set 1276# CONFIG_HFS_FS is not set
@@ -1205,17 +1278,7 @@ CONFIG_SYSFS=y
1205# CONFIG_BEFS_FS is not set 1278# CONFIG_BEFS_FS is not set
1206# CONFIG_BFS_FS is not set 1279# CONFIG_BFS_FS is not set
1207# CONFIG_EFS_FS is not set 1280# CONFIG_EFS_FS is not set
1208CONFIG_YAFFS_FS=m 1281CONFIG_JFFS2_FS=y
1209CONFIG_YAFFS_YAFFS1=y
1210# CONFIG_YAFFS_DOES_ECC is not set
1211CONFIG_YAFFS_YAFFS2=y
1212CONFIG_YAFFS_AUTO_YAFFS2=y
1213# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
1214CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
1215# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
1216# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
1217CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
1218CONFIG_JFFS2_FS=m
1219CONFIG_JFFS2_FS_DEBUG=0 1282CONFIG_JFFS2_FS_DEBUG=0
1220CONFIG_JFFS2_FS_WRITEBUFFER=y 1283CONFIG_JFFS2_FS_WRITEBUFFER=y
1221# CONFIG_JFFS2_FS_WBUF_VERIFY is not set 1284# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
@@ -1227,34 +1290,30 @@ CONFIG_JFFS2_ZLIB=y
1227CONFIG_JFFS2_RTIME=y 1290CONFIG_JFFS2_RTIME=y
1228# CONFIG_JFFS2_RUBIN is not set 1291# CONFIG_JFFS2_RUBIN is not set
1229# CONFIG_CRAMFS is not set 1292# CONFIG_CRAMFS is not set
1293# CONFIG_SQUASHFS is not set
1230# CONFIG_VXFS_FS is not set 1294# CONFIG_VXFS_FS is not set
1295# CONFIG_MINIX_FS is not set
1296# CONFIG_OMFS_FS is not set
1231# CONFIG_HPFS_FS is not set 1297# CONFIG_HPFS_FS is not set
1232# CONFIG_QNX4FS_FS is not set 1298# CONFIG_QNX4FS_FS is not set
1299# CONFIG_ROMFS_FS is not set
1233# CONFIG_SYSV_FS is not set 1300# CONFIG_SYSV_FS is not set
1234# CONFIG_UFS_FS is not set 1301# CONFIG_UFS_FS is not set
1302# CONFIG_NILFS2_FS is not set
1235CONFIG_NETWORK_FILESYSTEMS=y 1303CONFIG_NETWORK_FILESYSTEMS=y
1236CONFIG_NFS_FS=m 1304CONFIG_NFS_FS=m
1237CONFIG_NFS_V3=y 1305CONFIG_NFS_V3=y
1238# CONFIG_NFS_V3_ACL is not set 1306# CONFIG_NFS_V3_ACL is not set
1239# CONFIG_NFS_V4 is not set 1307# CONFIG_NFS_V4 is not set
1240# CONFIG_NFS_DIRECTIO is not set 1308# CONFIG_NFSD is not set
1241CONFIG_NFSD=m
1242CONFIG_NFSD_V3=y
1243# CONFIG_NFSD_V3_ACL is not set
1244# CONFIG_NFSD_V4 is not set
1245CONFIG_NFSD_TCP=y
1246CONFIG_LOCKD=m 1309CONFIG_LOCKD=m
1247CONFIG_LOCKD_V4=y 1310CONFIG_LOCKD_V4=y
1248CONFIG_EXPORTFS=m
1249CONFIG_NFS_COMMON=y 1311CONFIG_NFS_COMMON=y
1250CONFIG_SUNRPC=m 1312CONFIG_SUNRPC=m
1251# CONFIG_SUNRPC_BIND34 is not set
1252# CONFIG_RPCSEC_GSS_KRB5 is not set 1313# CONFIG_RPCSEC_GSS_KRB5 is not set
1253# CONFIG_RPCSEC_GSS_SPKM3 is not set 1314# CONFIG_RPCSEC_GSS_SPKM3 is not set
1254CONFIG_SMB_FS=m 1315# CONFIG_SMB_FS is not set
1255CONFIG_SMB_NLS_DEFAULT=y 1316CONFIG_CIFS=m
1256CONFIG_SMB_NLS_REMOTE="cp437"
1257CONFIG_CIFS=y
1258# CONFIG_CIFS_STATS is not set 1317# CONFIG_CIFS_STATS is not set
1259# CONFIG_CIFS_WEAK_PW_HASH is not set 1318# CONFIG_CIFS_WEAK_PW_HASH is not set
1260# CONFIG_CIFS_XATTR is not set 1319# CONFIG_CIFS_XATTR is not set
@@ -1267,24 +1326,8 @@ CONFIG_CIFS=y
1267# 1326#
1268# Partition Types 1327# Partition Types
1269# 1328#
1270CONFIG_PARTITION_ADVANCED=y 1329# CONFIG_PARTITION_ADVANCED is not set
1271# CONFIG_ACORN_PARTITION is not set
1272# CONFIG_OSF_PARTITION is not set
1273# CONFIG_AMIGA_PARTITION is not set
1274# CONFIG_ATARI_PARTITION is not set
1275# CONFIG_MAC_PARTITION is not set
1276CONFIG_MSDOS_PARTITION=y 1330CONFIG_MSDOS_PARTITION=y
1277# CONFIG_BSD_DISKLABEL is not set
1278# CONFIG_MINIX_SUBPARTITION is not set
1279# CONFIG_SOLARIS_X86_PARTITION is not set
1280# CONFIG_UNIXWARE_DISKLABEL is not set
1281# CONFIG_LDM_PARTITION is not set
1282# CONFIG_SGI_PARTITION is not set
1283# CONFIG_ULTRIX_PARTITION is not set
1284# CONFIG_SUN_PARTITION is not set
1285# CONFIG_KARMA_PARTITION is not set
1286# CONFIG_EFI_PARTITION is not set
1287# CONFIG_SYSV68_PARTITION is not set
1288CONFIG_NLS=y 1331CONFIG_NLS=y
1289CONFIG_NLS_DEFAULT="iso8859-1" 1332CONFIG_NLS_DEFAULT="iso8859-1"
1290CONFIG_NLS_CODEPAGE_437=m 1333CONFIG_NLS_CODEPAGE_437=m
@@ -1326,9 +1369,6 @@ CONFIG_NLS_KOI8_R=m
1326CONFIG_NLS_KOI8_U=m 1369CONFIG_NLS_KOI8_U=m
1327CONFIG_NLS_UTF8=m 1370CONFIG_NLS_UTF8=m
1328# CONFIG_DLM is not set 1371# CONFIG_DLM is not set
1329CONFIG_INSTRUMENTATION=y
1330# CONFIG_PROFILING is not set
1331# CONFIG_MARKERS is not set
1332 1372
1333# 1373#
1334# Kernel hacking 1374# Kernel hacking
@@ -1336,14 +1376,39 @@ CONFIG_INSTRUMENTATION=y
1336# CONFIG_PRINTK_TIME is not set 1376# CONFIG_PRINTK_TIME is not set
1337CONFIG_ENABLE_WARN_DEPRECATED=y 1377CONFIG_ENABLE_WARN_DEPRECATED=y
1338CONFIG_ENABLE_MUST_CHECK=y 1378CONFIG_ENABLE_MUST_CHECK=y
1379CONFIG_FRAME_WARN=1024
1339# CONFIG_MAGIC_SYSRQ is not set 1380# CONFIG_MAGIC_SYSRQ is not set
1340# CONFIG_UNUSED_SYMBOLS is not set 1381# CONFIG_UNUSED_SYMBOLS is not set
1341CONFIG_DEBUG_FS=y 1382CONFIG_DEBUG_FS=y
1342# CONFIG_HEADERS_CHECK is not set 1383# CONFIG_HEADERS_CHECK is not set
1384CONFIG_DEBUG_SECTION_MISMATCH=y
1343# CONFIG_DEBUG_KERNEL is not set 1385# CONFIG_DEBUG_KERNEL is not set
1344CONFIG_DEBUG_BUGVERBOSE=y 1386# CONFIG_DEBUG_BUGVERBOSE is not set
1387# CONFIG_DEBUG_MEMORY_INIT is not set
1388# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1389CONFIG_HAVE_FUNCTION_TRACER=y
1390CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1391CONFIG_TRACING_SUPPORT=y
1392
1393#
1394# Tracers
1395#
1396# CONFIG_FUNCTION_TRACER is not set
1397# CONFIG_SCHED_TRACER is not set
1398# CONFIG_CONTEXT_SWITCH_TRACER is not set
1399# CONFIG_EVENT_TRACER is not set
1400# CONFIG_BOOT_TRACER is not set
1401# CONFIG_TRACE_BRANCH_PROFILING is not set
1402# CONFIG_STACK_TRACER is not set
1403# CONFIG_KMEMTRACE is not set
1404# CONFIG_WORKQUEUE_TRACER is not set
1405# CONFIG_BLK_DEV_IO_TRACE is not set
1406# CONFIG_DYNAMIC_DEBUG is not set
1345# CONFIG_SAMPLES is not set 1407# CONFIG_SAMPLES is not set
1346CONFIG_DEBUG_MMRS=y 1408CONFIG_HAVE_ARCH_KGDB=y
1409CONFIG_DEBUG_VERBOSE=y
1410# CONFIG_DEBUG_MMRS is not set
1411# CONFIG_DEBUG_DOUBLEFAULT is not set
1347CONFIG_DEBUG_HUNT_FOR_ZERO=y 1412CONFIG_DEBUG_HUNT_FOR_ZERO=y
1348CONFIG_DEBUG_BFIN_HWTRACE_ON=y 1413CONFIG_DEBUG_BFIN_HWTRACE_ON=y
1349CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y 1414CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1352,33 +1417,125 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1352CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1417CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1353# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1418# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1354# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1419# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1355# CONFIG_EARLY_PRINTK is not set 1420CONFIG_EARLY_PRINTK=y
1356CONFIG_CPLB_INFO=y 1421CONFIG_CPLB_INFO=y
1357CONFIG_ACCESS_CHECK=y 1422CONFIG_ACCESS_CHECK=y
1423# CONFIG_BFIN_ISRAM_SELF_TEST is not set
1358 1424
1359# 1425#
1360# Security options 1426# Security options
1361# 1427#
1362# CONFIG_KEYS is not set 1428# CONFIG_KEYS is not set
1363CONFIG_SECURITY=y 1429CONFIG_SECURITY=y
1430# CONFIG_SECURITYFS is not set
1364# CONFIG_SECURITY_NETWORK is not set 1431# CONFIG_SECURITY_NETWORK is not set
1365# CONFIG_SECURITY_CAPABILITIES is not set 1432# CONFIG_SECURITY_PATH is not set
1366# CONFIG_SECURITY_ROOTPLUG is not set 1433# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1367# CONFIG_CRYPTO is not set 1434# CONFIG_SECURITY_TOMOYO is not set
1435CONFIG_CRYPTO=y
1436
1437#
1438# Crypto core or helper
1439#
1440# CONFIG_CRYPTO_FIPS is not set
1441# CONFIG_CRYPTO_MANAGER is not set
1442# CONFIG_CRYPTO_MANAGER2 is not set
1443# CONFIG_CRYPTO_GF128MUL is not set
1444# CONFIG_CRYPTO_NULL is not set
1445# CONFIG_CRYPTO_CRYPTD is not set
1446# CONFIG_CRYPTO_AUTHENC is not set
1447# CONFIG_CRYPTO_TEST is not set
1448
1449#
1450# Authenticated Encryption with Associated Data
1451#
1452# CONFIG_CRYPTO_CCM is not set
1453# CONFIG_CRYPTO_GCM is not set
1454# CONFIG_CRYPTO_SEQIV is not set
1455
1456#
1457# Block modes
1458#
1459# CONFIG_CRYPTO_CBC is not set
1460# CONFIG_CRYPTO_CTR is not set
1461# CONFIG_CRYPTO_CTS is not set
1462# CONFIG_CRYPTO_ECB is not set
1463# CONFIG_CRYPTO_LRW is not set
1464# CONFIG_CRYPTO_PCBC is not set
1465# CONFIG_CRYPTO_XTS is not set
1466
1467#
1468# Hash modes
1469#
1470# CONFIG_CRYPTO_HMAC is not set
1471# CONFIG_CRYPTO_XCBC is not set
1472
1473#
1474# Digest
1475#
1476# CONFIG_CRYPTO_CRC32C is not set
1477# CONFIG_CRYPTO_MD4 is not set
1478# CONFIG_CRYPTO_MD5 is not set
1479# CONFIG_CRYPTO_MICHAEL_MIC is not set
1480# CONFIG_CRYPTO_RMD128 is not set
1481# CONFIG_CRYPTO_RMD160 is not set
1482# CONFIG_CRYPTO_RMD256 is not set
1483# CONFIG_CRYPTO_RMD320 is not set
1484# CONFIG_CRYPTO_SHA1 is not set
1485# CONFIG_CRYPTO_SHA256 is not set
1486# CONFIG_CRYPTO_SHA512 is not set
1487# CONFIG_CRYPTO_TGR192 is not set
1488# CONFIG_CRYPTO_WP512 is not set
1489
1490#
1491# Ciphers
1492#
1493# CONFIG_CRYPTO_AES is not set
1494# CONFIG_CRYPTO_ANUBIS is not set
1495# CONFIG_CRYPTO_ARC4 is not set
1496# CONFIG_CRYPTO_BLOWFISH is not set
1497# CONFIG_CRYPTO_CAMELLIA is not set
1498# CONFIG_CRYPTO_CAST5 is not set
1499# CONFIG_CRYPTO_CAST6 is not set
1500# CONFIG_CRYPTO_DES is not set
1501# CONFIG_CRYPTO_FCRYPT is not set
1502# CONFIG_CRYPTO_KHAZAD is not set
1503# CONFIG_CRYPTO_SALSA20 is not set
1504# CONFIG_CRYPTO_SEED is not set
1505# CONFIG_CRYPTO_SERPENT is not set
1506# CONFIG_CRYPTO_TEA is not set
1507# CONFIG_CRYPTO_TWOFISH is not set
1508
1509#
1510# Compression
1511#
1512# CONFIG_CRYPTO_DEFLATE is not set
1513# CONFIG_CRYPTO_ZLIB is not set
1514# CONFIG_CRYPTO_LZO is not set
1515
1516#
1517# Random Number Generation
1518#
1519# CONFIG_CRYPTO_ANSI_CPRNG is not set
1520# CONFIG_CRYPTO_HW is not set
1521# CONFIG_BINARY_PRINTF is not set
1368 1522
1369# 1523#
1370# Library routines 1524# Library routines
1371# 1525#
1372CONFIG_BITREVERSE=y 1526CONFIG_BITREVERSE=y
1527CONFIG_GENERIC_FIND_LAST_BIT=y
1373CONFIG_CRC_CCITT=m 1528CONFIG_CRC_CCITT=m
1374# CONFIG_CRC16 is not set 1529# CONFIG_CRC16 is not set
1530# CONFIG_CRC_T10DIF is not set
1375# CONFIG_CRC_ITU_T is not set 1531# CONFIG_CRC_ITU_T is not set
1376CONFIG_CRC32=y 1532CONFIG_CRC32=y
1377# CONFIG_CRC7 is not set 1533# CONFIG_CRC7 is not set
1378# CONFIG_LIBCRC32C is not set 1534# CONFIG_LIBCRC32C is not set
1379CONFIG_ZLIB_INFLATE=y 1535CONFIG_ZLIB_INFLATE=y
1380CONFIG_ZLIB_DEFLATE=m 1536CONFIG_ZLIB_DEFLATE=y
1381CONFIG_PLIST=y 1537CONFIG_DECOMPRESS_LZMA=y
1382CONFIG_HAS_IOMEM=y 1538CONFIG_HAS_IOMEM=y
1383CONFIG_HAS_IOPORT=y 1539CONFIG_HAS_IOPORT=y
1384CONFIG_HAS_DMA=y 1540CONFIG_HAS_DMA=y
1541CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index bae4ee6e68bb..a6df01dac98a 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -1,15 +1,14 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24.4 3# Linux kernel version: 2.6.30.5
4# Tue Apr 1 10:50:11 2008
5# 4#
6# CONFIG_MMU is not set 5# CONFIG_MMU is not set
7# CONFIG_FPU is not set 6# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_SEMAPHORE_SLEEPERS=y
13CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_HARDIRQS=y 14CONFIG_GENERIC_HARDIRQS=y
@@ -17,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
17CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
18CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
19CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
20CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
21 23
22# 24#
@@ -27,62 +29,83 @@ CONFIG_BROKEN_ON_SMP=y
27CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
28CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
29CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
30CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
32# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
33# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
34# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
35# CONFIG_USER_NS is not set
36# CONFIG_PID_NS is not set
37# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
38CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
39CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
40CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
56# CONFIG_GROUP_SCHED is not set
41# CONFIG_CGROUPS is not set 57# CONFIG_CGROUPS is not set
42CONFIG_FAIR_GROUP_SCHED=y 58# CONFIG_SYSFS_DEPRECATED_V2 is not set
43CONFIG_FAIR_USER_SCHED=y
44# CONFIG_FAIR_CGROUP_SCHED is not set
45# CONFIG_SYSFS_DEPRECATED is not set
46# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
47# CONFIG_BLK_DEV_INITRD is not set 60# CONFIG_NAMESPACES is not set
61CONFIG_BLK_DEV_INITRD=y
62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
49# CONFIG_SYSCTL is not set 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
50CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
51# CONFIG_UID16 is not set 70# CONFIG_UID16 is not set
52# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
53CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
55# CONFIG_HOTPLUG is not set 74# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y
56CONFIG_PRINTK=y 76CONFIG_PRINTK=y
57CONFIG_BUG=y 77CONFIG_BUG=y
58# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
59CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
60# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y 81CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y 82# CONFIG_SIGNALFD is not set
64CONFIG_EVENTFD=y 83# CONFIG_TIMERFD is not set
84# CONFIG_EVENTFD is not set
85# CONFIG_AIO is not set
65CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 87CONFIG_COMPAT_BRK=y
67# CONFIG_NP2 is not set
68CONFIG_SLAB=y 88CONFIG_SLAB=y
69# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
70# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
71CONFIG_SLABINFO=y 97CONFIG_SLABINFO=y
72CONFIG_RT_MUTEXES=y
73CONFIG_TINY_SHMEM=y
74CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
75CONFIG_MODULES=y 99CONFIG_MODULES=y
100# CONFIG_MODULE_FORCE_LOAD is not set
76CONFIG_MODULE_UNLOAD=y 101CONFIG_MODULE_UNLOAD=y
77# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
78# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
79# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
80CONFIG_KMOD=y
81CONFIG_BLOCK=y 105CONFIG_BLOCK=y
82# CONFIG_LBD is not set 106# CONFIG_LBD is not set
83# CONFIG_BLK_DEV_IO_TRACE is not set
84# CONFIG_LSF is not set
85# CONFIG_BLK_DEV_BSG is not set 107# CONFIG_BLK_DEV_BSG is not set
108# CONFIG_BLK_DEV_INTEGRITY is not set
86 109
87# 110#
88# IO Schedulers 111# IO Schedulers
@@ -99,6 +122,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
99CONFIG_PREEMPT_NONE=y 122CONFIG_PREEMPT_NONE=y
100# CONFIG_PREEMPT_VOLUNTARY is not set 123# CONFIG_PREEMPT_VOLUNTARY is not set
101# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
125# CONFIG_FREEZER is not set
102 126
103# 127#
104# Blackfin Processor Options 128# Blackfin Processor Options
@@ -107,6 +131,10 @@ CONFIG_PREEMPT_NONE=y
107# 131#
108# Processor and Board Settings 132# Processor and Board Settings
109# 133#
134# CONFIG_BF512 is not set
135# CONFIG_BF514 is not set
136# CONFIG_BF516 is not set
137# CONFIG_BF518 is not set
110# CONFIG_BF522 is not set 138# CONFIG_BF522 is not set
111# CONFIG_BF523 is not set 139# CONFIG_BF523 is not set
112# CONFIG_BF524 is not set 140# CONFIG_BF524 is not set
@@ -119,30 +147,47 @@ CONFIG_PREEMPT_NONE=y
119# CONFIG_BF534 is not set 147# CONFIG_BF534 is not set
120# CONFIG_BF536 is not set 148# CONFIG_BF536 is not set
121# CONFIG_BF537 is not set 149# CONFIG_BF537 is not set
150# CONFIG_BF538 is not set
151# CONFIG_BF539 is not set
122# CONFIG_BF542 is not set 152# CONFIG_BF542 is not set
153# CONFIG_BF542M is not set
123# CONFIG_BF544 is not set 154# CONFIG_BF544 is not set
155# CONFIG_BF544M is not set
124# CONFIG_BF547 is not set 156# CONFIG_BF547 is not set
157# CONFIG_BF547M is not set
125# CONFIG_BF548 is not set 158# CONFIG_BF548 is not set
159# CONFIG_BF548M is not set
126# CONFIG_BF549 is not set 160# CONFIG_BF549 is not set
161# CONFIG_BF549M is not set
127CONFIG_BF561=y 162CONFIG_BF561=y
163# CONFIG_SMP is not set
164CONFIG_BF_REV_MIN=3
165CONFIG_BF_REV_MAX=5
128# CONFIG_BF_REV_0_0 is not set 166# CONFIG_BF_REV_0_0 is not set
129# CONFIG_BF_REV_0_1 is not set 167# CONFIG_BF_REV_0_1 is not set
130# CONFIG_BF_REV_0_2 is not set 168# CONFIG_BF_REV_0_2 is not set
131CONFIG_BF_REV_0_3=y 169CONFIG_BF_REV_0_3=y
132# CONFIG_BF_REV_0_4 is not set 170# CONFIG_BF_REV_0_4 is not set
133# CONFIG_BF_REV_0_5 is not set 171# CONFIG_BF_REV_0_5 is not set
172# CONFIG_BF_REV_0_6 is not set
134# CONFIG_BF_REV_ANY is not set 173# CONFIG_BF_REV_ANY is not set
135# CONFIG_BF_REV_NONE is not set 174# CONFIG_BF_REV_NONE is not set
136CONFIG_BFIN_DUAL_CORE=y
137CONFIG_MEM_MT48LC8M32B2B5_7=y 175CONFIG_MEM_MT48LC8M32B2B5_7=y
138CONFIG_IRQ_PLL_WAKEUP=7 176CONFIG_IRQ_PLL_WAKEUP=7
139CONFIG_IRQ_SPORT0_ERROR=7 177CONFIG_IRQ_SPORT0_ERROR=7
140CONFIG_IRQ_SPORT1_ERROR=7 178CONFIG_IRQ_SPORT1_ERROR=7
179CONFIG_IRQ_TIMER0=10
180CONFIG_IRQ_TIMER1=10
181CONFIG_IRQ_TIMER2=10
182CONFIG_IRQ_TIMER3=10
183CONFIG_IRQ_TIMER4=10
184CONFIG_IRQ_TIMER5=10
185CONFIG_IRQ_TIMER6=10
186CONFIG_IRQ_TIMER7=10
141CONFIG_IRQ_SPI_ERROR=7 187CONFIG_IRQ_SPI_ERROR=7
142# CONFIG_BFIN561_EZKIT is not set 188# CONFIG_BFIN561_EZKIT is not set
143# CONFIG_BFIN561_TEPLA is not set 189# CONFIG_BFIN561_TEPLA is not set
144CONFIG_BFIN561_BLUETECHNIX_CM=y 190CONFIG_BFIN561_BLUETECHNIX_CM=y
145# CONFIG_GENERIC_BF561_BOARD is not set
146 191
147# 192#
148# BF561 Specific Configuration 193# BF561 Specific Configuration
@@ -151,12 +196,7 @@ CONFIG_BFIN561_BLUETECHNIX_CM=y
151# 196#
152# Core B Support 197# Core B Support
153# 198#
154
155#
156# Core B Support
157#
158CONFIG_BF561_COREB=y 199CONFIG_BF561_COREB=y
159# CONFIG_BF561_COREB_RESET is not set
160 200
161# 201#
162# Interrupt Priority Assignment 202# Interrupt Priority Assignment
@@ -196,14 +236,6 @@ CONFIG_IRQ_DMA2_8=9
196CONFIG_IRQ_DMA2_9=9 236CONFIG_IRQ_DMA2_9=9
197CONFIG_IRQ_DMA2_10=9 237CONFIG_IRQ_DMA2_10=9
198CONFIG_IRQ_DMA2_11=9 238CONFIG_IRQ_DMA2_11=9
199CONFIG_IRQ_TIMER0=10
200CONFIG_IRQ_TIMER1=10
201CONFIG_IRQ_TIMER2=10
202CONFIG_IRQ_TIMER3=10
203CONFIG_IRQ_TIMER4=10
204CONFIG_IRQ_TIMER5=10
205CONFIG_IRQ_TIMER6=10
206CONFIG_IRQ_TIMER7=10
207CONFIG_IRQ_TIMER8=10 239CONFIG_IRQ_TIMER8=10
208CONFIG_IRQ_TIMER9=10 240CONFIG_IRQ_TIMER9=10
209CONFIG_IRQ_TIMER10=10 241CONFIG_IRQ_TIMER10=10
@@ -226,6 +258,7 @@ CONFIG_IRQ_WDTIMER=13
226# Board customizations 258# Board customizations
227# 259#
228# CONFIG_CMDLINE_BOOL is not set 260# CONFIG_CMDLINE_BOOL is not set
261CONFIG_BOOT_LOAD=0x1000
229 262
230# 263#
231# Clock/PLL Setup 264# Clock/PLL Setup
@@ -245,19 +278,20 @@ CONFIG_HZ_250=y
245# CONFIG_HZ_300 is not set 278# CONFIG_HZ_300 is not set
246# CONFIG_HZ_1000 is not set 279# CONFIG_HZ_1000 is not set
247CONFIG_HZ=250 280CONFIG_HZ=250
281# CONFIG_SCHED_HRTICK is not set
248CONFIG_GENERIC_TIME=y 282CONFIG_GENERIC_TIME=y
249CONFIG_GENERIC_CLOCKEVENTS=y 283CONFIG_GENERIC_CLOCKEVENTS=y
284# CONFIG_TICKSOURCE_GPTMR0 is not set
285CONFIG_TICKSOURCE_CORETMR=y
250# CONFIG_CYCLES_CLOCKSOURCE is not set 286# CONFIG_CYCLES_CLOCKSOURCE is not set
251# CONFIG_TICK_ONESHOT is not set 287# CONFIG_GPTMR0_CLOCKSOURCE is not set
252# CONFIG_NO_HZ is not set 288# CONFIG_NO_HZ is not set
253# CONFIG_HIGH_RES_TIMERS is not set 289# CONFIG_HIGH_RES_TIMERS is not set
254CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 290CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
255 291
256# 292#
257# Memory Setup 293# Misc
258# 294#
259CONFIG_MAX_MEM_SIZE=32
260CONFIG_BOOT_LOAD=0x1000
261CONFIG_BFIN_SCRATCH_REG_RETN=y 295CONFIG_BFIN_SCRATCH_REG_RETN=y
262# CONFIG_BFIN_SCRATCH_REG_RETE is not set 296# CONFIG_BFIN_SCRATCH_REG_RETE is not set
263# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set 297# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -284,6 +318,12 @@ CONFIG_IP_CHECKSUM_L1=y
284CONFIG_CACHELINE_ALIGNED_L1=y 318CONFIG_CACHELINE_ALIGNED_L1=y
285CONFIG_SYSCALL_TAB_L1=y 319CONFIG_SYSCALL_TAB_L1=y
286CONFIG_CPLB_SWITCH_TAB_L1=y 320CONFIG_CPLB_SWITCH_TAB_L1=y
321CONFIG_APP_STACK_L1=y
322
323#
324# Speed Optimizations
325#
326CONFIG_BFIN_INS_LOWOVERHEAD=y
287CONFIG_RAMKERNEL=y 327CONFIG_RAMKERNEL=y
288# CONFIG_ROMKERNEL is not set 328# CONFIG_ROMKERNEL is not set
289CONFIG_SELECT_MEMORY_MODEL=y 329CONFIG_SELECT_MEMORY_MODEL=y
@@ -292,14 +332,16 @@ CONFIG_FLATMEM_MANUAL=y
292# CONFIG_SPARSEMEM_MANUAL is not set 332# CONFIG_SPARSEMEM_MANUAL is not set
293CONFIG_FLATMEM=y 333CONFIG_FLATMEM=y
294CONFIG_FLAT_NODE_MEM_MAP=y 334CONFIG_FLAT_NODE_MEM_MAP=y
295# CONFIG_SPARSEMEM_STATIC is not set 335CONFIG_PAGEFLAGS_EXTENDED=y
296# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
297CONFIG_SPLIT_PTLOCK_CPUS=4 336CONFIG_SPLIT_PTLOCK_CPUS=4
298# CONFIG_RESOURCES_64BIT is not set 337# CONFIG_PHYS_ADDR_T_64BIT is not set
299CONFIG_ZONE_DMA_FLAG=1 338CONFIG_ZONE_DMA_FLAG=1
300CONFIG_VIRT_TO_BUS=y 339CONFIG_VIRT_TO_BUS=y
301CONFIG_LARGE_ALLOCS=y 340CONFIG_UNEVICTABLE_LRU=y
341CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
342CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
302# CONFIG_BFIN_GPTIMERS is not set 343# CONFIG_BFIN_GPTIMERS is not set
344# CONFIG_DMA_UNCACHED_4M is not set
303# CONFIG_DMA_UNCACHED_2M is not set 345# CONFIG_DMA_UNCACHED_2M is not set
304CONFIG_DMA_UNCACHED_1M=y 346CONFIG_DMA_UNCACHED_1M=y
305# CONFIG_DMA_UNCACHED_NONE is not set 347# CONFIG_DMA_UNCACHED_NONE is not set
@@ -308,15 +350,16 @@ CONFIG_DMA_UNCACHED_1M=y
308# Cache Support 350# Cache Support
309# 351#
310CONFIG_BFIN_ICACHE=y 352CONFIG_BFIN_ICACHE=y
311# CONFIG_BFIN_ICACHE_LOCK is not set 353CONFIG_BFIN_EXTMEM_ICACHEABLE=y
354# CONFIG_BFIN_L2_ICACHEABLE is not set
312CONFIG_BFIN_DCACHE=y 355CONFIG_BFIN_DCACHE=y
313# CONFIG_BFIN_DCACHE_BANKA is not set 356# CONFIG_BFIN_DCACHE_BANKA is not set
314CONFIG_BFIN_EXTMEM_ICACHEABLE=y
315CONFIG_BFIN_EXTMEM_DCACHEABLE=y 357CONFIG_BFIN_EXTMEM_DCACHEABLE=y
316CONFIG_BFIN_EXTMEM_WRITEBACK=y 358# CONFIG_BFIN_EXTMEM_WRITEBACK is not set
317# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 359CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
318# CONFIG_BFIN_L2_ICACHEABLE is not set
319# CONFIG_BFIN_L2_DCACHEABLE is not set 360# CONFIG_BFIN_L2_DCACHEABLE is not set
361# CONFIG_BFIN_L2_WRITEBACK is not set
362# CONFIG_BFIN_L2_WRITETHROUGH is not set
320 363
321# 364#
322# Memory Protection Unit 365# Memory Protection Unit
@@ -324,7 +367,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
324# CONFIG_MPU is not set 367# CONFIG_MPU is not set
325 368
326# 369#
327# Asynchonous Memory Configuration 370# Asynchronous Memory Configuration
328# 371#
329 372
330# 373#
@@ -353,8 +396,8 @@ CONFIG_BANK_3=0xFFC2
353# 396#
354# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 397# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
355# 398#
356# CONFIG_PCI is not set
357# CONFIG_ARCH_SUPPORTS_MSI is not set 399# CONFIG_ARCH_SUPPORTS_MSI is not set
400# CONFIG_PCCARD is not set
358 401
359# 402#
360# Executable file formats 403# Executable file formats
@@ -363,18 +406,19 @@ CONFIG_BINFMT_ELF_FDPIC=y
363CONFIG_BINFMT_FLAT=y 406CONFIG_BINFMT_FLAT=y
364CONFIG_BINFMT_ZFLAT=y 407CONFIG_BINFMT_ZFLAT=y
365CONFIG_BINFMT_SHARED_FLAT=y 408CONFIG_BINFMT_SHARED_FLAT=y
409# CONFIG_HAVE_AOUT is not set
366# CONFIG_BINFMT_MISC is not set 410# CONFIG_BINFMT_MISC is not set
367 411
368# 412#
369# Power management options 413# Power management options
370# 414#
371# CONFIG_PM is not set 415# CONFIG_PM is not set
372CONFIG_SUSPEND_UP_POSSIBLE=y 416CONFIG_ARCH_SUSPEND_POSSIBLE=y
373# CONFIG_PM_WAKEUP_BY_GPIO is not set
374 417
375# 418#
376# Networking 419# CPU Frequency scaling
377# 420#
421# CONFIG_CPU_FREQ is not set
378CONFIG_NET=y 422CONFIG_NET=y
379 423
380# 424#
@@ -383,10 +427,6 @@ CONFIG_NET=y
383CONFIG_PACKET=y 427CONFIG_PACKET=y
384# CONFIG_PACKET_MMAP is not set 428# CONFIG_PACKET_MMAP is not set
385CONFIG_UNIX=y 429CONFIG_UNIX=y
386CONFIG_XFRM=y
387# CONFIG_XFRM_USER is not set
388# CONFIG_XFRM_SUB_POLICY is not set
389# CONFIG_XFRM_MIGRATE is not set
390# CONFIG_NET_KEY is not set 430# CONFIG_NET_KEY is not set
391CONFIG_INET=y 431CONFIG_INET=y
392# CONFIG_IP_MULTICAST is not set 432# CONFIG_IP_MULTICAST is not set
@@ -407,14 +447,11 @@ CONFIG_IP_FIB_HASH=y
407# CONFIG_INET_XFRM_MODE_BEET is not set 447# CONFIG_INET_XFRM_MODE_BEET is not set
408# CONFIG_INET_LRO is not set 448# CONFIG_INET_LRO is not set
409# CONFIG_INET_DIAG is not set 449# CONFIG_INET_DIAG is not set
410CONFIG_INET_TCP_DIAG=y
411# CONFIG_TCP_CONG_ADVANCED is not set 450# CONFIG_TCP_CONG_ADVANCED is not set
412CONFIG_TCP_CONG_CUBIC=y 451CONFIG_TCP_CONG_CUBIC=y
413CONFIG_DEFAULT_TCP_CONG="cubic" 452CONFIG_DEFAULT_TCP_CONG="cubic"
414# CONFIG_TCP_MD5SIG is not set 453# CONFIG_TCP_MD5SIG is not set
415# CONFIG_IPV6 is not set 454# CONFIG_IPV6 is not set
416# CONFIG_INET6_XFRM_TUNNEL is not set
417# CONFIG_INET6_TUNNEL is not set
418# CONFIG_NETLABEL is not set 455# CONFIG_NETLABEL is not set
419# CONFIG_NETWORK_SECMARK is not set 456# CONFIG_NETWORK_SECMARK is not set
420# CONFIG_NETFILTER is not set 457# CONFIG_NETFILTER is not set
@@ -423,6 +460,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
423# CONFIG_TIPC is not set 460# CONFIG_TIPC is not set
424# CONFIG_ATM is not set 461# CONFIG_ATM is not set
425# CONFIG_BRIDGE is not set 462# CONFIG_BRIDGE is not set
463# CONFIG_NET_DSA is not set
426# CONFIG_VLAN_8021Q is not set 464# CONFIG_VLAN_8021Q is not set
427# CONFIG_DECNET is not set 465# CONFIG_DECNET is not set
428# CONFIG_LLC2 is not set 466# CONFIG_LLC2 is not set
@@ -432,24 +470,21 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
432# CONFIG_LAPB is not set 470# CONFIG_LAPB is not set
433# CONFIG_ECONET is not set 471# CONFIG_ECONET is not set
434# CONFIG_WAN_ROUTER is not set 472# CONFIG_WAN_ROUTER is not set
473# CONFIG_PHONET is not set
435# CONFIG_NET_SCHED is not set 474# CONFIG_NET_SCHED is not set
475# CONFIG_DCB is not set
436 476
437# 477#
438# Network testing 478# Network testing
439# 479#
440# CONFIG_NET_PKTGEN is not set 480# CONFIG_NET_PKTGEN is not set
441# CONFIG_HAMRADIO is not set 481# CONFIG_HAMRADIO is not set
482# CONFIG_CAN is not set
442# CONFIG_IRDA is not set 483# CONFIG_IRDA is not set
443# CONFIG_BT is not set 484# CONFIG_BT is not set
444# CONFIG_AF_RXRPC is not set 485# CONFIG_AF_RXRPC is not set
445 486# CONFIG_WIRELESS is not set
446# 487# CONFIG_WIMAX is not set
447# Wireless
448#
449# CONFIG_CFG80211 is not set
450# CONFIG_WIRELESS_EXT is not set
451# CONFIG_MAC80211 is not set
452# CONFIG_IEEE80211 is not set
453# CONFIG_RFKILL is not set 488# CONFIG_RFKILL is not set
454# CONFIG_NET_9P is not set 489# CONFIG_NET_9P is not set
455 490
@@ -460,16 +495,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
460# 495#
461# Generic Driver Options 496# Generic Driver Options
462# 497#
498CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
463CONFIG_STANDALONE=y 499CONFIG_STANDALONE=y
464CONFIG_PREVENT_FIRMWARE_BUILD=y 500CONFIG_PREVENT_FIRMWARE_BUILD=y
501CONFIG_FW_LOADER=y
502CONFIG_FIRMWARE_IN_KERNEL=y
503CONFIG_EXTRA_FIRMWARE=""
465# CONFIG_SYS_HYPERVISOR is not set 504# CONFIG_SYS_HYPERVISOR is not set
466# CONFIG_CONNECTOR is not set 505# CONFIG_CONNECTOR is not set
467CONFIG_MTD=y 506CONFIG_MTD=y
468# CONFIG_MTD_DEBUG is not set 507# CONFIG_MTD_DEBUG is not set
508# CONFIG_MTD_TESTS is not set
469# CONFIG_MTD_CONCAT is not set 509# CONFIG_MTD_CONCAT is not set
470CONFIG_MTD_PARTITIONS=y 510CONFIG_MTD_PARTITIONS=y
471# CONFIG_MTD_REDBOOT_PARTS is not set 511# CONFIG_MTD_REDBOOT_PARTS is not set
472# CONFIG_MTD_CMDLINE_PARTS is not set 512CONFIG_MTD_CMDLINE_PARTS=y
513# CONFIG_MTD_AR7_PARTS is not set
473 514
474# 515#
475# User Modules And Translation Layers 516# User Modules And Translation Layers
@@ -487,8 +528,10 @@ CONFIG_MTD_BLOCK=y
487# 528#
488# RAM/ROM/Flash chip drivers 529# RAM/ROM/Flash chip drivers
489# 530#
490# CONFIG_MTD_CFI is not set 531CONFIG_MTD_CFI=y
491# CONFIG_MTD_JEDECPROBE is not set 532# CONFIG_MTD_JEDECPROBE is not set
533CONFIG_MTD_GEN_PROBE=y
534# CONFIG_MTD_CFI_ADV_OPTIONS is not set
492CONFIG_MTD_MAP_BANK_WIDTH_1=y 535CONFIG_MTD_MAP_BANK_WIDTH_1=y
493CONFIG_MTD_MAP_BANK_WIDTH_2=y 536CONFIG_MTD_MAP_BANK_WIDTH_2=y
494CONFIG_MTD_MAP_BANK_WIDTH_4=y 537CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -499,20 +542,29 @@ CONFIG_MTD_CFI_I1=y
499CONFIG_MTD_CFI_I2=y 542CONFIG_MTD_CFI_I2=y
500# CONFIG_MTD_CFI_I4 is not set 543# CONFIG_MTD_CFI_I4 is not set
501# CONFIG_MTD_CFI_I8 is not set 544# CONFIG_MTD_CFI_I8 is not set
545CONFIG_MTD_CFI_INTELEXT=y
546# CONFIG_MTD_CFI_AMDSTD is not set
547# CONFIG_MTD_CFI_STAA is not set
548# CONFIG_MTD_PSD4256G is not set
549CONFIG_MTD_CFI_UTIL=y
502CONFIG_MTD_RAM=y 550CONFIG_MTD_RAM=y
503# CONFIG_MTD_ROM is not set 551CONFIG_MTD_ROM=m
504# CONFIG_MTD_ABSENT is not set 552# CONFIG_MTD_ABSENT is not set
505 553
506# 554#
507# Mapping drivers for chip access 555# Mapping drivers for chip access
508# 556#
509# CONFIG_MTD_COMPLEX_MAPPINGS is not set 557# CONFIG_MTD_COMPLEX_MAPPINGS is not set
510CONFIG_MTD_UCLINUX=y 558CONFIG_MTD_PHYSMAP=y
559# CONFIG_MTD_PHYSMAP_COMPAT is not set
560# CONFIG_MTD_UCLINUX is not set
511# CONFIG_MTD_PLATRAM is not set 561# CONFIG_MTD_PLATRAM is not set
512 562
513# 563#
514# Self-contained MTD device drivers 564# Self-contained MTD device drivers
515# 565#
566# CONFIG_MTD_DATAFLASH is not set
567# CONFIG_MTD_M25P80 is not set
516# CONFIG_MTD_SLRAM is not set 568# CONFIG_MTD_SLRAM is not set
517# CONFIG_MTD_PHRAM is not set 569# CONFIG_MTD_PHRAM is not set
518# CONFIG_MTD_MTDRAM is not set 570# CONFIG_MTD_MTDRAM is not set
@@ -528,6 +580,11 @@ CONFIG_MTD_UCLINUX=y
528# CONFIG_MTD_ONENAND is not set 580# CONFIG_MTD_ONENAND is not set
529 581
530# 582#
583# LPDDR flash memory drivers
584#
585# CONFIG_MTD_LPDDR is not set
586
587#
531# UBI - Unsorted block images 588# UBI - Unsorted block images
532# 589#
533# CONFIG_MTD_UBI is not set 590# CONFIG_MTD_UBI is not set
@@ -539,14 +596,21 @@ CONFIG_BLK_DEV=y
539CONFIG_BLK_DEV_RAM=y 596CONFIG_BLK_DEV_RAM=y
540CONFIG_BLK_DEV_RAM_COUNT=16 597CONFIG_BLK_DEV_RAM_COUNT=16
541CONFIG_BLK_DEV_RAM_SIZE=4096 598CONFIG_BLK_DEV_RAM_SIZE=4096
542CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 599# CONFIG_BLK_DEV_XIP is not set
543# CONFIG_CDROM_PKTCDVD is not set 600# CONFIG_CDROM_PKTCDVD is not set
544# CONFIG_ATA_OVER_ETH is not set 601# CONFIG_ATA_OVER_ETH is not set
602# CONFIG_BLK_DEV_HD is not set
545CONFIG_MISC_DEVICES=y 603CONFIG_MISC_DEVICES=y
604# CONFIG_ENCLOSURE_SERVICES is not set
605# CONFIG_C2PORT is not set
606
607#
608# EEPROM support
609#
610# CONFIG_EEPROM_AT25 is not set
546# CONFIG_EEPROM_93CX6 is not set 611# CONFIG_EEPROM_93CX6 is not set
612CONFIG_HAVE_IDE=y
547# CONFIG_IDE is not set 613# CONFIG_IDE is not set
548# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0 is not set
549# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set
550 614
551# 615#
552# SCSI device support 616# SCSI device support
@@ -558,26 +622,50 @@ CONFIG_MISC_DEVICES=y
558# CONFIG_ATA is not set 622# CONFIG_ATA is not set
559# CONFIG_MD is not set 623# CONFIG_MD is not set
560CONFIG_NETDEVICES=y 624CONFIG_NETDEVICES=y
561# CONFIG_NETDEVICES_MULTIQUEUE is not set 625CONFIG_COMPAT_NET_DEV_OPS=y
562# CONFIG_DUMMY is not set 626# CONFIG_DUMMY is not set
563# CONFIG_BONDING is not set 627# CONFIG_BONDING is not set
564# CONFIG_MACVLAN is not set 628# CONFIG_MACVLAN is not set
565# CONFIG_EQUALIZER is not set 629# CONFIG_EQUALIZER is not set
566# CONFIG_TUN is not set 630# CONFIG_TUN is not set
567# CONFIG_VETH is not set 631# CONFIG_VETH is not set
568# CONFIG_PHYLIB is not set 632CONFIG_PHYLIB=y
633
634#
635# MII PHY device drivers
636#
637# CONFIG_MARVELL_PHY is not set
638# CONFIG_DAVICOM_PHY is not set
639# CONFIG_QSEMI_PHY is not set
640# CONFIG_LXT_PHY is not set
641# CONFIG_CICADA_PHY is not set
642# CONFIG_VITESSE_PHY is not set
643# CONFIG_SMSC_PHY is not set
644# CONFIG_BROADCOM_PHY is not set
645# CONFIG_ICPLUS_PHY is not set
646# CONFIG_REALTEK_PHY is not set
647# CONFIG_NATIONAL_PHY is not set
648# CONFIG_STE10XP is not set
649# CONFIG_LSI_ET1011C_PHY is not set
650# CONFIG_FIXED_PHY is not set
651# CONFIG_MDIO_BITBANG is not set
569CONFIG_NET_ETHERNET=y 652CONFIG_NET_ETHERNET=y
570CONFIG_MII=y 653CONFIG_MII=y
571CONFIG_SMC91X=y 654# CONFIG_SMC91X is not set
572# CONFIG_SMSC911X is not set
573# CONFIG_DM9000 is not set 655# CONFIG_DM9000 is not set
656# CONFIG_ENC28J60 is not set
657# CONFIG_ETHOC is not set
658CONFIG_SMSC911X=m
659# CONFIG_DNET is not set
574# CONFIG_IBM_NEW_EMAC_ZMII is not set 660# CONFIG_IBM_NEW_EMAC_ZMII is not set
575# CONFIG_IBM_NEW_EMAC_RGMII is not set 661# CONFIG_IBM_NEW_EMAC_RGMII is not set
576# CONFIG_IBM_NEW_EMAC_TAH is not set 662# CONFIG_IBM_NEW_EMAC_TAH is not set
577# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 663# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
664# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
665# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
666# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
578# CONFIG_B44 is not set 667# CONFIG_B44 is not set
579# CONFIG_NETDEV_1000 is not set 668# CONFIG_NETDEV_1000 is not set
580# CONFIG_AX88180 is not set
581# CONFIG_NETDEV_10000 is not set 669# CONFIG_NETDEV_10000 is not set
582 670
583# 671#
@@ -585,10 +673,13 @@ CONFIG_SMC91X=y
585# 673#
586# CONFIG_WLAN_PRE80211 is not set 674# CONFIG_WLAN_PRE80211 is not set
587# CONFIG_WLAN_80211 is not set 675# CONFIG_WLAN_80211 is not set
676
677#
678# Enable WiMAX (Networking options) to see the WiMAX drivers
679#
588# CONFIG_WAN is not set 680# CONFIG_WAN is not set
589# CONFIG_PPP is not set 681# CONFIG_PPP is not set
590# CONFIG_SLIP is not set 682# CONFIG_SLIP is not set
591# CONFIG_SHAPER is not set
592# CONFIG_NETCONSOLE is not set 683# CONFIG_NETCONSOLE is not set
593# CONFIG_NETPOLL is not set 684# CONFIG_NETPOLL is not set
594# CONFIG_NET_POLL_CONTROLLER is not set 685# CONFIG_NET_POLL_CONTROLLER is not set
@@ -609,16 +700,15 @@ CONFIG_SMC91X=y
609# 700#
610# Character devices 701# Character devices
611# 702#
612# CONFIG_AD9960 is not set 703CONFIG_BFIN_DMA_INTERFACE=m
613# CONFIG_SPI_ADC_BF533 is not set 704# CONFIG_BFIN_PPI is not set
614# CONFIG_BF5xx_PPIFCD is not set 705# CONFIG_BFIN_PPIFCD is not set
615# CONFIG_BFIN_SIMPLE_TIMER is not set 706# CONFIG_BFIN_SIMPLE_TIMER is not set
616# CONFIG_BF5xx_PPI is not set 707# CONFIG_BFIN_SPI_ADC is not set
617# CONFIG_BFIN_SPORT is not set 708# CONFIG_BFIN_SPORT is not set
618# CONFIG_BFIN_TIMER_LATENCY is not set
619# CONFIG_SIMPLE_GPIO is not set
620# CONFIG_VT is not set 709# CONFIG_VT is not set
621# CONFIG_DEVKMEM is not set 710# CONFIG_DEVKMEM is not set
711# CONFIG_BFIN_JTAG_COMM is not set
622# CONFIG_SERIAL_NONSTANDARD is not set 712# CONFIG_SERIAL_NONSTANDARD is not set
623 713
624# 714#
@@ -629,6 +719,7 @@ CONFIG_SMC91X=y
629# 719#
630# Non-8250 serial port support 720# Non-8250 serial port support
631# 721#
722# CONFIG_SERIAL_MAX3100 is not set
632CONFIG_SERIAL_BFIN=y 723CONFIG_SERIAL_BFIN=y
633CONFIG_SERIAL_BFIN_CONSOLE=y 724CONFIG_SERIAL_BFIN_CONSOLE=y
634CONFIG_SERIAL_BFIN_DMA=y 725CONFIG_SERIAL_BFIN_DMA=y
@@ -639,6 +730,7 @@ CONFIG_SERIAL_CORE=y
639CONFIG_SERIAL_CORE_CONSOLE=y 730CONFIG_SERIAL_CORE_CONSOLE=y
640# CONFIG_SERIAL_BFIN_SPORT is not set 731# CONFIG_SERIAL_BFIN_SPORT is not set
641CONFIG_UNIX98_PTYS=y 732CONFIG_UNIX98_PTYS=y
733# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
642# CONFIG_LEGACY_PTYS is not set 734# CONFIG_LEGACY_PTYS is not set
643 735
644# 736#
@@ -647,54 +739,100 @@ CONFIG_UNIX98_PTYS=y
647# CONFIG_CAN4LINUX is not set 739# CONFIG_CAN4LINUX is not set
648# CONFIG_IPMI_HANDLER is not set 740# CONFIG_IPMI_HANDLER is not set
649# CONFIG_HW_RANDOM is not set 741# CONFIG_HW_RANDOM is not set
650# CONFIG_GEN_RTC is not set
651# CONFIG_R3964 is not set 742# CONFIG_R3964 is not set
652# CONFIG_RAW_DRIVER is not set 743# CONFIG_RAW_DRIVER is not set
653# CONFIG_TCG_TPM is not set 744# CONFIG_TCG_TPM is not set
654# CONFIG_I2C is not set 745# CONFIG_I2C is not set
746CONFIG_SPI=y
747CONFIG_SPI_MASTER=y
748
749#
750# SPI Master Controller Drivers
751#
752CONFIG_SPI_BFIN=y
753# CONFIG_SPI_BFIN_LOCK is not set
754# CONFIG_SPI_BFIN_SPORT is not set
755# CONFIG_SPI_BITBANG is not set
756# CONFIG_SPI_GPIO is not set
655 757
758#
759# SPI Protocol Masters
760#
761# CONFIG_SPI_SPIDEV is not set
762# CONFIG_SPI_TLE62X0 is not set
656CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 763CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
657CONFIG_GPIOLIB=y 764CONFIG_GPIOLIB=y
658CONFIG_GPIO_SYSFS=y 765CONFIG_GPIO_SYSFS=y
659 766
660# 767#
661# SPI support 768# Memory mapped GPIO expanders:
769#
770
771#
772# I2C GPIO expanders:
773#
774
662# 775#
663# CONFIG_SPI is not set 776# PCI GPIO expanders:
664# CONFIG_SPI_MASTER is not set 777#
778
779#
780# SPI GPIO expanders:
781#
782# CONFIG_GPIO_MAX7301 is not set
783# CONFIG_GPIO_MCP23S08 is not set
665# CONFIG_W1 is not set 784# CONFIG_W1 is not set
666# CONFIG_POWER_SUPPLY is not set 785# CONFIG_POWER_SUPPLY is not set
667CONFIG_HWMON=y 786CONFIG_HWMON=y
668# CONFIG_HWMON_VID is not set 787# CONFIG_HWMON_VID is not set
788# CONFIG_SENSORS_ADCXX is not set
669# CONFIG_SENSORS_F71805F is not set 789# CONFIG_SENSORS_F71805F is not set
670# CONFIG_SENSORS_F71882FG is not set 790# CONFIG_SENSORS_F71882FG is not set
671# CONFIG_SENSORS_IT87 is not set 791# CONFIG_SENSORS_IT87 is not set
792# CONFIG_SENSORS_LM70 is not set
793# CONFIG_SENSORS_MAX1111 is not set
672# CONFIG_SENSORS_PC87360 is not set 794# CONFIG_SENSORS_PC87360 is not set
673# CONFIG_SENSORS_PC87427 is not set 795# CONFIG_SENSORS_PC87427 is not set
796# CONFIG_SENSORS_SHT15 is not set
674# CONFIG_SENSORS_SMSC47M1 is not set 797# CONFIG_SENSORS_SMSC47M1 is not set
675# CONFIG_SENSORS_SMSC47B397 is not set 798# CONFIG_SENSORS_SMSC47B397 is not set
676# CONFIG_SENSORS_VT1211 is not set 799# CONFIG_SENSORS_VT1211 is not set
677# CONFIG_SENSORS_W83627HF is not set 800# CONFIG_SENSORS_W83627HF is not set
678# CONFIG_SENSORS_W83627EHF is not set 801# CONFIG_SENSORS_W83627EHF is not set
679# CONFIG_HWMON_DEBUG_CHIP is not set 802# CONFIG_HWMON_DEBUG_CHIP is not set
803# CONFIG_THERMAL is not set
804# CONFIG_THERMAL_HWMON is not set
680# CONFIG_WATCHDOG is not set 805# CONFIG_WATCHDOG is not set
806CONFIG_SSB_POSSIBLE=y
681 807
682# 808#
683# Sonics Silicon Backplane 809# Sonics Silicon Backplane
684# 810#
685CONFIG_SSB_POSSIBLE=y
686# CONFIG_SSB is not set 811# CONFIG_SSB is not set
687 812
688# 813#
689# Multifunction device drivers 814# Multifunction device drivers
690# 815#
816# CONFIG_MFD_CORE is not set
691# CONFIG_MFD_SM501 is not set 817# CONFIG_MFD_SM501 is not set
818# CONFIG_HTC_PASIC3 is not set
819# CONFIG_MFD_TMIO is not set
820# CONFIG_REGULATOR is not set
692 821
693# 822#
694# Multimedia devices 823# Multimedia devices
695# 824#
825
826#
827# Multimedia core support
828#
696# CONFIG_VIDEO_DEV is not set 829# CONFIG_VIDEO_DEV is not set
697# CONFIG_DVB_CORE is not set 830# CONFIG_DVB_CORE is not set
831# CONFIG_VIDEO_MEDIA is not set
832
833#
834# Multimedia drivers
835#
698# CONFIG_DAB is not set 836# CONFIG_DAB is not set
699 837
700# 838#
@@ -709,42 +847,85 @@ CONFIG_SSB_POSSIBLE=y
709# Display device support 847# Display device support
710# 848#
711# CONFIG_DISPLAY_SUPPORT is not set 849# CONFIG_DISPLAY_SUPPORT is not set
712
713#
714# Sound
715#
716# CONFIG_SOUND is not set 850# CONFIG_SOUND is not set
717CONFIG_USB_SUPPORT=y 851CONFIG_USB_SUPPORT=y
718CONFIG_USB_ARCH_HAS_HCD=y 852CONFIG_USB_ARCH_HAS_HCD=y
719# CONFIG_USB_ARCH_HAS_OHCI is not set 853# CONFIG_USB_ARCH_HAS_OHCI is not set
720# CONFIG_USB_ARCH_HAS_EHCI is not set 854# CONFIG_USB_ARCH_HAS_EHCI is not set
721# CONFIG_USB is not set 855# CONFIG_USB is not set
722 856# CONFIG_USB_OTG_WHITELIST is not set
723# 857# CONFIG_USB_OTG_BLACKLIST_HUB is not set
724# Enable Host or Gadget support to see Inventra options 858# CONFIG_USB_GADGET_MUSB_HDRC is not set
725# 859
726 860#
727# 861# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
728# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 862#
729# 863CONFIG_USB_GADGET=m
730 864# CONFIG_USB_GADGET_DEBUG_FILES is not set
731# 865# CONFIG_USB_GADGET_DEBUG_FS is not set
732# USB Gadget Support 866CONFIG_USB_GADGET_VBUS_DRAW=2
733# 867CONFIG_USB_GADGET_SELECTED=y
734# CONFIG_USB_GADGET is not set 868# CONFIG_USB_GADGET_AT91 is not set
735# CONFIG_MMC is not set 869# CONFIG_USB_GADGET_ATMEL_USBA is not set
870# CONFIG_USB_GADGET_FSL_USB2 is not set
871# CONFIG_USB_GADGET_LH7A40X is not set
872# CONFIG_USB_GADGET_OMAP is not set
873# CONFIG_USB_GADGET_PXA25X is not set
874# CONFIG_USB_GADGET_PXA27X is not set
875# CONFIG_USB_GADGET_S3C2410 is not set
876# CONFIG_USB_GADGET_IMX is not set
877# CONFIG_USB_GADGET_M66592 is not set
878# CONFIG_USB_GADGET_AMD5536UDC is not set
879# CONFIG_USB_GADGET_FSL_QE is not set
880# CONFIG_USB_GADGET_CI13XXX is not set
881CONFIG_USB_GADGET_NET2272=y
882CONFIG_USB_NET2272=m
883# CONFIG_USB_GADGET_NET2280 is not set
884# CONFIG_USB_GADGET_GOKU is not set
885# CONFIG_USB_GADGET_DUMMY_HCD is not set
886CONFIG_USB_GADGET_DUALSPEED=y
887# CONFIG_USB_ZERO is not set
888# CONFIG_USB_AUDIO is not set
889CONFIG_USB_ETH=m
890CONFIG_USB_ETH_RNDIS=y
891# CONFIG_USB_GADGETFS is not set
892CONFIG_USB_FILE_STORAGE=m
893# CONFIG_USB_FILE_STORAGE_TEST is not set
894CONFIG_USB_G_SERIAL=m
895# CONFIG_USB_MIDI_GADGET is not set
896CONFIG_USB_G_PRINTER=m
897# CONFIG_USB_CDC_COMPOSITE is not set
898
899#
900# OTG and related infrastructure
901#
902# CONFIG_USB_GPIO_VBUS is not set
903# CONFIG_NOP_USB_XCEIV is not set
904CONFIG_MMC=y
905# CONFIG_MMC_DEBUG is not set
906# CONFIG_MMC_UNSAFE_RESUME is not set
907
908#
909# MMC/SD/SDIO Card Drivers
910#
911CONFIG_MMC_BLOCK=y
912CONFIG_MMC_BLOCK_BOUNCE=y
913# CONFIG_SDIO_UART is not set
914# CONFIG_MMC_TEST is not set
915
916#
917# MMC/SD/SDIO Host Controller Drivers
918#
919# CONFIG_MMC_SDHCI is not set
920CONFIG_MMC_SPI=m
921# CONFIG_MEMSTICK is not set
736# CONFIG_NEW_LEDS is not set 922# CONFIG_NEW_LEDS is not set
923# CONFIG_ACCESSIBILITY is not set
737# CONFIG_RTC_CLASS is not set 924# CONFIG_RTC_CLASS is not set
738 925# CONFIG_DMADEVICES is not set
739# 926# CONFIG_AUXDISPLAY is not set
740# Userspace I/O
741#
742# CONFIG_UIO is not set 927# CONFIG_UIO is not set
743 928# CONFIG_STAGING is not set
744#
745# PBX support
746#
747# CONFIG_PBX is not set
748 929
749# 930#
750# File systems 931# File systems
@@ -754,25 +935,29 @@ CONFIG_EXT2_FS_XATTR=y
754# CONFIG_EXT2_FS_POSIX_ACL is not set 935# CONFIG_EXT2_FS_POSIX_ACL is not set
755# CONFIG_EXT2_FS_SECURITY is not set 936# CONFIG_EXT2_FS_SECURITY is not set
756# CONFIG_EXT3_FS is not set 937# CONFIG_EXT3_FS is not set
757# CONFIG_EXT4DEV_FS is not set 938# CONFIG_EXT4_FS is not set
758CONFIG_FS_MBCACHE=y 939CONFIG_FS_MBCACHE=y
759# CONFIG_REISERFS_FS is not set 940# CONFIG_REISERFS_FS is not set
760# CONFIG_JFS_FS is not set 941# CONFIG_JFS_FS is not set
761# CONFIG_FS_POSIX_ACL is not set 942# CONFIG_FS_POSIX_ACL is not set
762# CONFIG_XFS_FS is not set 943# CONFIG_XFS_FS is not set
763# CONFIG_GFS2_FS is not set
764# CONFIG_OCFS2_FS is not set 944# CONFIG_OCFS2_FS is not set
765# CONFIG_MINIX_FS is not set 945# CONFIG_BTRFS_FS is not set
766# CONFIG_ROMFS_FS is not set 946CONFIG_FILE_LOCKING=y
947# CONFIG_DNOTIFY is not set
767CONFIG_INOTIFY=y 948CONFIG_INOTIFY=y
768CONFIG_INOTIFY_USER=y 949CONFIG_INOTIFY_USER=y
769# CONFIG_QUOTA is not set 950# CONFIG_QUOTA is not set
770# CONFIG_DNOTIFY is not set
771# CONFIG_AUTOFS_FS is not set 951# CONFIG_AUTOFS_FS is not set
772# CONFIG_AUTOFS4_FS is not set 952# CONFIG_AUTOFS4_FS is not set
773# CONFIG_FUSE_FS is not set 953# CONFIG_FUSE_FS is not set
774 954
775# 955#
956# Caches
957#
958# CONFIG_FSCACHE is not set
959
960#
776# CD-ROM/DVD Filesystems 961# CD-ROM/DVD Filesystems
777# 962#
778# CONFIG_ISO9660_FS is not set 963# CONFIG_ISO9660_FS is not set
@@ -781,8 +966,11 @@ CONFIG_INOTIFY_USER=y
781# 966#
782# DOS/FAT/NT Filesystems 967# DOS/FAT/NT Filesystems
783# 968#
784# CONFIG_MSDOS_FS is not set 969CONFIG_FAT_FS=y
785# CONFIG_VFAT_FS is not set 970CONFIG_MSDOS_FS=y
971CONFIG_VFAT_FS=y
972CONFIG_FAT_DEFAULT_CODEPAGE=437
973CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
786# CONFIG_NTFS_FS is not set 974# CONFIG_NTFS_FS is not set
787 975
788# 976#
@@ -794,10 +982,7 @@ CONFIG_SYSFS=y
794# CONFIG_TMPFS is not set 982# CONFIG_TMPFS is not set
795# CONFIG_HUGETLB_PAGE is not set 983# CONFIG_HUGETLB_PAGE is not set
796# CONFIG_CONFIGFS_FS is not set 984# CONFIG_CONFIGFS_FS is not set
797 985CONFIG_MISC_FILESYSTEMS=y
798#
799# Miscellaneous filesystems
800#
801# CONFIG_ADFS_FS is not set 986# CONFIG_ADFS_FS is not set
802# CONFIG_AFFS_FS is not set 987# CONFIG_AFFS_FS is not set
803# CONFIG_HFS_FS is not set 988# CONFIG_HFS_FS is not set
@@ -805,14 +990,28 @@ CONFIG_SYSFS=y
805# CONFIG_BEFS_FS is not set 990# CONFIG_BEFS_FS is not set
806# CONFIG_BFS_FS is not set 991# CONFIG_BFS_FS is not set
807# CONFIG_EFS_FS is not set 992# CONFIG_EFS_FS is not set
808# CONFIG_YAFFS_FS is not set 993CONFIG_JFFS2_FS=y
809# CONFIG_JFFS2_FS is not set 994CONFIG_JFFS2_FS_DEBUG=0
995CONFIG_JFFS2_FS_WRITEBUFFER=y
996# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
997# CONFIG_JFFS2_SUMMARY is not set
998# CONFIG_JFFS2_FS_XATTR is not set
999# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1000CONFIG_JFFS2_ZLIB=y
1001# CONFIG_JFFS2_LZO is not set
1002CONFIG_JFFS2_RTIME=y
1003# CONFIG_JFFS2_RUBIN is not set
810# CONFIG_CRAMFS is not set 1004# CONFIG_CRAMFS is not set
1005# CONFIG_SQUASHFS is not set
811# CONFIG_VXFS_FS is not set 1006# CONFIG_VXFS_FS is not set
1007# CONFIG_MINIX_FS is not set
1008# CONFIG_OMFS_FS is not set
812# CONFIG_HPFS_FS is not set 1009# CONFIG_HPFS_FS is not set
813# CONFIG_QNX4FS_FS is not set 1010# CONFIG_QNX4FS_FS is not set
1011# CONFIG_ROMFS_FS is not set
814# CONFIG_SYSV_FS is not set 1012# CONFIG_SYSV_FS is not set
815# CONFIG_UFS_FS is not set 1013# CONFIG_UFS_FS is not set
1014# CONFIG_NILFS2_FS is not set
816CONFIG_NETWORK_FILESYSTEMS=y 1015CONFIG_NETWORK_FILESYSTEMS=y
817# CONFIG_NFS_FS is not set 1016# CONFIG_NFS_FS is not set
818# CONFIG_NFSD is not set 1017# CONFIG_NFSD is not set
@@ -827,11 +1026,47 @@ CONFIG_NETWORK_FILESYSTEMS=y
827# 1026#
828# CONFIG_PARTITION_ADVANCED is not set 1027# CONFIG_PARTITION_ADVANCED is not set
829CONFIG_MSDOS_PARTITION=y 1028CONFIG_MSDOS_PARTITION=y
830# CONFIG_NLS is not set 1029CONFIG_NLS=y
1030CONFIG_NLS_DEFAULT="iso8859-1"
1031CONFIG_NLS_CODEPAGE_437=y
1032# CONFIG_NLS_CODEPAGE_737 is not set
1033# CONFIG_NLS_CODEPAGE_775 is not set
1034# CONFIG_NLS_CODEPAGE_850 is not set
1035# CONFIG_NLS_CODEPAGE_852 is not set
1036# CONFIG_NLS_CODEPAGE_855 is not set
1037# CONFIG_NLS_CODEPAGE_857 is not set
1038# CONFIG_NLS_CODEPAGE_860 is not set
1039# CONFIG_NLS_CODEPAGE_861 is not set
1040# CONFIG_NLS_CODEPAGE_862 is not set
1041# CONFIG_NLS_CODEPAGE_863 is not set
1042# CONFIG_NLS_CODEPAGE_864 is not set
1043# CONFIG_NLS_CODEPAGE_865 is not set
1044# CONFIG_NLS_CODEPAGE_866 is not set
1045# CONFIG_NLS_CODEPAGE_869 is not set
1046# CONFIG_NLS_CODEPAGE_936 is not set
1047# CONFIG_NLS_CODEPAGE_950 is not set
1048# CONFIG_NLS_CODEPAGE_932 is not set
1049# CONFIG_NLS_CODEPAGE_949 is not set
1050# CONFIG_NLS_CODEPAGE_874 is not set
1051# CONFIG_NLS_ISO8859_8 is not set
1052# CONFIG_NLS_CODEPAGE_1250 is not set
1053# CONFIG_NLS_CODEPAGE_1251 is not set
1054# CONFIG_NLS_ASCII is not set
1055CONFIG_NLS_ISO8859_1=y
1056# CONFIG_NLS_ISO8859_2 is not set
1057# CONFIG_NLS_ISO8859_3 is not set
1058# CONFIG_NLS_ISO8859_4 is not set
1059# CONFIG_NLS_ISO8859_5 is not set
1060# CONFIG_NLS_ISO8859_6 is not set
1061# CONFIG_NLS_ISO8859_7 is not set
1062# CONFIG_NLS_ISO8859_9 is not set
1063# CONFIG_NLS_ISO8859_13 is not set
1064# CONFIG_NLS_ISO8859_14 is not set
1065# CONFIG_NLS_ISO8859_15 is not set
1066# CONFIG_NLS_KOI8_R is not set
1067# CONFIG_NLS_KOI8_U is not set
1068# CONFIG_NLS_UTF8 is not set
831# CONFIG_DLM is not set 1069# CONFIG_DLM is not set
832CONFIG_INSTRUMENTATION=y
833# CONFIG_PROFILING is not set
834# CONFIG_MARKERS is not set
835 1070
836# 1071#
837# Kernel hacking 1072# Kernel hacking
@@ -839,14 +1074,40 @@ CONFIG_INSTRUMENTATION=y
839# CONFIG_PRINTK_TIME is not set 1074# CONFIG_PRINTK_TIME is not set
840CONFIG_ENABLE_WARN_DEPRECATED=y 1075CONFIG_ENABLE_WARN_DEPRECATED=y
841CONFIG_ENABLE_MUST_CHECK=y 1076CONFIG_ENABLE_MUST_CHECK=y
1077CONFIG_FRAME_WARN=1024
842# CONFIG_MAGIC_SYSRQ is not set 1078# CONFIG_MAGIC_SYSRQ is not set
843# CONFIG_UNUSED_SYMBOLS is not set 1079# CONFIG_UNUSED_SYMBOLS is not set
844CONFIG_DEBUG_FS=y 1080CONFIG_DEBUG_FS=y
845# CONFIG_HEADERS_CHECK is not set 1081# CONFIG_HEADERS_CHECK is not set
1082CONFIG_DEBUG_SECTION_MISMATCH=y
846# CONFIG_DEBUG_KERNEL is not set 1083# CONFIG_DEBUG_KERNEL is not set
847CONFIG_DEBUG_BUGVERBOSE=y 1084# CONFIG_DEBUG_BUGVERBOSE is not set
1085# CONFIG_DEBUG_MEMORY_INIT is not set
1086# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1087CONFIG_HAVE_FUNCTION_TRACER=y
1088CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1089CONFIG_TRACING_SUPPORT=y
1090
1091#
1092# Tracers
1093#
1094# CONFIG_FUNCTION_TRACER is not set
1095# CONFIG_IRQSOFF_TRACER is not set
1096# CONFIG_SCHED_TRACER is not set
1097# CONFIG_CONTEXT_SWITCH_TRACER is not set
1098# CONFIG_EVENT_TRACER is not set
1099# CONFIG_BOOT_TRACER is not set
1100# CONFIG_TRACE_BRANCH_PROFILING is not set
1101# CONFIG_STACK_TRACER is not set
1102# CONFIG_KMEMTRACE is not set
1103# CONFIG_WORKQUEUE_TRACER is not set
1104# CONFIG_BLK_DEV_IO_TRACE is not set
1105# CONFIG_DYNAMIC_DEBUG is not set
848# CONFIG_SAMPLES is not set 1106# CONFIG_SAMPLES is not set
1107CONFIG_HAVE_ARCH_KGDB=y
1108CONFIG_DEBUG_VERBOSE=y
849CONFIG_DEBUG_MMRS=y 1109CONFIG_DEBUG_MMRS=y
1110# CONFIG_DEBUG_DOUBLEFAULT is not set
850CONFIG_DEBUG_HUNT_FOR_ZERO=y 1111CONFIG_DEBUG_HUNT_FOR_ZERO=y
851CONFIG_DEBUG_BFIN_HWTRACE_ON=y 1112CONFIG_DEBUG_BFIN_HWTRACE_ON=y
852CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y 1113CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -855,33 +1116,40 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
855CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1116CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
856# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1117# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
857# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1118# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
858# CONFIG_EARLY_PRINTK is not set 1119CONFIG_EARLY_PRINTK=y
859# CONFIG_DUAL_CORE_TEST_MODULE is not set
860CONFIG_CPLB_INFO=y 1120CONFIG_CPLB_INFO=y
861CONFIG_ACCESS_CHECK=y 1121CONFIG_ACCESS_CHECK=y
1122# CONFIG_BFIN_ISRAM_SELF_TEST is not set
862 1123
863# 1124#
864# Security options 1125# Security options
865# 1126#
866# CONFIG_KEYS is not set 1127# CONFIG_KEYS is not set
867CONFIG_SECURITY=y 1128CONFIG_SECURITY=y
1129# CONFIG_SECURITYFS is not set
868# CONFIG_SECURITY_NETWORK is not set 1130# CONFIG_SECURITY_NETWORK is not set
869CONFIG_SECURITY_CAPABILITIES=y 1131# CONFIG_SECURITY_PATH is not set
870# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1132# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1133# CONFIG_SECURITY_TOMOYO is not set
871# CONFIG_CRYPTO is not set 1134# CONFIG_CRYPTO is not set
1135# CONFIG_BINARY_PRINTF is not set
872 1136
873# 1137#
874# Library routines 1138# Library routines
875# 1139#
876CONFIG_BITREVERSE=y 1140CONFIG_BITREVERSE=y
1141CONFIG_GENERIC_FIND_LAST_BIT=y
877CONFIG_CRC_CCITT=m 1142CONFIG_CRC_CCITT=m
878# CONFIG_CRC16 is not set 1143# CONFIG_CRC16 is not set
879# CONFIG_CRC_ITU_T is not set 1144# CONFIG_CRC_T10DIF is not set
1145CONFIG_CRC_ITU_T=y
880CONFIG_CRC32=y 1146CONFIG_CRC32=y
881# CONFIG_CRC7 is not set 1147CONFIG_CRC7=y
882# CONFIG_LIBCRC32C is not set 1148# CONFIG_LIBCRC32C is not set
883CONFIG_ZLIB_INFLATE=y 1149CONFIG_ZLIB_INFLATE=y
884CONFIG_PLIST=y 1150CONFIG_ZLIB_DEFLATE=y
1151CONFIG_DECOMPRESS_LZMA=y
885CONFIG_HAS_IOMEM=y 1152CONFIG_HAS_IOMEM=y
886CONFIG_HAS_IOPORT=y 1153CONFIG_HAS_IOPORT=y
887CONFIG_HAS_DMA=y 1154CONFIG_HAS_DMA=y
1155CONFIG_NLATTR=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index a6a7c8ede705..bc7fae3d8b83 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -67,6 +67,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
67CONFIG_SLAB=y 67CONFIG_SLAB=y
68# CONFIG_SLUB is not set 68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set 69# CONFIG_SLOB is not set
70CONFIG_MMAP_ALLOW_UNINITIALIZED=y
70CONFIG_RT_MUTEXES=y 71CONFIG_RT_MUTEXES=y
71CONFIG_TINY_SHMEM=y 72CONFIG_TINY_SHMEM=y
72CONFIG_BASE_SMALL=0 73CONFIG_BASE_SMALL=0
@@ -249,6 +250,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
249# CONFIG_RESOURCES_64BIT is not set 250# CONFIG_RESOURCES_64BIT is not set
250CONFIG_ZONE_DMA_FLAG=1 251CONFIG_ZONE_DMA_FLAG=1
251CONFIG_LARGE_ALLOCS=y 252CONFIG_LARGE_ALLOCS=y
253CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
252CONFIG_BFIN_GPTIMERS=y 254CONFIG_BFIN_GPTIMERS=y
253# CONFIG_DMA_UNCACHED_2M is not set 255# CONFIG_DMA_UNCACHED_2M is not set
254CONFIG_DMA_UNCACHED_1M=y 256CONFIG_DMA_UNCACHED_1M=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index 1ec9ae2e964b..a7e49d631229 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -68,6 +68,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
68CONFIG_SLAB=y 68CONFIG_SLAB=y
69# CONFIG_SLUB is not set 69# CONFIG_SLUB is not set
70# CONFIG_SLOB is not set 70# CONFIG_SLOB is not set
71CONFIG_MMAP_ALLOW_UNINITIALIZED=y
71CONFIG_RT_MUTEXES=y 72CONFIG_RT_MUTEXES=y
72CONFIG_TINY_SHMEM=y 73CONFIG_TINY_SHMEM=y
73CONFIG_BASE_SMALL=0 74CONFIG_BASE_SMALL=0
@@ -261,6 +262,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
261# CONFIG_RESOURCES_64BIT is not set 262# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1 263CONFIG_ZONE_DMA_FLAG=1
263CONFIG_LARGE_ALLOCS=y 264CONFIG_LARGE_ALLOCS=y
265CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
264# CONFIG_BFIN_GPTIMERS is not set 266# CONFIG_BFIN_GPTIMERS is not set
265# CONFIG_DMA_UNCACHED_2M is not set 267# CONFIG_DMA_UNCACHED_2M is not set
266CONFIG_DMA_UNCACHED_1M=y 268CONFIG_DMA_UNCACHED_1M=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index ff377fae061b..67d12768602a 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -63,6 +63,7 @@ CONFIG_COMPAT_BRK=y
63CONFIG_SLAB=y 63CONFIG_SLAB=y
64# CONFIG_SLUB is not set 64# CONFIG_SLUB is not set
65# CONFIG_SLOB is not set 65# CONFIG_SLOB is not set
66CONFIG_MMAP_ALLOW_UNINITIALIZED=y
66# CONFIG_PROFILING is not set 67# CONFIG_PROFILING is not set
67# CONFIG_MARKERS is not set 68# CONFIG_MARKERS is not set
68CONFIG_HAVE_OPROFILE=y 69CONFIG_HAVE_OPROFILE=y
@@ -285,6 +286,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
285# CONFIG_PHYS_ADDR_T_64BIT is not set 286# CONFIG_PHYS_ADDR_T_64BIT is not set
286CONFIG_ZONE_DMA_FLAG=1 287CONFIG_ZONE_DMA_FLAG=1
287CONFIG_VIRT_TO_BUS=y 288CONFIG_VIRT_TO_BUS=y
289CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
288CONFIG_BFIN_GPTIMERS=y 290CONFIG_BFIN_GPTIMERS=y
289# CONFIG_DMA_UNCACHED_4M is not set 291# CONFIG_DMA_UNCACHED_4M is not set
290# CONFIG_DMA_UNCACHED_2M is not set 292# CONFIG_DMA_UNCACHED_2M is not set
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index 814f9cacf407..52bfa6bf18da 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -72,6 +72,7 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
72CONFIG_SLAB=y 72CONFIG_SLAB=y
73# CONFIG_SLUB is not set 73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set 74# CONFIG_SLOB is not set
75CONFIG_MMAP_ALLOW_UNINITIALIZED=y
75CONFIG_RT_MUTEXES=y 76CONFIG_RT_MUTEXES=y
76CONFIG_TINY_SHMEM=y 77CONFIG_TINY_SHMEM=y
77CONFIG_BASE_SMALL=0 78CONFIG_BASE_SMALL=0
@@ -271,6 +272,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
271# CONFIG_RESOURCES_64BIT is not set 272# CONFIG_RESOURCES_64BIT is not set
272CONFIG_ZONE_DMA_FLAG=1 273CONFIG_ZONE_DMA_FLAG=1
273CONFIG_LARGE_ALLOCS=y 274CONFIG_LARGE_ALLOCS=y
275CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
274CONFIG_DMA_UNCACHED_2M=y 276CONFIG_DMA_UNCACHED_2M=y
275# CONFIG_DMA_UNCACHED_1M is not set 277# CONFIG_DMA_UNCACHED_1M is not set
276# CONFIG_DMA_UNCACHED_NONE is not set 278# CONFIG_DMA_UNCACHED_NONE is not set
@@ -700,7 +702,7 @@ CONFIG_INPUT_MISC=y
700# CONFIG_INPUT_YEALINK is not set 702# CONFIG_INPUT_YEALINK is not set
701CONFIG_INPUT_UINPUT=y 703CONFIG_INPUT_UINPUT=y
702# CONFIG_BF53X_PFBUTTONS is not set 704# CONFIG_BF53X_PFBUTTONS is not set
703# CONFIG_TWI_KEYPAD is not set 705# CONFIG_INPUT_PCF8574 is not set
704 706
705# 707#
706# Hardware I/O ports 708# Hardware I/O ports
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 375e75a27abc..60adfad54db9 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -1,13 +1,13 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2 3# Linux kernel version: 2.6.30.5
4# Tue Jan 6 09:22:17 2009
5# 4#
6# CONFIG_MMU is not set 5# CONFIG_MMU is not set
7# CONFIG_FPU is not set 6# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 7CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set 8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y 9CONFIG_BLACKFIN=y
10CONFIG_GENERIC_BUG=y
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y 12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
@@ -16,6 +16,9 @@ CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y 16CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14 17CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y 18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_LOCKDEP_SUPPORT=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_TRACE_IRQFLAGS_SUPPORT=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20 23
21# 24#
@@ -26,49 +29,72 @@ CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32 29CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION="" 30CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y 31CONFIG_LOCALVERSION_AUTO=y
32CONFIG_HAVE_KERNEL_GZIP=y
33CONFIG_HAVE_KERNEL_BZIP2=y
34CONFIG_HAVE_KERNEL_LZMA=y
35# CONFIG_KERNEL_GZIP is not set
36# CONFIG_KERNEL_BZIP2 is not set
37CONFIG_KERNEL_LZMA=y
29CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
31# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
32CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
33CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
34CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
35# CONFIG_CGROUPS is not set
36# CONFIG_GROUP_SCHED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
37# CONFIG_SYSFS_DEPRECATED_V2 is not set 58# CONFIG_SYSFS_DEPRECATED_V2 is not set
38# CONFIG_RELAY is not set 59# CONFIG_RELAY is not set
39# CONFIG_NAMESPACES is not set 60# CONFIG_NAMESPACES is not set
40# CONFIG_BLK_DEV_INITRD is not set 61CONFIG_BLK_DEV_INITRD=y
62CONFIG_INITRAMFS_SOURCE=""
63# CONFIG_RD_GZIP is not set
64# CONFIG_RD_BZIP2 is not set
65CONFIG_RD_LZMA=y
41# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
42# CONFIG_SYSCTL is not set 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y
43CONFIG_EMBEDDED=y 69CONFIG_EMBEDDED=y
44# CONFIG_UID16 is not set 70# CONFIG_UID16 is not set
45# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
46CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
47# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
48# CONFIG_HOTPLUG is not set 74# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y
49CONFIG_PRINTK=y 76CONFIG_PRINTK=y
50CONFIG_BUG=y 77CONFIG_BUG=y
51# CONFIG_ELF_CORE is not set 78# CONFIG_ELF_CORE is not set
52CONFIG_COMPAT_BRK=y
53CONFIG_BASE_FULL=y 79CONFIG_BASE_FULL=y
54# CONFIG_FUTEX is not set 80# CONFIG_FUTEX is not set
55CONFIG_ANON_INODES=y
56CONFIG_EPOLL=y 81CONFIG_EPOLL=y
57CONFIG_SIGNALFD=y 82CONFIG_SIGNALFD=y
58CONFIG_TIMERFD=y 83CONFIG_TIMERFD=y
59CONFIG_EVENTFD=y 84CONFIG_EVENTFD=y
60# CONFIG_AIO is not set 85# CONFIG_AIO is not set
61CONFIG_VM_EVENT_COUNTERS=y 86CONFIG_VM_EVENT_COUNTERS=y
87CONFIG_COMPAT_BRK=y
62CONFIG_SLAB=y 88CONFIG_SLAB=y
63# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
64# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
91CONFIG_MMAP_ALLOW_UNINITIALIZED=y
65# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
66# CONFIG_MARKERS is not set 93# CONFIG_MARKERS is not set
67CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
95# CONFIG_SLOW_WORK is not set
68# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 96# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
69CONFIG_SLABINFO=y 97CONFIG_SLABINFO=y
70CONFIG_RT_MUTEXES=y
71CONFIG_TINY_SHMEM=y
72CONFIG_BASE_SMALL=0 98CONFIG_BASE_SMALL=0
73CONFIG_MODULES=y 99CONFIG_MODULES=y
74# CONFIG_MODULE_FORCE_LOAD is not set 100# CONFIG_MODULE_FORCE_LOAD is not set
@@ -76,11 +102,8 @@ CONFIG_MODULE_UNLOAD=y
76# CONFIG_MODULE_FORCE_UNLOAD is not set 102# CONFIG_MODULE_FORCE_UNLOAD is not set
77# CONFIG_MODVERSIONS is not set 103# CONFIG_MODVERSIONS is not set
78# CONFIG_MODULE_SRCVERSION_ALL is not set 104# CONFIG_MODULE_SRCVERSION_ALL is not set
79CONFIG_KMOD=y
80CONFIG_BLOCK=y 105CONFIG_BLOCK=y
81# CONFIG_LBD is not set 106# CONFIG_LBD is not set
82# CONFIG_BLK_DEV_IO_TRACE is not set
83# CONFIG_LSF is not set
84# CONFIG_BLK_DEV_BSG is not set 107# CONFIG_BLK_DEV_BSG is not set
85# CONFIG_BLK_DEV_INTEGRITY is not set 108# CONFIG_BLK_DEV_INTEGRITY is not set
86 109
@@ -96,7 +119,6 @@ CONFIG_IOSCHED_CFQ=y
96# CONFIG_DEFAULT_CFQ is not set 119# CONFIG_DEFAULT_CFQ is not set
97CONFIG_DEFAULT_NOOP=y 120CONFIG_DEFAULT_NOOP=y
98CONFIG_DEFAULT_IOSCHED="noop" 121CONFIG_DEFAULT_IOSCHED="noop"
99CONFIG_CLASSIC_RCU=y
100CONFIG_PREEMPT_NONE=y 122CONFIG_PREEMPT_NONE=y
101# CONFIG_PREEMPT_VOLUNTARY is not set 123# CONFIG_PREEMPT_VOLUNTARY is not set
102# CONFIG_PREEMPT is not set 124# CONFIG_PREEMPT is not set
@@ -128,10 +150,15 @@ CONFIG_BF537=y
128# CONFIG_BF538 is not set 150# CONFIG_BF538 is not set
129# CONFIG_BF539 is not set 151# CONFIG_BF539 is not set
130# CONFIG_BF542 is not set 152# CONFIG_BF542 is not set
153# CONFIG_BF542M is not set
131# CONFIG_BF544 is not set 154# CONFIG_BF544 is not set
155# CONFIG_BF544M is not set
132# CONFIG_BF547 is not set 156# CONFIG_BF547 is not set
157# CONFIG_BF547M is not set
133# CONFIG_BF548 is not set 158# CONFIG_BF548 is not set
159# CONFIG_BF548M is not set
134# CONFIG_BF549 is not set 160# CONFIG_BF549 is not set
161# CONFIG_BF549M is not set
135# CONFIG_BF561 is not set 162# CONFIG_BF561 is not set
136CONFIG_BF_REV_MIN=2 163CONFIG_BF_REV_MIN=2
137CONFIG_BF_REV_MAX=3 164CONFIG_BF_REV_MAX=3
@@ -173,11 +200,11 @@ CONFIG_IRQ_MEM_DMA1=13
173CONFIG_IRQ_WATCH=13 200CONFIG_IRQ_WATCH=13
174CONFIG_IRQ_SPI=10 201CONFIG_IRQ_SPI=10
175# CONFIG_BFIN537_STAMP is not set 202# CONFIG_BFIN537_STAMP is not set
176# CONFIG_BFIN537_BLUETECHNIX_CM is not set 203# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set
204# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set
177CONFIG_BFIN537_BLUETECHNIX_TCM=y 205CONFIG_BFIN537_BLUETECHNIX_TCM=y
178# CONFIG_PNAV10 is not set 206# CONFIG_PNAV10 is not set
179# CONFIG_CAMSIG_MINOTAUR is not set 207# CONFIG_CAMSIG_MINOTAUR is not set
180# CONFIG_GENERIC_BF537_BOARD is not set
181 208
182# 209#
183# BF537 Specific Configuration 210# BF537 Specific Configuration
@@ -223,7 +250,10 @@ CONFIG_HZ=250
223# CONFIG_SCHED_HRTICK is not set 250# CONFIG_SCHED_HRTICK is not set
224CONFIG_GENERIC_TIME=y 251CONFIG_GENERIC_TIME=y
225CONFIG_GENERIC_CLOCKEVENTS=y 252CONFIG_GENERIC_CLOCKEVENTS=y
253# CONFIG_TICKSOURCE_GPTMR0 is not set
254CONFIG_TICKSOURCE_CORETMR=y
226# CONFIG_CYCLES_CLOCKSOURCE is not set 255# CONFIG_CYCLES_CLOCKSOURCE is not set
256# CONFIG_GPTMR0_CLOCKSOURCE is not set
227# CONFIG_NO_HZ is not set 257# CONFIG_NO_HZ is not set
228# CONFIG_HIGH_RES_TIMERS is not set 258# CONFIG_HIGH_RES_TIMERS is not set
229CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 259CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -273,10 +303,12 @@ CONFIG_FLATMEM=y
273CONFIG_FLAT_NODE_MEM_MAP=y 303CONFIG_FLAT_NODE_MEM_MAP=y
274CONFIG_PAGEFLAGS_EXTENDED=y 304CONFIG_PAGEFLAGS_EXTENDED=y
275CONFIG_SPLIT_PTLOCK_CPUS=4 305CONFIG_SPLIT_PTLOCK_CPUS=4
276# CONFIG_RESOURCES_64BIT is not set
277# CONFIG_PHYS_ADDR_T_64BIT is not set 306# CONFIG_PHYS_ADDR_T_64BIT is not set
278CONFIG_ZONE_DMA_FLAG=1 307CONFIG_ZONE_DMA_FLAG=1
279CONFIG_VIRT_TO_BUS=y 308CONFIG_VIRT_TO_BUS=y
309CONFIG_UNEVICTABLE_LRU=y
310CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
311CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
280# CONFIG_BFIN_GPTIMERS is not set 312# CONFIG_BFIN_GPTIMERS is not set
281# CONFIG_DMA_UNCACHED_4M is not set 313# CONFIG_DMA_UNCACHED_4M is not set
282# CONFIG_DMA_UNCACHED_2M is not set 314# CONFIG_DMA_UNCACHED_2M is not set
@@ -287,10 +319,9 @@ CONFIG_DMA_UNCACHED_1M=y
287# Cache Support 319# Cache Support
288# 320#
289CONFIG_BFIN_ICACHE=y 321CONFIG_BFIN_ICACHE=y
290# CONFIG_BFIN_ICACHE_LOCK is not set 322CONFIG_BFIN_EXTMEM_ICACHEABLE=y
291CONFIG_BFIN_DCACHE=y 323CONFIG_BFIN_DCACHE=y
292# CONFIG_BFIN_DCACHE_BANKA is not set 324# CONFIG_BFIN_DCACHE_BANKA is not set
293CONFIG_BFIN_EXTMEM_ICACHEABLE=y
294CONFIG_BFIN_EXTMEM_DCACHEABLE=y 325CONFIG_BFIN_EXTMEM_DCACHEABLE=y
295CONFIG_BFIN_EXTMEM_WRITEBACK=y 326CONFIG_BFIN_EXTMEM_WRITEBACK=y
296# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set 327# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
@@ -301,7 +332,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y
301# CONFIG_MPU is not set 332# CONFIG_MPU is not set
302 333
303# 334#
304# Asynchonous Memory Configuration 335# Asynchronous Memory Configuration
305# 336#
306 337
307# 338#
@@ -327,6 +358,7 @@ CONFIG_BANK_3=0xFFC2
327# Bus options (PCI, PCMCIA, EISA, MCA, ISA) 358# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
328# 359#
329# CONFIG_ARCH_SUPPORTS_MSI is not set 360# CONFIG_ARCH_SUPPORTS_MSI is not set
361# CONFIG_PCCARD is not set
330 362
331# 363#
332# Executable file formats 364# Executable file formats
@@ -343,13 +375,83 @@ CONFIG_BINFMT_SHARED_FLAT=y
343# 375#
344# CONFIG_PM is not set 376# CONFIG_PM is not set
345CONFIG_ARCH_SUSPEND_POSSIBLE=y 377CONFIG_ARCH_SUSPEND_POSSIBLE=y
346# CONFIG_PM_WAKEUP_BY_GPIO is not set
347 378
348# 379#
349# CPU Frequency scaling 380# CPU Frequency scaling
350# 381#
351# CONFIG_CPU_FREQ is not set 382# CONFIG_CPU_FREQ is not set
352# CONFIG_NET is not set 383CONFIG_NET=y
384
385#
386# Networking options
387#
388CONFIG_PACKET=y
389# CONFIG_PACKET_MMAP is not set
390CONFIG_UNIX=y
391CONFIG_XFRM=y
392# CONFIG_XFRM_USER is not set
393# CONFIG_XFRM_SUB_POLICY is not set
394# CONFIG_XFRM_MIGRATE is not set
395# CONFIG_XFRM_STATISTICS is not set
396# CONFIG_NET_KEY is not set
397CONFIG_INET=y
398# CONFIG_IP_MULTICAST is not set
399# CONFIG_IP_ADVANCED_ROUTER is not set
400CONFIG_IP_FIB_HASH=y
401# CONFIG_IP_PNP is not set
402# CONFIG_NET_IPIP is not set
403# CONFIG_NET_IPGRE is not set
404# CONFIG_ARPD is not set
405# CONFIG_SYN_COOKIES is not set
406# CONFIG_INET_AH is not set
407# CONFIG_INET_ESP is not set
408# CONFIG_INET_IPCOMP is not set
409# CONFIG_INET_XFRM_TUNNEL is not set
410# CONFIG_INET_TUNNEL is not set
411CONFIG_INET_XFRM_MODE_TRANSPORT=y
412CONFIG_INET_XFRM_MODE_TUNNEL=y
413CONFIG_INET_XFRM_MODE_BEET=y
414CONFIG_INET_LRO=y
415# CONFIG_INET_DIAG is not set
416# CONFIG_TCP_CONG_ADVANCED is not set
417CONFIG_TCP_CONG_CUBIC=y
418CONFIG_DEFAULT_TCP_CONG="cubic"
419# CONFIG_TCP_MD5SIG is not set
420# CONFIG_IPV6 is not set
421# CONFIG_NETWORK_SECMARK is not set
422# CONFIG_NETFILTER is not set
423# CONFIG_IP_DCCP is not set
424# CONFIG_IP_SCTP is not set
425# CONFIG_TIPC is not set
426# CONFIG_ATM is not set
427# CONFIG_BRIDGE is not set
428# CONFIG_NET_DSA is not set
429# CONFIG_VLAN_8021Q is not set
430# CONFIG_DECNET is not set
431# CONFIG_LLC2 is not set
432# CONFIG_IPX is not set
433# CONFIG_ATALK is not set
434# CONFIG_X25 is not set
435# CONFIG_LAPB is not set
436# CONFIG_ECONET is not set
437# CONFIG_WAN_ROUTER is not set
438# CONFIG_PHONET is not set
439# CONFIG_NET_SCHED is not set
440# CONFIG_DCB is not set
441
442#
443# Network testing
444#
445# CONFIG_NET_PKTGEN is not set
446# CONFIG_HAMRADIO is not set
447# CONFIG_CAN is not set
448# CONFIG_IRDA is not set
449# CONFIG_BT is not set
450# CONFIG_AF_RXRPC is not set
451# CONFIG_WIRELESS is not set
452# CONFIG_WIMAX is not set
453# CONFIG_RFKILL is not set
454# CONFIG_NET_9P is not set
353 455
354# 456#
355# Device Drivers 457# Device Drivers
@@ -358,15 +460,21 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
358# 460#
359# Generic Driver Options 461# Generic Driver Options
360# 462#
463CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
361CONFIG_STANDALONE=y 464CONFIG_STANDALONE=y
362CONFIG_PREVENT_FIRMWARE_BUILD=y 465CONFIG_PREVENT_FIRMWARE_BUILD=y
466CONFIG_FW_LOADER=y
467CONFIG_FIRMWARE_IN_KERNEL=y
468CONFIG_EXTRA_FIRMWARE=""
363# CONFIG_SYS_HYPERVISOR is not set 469# CONFIG_SYS_HYPERVISOR is not set
470# CONFIG_CONNECTOR is not set
364CONFIG_MTD=y 471CONFIG_MTD=y
365# CONFIG_MTD_DEBUG is not set 472# CONFIG_MTD_DEBUG is not set
473# CONFIG_MTD_TESTS is not set
366# CONFIG_MTD_CONCAT is not set 474# CONFIG_MTD_CONCAT is not set
367CONFIG_MTD_PARTITIONS=y 475CONFIG_MTD_PARTITIONS=y
368# CONFIG_MTD_REDBOOT_PARTS is not set 476# CONFIG_MTD_REDBOOT_PARTS is not set
369# CONFIG_MTD_CMDLINE_PARTS is not set 477CONFIG_MTD_CMDLINE_PARTS=y
370# CONFIG_MTD_AR7_PARTS is not set 478# CONFIG_MTD_AR7_PARTS is not set
371 479
372# 480#
@@ -402,9 +510,10 @@ CONFIG_MTD_CFI_I2=y
402CONFIG_MTD_CFI_INTELEXT=y 510CONFIG_MTD_CFI_INTELEXT=y
403# CONFIG_MTD_CFI_AMDSTD is not set 511# CONFIG_MTD_CFI_AMDSTD is not set
404# CONFIG_MTD_CFI_STAA is not set 512# CONFIG_MTD_CFI_STAA is not set
513# CONFIG_MTD_PSD4256G is not set
405CONFIG_MTD_CFI_UTIL=y 514CONFIG_MTD_CFI_UTIL=y
406CONFIG_MTD_RAM=y 515CONFIG_MTD_RAM=y
407# CONFIG_MTD_ROM is not set 516CONFIG_MTD_ROM=m
408# CONFIG_MTD_ABSENT is not set 517# CONFIG_MTD_ABSENT is not set
409 518
410# 519#
@@ -413,7 +522,7 @@ CONFIG_MTD_RAM=y
413CONFIG_MTD_COMPLEX_MAPPINGS=y 522CONFIG_MTD_COMPLEX_MAPPINGS=y
414# CONFIG_MTD_PHYSMAP is not set 523# CONFIG_MTD_PHYSMAP is not set
415CONFIG_MTD_GPIO_ADDR=y 524CONFIG_MTD_GPIO_ADDR=y
416CONFIG_MTD_UCLINUX=y 525# CONFIG_MTD_UCLINUX is not set
417# CONFIG_MTD_PLATRAM is not set 526# CONFIG_MTD_PLATRAM is not set
418 527
419# 528#
@@ -436,6 +545,11 @@ CONFIG_MTD_UCLINUX=y
436# CONFIG_MTD_ONENAND is not set 545# CONFIG_MTD_ONENAND is not set
437 546
438# 547#
548# LPDDR flash memory drivers
549#
550# CONFIG_MTD_LPDDR is not set
551
552#
439# UBI - Unsorted block images 553# UBI - Unsorted block images
440# 554#
441# CONFIG_MTD_UBI is not set 555# CONFIG_MTD_UBI is not set
@@ -443,15 +557,23 @@ CONFIG_MTD_UCLINUX=y
443CONFIG_BLK_DEV=y 557CONFIG_BLK_DEV=y
444# CONFIG_BLK_DEV_COW_COMMON is not set 558# CONFIG_BLK_DEV_COW_COMMON is not set
445# CONFIG_BLK_DEV_LOOP is not set 559# CONFIG_BLK_DEV_LOOP is not set
560# CONFIG_BLK_DEV_NBD is not set
446CONFIG_BLK_DEV_RAM=y 561CONFIG_BLK_DEV_RAM=y
447CONFIG_BLK_DEV_RAM_COUNT=16 562CONFIG_BLK_DEV_RAM_COUNT=16
448CONFIG_BLK_DEV_RAM_SIZE=4096 563CONFIG_BLK_DEV_RAM_SIZE=4096
449# CONFIG_BLK_DEV_XIP is not set 564# CONFIG_BLK_DEV_XIP is not set
450# CONFIG_CDROM_PKTCDVD is not set 565# CONFIG_CDROM_PKTCDVD is not set
566# CONFIG_ATA_OVER_ETH is not set
451# CONFIG_BLK_DEV_HD is not set 567# CONFIG_BLK_DEV_HD is not set
452CONFIG_MISC_DEVICES=y 568CONFIG_MISC_DEVICES=y
453# CONFIG_EEPROM_93CX6 is not set
454# CONFIG_ENCLOSURE_SERVICES is not set 569# CONFIG_ENCLOSURE_SERVICES is not set
570# CONFIG_C2PORT is not set
571
572#
573# EEPROM support
574#
575# CONFIG_EEPROM_AT25 is not set
576# CONFIG_EEPROM_93CX6 is not set
455CONFIG_HAVE_IDE=y 577CONFIG_HAVE_IDE=y
456# CONFIG_IDE is not set 578# CONFIG_IDE is not set
457 579
@@ -464,6 +586,74 @@ CONFIG_HAVE_IDE=y
464# CONFIG_SCSI_NETLINK is not set 586# CONFIG_SCSI_NETLINK is not set
465# CONFIG_ATA is not set 587# CONFIG_ATA is not set
466# CONFIG_MD is not set 588# CONFIG_MD is not set
589CONFIG_NETDEVICES=y
590CONFIG_COMPAT_NET_DEV_OPS=y
591# CONFIG_DUMMY is not set
592# CONFIG_BONDING is not set
593# CONFIG_MACVLAN is not set
594# CONFIG_EQUALIZER is not set
595# CONFIG_TUN is not set
596# CONFIG_VETH is not set
597CONFIG_PHYLIB=y
598
599#
600# MII PHY device drivers
601#
602# CONFIG_MARVELL_PHY is not set
603# CONFIG_DAVICOM_PHY is not set
604# CONFIG_QSEMI_PHY is not set
605# CONFIG_LXT_PHY is not set
606# CONFIG_CICADA_PHY is not set
607# CONFIG_VITESSE_PHY is not set
608# CONFIG_SMSC_PHY is not set
609# CONFIG_BROADCOM_PHY is not set
610# CONFIG_ICPLUS_PHY is not set
611# CONFIG_REALTEK_PHY is not set
612# CONFIG_NATIONAL_PHY is not set
613# CONFIG_STE10XP is not set
614# CONFIG_LSI_ET1011C_PHY is not set
615# CONFIG_FIXED_PHY is not set
616# CONFIG_MDIO_BITBANG is not set
617CONFIG_NET_ETHERNET=y
618CONFIG_MII=y
619CONFIG_BFIN_MAC=y
620CONFIG_BFIN_MAC_USE_L1=y
621CONFIG_BFIN_TX_DESC_NUM=10
622CONFIG_BFIN_RX_DESC_NUM=20
623# CONFIG_BFIN_MAC_RMII is not set
624# CONFIG_SMC91X is not set
625# CONFIG_DM9000 is not set
626# CONFIG_ENC28J60 is not set
627# CONFIG_ETHOC is not set
628# CONFIG_SMSC911X is not set
629# CONFIG_DNET is not set
630# CONFIG_IBM_NEW_EMAC_ZMII is not set
631# CONFIG_IBM_NEW_EMAC_RGMII is not set
632# CONFIG_IBM_NEW_EMAC_TAH is not set
633# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
634# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
635# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
636# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
637# CONFIG_B44 is not set
638# CONFIG_NETDEV_1000 is not set
639# CONFIG_NETDEV_10000 is not set
640
641#
642# Wireless LAN
643#
644# CONFIG_WLAN_PRE80211 is not set
645# CONFIG_WLAN_80211 is not set
646
647#
648# Enable WiMAX (Networking options) to see the WiMAX drivers
649#
650# CONFIG_WAN is not set
651# CONFIG_PPP is not set
652# CONFIG_SLIP is not set
653# CONFIG_NETCONSOLE is not set
654# CONFIG_NETPOLL is not set
655# CONFIG_NET_POLL_CONTROLLER is not set
656# CONFIG_ISDN is not set
467# CONFIG_PHONE is not set 657# CONFIG_PHONE is not set
468 658
469# 659#
@@ -480,15 +670,12 @@ CONFIG_HAVE_IDE=y
480# 670#
481# Character devices 671# Character devices
482# 672#
483# CONFIG_AD9960 is not set 673CONFIG_BFIN_DMA_INTERFACE=m
484# CONFIG_SPI_ADC_BF533 is not set 674# CONFIG_BFIN_PPI is not set
485# CONFIG_BF5xx_PPIFCD is not set 675# CONFIG_BFIN_PPIFCD is not set
486# CONFIG_BFIN_SIMPLE_TIMER is not set 676# CONFIG_BFIN_SIMPLE_TIMER is not set
487# CONFIG_BF5xx_PPI is not set 677# CONFIG_BFIN_SPI_ADC is not set
488CONFIG_BFIN_SPORT=y 678CONFIG_BFIN_SPORT=y
489# CONFIG_BFIN_TIMER_LATENCY is not set
490CONFIG_BFIN_DMA_INTERFACE=m
491# CONFIG_SIMPLE_GPIO is not set
492# CONFIG_VT is not set 679# CONFIG_VT is not set
493# CONFIG_DEVKMEM is not set 680# CONFIG_DEVKMEM is not set
494# CONFIG_BFIN_JTAG_COMM is not set 681# CONFIG_BFIN_JTAG_COMM is not set
@@ -502,6 +689,7 @@ CONFIG_BFIN_DMA_INTERFACE=m
502# 689#
503# Non-8250 serial port support 690# Non-8250 serial port support
504# 691#
692# CONFIG_SERIAL_MAX3100 is not set
505CONFIG_SERIAL_BFIN=y 693CONFIG_SERIAL_BFIN=y
506CONFIG_SERIAL_BFIN_CONSOLE=y 694CONFIG_SERIAL_BFIN_CONSOLE=y
507CONFIG_SERIAL_BFIN_DMA=y 695CONFIG_SERIAL_BFIN_DMA=y
@@ -514,6 +702,7 @@ CONFIG_SERIAL_CORE=y
514CONFIG_SERIAL_CORE_CONSOLE=y 702CONFIG_SERIAL_CORE_CONSOLE=y
515# CONFIG_SERIAL_BFIN_SPORT is not set 703# CONFIG_SERIAL_BFIN_SPORT is not set
516CONFIG_UNIX98_PTYS=y 704CONFIG_UNIX98_PTYS=y
705# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
517# CONFIG_LEGACY_PTYS is not set 706# CONFIG_LEGACY_PTYS is not set
518 707
519# 708#
@@ -534,39 +723,17 @@ CONFIG_SPI_MASTER=y
534# 723#
535CONFIG_SPI_BFIN=y 724CONFIG_SPI_BFIN=y
536# CONFIG_SPI_BFIN_LOCK is not set 725# CONFIG_SPI_BFIN_LOCK is not set
726# CONFIG_SPI_BFIN_SPORT is not set
537# CONFIG_SPI_BITBANG is not set 727# CONFIG_SPI_BITBANG is not set
728# CONFIG_SPI_GPIO is not set
538 729
539# 730#
540# SPI Protocol Masters 731# SPI Protocol Masters
541# 732#
542# CONFIG_EEPROM_AT25 is not set
543# CONFIG_SPI_SPIDEV is not set 733# CONFIG_SPI_SPIDEV is not set
544# CONFIG_SPI_TLE62X0 is not set 734# CONFIG_SPI_TLE62X0 is not set
545CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 735CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
546CONFIG_GPIOLIB=y 736# CONFIG_GPIOLIB is not set
547# CONFIG_DEBUG_GPIO is not set
548CONFIG_GPIO_SYSFS=y
549
550#
551# Memory mapped GPIO expanders:
552#
553
554#
555# I2C GPIO expanders:
556#
557# CONFIG_GPIO_MAX732X is not set
558# CONFIG_GPIO_PCA953X is not set
559# CONFIG_GPIO_PCF857X is not set
560
561#
562# PCI GPIO expanders:
563#
564
565#
566# SPI GPIO expanders:
567#
568# CONFIG_GPIO_MAX7301 is not set
569# CONFIG_GPIO_MCP23S08 is not set
570# CONFIG_W1 is not set 737# CONFIG_W1 is not set
571# CONFIG_POWER_SUPPLY is not set 738# CONFIG_POWER_SUPPLY is not set
572# CONFIG_HWMON is not set 739# CONFIG_HWMON is not set
@@ -580,6 +747,12 @@ CONFIG_WATCHDOG=y
580# 747#
581# CONFIG_SOFT_WATCHDOG is not set 748# CONFIG_SOFT_WATCHDOG is not set
582CONFIG_BFIN_WDT=y 749CONFIG_BFIN_WDT=y
750CONFIG_SSB_POSSIBLE=y
751
752#
753# Sonics Silicon Backplane
754#
755# CONFIG_SSB is not set
583 756
584# 757#
585# Multifunction device drivers 758# Multifunction device drivers
@@ -588,7 +761,7 @@ CONFIG_BFIN_WDT=y
588# CONFIG_MFD_SM501 is not set 761# CONFIG_MFD_SM501 is not set
589# CONFIG_HTC_PASIC3 is not set 762# CONFIG_HTC_PASIC3 is not set
590# CONFIG_MFD_TMIO is not set 763# CONFIG_MFD_TMIO is not set
591# CONFIG_MFD_WM8400 is not set 764# CONFIG_REGULATOR is not set
592 765
593# 766#
594# Multimedia devices 767# Multimedia devices
@@ -598,6 +771,7 @@ CONFIG_BFIN_WDT=y
598# Multimedia core support 771# Multimedia core support
599# 772#
600# CONFIG_VIDEO_DEV is not set 773# CONFIG_VIDEO_DEV is not set
774# CONFIG_DVB_CORE is not set
601# CONFIG_VIDEO_MEDIA is not set 775# CONFIG_VIDEO_MEDIA is not set
602 776
603# 777#
@@ -618,13 +792,81 @@ CONFIG_BFIN_WDT=y
618# 792#
619# CONFIG_DISPLAY_SUPPORT is not set 793# CONFIG_DISPLAY_SUPPORT is not set
620# CONFIG_SOUND is not set 794# CONFIG_SOUND is not set
621# CONFIG_USB_SUPPORT is not set 795CONFIG_USB_SUPPORT=y
622# CONFIG_MMC is not set 796CONFIG_USB_ARCH_HAS_HCD=y
797# CONFIG_USB_ARCH_HAS_OHCI is not set
798# CONFIG_USB_ARCH_HAS_EHCI is not set
799# CONFIG_USB is not set
800# CONFIG_USB_OTG_WHITELIST is not set
801# CONFIG_USB_OTG_BLACKLIST_HUB is not set
802# CONFIG_USB_GADGET_MUSB_HDRC is not set
803
804#
805# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
806#
807CONFIG_USB_GADGET=y
808# CONFIG_USB_GADGET_DEBUG_FILES is not set
809# CONFIG_USB_GADGET_DEBUG_FS is not set
810CONFIG_USB_GADGET_VBUS_DRAW=2
811CONFIG_USB_GADGET_SELECTED=y
812# CONFIG_USB_GADGET_AT91 is not set
813# CONFIG_USB_GADGET_ATMEL_USBA is not set
814# CONFIG_USB_GADGET_FSL_USB2 is not set
815# CONFIG_USB_GADGET_LH7A40X is not set
816# CONFIG_USB_GADGET_OMAP is not set
817# CONFIG_USB_GADGET_PXA25X is not set
818# CONFIG_USB_GADGET_PXA27X is not set
819# CONFIG_USB_GADGET_S3C2410 is not set
820# CONFIG_USB_GADGET_IMX is not set
821# CONFIG_USB_GADGET_M66592 is not set
822# CONFIG_USB_GADGET_AMD5536UDC is not set
823# CONFIG_USB_GADGET_FSL_QE is not set
824# CONFIG_USB_GADGET_CI13XXX is not set
825CONFIG_USB_GADGET_NET2272=y
826CONFIG_USB_NET2272=y
827# CONFIG_USB_GADGET_NET2280 is not set
828# CONFIG_USB_GADGET_GOKU is not set
829# CONFIG_USB_GADGET_DUMMY_HCD is not set
830CONFIG_USB_GADGET_DUALSPEED=y
831# CONFIG_USB_ZERO is not set
832# CONFIG_USB_AUDIO is not set
833CONFIG_USB_ETH=y
834CONFIG_USB_ETH_RNDIS=y
835# CONFIG_USB_GADGETFS is not set
836# CONFIG_USB_FILE_STORAGE is not set
837# CONFIG_USB_G_SERIAL is not set
838# CONFIG_USB_MIDI_GADGET is not set
839# CONFIG_USB_G_PRINTER is not set
840# CONFIG_USB_CDC_COMPOSITE is not set
841
842#
843# OTG and related infrastructure
844#
845# CONFIG_USB_GPIO_VBUS is not set
846# CONFIG_NOP_USB_XCEIV is not set
847CONFIG_MMC=y
848# CONFIG_MMC_DEBUG is not set
849# CONFIG_MMC_UNSAFE_RESUME is not set
850
851#
852# MMC/SD/SDIO Card Drivers
853#
854CONFIG_MMC_BLOCK=y
855CONFIG_MMC_BLOCK_BOUNCE=y
856# CONFIG_SDIO_UART is not set
857# CONFIG_MMC_TEST is not set
858
859#
860# MMC/SD/SDIO Host Controller Drivers
861#
862# CONFIG_MMC_SDHCI is not set
863CONFIG_MMC_SPI=m
623# CONFIG_MEMSTICK is not set 864# CONFIG_MEMSTICK is not set
624# CONFIG_NEW_LEDS is not set 865# CONFIG_NEW_LEDS is not set
625# CONFIG_ACCESSIBILITY is not set 866# CONFIG_ACCESSIBILITY is not set
626# CONFIG_RTC_CLASS is not set 867# CONFIG_RTC_CLASS is not set
627# CONFIG_DMADEVICES is not set 868# CONFIG_DMADEVICES is not set
869# CONFIG_AUXDISPLAY is not set
628# CONFIG_UIO is not set 870# CONFIG_UIO is not set
629# CONFIG_STAGING is not set 871# CONFIG_STAGING is not set
630 872
@@ -641,8 +883,10 @@ CONFIG_FS_MBCACHE=y
641# CONFIG_REISERFS_FS is not set 883# CONFIG_REISERFS_FS is not set
642# CONFIG_JFS_FS is not set 884# CONFIG_JFS_FS is not set
643# CONFIG_FS_POSIX_ACL is not set 885# CONFIG_FS_POSIX_ACL is not set
644CONFIG_FILE_LOCKING=y
645# CONFIG_XFS_FS is not set 886# CONFIG_XFS_FS is not set
887# CONFIG_OCFS2_FS is not set
888# CONFIG_BTRFS_FS is not set
889CONFIG_FILE_LOCKING=y
646# CONFIG_DNOTIFY is not set 890# CONFIG_DNOTIFY is not set
647CONFIG_INOTIFY=y 891CONFIG_INOTIFY=y
648CONFIG_INOTIFY_USER=y 892CONFIG_INOTIFY_USER=y
@@ -652,6 +896,11 @@ CONFIG_INOTIFY_USER=y
652# CONFIG_FUSE_FS is not set 896# CONFIG_FUSE_FS is not set
653 897
654# 898#
899# Caches
900#
901# CONFIG_FSCACHE is not set
902
903#
655# CD-ROM/DVD Filesystems 904# CD-ROM/DVD Filesystems
656# 905#
657# CONFIG_ISO9660_FS is not set 906# CONFIG_ISO9660_FS is not set
@@ -660,8 +909,11 @@ CONFIG_INOTIFY_USER=y
660# 909#
661# DOS/FAT/NT Filesystems 910# DOS/FAT/NT Filesystems
662# 911#
663# CONFIG_MSDOS_FS is not set 912CONFIG_FAT_FS=y
664# CONFIG_VFAT_FS is not set 913CONFIG_MSDOS_FS=y
914CONFIG_VFAT_FS=y
915CONFIG_FAT_DEFAULT_CODEPAGE=437
916CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
665# CONFIG_NTFS_FS is not set 917# CONFIG_NTFS_FS is not set
666 918
667# 919#
@@ -673,10 +925,7 @@ CONFIG_SYSFS=y
673# CONFIG_TMPFS is not set 925# CONFIG_TMPFS is not set
674# CONFIG_HUGETLB_PAGE is not set 926# CONFIG_HUGETLB_PAGE is not set
675# CONFIG_CONFIGFS_FS is not set 927# CONFIG_CONFIGFS_FS is not set
676 928CONFIG_MISC_FILESYSTEMS=y
677#
678# Miscellaneous filesystems
679#
680# CONFIG_ADFS_FS is not set 929# CONFIG_ADFS_FS is not set
681# CONFIG_AFFS_FS is not set 930# CONFIG_AFFS_FS is not set
682# CONFIG_HFS_FS is not set 931# CONFIG_HFS_FS is not set
@@ -684,9 +933,19 @@ CONFIG_SYSFS=y
684# CONFIG_BEFS_FS is not set 933# CONFIG_BEFS_FS is not set
685# CONFIG_BFS_FS is not set 934# CONFIG_BFS_FS is not set
686# CONFIG_EFS_FS is not set 935# CONFIG_EFS_FS is not set
687# CONFIG_YAFFS_FS is not set 936CONFIG_JFFS2_FS=y
688# CONFIG_JFFS2_FS is not set 937CONFIG_JFFS2_FS_DEBUG=0
938CONFIG_JFFS2_FS_WRITEBUFFER=y
939# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
940# CONFIG_JFFS2_SUMMARY is not set
941# CONFIG_JFFS2_FS_XATTR is not set
942# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
943CONFIG_JFFS2_ZLIB=y
944# CONFIG_JFFS2_LZO is not set
945CONFIG_JFFS2_RTIME=y
946# CONFIG_JFFS2_RUBIN is not set
689# CONFIG_CRAMFS is not set 947# CONFIG_CRAMFS is not set
948# CONFIG_SQUASHFS is not set
690# CONFIG_VXFS_FS is not set 949# CONFIG_VXFS_FS is not set
691# CONFIG_MINIX_FS is not set 950# CONFIG_MINIX_FS is not set
692# CONFIG_OMFS_FS is not set 951# CONFIG_OMFS_FS is not set
@@ -695,13 +954,62 @@ CONFIG_SYSFS=y
695# CONFIG_ROMFS_FS is not set 954# CONFIG_ROMFS_FS is not set
696# CONFIG_SYSV_FS is not set 955# CONFIG_SYSV_FS is not set
697# CONFIG_UFS_FS is not set 956# CONFIG_UFS_FS is not set
957# CONFIG_NILFS2_FS is not set
958CONFIG_NETWORK_FILESYSTEMS=y
959# CONFIG_NFS_FS is not set
960# CONFIG_NFSD is not set
961# CONFIG_SMB_FS is not set
962# CONFIG_CIFS is not set
963# CONFIG_NCP_FS is not set
964# CONFIG_CODA_FS is not set
965# CONFIG_AFS_FS is not set
698 966
699# 967#
700# Partition Types 968# Partition Types
701# 969#
702# CONFIG_PARTITION_ADVANCED is not set 970# CONFIG_PARTITION_ADVANCED is not set
703CONFIG_MSDOS_PARTITION=y 971CONFIG_MSDOS_PARTITION=y
704# CONFIG_NLS is not set 972CONFIG_NLS=y
973CONFIG_NLS_DEFAULT="iso8859-1"
974CONFIG_NLS_CODEPAGE_437=y
975# CONFIG_NLS_CODEPAGE_737 is not set
976# CONFIG_NLS_CODEPAGE_775 is not set
977# CONFIG_NLS_CODEPAGE_850 is not set
978# CONFIG_NLS_CODEPAGE_852 is not set
979# CONFIG_NLS_CODEPAGE_855 is not set
980# CONFIG_NLS_CODEPAGE_857 is not set
981# CONFIG_NLS_CODEPAGE_860 is not set
982# CONFIG_NLS_CODEPAGE_861 is not set
983# CONFIG_NLS_CODEPAGE_862 is not set
984# CONFIG_NLS_CODEPAGE_863 is not set
985# CONFIG_NLS_CODEPAGE_864 is not set
986# CONFIG_NLS_CODEPAGE_865 is not set
987# CONFIG_NLS_CODEPAGE_866 is not set
988# CONFIG_NLS_CODEPAGE_869 is not set
989# CONFIG_NLS_CODEPAGE_936 is not set
990# CONFIG_NLS_CODEPAGE_950 is not set
991# CONFIG_NLS_CODEPAGE_932 is not set
992# CONFIG_NLS_CODEPAGE_949 is not set
993# CONFIG_NLS_CODEPAGE_874 is not set
994# CONFIG_NLS_ISO8859_8 is not set
995# CONFIG_NLS_CODEPAGE_1250 is not set
996# CONFIG_NLS_CODEPAGE_1251 is not set
997# CONFIG_NLS_ASCII is not set
998CONFIG_NLS_ISO8859_1=y
999# CONFIG_NLS_ISO8859_2 is not set
1000# CONFIG_NLS_ISO8859_3 is not set
1001# CONFIG_NLS_ISO8859_4 is not set
1002# CONFIG_NLS_ISO8859_5 is not set
1003# CONFIG_NLS_ISO8859_6 is not set
1004# CONFIG_NLS_ISO8859_7 is not set
1005# CONFIG_NLS_ISO8859_9 is not set
1006# CONFIG_NLS_ISO8859_13 is not set
1007# CONFIG_NLS_ISO8859_14 is not set
1008# CONFIG_NLS_ISO8859_15 is not set
1009# CONFIG_NLS_KOI8_R is not set
1010# CONFIG_NLS_KOI8_U is not set
1011# CONFIG_NLS_UTF8 is not set
1012# CONFIG_DLM is not set
705 1013
706# 1014#
707# Kernel hacking 1015# Kernel hacking
@@ -714,12 +1022,30 @@ CONFIG_FRAME_WARN=1024
714# CONFIG_UNUSED_SYMBOLS is not set 1022# CONFIG_UNUSED_SYMBOLS is not set
715CONFIG_DEBUG_FS=y 1023CONFIG_DEBUG_FS=y
716# CONFIG_HEADERS_CHECK is not set 1024# CONFIG_HEADERS_CHECK is not set
1025CONFIG_DEBUG_SECTION_MISMATCH=y
717# CONFIG_DEBUG_KERNEL is not set 1026# CONFIG_DEBUG_KERNEL is not set
718CONFIG_DEBUG_BUGVERBOSE=y 1027# CONFIG_DEBUG_BUGVERBOSE is not set
719# CONFIG_DEBUG_MEMORY_INIT is not set 1028# CONFIG_DEBUG_MEMORY_INIT is not set
720# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1029# CONFIG_RCU_CPU_STALL_DETECTOR is not set
721# CONFIG_SYSCTL_SYSCALL_CHECK is not set 1030CONFIG_HAVE_FUNCTION_TRACER=y
722# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1031CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1032CONFIG_TRACING_SUPPORT=y
1033
1034#
1035# Tracers
1036#
1037# CONFIG_FUNCTION_TRACER is not set
1038# CONFIG_IRQSOFF_TRACER is not set
1039# CONFIG_SCHED_TRACER is not set
1040# CONFIG_CONTEXT_SWITCH_TRACER is not set
1041# CONFIG_EVENT_TRACER is not set
1042# CONFIG_BOOT_TRACER is not set
1043# CONFIG_TRACE_BRANCH_PROFILING is not set
1044# CONFIG_STACK_TRACER is not set
1045# CONFIG_KMEMTRACE is not set
1046# CONFIG_WORKQUEUE_TRACER is not set
1047# CONFIG_BLK_DEV_IO_TRACE is not set
1048# CONFIG_DYNAMIC_DEBUG is not set
723# CONFIG_SAMPLES is not set 1049# CONFIG_SAMPLES is not set
724CONFIG_HAVE_ARCH_KGDB=y 1050CONFIG_HAVE_ARCH_KGDB=y
725CONFIG_DEBUG_VERBOSE=y 1051CONFIG_DEBUG_VERBOSE=y
@@ -733,9 +1059,10 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
733CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 1059CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
734# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set 1060# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
735# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set 1061# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
736# CONFIG_EARLY_PRINTK is not set 1062CONFIG_EARLY_PRINTK=y
737CONFIG_CPLB_INFO=y 1063CONFIG_CPLB_INFO=y
738CONFIG_ACCESS_CHECK=y 1064CONFIG_ACCESS_CHECK=y
1065# CONFIG_BFIN_ISRAM_SELF_TEST is not set
739 1066
740# 1067#
741# Security options 1068# Security options
@@ -744,20 +1071,110 @@ CONFIG_ACCESS_CHECK=y
744# CONFIG_SECURITY is not set 1071# CONFIG_SECURITY is not set
745# CONFIG_SECURITYFS is not set 1072# CONFIG_SECURITYFS is not set
746# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1073# CONFIG_SECURITY_FILE_CAPABILITIES is not set
747# CONFIG_CRYPTO is not set 1074CONFIG_CRYPTO=y
1075
1076#
1077# Crypto core or helper
1078#
1079# CONFIG_CRYPTO_FIPS is not set
1080# CONFIG_CRYPTO_MANAGER is not set
1081# CONFIG_CRYPTO_MANAGER2 is not set
1082# CONFIG_CRYPTO_GF128MUL is not set
1083# CONFIG_CRYPTO_NULL is not set
1084# CONFIG_CRYPTO_CRYPTD is not set
1085# CONFIG_CRYPTO_AUTHENC is not set
1086# CONFIG_CRYPTO_TEST is not set
1087
1088#
1089# Authenticated Encryption with Associated Data
1090#
1091# CONFIG_CRYPTO_CCM is not set
1092# CONFIG_CRYPTO_GCM is not set
1093# CONFIG_CRYPTO_SEQIV is not set
1094
1095#
1096# Block modes
1097#
1098# CONFIG_CRYPTO_CBC is not set
1099# CONFIG_CRYPTO_CTR is not set
1100# CONFIG_CRYPTO_CTS is not set
1101# CONFIG_CRYPTO_ECB is not set
1102# CONFIG_CRYPTO_LRW is not set
1103# CONFIG_CRYPTO_PCBC is not set
1104# CONFIG_CRYPTO_XTS is not set
1105
1106#
1107# Hash modes
1108#
1109# CONFIG_CRYPTO_HMAC is not set
1110# CONFIG_CRYPTO_XCBC is not set
1111
1112#
1113# Digest
1114#
1115# CONFIG_CRYPTO_CRC32C is not set
1116# CONFIG_CRYPTO_MD4 is not set
1117# CONFIG_CRYPTO_MD5 is not set
1118# CONFIG_CRYPTO_MICHAEL_MIC is not set
1119# CONFIG_CRYPTO_RMD128 is not set
1120# CONFIG_CRYPTO_RMD160 is not set
1121# CONFIG_CRYPTO_RMD256 is not set
1122# CONFIG_CRYPTO_RMD320 is not set
1123# CONFIG_CRYPTO_SHA1 is not set
1124# CONFIG_CRYPTO_SHA256 is not set
1125# CONFIG_CRYPTO_SHA512 is not set
1126# CONFIG_CRYPTO_TGR192 is not set
1127# CONFIG_CRYPTO_WP512 is not set
1128
1129#
1130# Ciphers
1131#
1132# CONFIG_CRYPTO_AES is not set
1133# CONFIG_CRYPTO_ANUBIS is not set
1134# CONFIG_CRYPTO_ARC4 is not set
1135# CONFIG_CRYPTO_BLOWFISH is not set
1136# CONFIG_CRYPTO_CAMELLIA is not set
1137# CONFIG_CRYPTO_CAST5 is not set
1138# CONFIG_CRYPTO_CAST6 is not set
1139# CONFIG_CRYPTO_DES is not set
1140# CONFIG_CRYPTO_FCRYPT is not set
1141# CONFIG_CRYPTO_KHAZAD is not set
1142# CONFIG_CRYPTO_SALSA20 is not set
1143# CONFIG_CRYPTO_SEED is not set
1144# CONFIG_CRYPTO_SERPENT is not set
1145# CONFIG_CRYPTO_TEA is not set
1146# CONFIG_CRYPTO_TWOFISH is not set
1147
1148#
1149# Compression
1150#
1151# CONFIG_CRYPTO_DEFLATE is not set
1152# CONFIG_CRYPTO_ZLIB is not set
1153# CONFIG_CRYPTO_LZO is not set
1154
1155#
1156# Random Number Generation
1157#
1158# CONFIG_CRYPTO_ANSI_CPRNG is not set
1159CONFIG_CRYPTO_HW=y
1160# CONFIG_BINARY_PRINTF is not set
748 1161
749# 1162#
750# Library routines 1163# Library routines
751# 1164#
1165CONFIG_BITREVERSE=y
1166CONFIG_GENERIC_FIND_LAST_BIT=y
752# CONFIG_CRC_CCITT is not set 1167# CONFIG_CRC_CCITT is not set
753# CONFIG_CRC16 is not set 1168# CONFIG_CRC16 is not set
754# CONFIG_CRC_T10DIF is not set 1169# CONFIG_CRC_T10DIF is not set
755# CONFIG_CRC_ITU_T is not set 1170CONFIG_CRC_ITU_T=y
756# CONFIG_CRC32 is not set 1171CONFIG_CRC32=y
757# CONFIG_CRC7 is not set 1172CONFIG_CRC7=y
758# CONFIG_LIBCRC32C is not set 1173# CONFIG_LIBCRC32C is not set
759CONFIG_ZLIB_INFLATE=y 1174CONFIG_ZLIB_INFLATE=y
760CONFIG_PLIST=y 1175CONFIG_ZLIB_DEFLATE=y
1176CONFIG_DECOMPRESS_LZMA=y
761CONFIG_HAS_IOMEM=y 1177CONFIG_HAS_IOMEM=y
762CONFIG_HAS_IOPORT=y 1178CONFIG_HAS_IOPORT=y
763CONFIG_HAS_DMA=y 1179CONFIG_HAS_DMA=y
1180CONFIG_NLATTR=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 10064f902d20..e6485c305ea6 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -11,9 +11,6 @@
11 11
12#ifndef __ASSEMBLY__ 12#ifndef __ASSEMBLY__
13 13
14#include <asm/sections.h>
15#include <asm/ptrace.h>
16#include <asm/user.h>
17#include <linux/linkage.h> 14#include <linux/linkage.h>
18#include <linux/types.h> 15#include <linux/types.h>
19 16
@@ -23,6 +20,12 @@
23# define DMA_UNCACHED_REGION (2 * 1024 * 1024) 20# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
24#elif defined(CONFIG_DMA_UNCACHED_1M) 21#elif defined(CONFIG_DMA_UNCACHED_1M)
25# define DMA_UNCACHED_REGION (1024 * 1024) 22# define DMA_UNCACHED_REGION (1024 * 1024)
23#elif defined(CONFIG_DMA_UNCACHED_512K)
24# define DMA_UNCACHED_REGION (512 * 1024)
25#elif defined(CONFIG_DMA_UNCACHED_256K)
26# define DMA_UNCACHED_REGION (256 * 1024)
27#elif defined(CONFIG_DMA_UNCACHED_128K)
28# define DMA_UNCACHED_REGION (128 * 1024)
26#else 29#else
27# define DMA_UNCACHED_REGION (0) 30# define DMA_UNCACHED_REGION (0)
28#endif 31#endif
@@ -35,6 +38,7 @@ extern unsigned long get_sclk(void);
35extern unsigned long sclk_to_usecs(unsigned long sclk); 38extern unsigned long sclk_to_usecs(unsigned long sclk);
36extern unsigned long usecs_to_sclk(unsigned long usecs); 39extern unsigned long usecs_to_sclk(unsigned long usecs);
37 40
41struct pt_regs;
38extern void dump_bfin_process(struct pt_regs *regs); 42extern void dump_bfin_process(struct pt_regs *regs);
39extern void dump_bfin_mem(struct pt_regs *regs); 43extern void dump_bfin_mem(struct pt_regs *regs);
40extern void dump_bfin_trace_buffer(void); 44extern void dump_bfin_trace_buffer(void);
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 6f4548a13555..75f6dc336d46 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -47,7 +47,7 @@
47#define BUG() \ 47#define BUG() \
48 do { \ 48 do { \
49 _BUG_OR_WARN(0); \ 49 _BUG_OR_WARN(0); \
50 for (;;); \ 50 unreachable(); \
51 } while (0) 51 } while (0)
52 52
53#define WARN_ON(condition) \ 53#define WARN_ON(condition) \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 417eaac7fe99..2666ff8ea952 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -10,6 +10,7 @@
10#define _BLACKFIN_CACHEFLUSH_H 10#define _BLACKFIN_CACHEFLUSH_H
11 11
12#include <asm/blackfin.h> /* for SSYNC() */ 12#include <asm/blackfin.h> /* for SSYNC() */
13#include <asm/sections.h> /* for _ramend */
13 14
14extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 15extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
15extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 16extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
index a23415be0de1..623cc7fb00bc 100644
--- a/arch/blackfin/include/asm/checksum.h
+++ b/arch/blackfin/include/asm/checksum.h
@@ -9,63 +9,12 @@
9#define _BFIN_CHECKSUM_H 9#define _BFIN_CHECKSUM_H
10 10
11/* 11/*
12 * computes the checksum of a memory block at buff, length len,
13 * and adds in "sum" (32-bit)
14 *
15 * returns a 32-bit number suitable for feeding into itself
16 * or csum_tcpudp_magic
17 *
18 * this function must be called with even lengths, except
19 * for the last fragment, which may be odd
20 *
21 * it's best to have buff aligned on a 32-bit boundary
22 */
23__wsum csum_partial(const void *buff, int len, __wsum sum);
24
25/*
26 * the same as csum_partial, but copies from src while it
27 * checksums
28 *
29 * here even more important to align src and dst on a 32-bit (or even
30 * better 64-bit) boundary
31 */
32
33__wsum csum_partial_copy(const void *src, void *dst,
34 int len, __wsum sum);
35
36/*
37 * the same as csum_partial_copy, but copies from user space.
38 *
39 * here even more important to align src and dst on a 32-bit (or even
40 * better 64-bit) boundary
41 */
42
43extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
44 int len, __wsum sum, int *csum_err);
45
46#define csum_partial_copy_nocheck(src, dst, len, sum) \
47 csum_partial_copy((src), (dst), (len), (sum))
48
49__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
50
51/*
52 * Fold a partial checksum
53 */
54
55static inline __sum16 csum_fold(__wsum sum)
56{
57 while (sum >> 16)
58 sum = (sum & 0xffff) + (sum >> 16);
59 return ((~(sum << 16)) >> 16);
60}
61
62/*
63 * computes the checksum of the TCP/UDP pseudo-header 12 * computes the checksum of the TCP/UDP pseudo-header
64 * returns a 16-bit checksum, already complemented 13 * returns a 16-bit checksum, already complemented
65 */ 14 */
66 15
67static inline __wsum 16static inline __wsum
68csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, 17__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
69 unsigned short proto, __wsum sum) 18 unsigned short proto, __wsum sum)
70{ 19{
71 unsigned int carry; 20 unsigned int carry;
@@ -88,19 +37,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
88 37
89 return (sum); 38 return (sum);
90} 39}
40#define csum_tcpudp_nofold __csum_tcpudp_nofold
91 41
92static inline __sum16 42#include <asm-generic/checksum.h>
93csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
94 unsigned short proto, __wsum sum)
95{
96 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
97}
98
99/*
100 * this routine is used for miscellaneous IP-like checksums, mainly
101 * in icmp.c
102 */
103
104extern __sum16 ip_compute_csum(const void *buff, int len);
105 43
106#endif /* _BFIN_CHECKSUM_H */ 44#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index f80dad5ff257..6f0b61852f58 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -9,6 +9,8 @@
9#ifndef _BFIN_CLOCKS_H 9#ifndef _BFIN_CLOCKS_H
10#define _BFIN_CLOCKS_H 10#define _BFIN_CLOCKS_H
11 11
12#include <asm/dpmc.h>
13
12#ifdef CONFIG_CCLK_DIV_1 14#ifdef CONFIG_CCLK_DIV_1
13# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 15# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
14# define CONFIG_CCLK_DIV 1 16# define CONFIG_CCLK_DIV 1
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 7a23d824ac96..f9172ff30e5c 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -7,9 +7,9 @@
7#ifndef _BLACKFIN_DMA_MAPPING_H 7#ifndef _BLACKFIN_DMA_MAPPING_H
8#define _BLACKFIN_DMA_MAPPING_H 8#define _BLACKFIN_DMA_MAPPING_H
9 9
10#include <asm/scatterlist.h> 10#include <asm/cacheflush.h>
11struct scatterlist;
11 12
12void dma_alloc_init(unsigned long start, unsigned long end);
13void *dma_alloc_coherent(struct device *dev, size_t size, 13void *dma_alloc_coherent(struct device *dev, size_t size,
14 dma_addr_t *dma_handle, gfp_t gfp); 14 dma_addr_t *dma_handle, gfp_t gfp);
15void dma_free_coherent(struct device *dev, size_t size, void *vaddr, 15void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
@@ -20,13 +20,51 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
20 */ 20 */
21#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) 21#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
22#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) 22#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
23#define dma_supported(d, m) (1)
24#define dma_get_cache_alignment() (32)
25#define dma_is_consistent(d, h) (1)
23 26
24static inline 27static inline int
25int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 28dma_set_mask(struct device *dev, u64 dma_mask)
26{ 29{
30 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
31 return -EIO;
32
33 *dev->dma_mask = dma_mask;
34
27 return 0; 35 return 0;
28} 36}
29 37
38static inline int
39dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
40{
41 return 0;
42}
43
44extern void
45__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
46static inline void
47_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
48{
49 if (!__builtin_constant_p(dir)) {
50 __dma_sync(addr, size, dir);
51 return;
52 }
53
54 switch (dir) {
55 case DMA_NONE:
56 BUG();
57 case DMA_TO_DEVICE: /* writeback only */
58 flush_dcache_range(addr, addr + size);
59 break;
60 case DMA_FROM_DEVICE: /* invalidate only */
61 case DMA_BIDIRECTIONAL: /* flush and invalidate */
62 /* Blackfin has no dedicated invalidate (it includes a flush) */
63 invalidate_dcache_range(addr, addr + size);
64 break;
65 }
66}
67
30/* 68/*
31 * Map a single buffer of the indicated size for DMA in streaming mode. 69 * Map a single buffer of the indicated size for DMA in streaming mode.
32 * The 32-bit bus address to use is returned. 70 * The 32-bit bus address to use is returned.
@@ -34,8 +72,13 @@ int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
34 * Once the device is given the dma address, the device owns this memory 72 * Once the device is given the dma address, the device owns this memory
35 * until either pci_unmap_single or pci_dma_sync_single is performed. 73 * until either pci_unmap_single or pci_dma_sync_single is performed.
36 */ 74 */
37extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, 75static inline dma_addr_t
38 enum dma_data_direction direction); 76dma_map_single(struct device *dev, void *ptr, size_t size,
77 enum dma_data_direction dir)
78{
79 _dma_sync((dma_addr_t)ptr, size, dir);
80 return (dma_addr_t) ptr;
81}
39 82
40static inline dma_addr_t 83static inline dma_addr_t
41dma_map_page(struct device *dev, struct page *page, 84dma_map_page(struct device *dev, struct page *page,
@@ -53,8 +96,12 @@ dma_map_page(struct device *dev, struct page *page,
53 * After this call, reads by the cpu to the buffer are guarenteed to see 96 * After this call, reads by the cpu to the buffer are guarenteed to see
54 * whatever the device wrote there. 97 * whatever the device wrote there.
55 */ 98 */
56extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 99static inline void
57 enum dma_data_direction direction); 100dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
101 enum dma_data_direction dir)
102{
103 BUG_ON(!valid_dma_direction(dir));
104}
58 105
59static inline void 106static inline void
60dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, 107dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
@@ -80,38 +127,66 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
80 * the same here. 127 * the same here.
81 */ 128 */
82extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 129extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
83 enum dma_data_direction direction); 130 enum dma_data_direction dir);
84 131
85/* 132/*
86 * Unmap a set of streaming mode DMA translations. 133 * Unmap a set of streaming mode DMA translations.
87 * Again, cpu read rules concerning calls here are the same as for 134 * Again, cpu read rules concerning calls here are the same as for
88 * pci_unmap_single() above. 135 * pci_unmap_single() above.
89 */ 136 */
90extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 137static inline void
91 int nhwentries, enum dma_data_direction direction); 138dma_unmap_sg(struct device *dev, struct scatterlist *sg,
139 int nhwentries, enum dma_data_direction dir)
140{
141 BUG_ON(!valid_dma_direction(dir));
142}
92 143
93static inline void dma_sync_single_for_cpu(struct device *dev, 144static inline void
94 dma_addr_t handle, size_t size, 145dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
95 enum dma_data_direction dir) 146 unsigned long offset, size_t size,
147 enum dma_data_direction dir)
96{ 148{
149 BUG_ON(!valid_dma_direction(dir));
97} 150}
98 151
99static inline void dma_sync_single_for_device(struct device *dev, 152static inline void
100 dma_addr_t handle, size_t size, 153dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
101 enum dma_data_direction dir) 154 unsigned long offset, size_t size,
155 enum dma_data_direction dir)
102{ 156{
157 _dma_sync(handle + offset, size, dir);
103} 158}
104 159
105static inline void dma_sync_sg_for_cpu(struct device *dev, 160static inline void
106 struct scatterlist *sg, 161dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
107 int nents, enum dma_data_direction dir) 162 enum dma_data_direction dir)
108{ 163{
164 dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
109} 165}
110 166
111static inline void dma_sync_sg_for_device(struct device *dev, 167static inline void
112 struct scatterlist *sg, 168dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
113 int nents, enum dma_data_direction dir) 169 enum dma_data_direction dir)
170{
171 dma_sync_single_range_for_device(dev, handle, 0, size, dir);
172}
173
174static inline void
175dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
176 enum dma_data_direction dir)
177{
178 BUG_ON(!valid_dma_direction(dir));
179}
180
181extern void
182dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
183 int nents, enum dma_data_direction dir);
184
185static inline void
186dma_cache_sync(struct device *dev, void *vaddr, size_t size,
187 enum dma_data_direction dir)
114{ 188{
189 _dma_sync((dma_addr_t)vaddr, size, dir);
115} 190}
116 191
117#endif /* _BLACKFIN_DMA_MAPPING_H */ 192#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index c9a59622e23f..bd2e62243abe 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -10,46 +10,70 @@
10 10
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <mach/dma.h> 12#include <mach/dma.h>
13#include <asm/atomic.h>
13#include <asm/blackfin.h> 14#include <asm/blackfin.h>
14#include <asm/page.h> 15#include <asm/page.h>
15 16#include <asm-generic/dma.h>
16#define MAX_DMA_ADDRESS PAGE_OFFSET 17
17 18/* DMA_CONFIG Masks */
18/***************************************************************************** 19#define DMAEN 0x0001 /* DMA Channel Enable */
19* Generic DMA Declarations 20#define WNR 0x0002 /* Channel Direction (W/R*) */
20* 21#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
21****************************************************************************/ 22#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
22enum dma_chan_status { 23#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
23 DMA_CHANNEL_FREE, 24#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
24 DMA_CHANNEL_REQUESTED, 25#define RESTART 0x0020 /* DMA Buffer Clear */
25 DMA_CHANNEL_ENABLED, 26#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
26}; 27#define DI_EN 0x0080 /* Data Interrupt Enable */
28#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
29#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
30#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
31#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
32#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
33#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
34#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
35#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
36#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
37#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
38#define NDSIZE 0x0f00 /* Next Descriptor Size */
39#define DMAFLOW 0x7000 /* Flow Control */
40#define DMAFLOW_STOP 0x0000 /* Stop Mode */
41#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
42#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
43#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
44#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
45
46/* DMA_IRQ_STATUS Masks */
47#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
48#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
49#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
50#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
27 51
28/*------------------------- 52/*-------------------------
29 * config reg bits value 53 * config reg bits value
30 *-------------------------*/ 54 *-------------------------*/
31#define DATA_SIZE_8 0 55#define DATA_SIZE_8 0
32#define DATA_SIZE_16 1 56#define DATA_SIZE_16 1
33#define DATA_SIZE_32 2 57#define DATA_SIZE_32 2
34 58
35#define DMA_FLOW_STOP 0 59#define DMA_FLOW_STOP 0
36#define DMA_FLOW_AUTO 1 60#define DMA_FLOW_AUTO 1
37#define DMA_FLOW_ARRAY 4 61#define DMA_FLOW_ARRAY 4
38#define DMA_FLOW_SMALL 6 62#define DMA_FLOW_SMALL 6
39#define DMA_FLOW_LARGE 7 63#define DMA_FLOW_LARGE 7
40 64
41#define DIMENSION_LINEAR 0 65#define DIMENSION_LINEAR 0
42#define DIMENSION_2D 1 66#define DIMENSION_2D 1
43 67
44#define DIR_READ 0 68#define DIR_READ 0
45#define DIR_WRITE 1 69#define DIR_WRITE 1
46 70
47#define INTR_DISABLE 0 71#define INTR_DISABLE 0
48#define INTR_ON_BUF 2 72#define INTR_ON_BUF 2
49#define INTR_ON_ROW 3 73#define INTR_ON_ROW 3
50 74
51#define DMA_NOSYNC_KEEP_DMA_BUF 0 75#define DMA_NOSYNC_KEEP_DMA_BUF 0
52#define DMA_SYNC_RESTART 1 76#define DMA_SYNC_RESTART 1
53 77
54struct dmasg { 78struct dmasg {
55 void *next_desc_addr; 79 void *next_desc_addr;
@@ -104,11 +128,9 @@ struct dma_register {
104 128
105}; 129};
106 130
107struct mutex;
108struct dma_channel { 131struct dma_channel {
109 struct mutex dmalock;
110 const char *device_id; 132 const char *device_id;
111 enum dma_chan_status chan_status; 133 atomic_t chan_status;
112 volatile struct dma_register *regs; 134 volatile struct dma_register *regs;
113 struct dmasg *sg; /* large mode descriptor */ 135 struct dmasg *sg; /* large mode descriptor */
114 unsigned int irq; 136 unsigned int irq;
@@ -220,27 +242,20 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
220 242
221static inline int dma_channel_active(unsigned int channel) 243static inline int dma_channel_active(unsigned int channel)
222{ 244{
223 if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) 245 return atomic_read(&dma_ch[channel].chan_status);
224 return 0;
225 else
226 return 1;
227} 246}
228 247
229static inline void disable_dma(unsigned int channel) 248static inline void disable_dma(unsigned int channel)
230{ 249{
231 dma_ch[channel].regs->cfg &= ~DMAEN; 250 dma_ch[channel].regs->cfg &= ~DMAEN;
232 SSYNC(); 251 SSYNC();
233 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
234} 252}
235static inline void enable_dma(unsigned int channel) 253static inline void enable_dma(unsigned int channel)
236{ 254{
237 dma_ch[channel].regs->curr_x_count = 0; 255 dma_ch[channel].regs->curr_x_count = 0;
238 dma_ch[channel].regs->curr_y_count = 0; 256 dma_ch[channel].regs->curr_y_count = 0;
239 dma_ch[channel].regs->cfg |= DMAEN; 257 dma_ch[channel].regs->cfg |= DMAEN;
240 dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
241} 258}
242void free_dma(unsigned int channel);
243int request_dma(unsigned int channel, const char *device_id);
244int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); 259int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
245 260
246static inline void dma_disable_irq(unsigned int channel) 261static inline void dma_disable_irq(unsigned int channel)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 925e66cb2d49..1597ae5041ee 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver 2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
3 * 3 *
4 * Copyright (C) 2004-2008 Analog Device Inc. 4 * Copyright (C) 2004-2009 Analog Device Inc.
5 * 5 *
6 * Licensed under the GPL-2 6 * Licensed under the GPL-2
7 */ 7 */
@@ -9,7 +9,109 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#ifdef __KERNEL__ 12/* PLL_CTL Masks */
13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
14#define PLL_OFF 0x0002 /* PLL Not Powered */
15#define STOPCK 0x0008 /* Core Clock Off */
16#define PDWN 0x0020 /* Enter Deep Sleep Mode */
17#ifdef __ADSPBF539__
18# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
19# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
20#else
21# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
22# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
23#endif
24#define BYPASS 0x0100 /* Bypass the PLL */
25#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
26#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
27#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
28
29/* PLL_DIV Masks */
30#define SSEL 0x000F /* System Select */
31#define CSEL 0x0030 /* Core Select */
32#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
33#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
34#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
35#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
36
37#define CCLK_DIV1 CSEL_DIV1
38#define CCLK_DIV2 CSEL_DIV2
39#define CCLK_DIV4 CSEL_DIV4
40#define CCLK_DIV8 CSEL_DIV8
41
42#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
43#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
44
45/* PLL_STAT Masks */
46#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
47#define FULL_ON 0x0002 /* Processor In Full On Mode */
48#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
49#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
50
51#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
52#define CANWS 0x0800 /* CAN Wake-Up Status */
53#define USBWS 0x2000 /* USB Wake-Up Status */
54#define KPADWS 0x4000 /* Keypad Wake-Up Status */
55#define ROTWS 0x8000 /* Rotary Wake-Up Status */
56#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
57
58/* VR_CTL Masks */
59#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
60#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
61#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
62#else
63#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
64#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
65#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
66#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
67#endif
68#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
69
70#define GAIN 0x000C /* Voltage Level Gain */
71#define GAIN_5 0x0000 /* GAIN = 5 */
72#define GAIN_10 0x0004 /* GAIN = 1 */
73#define GAIN_20 0x0008 /* GAIN = 2 */
74#define GAIN_50 0x000C /* GAIN = 5 */
75
76#define VLEV 0x00F0 /* Internal Voltage Level */
77#ifdef __ADSPBF52x__
78#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
79#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
80#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
81#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
82#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
83#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
84#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
85#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
86#else
87#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
88#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
89#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
90#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
91#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
92#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
93#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
94#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
95#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
96#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
97#endif
98
99#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
100#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
101#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
102#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
103#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
104#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
105#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
106#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
107#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
108
109#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
110#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
111#else
112#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
113#endif
114
13#ifndef __ASSEMBLY__ 115#ifndef __ASSEMBLY__
14 116
15void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 117void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
@@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
54 w[P0 + (x - PLL_CTL)] = R0;\ 156 w[P0 + (x - PLL_CTL)] = R0;\
55 157
56#endif 158#endif
57#endif /* __KERNEL__ */
58 159
59#endif /*_BLACKFIN_DPMC_H_*/ 160#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 5b44d05ca53e..539468a05057 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -159,6 +159,11 @@ struct gpio_port_t {
159}; 159};
160#endif 160#endif
161 161
162#ifdef BFIN_SPECIAL_GPIO_BANKS
163void bfin_special_gpio_free(unsigned gpio);
164int bfin_special_gpio_request(unsigned gpio, const char *label);
165#endif
166
162#ifdef CONFIG_PM 167#ifdef CONFIG_PM
163 168
164unsigned int bfin_pm_standby_setup(void); 169unsigned int bfin_pm_standby_setup(void);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 89f08decb8e0..c722acdda0d3 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -172,25 +172,25 @@
172 172
173/* The actual gptimer API */ 173/* The actual gptimer API */
174 174
175void set_gptimer_pwidth(int timer_id, uint32_t width); 175void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
176uint32_t get_gptimer_pwidth(int timer_id); 176uint32_t get_gptimer_pwidth(unsigned int timer_id);
177void set_gptimer_period(int timer_id, uint32_t period); 177void set_gptimer_period(unsigned int timer_id, uint32_t period);
178uint32_t get_gptimer_period(int timer_id); 178uint32_t get_gptimer_period(unsigned int timer_id);
179uint32_t get_gptimer_count(int timer_id); 179uint32_t get_gptimer_count(unsigned int timer_id);
180int get_gptimer_intr(int timer_id); 180int get_gptimer_intr(unsigned int timer_id);
181void clear_gptimer_intr(int timer_id); 181void clear_gptimer_intr(unsigned int timer_id);
182int get_gptimer_over(int timer_id); 182int get_gptimer_over(unsigned int timer_id);
183void clear_gptimer_over(int timer_id); 183void clear_gptimer_over(unsigned int timer_id);
184void set_gptimer_config(int timer_id, uint16_t config); 184void set_gptimer_config(unsigned int timer_id, uint16_t config);
185uint16_t get_gptimer_config(int timer_id); 185uint16_t get_gptimer_config(unsigned int timer_id);
186int get_gptimer_run(int timer_id); 186int get_gptimer_run(unsigned int timer_id);
187void set_gptimer_pulse_hi(int timer_id); 187void set_gptimer_pulse_hi(unsigned int timer_id);
188void clear_gptimer_pulse_hi(int timer_id); 188void clear_gptimer_pulse_hi(unsigned int timer_id);
189void enable_gptimers(uint16_t mask); 189void enable_gptimers(uint16_t mask);
190void disable_gptimers(uint16_t mask); 190void disable_gptimers(uint16_t mask);
191void disable_gptimers_sync(uint16_t mask); 191void disable_gptimers_sync(uint16_t mask);
192uint16_t get_enabled_gptimers(void); 192uint16_t get_enabled_gptimers(void);
193uint32_t get_gptimer_status(int group); 193uint32_t get_gptimer_status(unsigned int group);
194void set_gptimer_status(int group, uint32_t value); 194void set_gptimer_status(unsigned int group, uint32_t value);
195 195
196#endif 196#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index d1f5029189a7..29e55b9d88bc 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -31,12 +31,14 @@ static inline unsigned char readb(const volatile void __iomem *addr)
31 unsigned int val; 31 unsigned int val;
32 int tmp; 32 int tmp;
33 33
34 __asm__ __volatile__ ("cli %1;\n\t" 34 __asm__ __volatile__ (
35 "NOP; NOP; SSYNC;\n\t" 35 "cli %1;"
36 "%0 = b [%2] (z);\n\t" 36 "NOP; NOP; SSYNC;"
37 "sti %1;\n\t" 37 "%0 = b [%2] (z);"
38 : "=d"(val), "=d"(tmp): "a"(addr) 38 "sti %1;"
39 ); 39 : "=d"(val), "=d"(tmp)
40 : "a"(addr)
41 );
40 42
41 return (unsigned char) val; 43 return (unsigned char) val;
42} 44}
@@ -46,12 +48,14 @@ static inline unsigned short readw(const volatile void __iomem *addr)
46 unsigned int val; 48 unsigned int val;
47 int tmp; 49 int tmp;
48 50
49 __asm__ __volatile__ ("cli %1;\n\t" 51 __asm__ __volatile__ (
50 "NOP; NOP; SSYNC;\n\t" 52 "cli %1;"
51 "%0 = w [%2] (z);\n\t" 53 "NOP; NOP; SSYNC;"
52 "sti %1;\n\t" 54 "%0 = w [%2] (z);"
53 : "=d"(val), "=d"(tmp): "a"(addr) 55 "sti %1;"
54 ); 56 : "=d"(val), "=d"(tmp)
57 : "a"(addr)
58 );
55 59
56 return (unsigned short) val; 60 return (unsigned short) val;
57} 61}
@@ -61,20 +65,23 @@ static inline unsigned int readl(const volatile void __iomem *addr)
61 unsigned int val; 65 unsigned int val;
62 int tmp; 66 int tmp;
63 67
64 __asm__ __volatile__ ("cli %1;\n\t" 68 __asm__ __volatile__ (
65 "NOP; NOP; SSYNC;\n\t" 69 "cli %1;"
66 "%0 = [%2];\n\t" 70 "NOP; NOP; SSYNC;"
67 "sti %1;\n\t" 71 "%0 = [%2];"
68 : "=d"(val), "=d"(tmp): "a"(addr) 72 "sti %1;"
69 ); 73 : "=d"(val), "=d"(tmp)
74 : "a"(addr)
75 );
76
70 return val; 77 return val;
71} 78}
72 79
73#endif /* __ASSEMBLY__ */ 80#endif /* __ASSEMBLY__ */
74 81
75#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) 82#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
76#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) 83#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
77#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) 84#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
78 85
79#define __raw_readb readb 86#define __raw_readb readb
80#define __raw_readw readw 87#define __raw_readw readw
@@ -82,9 +89,9 @@ static inline unsigned int readl(const volatile void __iomem *addr)
82#define __raw_writeb writeb 89#define __raw_writeb writeb
83#define __raw_writew writew 90#define __raw_writew writew
84#define __raw_writel writel 91#define __raw_writel writel
85#define memset_io(a,b,c) memset((void *)(a),(b),(c)) 92#define memset_io(a, b, c) memset((void *)(a), (b), (c))
86#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) 93#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
87#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) 94#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
88 95
89/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ 96/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
90#define __io(port) ((void *)(unsigned long)(port)) 97#define __io(port) ((void *)(unsigned long)(port))
@@ -92,30 +99,30 @@ static inline unsigned int readl(const volatile void __iomem *addr)
92#define inb(port) readb(__io(port)) 99#define inb(port) readb(__io(port))
93#define inw(port) readw(__io(port)) 100#define inw(port) readw(__io(port))
94#define inl(port) readl(__io(port)) 101#define inl(port) readl(__io(port))
95#define outb(x,port) writeb(x,__io(port)) 102#define outb(x, port) writeb(x, __io(port))
96#define outw(x,port) writew(x,__io(port)) 103#define outw(x, port) writew(x, __io(port))
97#define outl(x,port) writel(x,__io(port)) 104#define outl(x, port) writel(x, __io(port))
98 105
99#define inb_p(port) inb(__io(port)) 106#define inb_p(port) inb(__io(port))
100#define inw_p(port) inw(__io(port)) 107#define inw_p(port) inw(__io(port))
101#define inl_p(port) inl(__io(port)) 108#define inl_p(port) inl(__io(port))
102#define outb_p(x,port) outb(x,__io(port)) 109#define outb_p(x, port) outb(x, __io(port))
103#define outw_p(x,port) outw(x,__io(port)) 110#define outw_p(x, port) outw(x, __io(port))
104#define outl_p(x,port) outl(x,__io(port)) 111#define outl_p(x, port) outl(x, __io(port))
105 112
106#define ioread8_rep(a,d,c) readsb(a,d,c) 113#define ioread8_rep(a, d, c) readsb(a, d, c)
107#define ioread16_rep(a,d,c) readsw(a,d,c) 114#define ioread16_rep(a, d, c) readsw(a, d, c)
108#define ioread32_rep(a,d,c) readsl(a,d,c) 115#define ioread32_rep(a, d, c) readsl(a, d, c)
109#define iowrite8_rep(a,s,c) writesb(a,s,c) 116#define iowrite8_rep(a, s, c) writesb(a, s, c)
110#define iowrite16_rep(a,s,c) writesw(a,s,c) 117#define iowrite16_rep(a, s, c) writesw(a, s, c)
111#define iowrite32_rep(a,s,c) writesl(a,s,c) 118#define iowrite32_rep(a, s, c) writesl(a, s, c)
112 119
113#define ioread8(X) readb(X) 120#define ioread8(x) readb(x)
114#define ioread16(X) readw(X) 121#define ioread16(x) readw(x)
115#define ioread32(X) readl(X) 122#define ioread32(x) readl(x)
116#define iowrite8(val,X) writeb(val,X) 123#define iowrite8(val, x) writeb(val, x)
117#define iowrite16(val,X) writew(val,X) 124#define iowrite16(val, x) writew(val, x)
118#define iowrite32(val,X) writel(val,X) 125#define iowrite32(val, x) writel(val, x)
119 126
120#define mmiowb() wmb() 127#define mmiowb() wmb()
121 128
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 4617ba66278f..d3b40449ca0e 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.11-00" 38#define IPIPE_ARCH_STRING "1.12-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 11 40#define IPIPE_MINOR_NUMBER 12
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -124,16 +124,6 @@ static inline int __ipipe_check_tickdev(const char *devname)
124 return 1; 124 return 1;
125} 125}
126 126
127static inline void __ipipe_lock_root(void)
128{
129 set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
130}
131
132static inline void __ipipe_unlock_root(void)
133{
134 clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
135}
136
137void __ipipe_enable_pipeline(void); 127void __ipipe_enable_pipeline(void);
138 128
139#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 129#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 490098f532a7..00409201d9ed 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -51,23 +51,15 @@
51 51
52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
53 53
54#define __ipipe_stall_root() \ 54void __ipipe_stall_root(void);
55 do { \ 55
56 volatile unsigned long *p = &__ipipe_root_status; \ 56unsigned long __ipipe_test_and_stall_root(void);
57 set_bit(0, p); \ 57
58 } while (0) 58unsigned long __ipipe_test_root(void);
59 59
60#define __ipipe_test_and_stall_root() \ 60void __ipipe_lock_root(void);
61 ({ \ 61
62 volatile unsigned long *p = &__ipipe_root_status; \ 62void __ipipe_unlock_root(void);
63 test_and_set_bit(0, p); \
64 })
65
66#define __ipipe_test_root() \
67 ({ \
68 const unsigned long *p = &__ipipe_root_status; \
69 test_bit(0, p); \
70 })
71 63
72#endif /* !__ASSEMBLY__ */ 64#endif /* !__ASSEMBLY__ */
73 65
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 9b19a19d9ae9..813a1af3e865 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -33,6 +33,7 @@ static inline unsigned long bfin_cli(void)
33 33
34#ifdef CONFIG_IPIPE 34#ifdef CONFIG_IPIPE
35 35
36#include <linux/compiler.h>
36#include <linux/ipipe_base.h> 37#include <linux/ipipe_base.h>
37#include <linux/ipipe_trace.h> 38#include <linux/ipipe_trace.h>
38 39
@@ -49,12 +50,12 @@ static inline unsigned long bfin_cli(void)
49 barrier(); \ 50 barrier(); \
50 } while (0) 51 } while (0)
51 52
52static inline void raw_local_irq_enable(void) 53#define raw_local_irq_enable() \
53{ 54 do { \
54 barrier(); 55 barrier(); \
55 ipipe_check_context(ipipe_root_domain); 56 ipipe_check_context(ipipe_root_domain); \
56 __ipipe_unstall_root(); 57 __ipipe_unstall_root(); \
57} 58 } while (0)
58 59
59#define raw_local_save_flags_ptr(x) \ 60#define raw_local_save_flags_ptr(x) \
60 do { \ 61 do { \
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index c8b256d2ea30..8651afe12990 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -10,9 +10,6 @@
10 10
11#include <linux/ptrace.h> 11#include <linux/ptrace.h>
12 12
13/* gdb locks */
14#define KGDB_MAX_NO_CPUS 8
15
16/* 13/*
17 * BUFMAX defines the maximum number of characters in inbound/outbound buffers. 14 * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
18 * At least NUMREGBYTES*2 are needed for register packets. 15 * At least NUMREGBYTES*2 are needed for register packets.
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 4179e329b9c9..7c8fe834ff22 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -295,156 +295,3 @@
295#else 295#else
296#define PLL_BYPASS 0 296#define PLL_BYPASS 0
297#endif 297#endif
298
299/***************************************Currently Not Being Used *********************************/
300
301#if defined(CONFIG_FLASH_SPEED_BWAT) && \
302defined(CONFIG_FLASH_SPEED_BRAT) && \
303defined(CONFIG_FLASH_SPEED_BHT) && \
304defined(CONFIG_FLASH_SPEED_BST) && \
305defined(CONFIG_FLASH_SPEED_BTT)
306
307#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
308#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
309#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
310#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
311#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
312
313#if (flash_EBIU_AMBCTL_TT > 3)
314#define flash_EBIU_AMBCTL0_TT B0TT_4
315#endif
316#if (flash_EBIU_AMBCTL_TT == 3)
317#define flash_EBIU_AMBCTL0_TT B0TT_3
318#endif
319#if (flash_EBIU_AMBCTL_TT == 2)
320#define flash_EBIU_AMBCTL0_TT B0TT_2
321#endif
322#if (flash_EBIU_AMBCTL_TT < 2)
323#define flash_EBIU_AMBCTL0_TT B0TT_1
324#endif
325
326#if (flash_EBIU_AMBCTL_ST > 3)
327#define flash_EBIU_AMBCTL0_ST B0ST_4
328#endif
329#if (flash_EBIU_AMBCTL_ST == 3)
330#define flash_EBIU_AMBCTL0_ST B0ST_3
331#endif
332#if (flash_EBIU_AMBCTL_ST == 2)
333#define flash_EBIU_AMBCTL0_ST B0ST_2
334#endif
335#if (flash_EBIU_AMBCTL_ST < 2)
336#define flash_EBIU_AMBCTL0_ST B0ST_1
337#endif
338
339#if (flash_EBIU_AMBCTL_HT > 2)
340#define flash_EBIU_AMBCTL0_HT B0HT_3
341#endif
342#if (flash_EBIU_AMBCTL_HT == 2)
343#define flash_EBIU_AMBCTL0_HT B0HT_2
344#endif
345#if (flash_EBIU_AMBCTL_HT == 1)
346#define flash_EBIU_AMBCTL0_HT B0HT_1
347#endif
348#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
349#define flash_EBIU_AMBCTL0_HT B0HT_0
350#endif
351#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
352#define flash_EBIU_AMBCTL0_HT B0HT_1
353#endif
354
355#if (flash_EBIU_AMBCTL_WAT > 14)
356#define flash_EBIU_AMBCTL0_WAT B0WAT_15
357#endif
358#if (flash_EBIU_AMBCTL_WAT == 14)
359#define flash_EBIU_AMBCTL0_WAT B0WAT_14
360#endif
361#if (flash_EBIU_AMBCTL_WAT == 13)
362#define flash_EBIU_AMBCTL0_WAT B0WAT_13
363#endif
364#if (flash_EBIU_AMBCTL_WAT == 12)
365#define flash_EBIU_AMBCTL0_WAT B0WAT_12
366#endif
367#if (flash_EBIU_AMBCTL_WAT == 11)
368#define flash_EBIU_AMBCTL0_WAT B0WAT_11
369#endif
370#if (flash_EBIU_AMBCTL_WAT == 10)
371#define flash_EBIU_AMBCTL0_WAT B0WAT_10
372#endif
373#if (flash_EBIU_AMBCTL_WAT == 9)
374#define flash_EBIU_AMBCTL0_WAT B0WAT_9
375#endif
376#if (flash_EBIU_AMBCTL_WAT == 8)
377#define flash_EBIU_AMBCTL0_WAT B0WAT_8
378#endif
379#if (flash_EBIU_AMBCTL_WAT == 7)
380#define flash_EBIU_AMBCTL0_WAT B0WAT_7
381#endif
382#if (flash_EBIU_AMBCTL_WAT == 6)
383#define flash_EBIU_AMBCTL0_WAT B0WAT_6
384#endif
385#if (flash_EBIU_AMBCTL_WAT == 5)
386#define flash_EBIU_AMBCTL0_WAT B0WAT_5
387#endif
388#if (flash_EBIU_AMBCTL_WAT == 4)
389#define flash_EBIU_AMBCTL0_WAT B0WAT_4
390#endif
391#if (flash_EBIU_AMBCTL_WAT == 3)
392#define flash_EBIU_AMBCTL0_WAT B0WAT_3
393#endif
394#if (flash_EBIU_AMBCTL_WAT == 2)
395#define flash_EBIU_AMBCTL0_WAT B0WAT_2
396#endif
397#if (flash_EBIU_AMBCTL_WAT == 1)
398#define flash_EBIU_AMBCTL0_WAT B0WAT_1
399#endif
400
401#if (flash_EBIU_AMBCTL_RAT > 14)
402#define flash_EBIU_AMBCTL0_RAT B0RAT_15
403#endif
404#if (flash_EBIU_AMBCTL_RAT == 14)
405#define flash_EBIU_AMBCTL0_RAT B0RAT_14
406#endif
407#if (flash_EBIU_AMBCTL_RAT == 13)
408#define flash_EBIU_AMBCTL0_RAT B0RAT_13
409#endif
410#if (flash_EBIU_AMBCTL_RAT == 12)
411#define flash_EBIU_AMBCTL0_RAT B0RAT_12
412#endif
413#if (flash_EBIU_AMBCTL_RAT == 11)
414#define flash_EBIU_AMBCTL0_RAT B0RAT_11
415#endif
416#if (flash_EBIU_AMBCTL_RAT == 10)
417#define flash_EBIU_AMBCTL0_RAT B0RAT_10
418#endif
419#if (flash_EBIU_AMBCTL_RAT == 9)
420#define flash_EBIU_AMBCTL0_RAT B0RAT_9
421#endif
422#if (flash_EBIU_AMBCTL_RAT == 8)
423#define flash_EBIU_AMBCTL0_RAT B0RAT_8
424#endif
425#if (flash_EBIU_AMBCTL_RAT == 7)
426#define flash_EBIU_AMBCTL0_RAT B0RAT_7
427#endif
428#if (flash_EBIU_AMBCTL_RAT == 6)
429#define flash_EBIU_AMBCTL0_RAT B0RAT_6
430#endif
431#if (flash_EBIU_AMBCTL_RAT == 5)
432#define flash_EBIU_AMBCTL0_RAT B0RAT_5
433#endif
434#if (flash_EBIU_AMBCTL_RAT == 4)
435#define flash_EBIU_AMBCTL0_RAT B0RAT_4
436#endif
437#if (flash_EBIU_AMBCTL_RAT == 3)
438#define flash_EBIU_AMBCTL0_RAT B0RAT_3
439#endif
440#if (flash_EBIU_AMBCTL_RAT == 2)
441#define flash_EBIU_AMBCTL0_RAT B0RAT_2
442#endif
443#if (flash_EBIU_AMBCTL_RAT == 1)
444#define flash_EBIU_AMBCTL0_RAT B0RAT_1
445#endif
446
447#define flash_EBIU_AMBCTL0 \
448 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
449 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
450#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 4a3be376ad5b..ae8ef4ffd806 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -66,8 +66,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
66 66
67#define activate_mm(prev, next) switch_mm(prev, next, NULL) 67#define activate_mm(prev, next) switch_mm(prev, next, NULL)
68 68
69static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, 69static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
70 struct task_struct *tsk) 70 struct task_struct *tsk)
71{ 71{
72#ifdef CONFIG_MPU 72#ifdef CONFIG_MPU
73 unsigned int cpu = smp_processor_id(); 73 unsigned int cpu = smp_processor_id();
@@ -95,7 +95,24 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
95#endif 95#endif
96} 96}
97 97
98#ifdef CONFIG_IPIPE
99#define lock_mm_switch(flags) local_irq_save_hw_cond(flags)
100#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
101#else
102#define lock_mm_switch(flags) do { (void)(flags); } while (0)
103#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
104#endif /* CONFIG_IPIPE */
105
98#ifdef CONFIG_MPU 106#ifdef CONFIG_MPU
107static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
108 struct task_struct *tsk)
109{
110 unsigned long flags;
111 lock_mm_switch(flags);
112 __switch_mm(prev, next, tsk);
113 unlock_mm_switch(flags);
114}
115
99static inline void protect_page(struct mm_struct *mm, unsigned long addr, 116static inline void protect_page(struct mm_struct *mm, unsigned long addr,
100 unsigned long flags) 117 unsigned long flags)
101{ 118{
@@ -128,6 +145,12 @@ static inline void update_protections(struct mm_struct *mm)
128 set_mask_dcplbs(mm->context.page_rwx_mask, cpu); 145 set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
129 } 146 }
130} 147}
148#else /* !CONFIG_MPU */
149static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
150 struct task_struct *tsk)
151{
152 __switch_mm(prev, next, tsk);
153}
131#endif 154#endif
132 155
133static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 156static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
@@ -173,4 +196,10 @@ static inline void destroy_context(struct mm_struct *mm)
173#endif 196#endif
174} 197}
175 198
199#define ipipe_mm_switch_protect(flags) \
200 local_irq_save_hw_cond(flags)
201
202#define ipipe_mm_switch_unprotect(flags) \
203 local_irq_restore_hw_cond(flags)
204
176#endif 205#endif
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
index 61277358c865..99cae2e3bac7 100644
--- a/arch/blackfin/include/asm/pci.h
+++ b/arch/blackfin/include/asm/pci.h
@@ -4,145 +4,19 @@
4#define _ASM_BFIN_PCI_H 4#define _ASM_BFIN_PCI_H
5 5
6#include <asm/scatterlist.h> 6#include <asm/scatterlist.h>
7#include <asm-generic/pci-dma-compat.h>
8#include <asm-generic/pci.h>
7 9
8/*
9 *
10 * Written by Wout Klaren.
11 */
12
13/* Added by Chang Junxiao */
14#define PCIBIOS_MIN_IO 0x00001000 10#define PCIBIOS_MIN_IO 0x00001000
15#define PCIBIOS_MIN_MEM 0x10000000 11#define PCIBIOS_MIN_MEM 0x10000000
16 12
17#define PCI_DMA_BUS_IS_PHYS (1)
18struct pci_ops;
19
20/*
21 * Structure with hardware dependent information and functions of the
22 * PCI bus.
23 */
24struct pci_bus_info {
25
26 /*
27 * Resources of the PCI bus.
28 */
29 struct resource mem_space;
30 struct resource io_space;
31
32 /*
33 * System dependent functions.
34 */
35 struct pci_ops *bfin_pci_ops;
36 void (*fixup) (int pci_modify);
37 void (*conf_device) (unsigned char bus, unsigned char device_fn);
38};
39
40#define pcibios_assign_all_busses() 0
41static inline void pcibios_set_master(struct pci_dev *dev) 13static inline void pcibios_set_master(struct pci_dev *dev)
42{ 14{
43
44 /* No special bus mastering setup handling */ 15 /* No special bus mastering setup handling */
45} 16}
46static inline void pcibios_penalize_isa_irq(int irq) 17static inline void pcibios_penalize_isa_irq(int irq)
47{ 18{
48
49 /* We don't do dynamic PCI IRQ allocation */ 19 /* We don't do dynamic PCI IRQ allocation */
50} 20}
51static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
52 size_t size, int direction)
53{
54 if (direction == PCI_DMA_NONE)
55 BUG();
56
57 /* return virt_to_bus(ptr); */
58 return (dma_addr_t) ptr;
59}
60
61/* Unmap a single streaming mode DMA translation. The dma_addr and size
62 * must match what was provided for in a previous pci_map_single call. All
63 * other usages are undefined.
64 *
65 * After this call, reads by the cpu to the buffer are guarenteed to see
66 * whatever the device wrote there.
67 */
68static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
69 size_t size, int direction)
70{
71 if (direction == PCI_DMA_NONE)
72 BUG();
73
74 /* Nothing to do */
75}
76
77/* Map a set of buffers described by scatterlist in streaming
78 * mode for DMA. This is the scather-gather version of the
79 * above pci_map_single interface. Here the scatter gather list
80 * elements are each tagged with the appropriate dma address
81 * and length. They are obtained via sg_dma_{address,length}(SG).
82 *
83 * NOTE: An implementation may be able to use a smaller number of
84 * DMA address/length pairs than there are SG table elements.
85 * (for example via virtual mapping capabilities)
86 * The routine returns the number of addr/length pairs actually
87 * used, at most nents.
88 *
89 * Device ownership issues as mentioned above for pci_map_single are
90 * the same here.
91 */
92static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
93 int nents, int direction)
94{
95 if (direction == PCI_DMA_NONE)
96 BUG();
97 return nents;
98}
99
100/* Unmap a set of streaming mode DMA translations.
101 * Again, cpu read rules concerning calls here are the same as for
102 * pci_unmap_single() above.
103 */
104static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
105 int nents, int direction)
106{
107 if (direction == PCI_DMA_NONE)
108 BUG();
109
110 /* Nothing to do */
111}
112
113/* Make physical memory consistent for a single
114 * streaming mode DMA translation after a transfer.
115 *
116 * If you perform a pci_map_single() but wish to interrogate the
117 * buffer using the cpu, yet do not wish to teardown the PCI dma
118 * mapping, you must call this function before doing so. At the
119 * next point you give the PCI dma address back to the card, the
120 * device again owns the buffer.
121 */
122static inline void pci_dma_sync_single(struct pci_dev *hwdev,
123 dma_addr_t dma_handle, size_t size,
124 int direction)
125{
126 if (direction == PCI_DMA_NONE)
127 BUG();
128
129 /* Nothing to do */
130}
131
132/* Make physical memory consistent for a set of streaming
133 * mode DMA translations after a transfer.
134 *
135 * The same as pci_dma_sync_single but for a scatter-gather list,
136 * same rules and usage.
137 */
138static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
139 struct scatterlist *sg, int nelems,
140 int direction)
141{
142 if (direction == PCI_DMA_NONE)
143 BUG();
144
145 /* Nothing to do */
146}
147 21
148#endif /* _ASM_BFIN_PCI_H */ 22#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 27290c955a7a..b33a4488f498 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -89,9 +89,9 @@ struct pt_regs {
89#define PTRACE_GETREGS 12 89#define PTRACE_GETREGS 12
90#define PTRACE_SETREGS 13 /* ptrace signal */ 90#define PTRACE_SETREGS 13 /* ptrace signal */
91 91
92#define PTRACE_GETFDPIC 31 92#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
93#define PTRACE_GETFDPIC_EXEC 0 93#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
94#define PTRACE_GETFDPIC_INTERP 1 94#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
95 95
96#define PS_S (0x0002) 96#define PS_S (0x0002)
97 97
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 1f5381fbb4a7..42f6c53c59c6 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -13,10 +13,18 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
13extern unsigned long _ramstart, _ramend, _rambase; 13extern unsigned long _ramstart, _ramend, _rambase;
14extern unsigned long memory_start, memory_end, physical_mem_end; 14extern unsigned long memory_start, memory_end, physical_mem_end;
15 15
16extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], 16/*
17 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], 17 * The weak markings on the lengths might seem weird, but this is required
18 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], 18 * in order to make gcc accept the fact that these may actually have a value
19 _ebss_l2[], _l2_lma_start[]; 19 * of 0 (since they aren't actually addresses, but sizes of sections).
20 */
21extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
22extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
23 _data_l1_lma[], __weak _data_l1_len[];
24extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
25 _data_b_l1_lma[], __weak _data_b_l1_len[];
26extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
27 _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
20 28
21#include <asm/mem_map.h> 29#include <asm/mem_map.h>
22 30
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index afb3a8626380..a40d9368c38a 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -103,11 +103,13 @@ static inline struct thread_info *current_thread_info(void)
103#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ 103#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
104#define TIF_FREEZE 6 /* is freezing for suspend */ 104#define TIF_FREEZE 6 /* is freezing for suspend */
105#define TIF_IRQ_SYNC 7 /* sync pipeline stage */ 105#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
106#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
106 107
107/* as above, but as bit values */ 108/* as above, but as bit values */
108#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 109#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
109#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 110#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 111#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
112#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 113#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
112#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 114#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
113#define _TIF_FREEZE (1<<TIF_FREEZE) 115#define _TIF_FREEZE (1<<TIF_FREEZE)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
index 609ad3c84189..dc0aa55ae773 100644
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@@ -28,6 +28,8 @@ extern unsigned long software_trace_buff[];
28 28
29#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON 29#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
30 30
31#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
32
31#define trace_buffer_save(x) \ 33#define trace_buffer_save(x) \
32 do { \ 34 do { \
33 (x) = bfin_read_TBUFCTL(); \ 35 (x) = bfin_read_TBUFCTL(); \
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index c03b8532aad3..1c0d190adaef 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -17,9 +17,7 @@
17#include <linux/string.h> 17#include <linux/string.h>
18 18
19#include <asm/segment.h> 19#include <asm/segment.h>
20#ifdef CONFIG_ACCESS_CHECK 20#include <asm/sections.h>
21# include <asm/bfin-global.h>
22#endif
23 21
24#define get_ds() (KERNEL_DS) 22#define get_ds() (KERNEL_DS)
25#define get_fs() (current_thread_info()->addr_limit) 23#define get_fs() (current_thread_info()->addr_limit)
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 779be02a910a..22886cbdae7a 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -388,8 +388,9 @@
388#define __NR_pwritev 367 388#define __NR_pwritev 367
389#define __NR_rt_tgsigqueueinfo 368 389#define __NR_rt_tgsigqueueinfo 368
390#define __NR_perf_event_open 369 390#define __NR_perf_event_open 369
391#define __NR_recvmmsg 370
391 392
392#define __NR_syscall 370 393#define __NR_syscall 371
393#define NR_syscalls __NR_syscall 394#define NR_syscalls __NR_syscall
394 395
395/* Old optional stuff no one actually uses */ 396/* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 3946aff4f414..924c00286bab 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -37,9 +37,8 @@ static int __init blackfin_dma_init(void)
37 printk(KERN_INFO "Blackfin DMA Controller\n"); 37 printk(KERN_INFO "Blackfin DMA Controller\n");
38 38
39 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 39 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
40 dma_ch[i].chan_status = DMA_CHANNEL_FREE; 40 atomic_set(&dma_ch[i].chan_status, 0);
41 dma_ch[i].regs = dma_io_base_addr[i]; 41 dma_ch[i].regs = dma_io_base_addr[i];
42 mutex_init(&(dma_ch[i].dmalock));
43 } 42 }
44 /* Mark MEMDMA Channel 0 as requested since we're using it internally */ 43 /* Mark MEMDMA Channel 0 as requested since we're using it internally */
45 request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); 44 request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
@@ -60,7 +59,7 @@ static int proc_dma_show(struct seq_file *m, void *v)
60 int i; 59 int i;
61 60
62 for (i = 0; i < MAX_DMA_CHANNELS; ++i) 61 for (i = 0; i < MAX_DMA_CHANNELS; ++i)
63 if (dma_ch[i].chan_status != DMA_CHANNEL_FREE) 62 if (dma_channel_active(i))
64 seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); 63 seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
65 64
66 return 0; 65 return 0;
@@ -107,20 +106,11 @@ int request_dma(unsigned int channel, const char *device_id)
107 } 106 }
108#endif 107#endif
109 108
110 mutex_lock(&(dma_ch[channel].dmalock)); 109 if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
111
112 if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
113 || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
114 mutex_unlock(&(dma_ch[channel].dmalock));
115 pr_debug("DMA CHANNEL IN USE \n"); 110 pr_debug("DMA CHANNEL IN USE \n");
116 return -EBUSY; 111 return -EBUSY;
117 } else {
118 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
119 pr_debug("DMA CHANNEL IS ALLOCATED \n");
120 } 112 }
121 113
122 mutex_unlock(&(dma_ch[channel].dmalock));
123
124#ifdef CONFIG_BF54x 114#ifdef CONFIG_BF54x
125 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { 115 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
126 unsigned int per_map; 116 unsigned int per_map;
@@ -148,21 +138,20 @@ EXPORT_SYMBOL(request_dma);
148 138
149int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) 139int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
150{ 140{
151 BUG_ON(channel >= MAX_DMA_CHANNELS || 141 int ret;
152 dma_ch[channel].chan_status == DMA_CHANNEL_FREE); 142 unsigned int irq;
153 143
154 if (callback != NULL) { 144 BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
155 int ret; 145 !atomic_read(&dma_ch[channel].chan_status));
156 unsigned int irq = channel2irq(channel);
157 146
158 ret = request_irq(irq, callback, IRQF_DISABLED, 147 irq = channel2irq(channel);
159 dma_ch[channel].device_id, data); 148 ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
160 if (ret) 149 if (ret)
161 return ret; 150 return ret;
151
152 dma_ch[channel].irq = irq;
153 dma_ch[channel].data = data;
162 154
163 dma_ch[channel].irq = irq;
164 dma_ch[channel].data = data;
165 }
166 return 0; 155 return 0;
167} 156}
168EXPORT_SYMBOL(set_dma_callback); 157EXPORT_SYMBOL(set_dma_callback);
@@ -184,7 +173,7 @@ void free_dma(unsigned int channel)
184{ 173{
185 pr_debug("freedma() : BEGIN \n"); 174 pr_debug("freedma() : BEGIN \n");
186 BUG_ON(channel >= MAX_DMA_CHANNELS || 175 BUG_ON(channel >= MAX_DMA_CHANNELS ||
187 dma_ch[channel].chan_status == DMA_CHANNEL_FREE); 176 !atomic_read(&dma_ch[channel].chan_status));
188 177
189 /* Halt the DMA */ 178 /* Halt the DMA */
190 disable_dma(channel); 179 disable_dma(channel);
@@ -194,9 +183,7 @@ void free_dma(unsigned int channel)
194 free_irq(dma_ch[channel].irq, dma_ch[channel].data); 183 free_irq(dma_ch[channel].irq, dma_ch[channel].data);
195 184
196 /* Clear the DMA Variable in the Channel */ 185 /* Clear the DMA Variable in the Channel */
197 mutex_lock(&(dma_ch[channel].dmalock)); 186 atomic_set(&dma_ch[channel].chan_status, 0);
198 dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
199 mutex_unlock(&(dma_ch[channel].dmalock));
200 187
201 pr_debug("freedma() : END \n"); 188 pr_debug("freedma() : END \n");
202} 189}
@@ -210,13 +197,14 @@ int blackfin_dma_suspend(void)
210{ 197{
211 int i; 198 int i;
212 199
213 for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) { 200 for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
214 if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { 201 if (dma_ch[i].regs->cfg & DMAEN) {
215 printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); 202 printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
216 return -EBUSY; 203 return -EBUSY;
217 } 204 }
218 205
219 dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; 206 if (i < MAX_DMA_SUSPEND_CHANNELS)
207 dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
220 } 208 }
221 209
222 return 0; 210 return 0;
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 22705eeff34f..a174596cc009 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -100,6 +100,12 @@ u8 pmux_offset[][16] = {
100}; 100};
101# endif 101# endif
102 102
103#elif defined(BF538_FAMILY)
104static unsigned short * const port_fer[] = {
105 (unsigned short *) PORTCIO_FER,
106 (unsigned short *) PORTDIO_FER,
107 (unsigned short *) PORTEIO_FER,
108};
103#endif 109#endif
104 110
105static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; 111static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
@@ -163,6 +169,27 @@ static int cmp_label(unsigned short ident, const char *label)
163 169
164static void port_setup(unsigned gpio, unsigned short usage) 170static void port_setup(unsigned gpio, unsigned short usage)
165{ 171{
172#if defined(BF538_FAMILY)
173 /*
174 * BF538/9 Port C,D and E are special.
175 * Inverted PORT_FER polarity on CDE and no PORF_FER on F
176 * Regular PORT F GPIOs are handled here, CDE are exclusively
177 * managed by GPIOLIB
178 */
179
180 if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
181 return;
182
183 gpio -= MAX_BLACKFIN_GPIOS;
184
185 if (usage == GPIO_USAGE)
186 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
187 else
188 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
189 SSYNC();
190 return;
191#endif
192
166 if (check_gpio(gpio)) 193 if (check_gpio(gpio))
167 return; 194 return;
168 195
@@ -762,6 +789,8 @@ int peripheral_request(unsigned short per, const char *label)
762 if (!(per & P_DEFINED)) 789 if (!(per & P_DEFINED))
763 return -ENODEV; 790 return -ENODEV;
764 791
792 BUG_ON(ident >= MAX_RESOURCES);
793
765 local_irq_save_hw(flags); 794 local_irq_save_hw(flags);
766 795
767 /* If a pin can be muxed as either GPIO or peripheral, make 796 /* If a pin can be muxed as either GPIO or peripheral, make
@@ -979,6 +1008,76 @@ void bfin_gpio_free(unsigned gpio)
979} 1008}
980EXPORT_SYMBOL(bfin_gpio_free); 1009EXPORT_SYMBOL(bfin_gpio_free);
981 1010
1011#ifdef BFIN_SPECIAL_GPIO_BANKS
1012static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)];
1013
1014int bfin_special_gpio_request(unsigned gpio, const char *label)
1015{
1016 unsigned long flags;
1017
1018 local_irq_save_hw(flags);
1019
1020 /*
1021 * Allow that the identical GPIO can
1022 * be requested from the same driver twice
1023 * Do nothing and return -
1024 */
1025
1026 if (cmp_label(gpio, label) == 0) {
1027 local_irq_restore_hw(flags);
1028 return 0;
1029 }
1030
1031 if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1032 local_irq_restore_hw(flags);
1033 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1034 gpio, get_label(gpio));
1035
1036 return -EBUSY;
1037 }
1038 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1039 local_irq_restore_hw(flags);
1040 printk(KERN_ERR
1041 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1042 gpio, get_label(gpio));
1043
1044 return -EBUSY;
1045 }
1046
1047 reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1048 reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1049
1050 set_label(gpio, label);
1051 local_irq_restore_hw(flags);
1052 port_setup(gpio, GPIO_USAGE);
1053
1054 return 0;
1055}
1056EXPORT_SYMBOL(bfin_special_gpio_request);
1057
1058void bfin_special_gpio_free(unsigned gpio)
1059{
1060 unsigned long flags;
1061
1062 might_sleep();
1063
1064 local_irq_save_hw(flags);
1065
1066 if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1067 gpio_error(gpio);
1068 local_irq_restore_hw(flags);
1069 return;
1070 }
1071
1072 reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1073 reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1074 set_label(gpio, "free");
1075 local_irq_restore_hw(flags);
1076}
1077EXPORT_SYMBOL(bfin_special_gpio_free);
1078#endif
1079
1080
982int bfin_gpio_irq_request(unsigned gpio, const char *label) 1081int bfin_gpio_irq_request(unsigned gpio, const char *label)
983{ 1082{
984 unsigned long flags; 1083 unsigned long flags;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index b52c1f8c4bc0..8d42b9e50dfa 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -92,6 +92,6 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
92 icplb_tbl[cpu][i_i++].data = 0; 92 icplb_tbl[cpu][i_i++].data = 0;
93} 93}
94 94
95void generate_cplb_tables_all(void) 95void __init generate_cplb_tables_all(void)
96{ 96{
97} 97}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 69e0e530d70f..930c01c06813 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu)
113 addr = L2_START; 113 addr = L2_START;
114 d_data = L2_DMEMORY; 114 d_data = L2_DMEMORY;
115 } else if (addr >= physical_mem_end) { 115 } else if (addr >= physical_mem_end) {
116 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE 116 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
117 && (status & FAULT_USERSUPV)) { 117 addr &= ~(4 * 1024 * 1024 - 1);
118 addr &= ~0x3fffff;
119 d_data &= ~PAGE_SIZE_4KB; 118 d_data &= ~PAGE_SIZE_4KB;
120 d_data |= PAGE_SIZE_4MB; 119 d_data |= PAGE_SIZE_4MB;
120 d_data |= CPLB_USER_RD | CPLB_USER_WR;
121 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH 121 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
122 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { 122 && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
123 addr &= ~(1 * 1024 * 1024 - 1); 123 addr &= ~(1 * 1024 * 1024 - 1);
@@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu)
203 addr = L2_START; 203 addr = L2_START;
204 i_data = L2_IMEMORY; 204 i_data = L2_IMEMORY;
205 } else if (addr >= physical_mem_end) { 205 } else if (addr >= physical_mem_end) {
206 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH 206 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
207 addr &= ~(4 * 1024 * 1024 - 1);
208 i_data &= ~PAGE_SIZE_4KB;
209 i_data |= PAGE_SIZE_4MB;
210 i_data |= CPLB_USER_RD;
211 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
207 && (status & FAULT_USERSUPV)) { 212 && (status & FAULT_USERSUPV)) {
208 addr &= ~(1 * 1024 * 1024 - 1); 213 addr &= ~(1 * 1024 * 1024 - 1);
209 i_data &= ~PAGE_SIZE_4KB; 214 i_data &= ~PAGE_SIZE_4KB;
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index fd9a2f31e686..282a7919821b 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -89,15 +89,25 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
89 89
90void __init generate_cplb_tables_all(void) 90void __init generate_cplb_tables_all(void)
91{ 91{
92 unsigned long uncached_end;
92 int i_d, i_i; 93 int i_d, i_i;
93 94
94 i_d = 0; 95 i_d = 0;
95 /* Normal RAM, including MTD FS. */ 96 /* Normal RAM, including MTD FS. */
96#ifdef CONFIG_MTD_UCLINUX 97#ifdef CONFIG_MTD_UCLINUX
97 dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size; 98 uncached_end = memory_mtd_start + mtd_size;
98#else 99#else
99 dcplb_bounds[i_d].eaddr = memory_end; 100 uncached_end = memory_end;
100#endif 101#endif
102 /*
103 * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
104 * so that we don't have to use 4kB pages and cause CPLB thrashing
105 */
106 if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
107 ((_ramend - uncached_end) >= 1 * 1024 * 1024))
108 dcplb_bounds[i_d].eaddr = uncached_end;
109 else
110 dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
101 dcplb_bounds[i_d++].data = SDRAM_DGENERIC; 111 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
102 /* DMA uncached region. */ 112 /* DMA uncached region. */
103 if (DMA_UNCACHED_REGION) { 113 if (DMA_UNCACHED_REGION) {
@@ -135,18 +145,15 @@ void __init generate_cplb_tables_all(void)
135 145
136 i_i = 0; 146 i_i = 0;
137 /* Normal RAM, including MTD FS. */ 147 /* Normal RAM, including MTD FS. */
138#ifdef CONFIG_MTD_UCLINUX 148 icplb_bounds[i_i].eaddr = uncached_end;
139 icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
140#else
141 icplb_bounds[i_i].eaddr = memory_end;
142#endif
143 icplb_bounds[i_i++].data = SDRAM_IGENERIC; 149 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
144 /* DMA uncached region. */
145 if (DMA_UNCACHED_REGION) {
146 icplb_bounds[i_i].eaddr = _ramend;
147 icplb_bounds[i_i++].data = 0;
148 }
149 if (_ramend != physical_mem_end) { 150 if (_ramend != physical_mem_end) {
151 /* DMA uncached region. */
152 if (DMA_UNCACHED_REGION) {
153 /* Normally this hole is caught by the async below. */
154 icplb_bounds[i_i].eaddr = _ramend;
155 icplb_bounds[i_i++].data = 0;
156 }
150 /* Reserved memory. */ 157 /* Reserved memory. */
151 icplb_bounds[i_i].eaddr = physical_mem_end; 158 icplb_bounds[i_i].eaddr = physical_mem_end;
152 icplb_bounds[i_i++].data = (reserved_mem_icache_on ? 159 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index e74e74d7733f..e937f323d82c 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -7,30 +7,25 @@
7 */ 7 */
8 8
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/mm.h> 10#include <linux/gfp.h>
11#include <linux/string.h> 11#include <linux/string.h>
12#include <linux/bootmem.h>
13#include <linux/spinlock.h> 12#include <linux/spinlock.h>
14#include <linux/device.h>
15#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
16#include <linux/io.h>
17#include <linux/scatterlist.h> 14#include <linux/scatterlist.h>
18#include <asm/cacheflush.h>
19#include <asm/bfin-global.h>
20 15
21static spinlock_t dma_page_lock; 16static spinlock_t dma_page_lock;
22static unsigned int *dma_page; 17static unsigned long *dma_page;
23static unsigned int dma_pages; 18static unsigned int dma_pages;
24static unsigned long dma_base; 19static unsigned long dma_base;
25static unsigned long dma_size; 20static unsigned long dma_size;
26static unsigned int dma_initialized; 21static unsigned int dma_initialized;
27 22
28void dma_alloc_init(unsigned long start, unsigned long end) 23static void dma_alloc_init(unsigned long start, unsigned long end)
29{ 24{
30 spin_lock_init(&dma_page_lock); 25 spin_lock_init(&dma_page_lock);
31 dma_initialized = 0; 26 dma_initialized = 0;
32 27
33 dma_page = (unsigned int *)__get_free_page(GFP_KERNEL); 28 dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
34 memset(dma_page, 0, PAGE_SIZE); 29 memset(dma_page, 0, PAGE_SIZE);
35 dma_base = PAGE_ALIGN(start); 30 dma_base = PAGE_ALIGN(start);
36 dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start); 31 dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
@@ -58,10 +53,11 @@ static unsigned long __alloc_dma_pages(unsigned int pages)
58 spin_lock_irqsave(&dma_page_lock, flags); 53 spin_lock_irqsave(&dma_page_lock, flags);
59 54
60 for (i = 0; i < dma_pages;) { 55 for (i = 0; i < dma_pages;) {
61 if (dma_page[i++] == 0) { 56 if (test_bit(i++, dma_page) == 0) {
62 if (++count == pages) { 57 if (++count == pages) {
63 while (count--) 58 while (count--)
64 dma_page[--i] = 1; 59 __set_bit(--i, dma_page);
60
65 ret = dma_base + (i << PAGE_SHIFT); 61 ret = dma_base + (i << PAGE_SHIFT);
66 break; 62 break;
67 } 63 }
@@ -84,14 +80,14 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages)
84 } 80 }
85 81
86 spin_lock_irqsave(&dma_page_lock, flags); 82 spin_lock_irqsave(&dma_page_lock, flags);
87 for (i = page; i < page + pages; i++) { 83 for (i = page; i < page + pages; i++)
88 dma_page[i] = 0; 84 __clear_bit(i, dma_page);
89 } 85
90 spin_unlock_irqrestore(&dma_page_lock, flags); 86 spin_unlock_irqrestore(&dma_page_lock, flags);
91} 87}
92 88
93void *dma_alloc_coherent(struct device *dev, size_t size, 89void *dma_alloc_coherent(struct device *dev, size_t size,
94 dma_addr_t * dma_handle, gfp_t gfp) 90 dma_addr_t *dma_handle, gfp_t gfp)
95{ 91{
96 void *ret; 92 void *ret;
97 93
@@ -115,21 +111,14 @@ dma_free_coherent(struct device *dev, size_t size, void *vaddr,
115EXPORT_SYMBOL(dma_free_coherent); 111EXPORT_SYMBOL(dma_free_coherent);
116 112
117/* 113/*
118 * Dummy functions defined for some existing drivers 114 * Streaming DMA mappings
119 */ 115 */
120 116void __dma_sync(dma_addr_t addr, size_t size,
121dma_addr_t 117 enum dma_data_direction dir)
122dma_map_single(struct device *dev, void *ptr, size_t size,
123 enum dma_data_direction direction)
124{ 118{
125 BUG_ON(direction == DMA_NONE); 119 _dma_sync(addr, size, dir);
126
127 invalidate_dcache_range((unsigned long)ptr,
128 (unsigned long)ptr + size);
129
130 return (dma_addr_t) ptr;
131} 120}
132EXPORT_SYMBOL(dma_map_single); 121EXPORT_SYMBOL(__dma_sync);
133 122
134int 123int
135dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 124dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
@@ -137,30 +126,23 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
137{ 126{
138 int i; 127 int i;
139 128
140 BUG_ON(direction == DMA_NONE);
141
142 for (i = 0; i < nents; i++, sg++) { 129 for (i = 0; i < nents; i++, sg++) {
143 sg->dma_address = (dma_addr_t) sg_virt(sg); 130 sg->dma_address = (dma_addr_t) sg_virt(sg);
144 131 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
145 invalidate_dcache_range(sg_dma_address(sg),
146 sg_dma_address(sg) +
147 sg_dma_len(sg));
148 } 132 }
149 133
150 return nents; 134 return nents;
151} 135}
152EXPORT_SYMBOL(dma_map_sg); 136EXPORT_SYMBOL(dma_map_sg);
153 137
154void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 138void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
155 enum dma_data_direction direction) 139 int nelems, enum dma_data_direction direction)
156{ 140{
157 BUG_ON(direction == DMA_NONE); 141 int i;
158}
159EXPORT_SYMBOL(dma_unmap_single);
160 142
161void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 143 for (i = 0; i < nelems; i++, sg++) {
162 int nhwentries, enum dma_data_direction direction) 144 sg->dma_address = (dma_addr_t) sg_virt(sg);
163{ 145 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
164 BUG_ON(direction == DMA_NONE); 146 }
165} 147}
166EXPORT_SYMBOL(dma_unmap_sg); 148EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 7281a91d26b5..cdbe075de1dc 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -137,7 +137,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
137#endif 137#endif
138}; 138};
139 139
140void set_gptimer_pwidth(int timer_id, uint32_t value) 140void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
141{ 141{
142 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 142 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
143 timer_regs[timer_id]->width = value; 143 timer_regs[timer_id]->width = value;
@@ -145,14 +145,14 @@ void set_gptimer_pwidth(int timer_id, uint32_t value)
145} 145}
146EXPORT_SYMBOL(set_gptimer_pwidth); 146EXPORT_SYMBOL(set_gptimer_pwidth);
147 147
148uint32_t get_gptimer_pwidth(int timer_id) 148uint32_t get_gptimer_pwidth(unsigned int timer_id)
149{ 149{
150 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 150 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
151 return timer_regs[timer_id]->width; 151 return timer_regs[timer_id]->width;
152} 152}
153EXPORT_SYMBOL(get_gptimer_pwidth); 153EXPORT_SYMBOL(get_gptimer_pwidth);
154 154
155void set_gptimer_period(int timer_id, uint32_t period) 155void set_gptimer_period(unsigned int timer_id, uint32_t period)
156{ 156{
157 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 157 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
158 timer_regs[timer_id]->period = period; 158 timer_regs[timer_id]->period = period;
@@ -160,28 +160,28 @@ void set_gptimer_period(int timer_id, uint32_t period)
160} 160}
161EXPORT_SYMBOL(set_gptimer_period); 161EXPORT_SYMBOL(set_gptimer_period);
162 162
163uint32_t get_gptimer_period(int timer_id) 163uint32_t get_gptimer_period(unsigned int timer_id)
164{ 164{
165 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 165 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
166 return timer_regs[timer_id]->period; 166 return timer_regs[timer_id]->period;
167} 167}
168EXPORT_SYMBOL(get_gptimer_period); 168EXPORT_SYMBOL(get_gptimer_period);
169 169
170uint32_t get_gptimer_count(int timer_id) 170uint32_t get_gptimer_count(unsigned int timer_id)
171{ 171{
172 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 172 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
173 return timer_regs[timer_id]->counter; 173 return timer_regs[timer_id]->counter;
174} 174}
175EXPORT_SYMBOL(get_gptimer_count); 175EXPORT_SYMBOL(get_gptimer_count);
176 176
177uint32_t get_gptimer_status(int group) 177uint32_t get_gptimer_status(unsigned int group)
178{ 178{
179 tassert(group < BFIN_TIMER_NUM_GROUP); 179 tassert(group < BFIN_TIMER_NUM_GROUP);
180 return group_regs[group]->status; 180 return group_regs[group]->status;
181} 181}
182EXPORT_SYMBOL(get_gptimer_status); 182EXPORT_SYMBOL(get_gptimer_status);
183 183
184void set_gptimer_status(int group, uint32_t value) 184void set_gptimer_status(unsigned int group, uint32_t value)
185{ 185{
186 tassert(group < BFIN_TIMER_NUM_GROUP); 186 tassert(group < BFIN_TIMER_NUM_GROUP);
187 group_regs[group]->status = value; 187 group_regs[group]->status = value;
@@ -189,42 +189,42 @@ void set_gptimer_status(int group, uint32_t value)
189} 189}
190EXPORT_SYMBOL(set_gptimer_status); 190EXPORT_SYMBOL(set_gptimer_status);
191 191
192int get_gptimer_intr(int timer_id) 192int get_gptimer_intr(unsigned int timer_id)
193{ 193{
194 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 194 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
195 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); 195 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]);
196} 196}
197EXPORT_SYMBOL(get_gptimer_intr); 197EXPORT_SYMBOL(get_gptimer_intr);
198 198
199void clear_gptimer_intr(int timer_id) 199void clear_gptimer_intr(unsigned int timer_id)
200{ 200{
201 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 201 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
202 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id]; 202 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id];
203} 203}
204EXPORT_SYMBOL(clear_gptimer_intr); 204EXPORT_SYMBOL(clear_gptimer_intr);
205 205
206int get_gptimer_over(int timer_id) 206int get_gptimer_over(unsigned int timer_id)
207{ 207{
208 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 208 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
209 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); 209 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]);
210} 210}
211EXPORT_SYMBOL(get_gptimer_over); 211EXPORT_SYMBOL(get_gptimer_over);
212 212
213void clear_gptimer_over(int timer_id) 213void clear_gptimer_over(unsigned int timer_id)
214{ 214{
215 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 215 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
216 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id]; 216 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id];
217} 217}
218EXPORT_SYMBOL(clear_gptimer_over); 218EXPORT_SYMBOL(clear_gptimer_over);
219 219
220int get_gptimer_run(int timer_id) 220int get_gptimer_run(unsigned int timer_id)
221{ 221{
222 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 222 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
223 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); 223 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]);
224} 224}
225EXPORT_SYMBOL(get_gptimer_run); 225EXPORT_SYMBOL(get_gptimer_run);
226 226
227void set_gptimer_config(int timer_id, uint16_t config) 227void set_gptimer_config(unsigned int timer_id, uint16_t config)
228{ 228{
229 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 229 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
230 timer_regs[timer_id]->config = config; 230 timer_regs[timer_id]->config = config;
@@ -232,7 +232,7 @@ void set_gptimer_config(int timer_id, uint16_t config)
232} 232}
233EXPORT_SYMBOL(set_gptimer_config); 233EXPORT_SYMBOL(set_gptimer_config);
234 234
235uint16_t get_gptimer_config(int timer_id) 235uint16_t get_gptimer_config(unsigned int timer_id)
236{ 236{
237 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 237 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
238 return timer_regs[timer_id]->config; 238 return timer_regs[timer_id]->config;
@@ -280,7 +280,7 @@ void disable_gptimers_sync(uint16_t mask)
280} 280}
281EXPORT_SYMBOL(disable_gptimers_sync); 281EXPORT_SYMBOL(disable_gptimers_sync);
282 282
283void set_gptimer_pulse_hi(int timer_id) 283void set_gptimer_pulse_hi(unsigned int timer_id)
284{ 284{
285 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 285 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
286 timer_regs[timer_id]->config |= TIMER_PULSE_HI; 286 timer_regs[timer_id]->config |= TIMER_PULSE_HI;
@@ -288,7 +288,7 @@ void set_gptimer_pulse_hi(int timer_id)
288} 288}
289EXPORT_SYMBOL(set_gptimer_pulse_hi); 289EXPORT_SYMBOL(set_gptimer_pulse_hi);
290 290
291void clear_gptimer_pulse_hi(int timer_id) 291void clear_gptimer_pulse_hi(unsigned int timer_id)
292{ 292{
293 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 293 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
294 timer_regs[timer_id]->config &= ~TIMER_PULSE_HI; 294 timer_regs[timer_id]->config &= ~TIMER_PULSE_HI;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 5d7382396dc0..a77307a4473b 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -335,3 +335,70 @@ void __ipipe_enable_root_irqs_hw(void)
335 __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); 335 __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
336 bfin_sti(bfin_irq_flags); 336 bfin_sti(bfin_irq_flags);
337} 337}
338
339/*
340 * We could use standard atomic bitops in the following root status
341 * manipulation routines, but let's prepare for SMP support in the
342 * same move, preventing CPU migration as required.
343 */
344void __ipipe_stall_root(void)
345{
346 unsigned long *p, flags;
347
348 local_irq_save_hw(flags);
349 p = &__ipipe_root_status;
350 __set_bit(IPIPE_STALL_FLAG, p);
351 local_irq_restore_hw(flags);
352}
353EXPORT_SYMBOL(__ipipe_stall_root);
354
355unsigned long __ipipe_test_and_stall_root(void)
356{
357 unsigned long *p, flags;
358 int x;
359
360 local_irq_save_hw(flags);
361 p = &__ipipe_root_status;
362 x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
363 local_irq_restore_hw(flags);
364
365 return x;
366}
367EXPORT_SYMBOL(__ipipe_test_and_stall_root);
368
369unsigned long __ipipe_test_root(void)
370{
371 const unsigned long *p;
372 unsigned long flags;
373 int x;
374
375 local_irq_save_hw_smp(flags);
376 p = &__ipipe_root_status;
377 x = test_bit(IPIPE_STALL_FLAG, p);
378 local_irq_restore_hw_smp(flags);
379
380 return x;
381}
382EXPORT_SYMBOL(__ipipe_test_root);
383
384void __ipipe_lock_root(void)
385{
386 unsigned long *p, flags;
387
388 local_irq_save_hw(flags);
389 p = &__ipipe_root_status;
390 __set_bit(IPIPE_SYNCDEFER_FLAG, p);
391 local_irq_restore_hw(flags);
392}
393EXPORT_SYMBOL(__ipipe_lock_root);
394
395void __ipipe_unlock_root(void)
396{
397 unsigned long *p, flags;
398
399 local_irq_save_hw(flags);
400 p = &__ipipe_root_status;
401 __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
402 local_irq_restore_hw(flags);
403}
404EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index cce79d05b90b..f1036b6b9293 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -24,16 +24,6 @@
24#include <asm/blackfin.h> 24#include <asm/blackfin.h>
25#include <asm/dma.h> 25#include <asm/dma.h>
26 26
27/* Put the error code here just in case the user cares. */
28int gdb_bfin_errcode;
29/* Likewise, the vector number here (since GDB only gets the signal
30 number through the usual means, and that's not very specific). */
31int gdb_bfin_vector = -1;
32
33#if KGDB_MAX_NO_CPUS != 8
34#error change the definition of slavecpulocks
35#endif
36
37void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) 27void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
38{ 28{
39 gdb_regs[BFIN_R0] = regs->r0; 29 gdb_regs[BFIN_R0] = regs->r0;
@@ -369,13 +359,6 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
369} 359}
370#endif 360#endif
371 361
372void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
373{
374 /* Master processor is completely in the debugger */
375 gdb_bfin_vector = eVector;
376 gdb_bfin_errcode = err_code;
377}
378
379int kgdb_arch_handle_exception(int vector, int signo, 362int kgdb_arch_handle_exception(int vector, int signo,
380 int err_code, char *remcom_in_buffer, 363 int err_code, char *remcom_in_buffer,
381 char *remcom_out_buffer, 364 char *remcom_out_buffer,
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 59fc42dc5d6a..9a4b07594389 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -17,8 +17,9 @@
17 17
18#include <asm/blackfin.h> 18#include <asm/blackfin.h>
19 19
20/* Symbols are here for kgdb test to poke directly */
20static char cmdline[256]; 21static char cmdline[256];
21static unsigned long len; 22static size_t len;
22 23
23#ifndef CONFIG_SMP 24#ifndef CONFIG_SMP
24static int num1 __attribute__((l1_data)); 25static int num1 __attribute__((l1_data));
@@ -27,11 +28,10 @@ void kgdb_l1_test(void) __attribute__((l1_text));
27 28
28void kgdb_l1_test(void) 29void kgdb_l1_test(void)
29{ 30{
30 printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); 31 pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
31 printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test); 32 pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
32 num1 = num1 + 10 ; 33 num1 = num1 + 10;
33 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); 34 pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
34 return ;
35} 35}
36#endif 36#endif
37 37
@@ -42,11 +42,10 @@ void kgdb_l2_test(void) __attribute__((l2));
42 42
43void kgdb_l2_test(void) 43void kgdb_l2_test(void)
44{ 44{
45 printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); 45 pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
46 printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test); 46 pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
47 num2 = num2 + 20 ; 47 num2 = num2 + 20;
48 printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); 48 pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
49 return ;
50} 49}
51 50
52#endif 51#endif
@@ -54,12 +53,14 @@ void kgdb_l2_test(void)
54 53
55int kgdb_test(char *name, int len, int count, int z) 54int kgdb_test(char *name, int len, int count, int z)
56{ 55{
57 printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z); 56 pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
58 count = z; 57 count = z;
59 return count; 58 return count;
60} 59}
61 60
62static int test_proc_output(char *buf) 61static ssize_t
62kgdb_test_proc_read(struct file *file, char __user *buf,
63 size_t count, loff_t *ppos)
63{ 64{
64 kgdb_test("hello world!", 12, 0x55, 0x10); 65 kgdb_test("hello world!", 12, 0x55, 0x10);
65#ifndef CONFIG_SMP 66#ifndef CONFIG_SMP
@@ -72,49 +73,31 @@ static int test_proc_output(char *buf)
72 return 0; 73 return 0;
73} 74}
74 75
75static int test_read_proc(char *page, char **start, off_t off, 76static ssize_t
76 int count, int *eof, void *data) 77kgdb_test_proc_write(struct file *file, const char __user *buffer,
78 size_t count, loff_t *pos)
77{ 79{
78 int len; 80 len = min_t(size_t, 255, count);
79
80 len = test_proc_output(page);
81 if (len <= off+count)
82 *eof = 1;
83 *start = page + off;
84 len -= off;
85 if (len > count)
86 len = count;
87 if (len < 0)
88 len = 0;
89 return len;
90}
91
92static int test_write_proc(struct file *file, const char *buffer,
93 unsigned long count, void *data)
94{
95 if (count >= 256)
96 len = 255;
97 else
98 len = count;
99
100 memcpy(cmdline, buffer, count); 81 memcpy(cmdline, buffer, count);
101 cmdline[len] = 0; 82 cmdline[len] = 0;
102 83
103 return len; 84 return len;
104} 85}
105 86
87static const struct file_operations kgdb_test_proc_fops = {
88 .owner = THIS_MODULE,
89 .read = kgdb_test_proc_read,
90 .write = kgdb_test_proc_write,
91};
92
106static int __init kgdbtest_init(void) 93static int __init kgdbtest_init(void)
107{ 94{
108 struct proc_dir_entry *entry; 95 struct proc_dir_entry *entry;
109 96
110 entry = create_proc_entry("kgdbtest", 0, NULL); 97 entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
111 if (entry == NULL) 98 if (entry == NULL)
112 return -ENOMEM; 99 return -ENOMEM;
113 100
114 entry->read_proc = test_read_proc;
115 entry->write_proc = test_write_proc;
116 entry->data = NULL;
117
118 return 0; 101 return 0;
119} 102}
120 103
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 45876427eb2d..b56b0e485e0b 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -258,9 +258,12 @@ void finish_atomic_sections (struct pt_regs *regs)
258 int __user *up0 = (int __user *)regs->p0; 258 int __user *up0 = (int __user *)regs->p0;
259 259
260 switch (regs->pc) { 260 switch (regs->pc) {
261 default:
262 /* not in middle of an atomic step, so resume like normal */
263 return;
264
261 case ATOMIC_XCHG32 + 2: 265 case ATOMIC_XCHG32 + 2:
262 put_user(regs->r1, up0); 266 put_user(regs->r1, up0);
263 regs->pc = ATOMIC_XCHG32 + 4;
264 break; 267 break;
265 268
266 case ATOMIC_CAS32 + 2: 269 case ATOMIC_CAS32 + 2:
@@ -268,7 +271,6 @@ void finish_atomic_sections (struct pt_regs *regs)
268 if (regs->r0 == regs->r1) 271 if (regs->r0 == regs->r1)
269 case ATOMIC_CAS32 + 6: 272 case ATOMIC_CAS32 + 6:
270 put_user(regs->r2, up0); 273 put_user(regs->r2, up0);
271 regs->pc = ATOMIC_CAS32 + 8;
272 break; 274 break;
273 275
274 case ATOMIC_ADD32 + 2: 276 case ATOMIC_ADD32 + 2:
@@ -276,7 +278,6 @@ void finish_atomic_sections (struct pt_regs *regs)
276 /* fall through */ 278 /* fall through */
277 case ATOMIC_ADD32 + 4: 279 case ATOMIC_ADD32 + 4:
278 put_user(regs->r0, up0); 280 put_user(regs->r0, up0);
279 regs->pc = ATOMIC_ADD32 + 6;
280 break; 281 break;
281 282
282 case ATOMIC_SUB32 + 2: 283 case ATOMIC_SUB32 + 2:
@@ -284,7 +285,6 @@ void finish_atomic_sections (struct pt_regs *regs)
284 /* fall through */ 285 /* fall through */
285 case ATOMIC_SUB32 + 4: 286 case ATOMIC_SUB32 + 4:
286 put_user(regs->r0, up0); 287 put_user(regs->r0, up0);
287 regs->pc = ATOMIC_SUB32 + 6;
288 break; 288 break;
289 289
290 case ATOMIC_IOR32 + 2: 290 case ATOMIC_IOR32 + 2:
@@ -292,7 +292,6 @@ void finish_atomic_sections (struct pt_regs *regs)
292 /* fall through */ 292 /* fall through */
293 case ATOMIC_IOR32 + 4: 293 case ATOMIC_IOR32 + 4:
294 put_user(regs->r0, up0); 294 put_user(regs->r0, up0);
295 regs->pc = ATOMIC_IOR32 + 6;
296 break; 295 break;
297 296
298 case ATOMIC_AND32 + 2: 297 case ATOMIC_AND32 + 2:
@@ -300,7 +299,6 @@ void finish_atomic_sections (struct pt_regs *regs)
300 /* fall through */ 299 /* fall through */
301 case ATOMIC_AND32 + 4: 300 case ATOMIC_AND32 + 4:
302 put_user(regs->r0, up0); 301 put_user(regs->r0, up0);
303 regs->pc = ATOMIC_AND32 + 6;
304 break; 302 break;
305 303
306 case ATOMIC_XOR32 + 2: 304 case ATOMIC_XOR32 + 2:
@@ -308,9 +306,15 @@ void finish_atomic_sections (struct pt_regs *regs)
308 /* fall through */ 306 /* fall through */
309 case ATOMIC_XOR32 + 4: 307 case ATOMIC_XOR32 + 4:
310 put_user(regs->r0, up0); 308 put_user(regs->r0, up0);
311 regs->pc = ATOMIC_XOR32 + 6;
312 break; 309 break;
313 } 310 }
311
312 /*
313 * We've finished the atomic section, and the only thing left for
314 * userspace is to do a RTS, so we might as well handle that too
315 * since we need to update the PC anyways.
316 */
317 regs->pc = regs->rets;
314} 318}
315 319
316static inline 320static inline
@@ -332,12 +336,58 @@ int in_mem_const(unsigned long addr, unsigned long size,
332{ 336{
333 return in_mem_const_off(addr, size, 0, const_addr, const_size); 337 return in_mem_const_off(addr, size, 0, const_addr, const_size);
334} 338}
335#define IN_ASYNC(bnum, bctlnum) \ 339#define ASYNC_ENABLED(bnum, bctlnum) \
336({ \ 340({ \
337 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ 341 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
338 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ 342 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
339 BFIN_MEM_ACCESS_CORE; \ 343 1; \
340}) 344})
345/*
346 * We can't read EBIU banks that aren't enabled or we end up hanging
347 * on the access to the async space. Make sure we validate accesses
348 * that cross async banks too.
349 * 0 - found, but unusable
350 * 1 - found & usable
351 * 2 - not found
352 */
353static
354int in_async(unsigned long addr, unsigned long size)
355{
356 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
357 if (!ASYNC_ENABLED(0, 0))
358 return 0;
359 if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
360 return 1;
361 size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
362 addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
363 }
364 if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
365 if (!ASYNC_ENABLED(1, 0))
366 return 0;
367 if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
368 return 1;
369 size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
370 addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
371 }
372 if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
373 if (!ASYNC_ENABLED(2, 1))
374 return 0;
375 if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
376 return 1;
377 size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
378 addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
379 }
380 if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
381 if (ASYNC_ENABLED(3, 1))
382 return 0;
383 if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
384 return 1;
385 return 0;
386 }
387
388 /* not within async bounds */
389 return 2;
390}
341 391
342int bfin_mem_access_type(unsigned long addr, unsigned long size) 392int bfin_mem_access_type(unsigned long addr, unsigned long size)
343{ 393{
@@ -374,17 +424,11 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
374 if (addr >= SYSMMR_BASE) 424 if (addr >= SYSMMR_BASE)
375 return BFIN_MEM_ACCESS_CORE_ONLY; 425 return BFIN_MEM_ACCESS_CORE_ONLY;
376 426
377 /* We can't read EBIU banks that aren't enabled or we end up hanging 427 switch (in_async(addr, size)) {
378 * on the access to the async space. 428 case 0: return -EFAULT;
379 */ 429 case 1: return BFIN_MEM_ACCESS_CORE;
380 if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) 430 case 2: /* fall through */;
381 return IN_ASYNC(0, 0); 431 }
382 if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
383 return IN_ASYNC(1, 0);
384 if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
385 return IN_ASYNC(2, 1);
386 if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
387 return IN_ASYNC(3, 1);
388 432
389 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) 433 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
390 return BFIN_MEM_ACCESS_CORE; 434 return BFIN_MEM_ACCESS_CORE;
@@ -401,6 +445,8 @@ __attribute__((l1_text))
401/* Return 1 if access to memory range is OK, 0 otherwise */ 445/* Return 1 if access to memory range is OK, 0 otherwise */
402int _access_ok(unsigned long addr, unsigned long size) 446int _access_ok(unsigned long addr, unsigned long size)
403{ 447{
448 int aret;
449
404 if (size == 0) 450 if (size == 0)
405 return 1; 451 return 1;
406 /* Check that things do not wrap around */ 452 /* Check that things do not wrap around */
@@ -450,6 +496,11 @@ int _access_ok(unsigned long addr, unsigned long size)
450 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) 496 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
451 return 1; 497 return 1;
452#endif 498#endif
499
500 aret = in_async(addr, size);
501 if (aret < 2)
502 return aret;
503
453 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) 504 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
454 return 1; 505 return 1;
455 506
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 56b0ba12175f..65567dc4b9f5 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -316,19 +316,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
316 case BFIN_MEM_ACCESS_CORE_ONLY: 316 case BFIN_MEM_ACCESS_CORE_ONLY:
317 copied = access_process_vm(child, addr, &data, 317 copied = access_process_vm(child, addr, &data,
318 to_copy, 1); 318 to_copy, 1);
319 if (copied)
320 break;
321
322 /* hrm, why didn't that work ... maybe no mapping */
323 if (addr >= FIXED_CODE_START &&
324 addr + to_copy <= FIXED_CODE_END) {
325 copy_to_user_page(0, 0, 0, paddr, &data, to_copy);
326 copied = to_copy;
327 } else if (addr >= BOOT_ROM_START) {
328 memcpy(paddr, &data, to_copy);
329 copied = to_copy;
330 }
331
332 break; 319 break;
333 case BFIN_MEM_ACCESS_DMA: 320 case BFIN_MEM_ACCESS_DMA:
334 if (safe_dma_memcpy(paddr, &data, to_copy)) 321 if (safe_dma_memcpy(paddr, &data, to_copy))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index c202a44d1416..95448ae9c43a 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -178,10 +178,10 @@ void __init bfin_cache_init(void)
178 178
179void __init bfin_relocate_l1_mem(void) 179void __init bfin_relocate_l1_mem(void)
180{ 180{
181 unsigned long l1_code_length; 181 unsigned long text_l1_len = (unsigned long)_text_l1_len;
182 unsigned long l1_data_a_length; 182 unsigned long data_l1_len = (unsigned long)_data_l1_len;
183 unsigned long l1_data_b_length; 183 unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
184 unsigned long l2_length; 184 unsigned long l2_len = (unsigned long)_l2_len;
185 185
186 early_shadow_stamp(); 186 early_shadow_stamp();
187 187
@@ -201,30 +201,23 @@ void __init bfin_relocate_l1_mem(void)
201 201
202 blackfin_dma_early_init(); 202 blackfin_dma_early_init();
203 203
204 /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ 204 /* if necessary, copy L1 text to L1 instruction SRAM */
205 l1_code_length = _etext_l1 - _stext_l1; 205 if (L1_CODE_LENGTH && text_l1_len)
206 if (l1_code_length) 206 early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
207 early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
208 207
209 /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ 208 /* if necessary, copy L1 data to L1 data bank A SRAM */
210 l1_data_a_length = _sbss_l1 - _sdata_l1; 209 if (L1_DATA_A_LENGTH && data_l1_len)
211 if (l1_data_a_length) 210 early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
212 early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
213 211
214 /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ 212 /* if necessary, copy L1 data B to L1 data bank B SRAM */
215 l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; 213 if (L1_DATA_B_LENGTH && data_b_l1_len)
216 if (l1_data_b_length) 214 early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
217 early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
218 l1_data_a_length, l1_data_b_length);
219 215
220 early_dma_memcpy_done(); 216 early_dma_memcpy_done();
221 217
222 /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ 218 /* if necessary, copy L2 text/data to L2 SRAM */
223 if (L2_LENGTH != 0) { 219 if (L2_LENGTH && l2_len)
224 l2_length = _sbss_l2 - _stext_l2; 220 memcpy(_stext_l2, _l2_lma, l2_len);
225 if (l2_length)
226 memcpy(_stext_l2, _l2_lma_start, l2_length);
227 }
228} 221}
229 222
230/* add_memory_region to memmap */ 223/* add_memory_region to memmap */
@@ -608,11 +601,6 @@ static __init void memory_setup(void)
608 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); 601 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
609#endif 602#endif
610 603
611#if !defined(CONFIG_MTD_UCLINUX)
612 /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
613 memory_end -= SIZE_4K;
614#endif
615
616 init_mm.start_code = (unsigned long)_stext; 604 init_mm.start_code = (unsigned long)_stext;
617 init_mm.end_code = (unsigned long)_etext; 605 init_mm.end_code = (unsigned long)_etext;
618 init_mm.end_data = (unsigned long)_edata; 606 init_mm.end_data = (unsigned long)_edata;
@@ -917,7 +905,7 @@ void __init setup_arch(char **cmdline_p)
917 905
918 printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); 906 printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
919 if (bfin_compiled_revid() == 0xffff) 907 if (bfin_compiled_revid() == 0xffff)
920 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); 908 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
921 else if (bfin_compiled_revid() == -1) 909 else if (bfin_compiled_revid() == -1)
922 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); 910 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
923 else 911 else
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
index 9d90c18fab23..e0fd63e9e38a 100644
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@@ -12,6 +12,7 @@
12#include <linux/binfmts.h> 12#include <linux/binfmts.h>
13#include <linux/freezer.h> 13#include <linux/freezer.h>
14#include <linux/uaccess.h> 14#include <linux/uaccess.h>
15#include <linux/tracehook.h>
15 16
16#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
17#include <asm/ucontext.h> 18#include <asm/ucontext.h>
@@ -332,3 +333,20 @@ asmlinkage void do_signal(struct pt_regs *regs)
332 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL); 333 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
333 } 334 }
334} 335}
336
337/*
338 * notification of userspace execution resumption
339 */
340asmlinkage void do_notify_resume(struct pt_regs *regs)
341{
342 if (test_thread_flag(TIF_SIGPENDING) || test_thread_flag(TIF_RESTORE_SIGMASK))
343 do_signal(regs);
344
345 if (test_thread_flag(TIF_NOTIFY_RESUME)) {
346 clear_thread_flag(TIF_NOTIFY_RESUME);
347 tracehook_notify_resume(regs);
348 if (current->replacement_session_keyring)
349 key_replace_session_keyring();
350 }
351}
352
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index 359cfb1815ca..17c38c5b5b22 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -22,8 +22,6 @@
22#include <asm/time.h> 22#include <asm/time.h>
23#include <asm/gptimers.h> 23#include <asm/gptimers.h>
24 24
25#if defined(CONFIG_CYCLES_CLOCKSOURCE)
26
27/* Accelerators for sched_clock() 25/* Accelerators for sched_clock()
28 * convert from cycles(64bits) => nanoseconds (64bits) 26 * convert from cycles(64bits) => nanoseconds (64bits)
29 * basic equation: 27 * basic equation:
@@ -46,20 +44,11 @@
46 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 44 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
47 */ 45 */
48 46
49static unsigned long cyc2ns_scale;
50#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ 47#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
51 48
52static inline void set_cyc2ns_scale(unsigned long cpu_khz) 49#if defined(CONFIG_CYCLES_CLOCKSOURCE)
53{
54 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz;
55}
56
57static inline unsigned long long cycles_2_ns(cycle_t cyc)
58{
59 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
60}
61 50
62static cycle_t bfin_read_cycles(struct clocksource *cs) 51static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
63{ 52{
64 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); 53 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
65} 54}
@@ -69,19 +58,18 @@ static struct clocksource bfin_cs_cycles = {
69 .rating = 400, 58 .rating = 400,
70 .read = bfin_read_cycles, 59 .read = bfin_read_cycles,
71 .mask = CLOCKSOURCE_MASK(64), 60 .mask = CLOCKSOURCE_MASK(64),
72 .shift = 22, 61 .shift = CYC2NS_SCALE_FACTOR,
73 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 62 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
74}; 63};
75 64
76unsigned long long sched_clock(void) 65static inline unsigned long long bfin_cs_cycles_sched_clock(void)
77{ 66{
78 return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles)); 67 return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
68 bfin_cs_cycles.mult, bfin_cs_cycles.shift);
79} 69}
80 70
81static int __init bfin_cs_cycles_init(void) 71static int __init bfin_cs_cycles_init(void)
82{ 72{
83 set_cyc2ns_scale(get_cclk() / 1000);
84
85 bfin_cs_cycles.mult = \ 73 bfin_cs_cycles.mult = \
86 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift); 74 clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);
87 75
@@ -108,7 +96,7 @@ void __init setup_gptimer0(void)
108 enable_gptimers(TIMER0bit); 96 enable_gptimers(TIMER0bit);
109} 97}
110 98
111static cycle_t bfin_read_gptimer0(void) 99static cycle_t bfin_read_gptimer0(struct clocksource *cs)
112{ 100{
113 return bfin_read_TIMER0_COUNTER(); 101 return bfin_read_TIMER0_COUNTER();
114} 102}
@@ -118,10 +106,16 @@ static struct clocksource bfin_cs_gptimer0 = {
118 .rating = 350, 106 .rating = 350,
119 .read = bfin_read_gptimer0, 107 .read = bfin_read_gptimer0,
120 .mask = CLOCKSOURCE_MASK(32), 108 .mask = CLOCKSOURCE_MASK(32),
121 .shift = 22, 109 .shift = CYC2NS_SCALE_FACTOR,
122 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 110 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
123}; 111};
124 112
113static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
114{
115 return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
116 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
117}
118
125static int __init bfin_cs_gptimer0_init(void) 119static int __init bfin_cs_gptimer0_init(void)
126{ 120{
127 setup_gptimer0(); 121 setup_gptimer0();
@@ -138,6 +132,19 @@ static int __init bfin_cs_gptimer0_init(void)
138# define bfin_cs_gptimer0_init() 132# define bfin_cs_gptimer0_init()
139#endif 133#endif
140 134
135
136#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
137/* prefer to use cycles since it has higher rating */
138notrace unsigned long long sched_clock(void)
139{
140#if defined(CONFIG_CYCLES_CLOCKSOURCE)
141 return bfin_cs_cycles_sched_clock();
142#else
143 return bfin_cs_gptimer0_sched_clock();
144#endif
145}
146#endif
147
141#ifdef CONFIG_CORE_TIMER_IRQ_L1 148#ifdef CONFIG_CORE_TIMER_IRQ_L1
142__attribute__((l1_text)) 149__attribute__((l1_text))
143#endif 150#endif
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index bd3b53da295e..13c1ee3e6408 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -184,11 +184,3 @@ void __init time_init(void)
184 184
185 time_sched_init(timer_interrupt); 185 time_sched_init(timer_interrupt);
186} 186}
187
188/*
189 * Scheduler clock - returns current time in nanosec units.
190 */
191unsigned long long sched_clock(void)
192{
193 return (unsigned long long)jiffies *(NSEC_PER_SEC / HZ);
194}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 9636bace00e8..d3cbcd6bd985 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -119,6 +119,15 @@ static void decode_address(char *buf, unsigned long address)
119 return; 119 return;
120 } 120 }
121 121
122 /*
123 * Don't walk any of the vmas if we are oopsing, it has been known
124 * to cause problems - corrupt vmas (kernel crashes) cause double faults
125 */
126 if (oops_in_progress) {
127 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
128 return;
129 }
130
122 /* looks like we're off in user-land, so let's walk all the 131 /* looks like we're off in user-land, so let's walk all the
123 * mappings of all our processes and see if we can't be a whee 132 * mappings of all our processes and see if we can't be a whee
124 * bit more specific 133 * bit more specific
@@ -515,6 +524,36 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
515 break; 524 break;
516 /* External Memory Addressing Error */ 525 /* External Memory Addressing Error */
517 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): 526 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
527 if (ANOMALY_05000310) {
528 static unsigned long anomaly_rets;
529
530 if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
531 (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
532 /*
533 * A false hardware error will happen while fetching at
534 * the L1 instruction SRAM boundary. Ignore it.
535 */
536 anomaly_rets = fp->rets;
537 goto traps_done;
538 } else if (fp->rets == anomaly_rets) {
539 /*
540 * While boundary code returns to a function, at the ret
541 * point, a new false hardware error might occur too based
542 * on tests. Ignore it too.
543 */
544 goto traps_done;
545 } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
546 (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
547 /*
548 * If boundary code calls a function, at the entry point,
549 * a new false hardware error maybe happen based on tests.
550 * Ignore it too.
551 */
552 goto traps_done;
553 } else
554 anomaly_rets = 0;
555 }
556
518 info.si_code = BUS_ADRERR; 557 info.si_code = BUS_ADRERR;
519 sig = SIGBUS; 558 sig = SIGBUS;
520 strerror = KERN_NOTICE HWC_x3(KERN_NOTICE); 559 strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
@@ -976,12 +1015,12 @@ void dump_bfin_process(struct pt_regs *fp)
976 !((unsigned long)current & 0x3) && current->pid) { 1015 !((unsigned long)current & 0x3) && current->pid) {
977 verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n"); 1016 verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
978 if (current->comm >= (char *)FIXED_CODE_START) 1017 if (current->comm >= (char *)FIXED_CODE_START)
979 verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n", 1018 verbose_printk(KERN_NOTICE "COMM=%s PID=%d",
980 current->comm, current->pid); 1019 current->comm, current->pid);
981 else 1020 else
982 verbose_printk(KERN_NOTICE "COMM= invalid\n"); 1021 verbose_printk(KERN_NOTICE "COMM= invalid");
983 1022
984 printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu); 1023 printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu);
985 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) 1024 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
986 verbose_printk(KERN_NOTICE 1025 verbose_printk(KERN_NOTICE
987 "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" 1026 "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index f39707c6590d..66799e763dc9 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -121,8 +121,6 @@ SECTIONS
121 EXIT_DATA 121 EXIT_DATA
122 } 122 }
123 123
124 __l1_lma_start = .;
125
126 .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data)) 124 .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
127 { 125 {
128 . = ALIGN(4); 126 . = ALIGN(4);
@@ -134,9 +132,11 @@ SECTIONS
134 . = ALIGN(4); 132 . = ALIGN(4);
135 __etext_l1 = .; 133 __etext_l1 = .;
136 } 134 }
137 ASSERT (SIZEOF(.text_l1) <= L1_CODE_LENGTH, "L1 text overflow!") 135 __text_l1_lma = LOADADDR(.text_l1);
136 __text_l1_len = SIZEOF(.text_l1);
137 ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
138 138
139 .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1)) 139 .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
140 { 140 {
141 . = ALIGN(4); 141 . = ALIGN(4);
142 __sdata_l1 = .; 142 __sdata_l1 = .;
@@ -152,9 +152,11 @@ SECTIONS
152 . = ALIGN(4); 152 . = ALIGN(4);
153 __ebss_l1 = .; 153 __ebss_l1 = .;
154 } 154 }
155 ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!") 155 __data_l1_lma = LOADADDR(.data_l1);
156 __data_l1_len = SIZEOF(.data_l1);
157 ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
156 158
157 .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) 159 .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
158 { 160 {
159 . = ALIGN(4); 161 . = ALIGN(4);
160 __sdata_b_l1 = .; 162 __sdata_b_l1 = .;
@@ -167,11 +169,11 @@ SECTIONS
167 . = ALIGN(4); 169 . = ALIGN(4);
168 __ebss_b_l1 = .; 170 __ebss_b_l1 = .;
169 } 171 }
170 ASSERT (SIZEOF(.data_b_l1) <= L1_DATA_B_LENGTH, "L1 data B overflow!") 172 __data_b_l1_lma = LOADADDR(.data_b_l1);
171 173 __data_b_l1_len = SIZEOF(.data_b_l1);
172 __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); 174 ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
173 175
174 .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) 176 .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
175 { 177 {
176 . = ALIGN(4); 178 . = ALIGN(4);
177 __stext_l2 = .; 179 __stext_l2 = .;
@@ -193,12 +195,14 @@ SECTIONS
193 . = ALIGN(4); 195 . = ALIGN(4);
194 __ebss_l2 = .; 196 __ebss_l2 = .;
195 } 197 }
196 ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!") 198 __l2_lma = LOADADDR(.text_data_l2);
199 __l2_len = SIZEOF(.text_data_l2);
200 ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
197 201
198 /* Force trailing alignment of our init section so that when we 202 /* Force trailing alignment of our init section so that when we
199 * free our init memory, we don't leave behind a partial page. 203 * free our init memory, we don't leave behind a partial page.
200 */ 204 */
201 . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2); 205 . = __l2_lma + __l2_len;
202 . = ALIGN(PAGE_SIZE); 206 . = ALIGN(PAGE_SIZE);
203 ___init_end = .; 207 ___init_end = .;
204 208
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
index 635288fc5f54..42c47dc9e12f 100644
--- a/arch/blackfin/lib/Makefile
+++ b/arch/blackfin/lib/Makefile
@@ -5,7 +5,7 @@
5lib-y := \ 5lib-y := \
6 ashldi3.o ashrdi3.o lshrdi3.o \ 6 ashldi3.o ashrdi3.o lshrdi3.o \
7 muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \ 7 muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
8 checksum.o memcpy.o memset.o memcmp.o memchr.o memmove.o \ 8 memcpy.o memset.o memcmp.o memchr.o memmove.o \
9 strcmp.o strcpy.o strncmp.o strncpy.o \ 9 strcmp.o strcpy.o strncmp.o strncpy.o \
10 umulsi3_highpart.o smulsi3_highpart.o \ 10 umulsi3_highpart.o smulsi3_highpart.o \
11 ins.o outs.o 11 ins.o outs.o
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c
deleted file mode 100644
index c62969dc1bbb..000000000000
--- a/arch/blackfin/lib/checksum.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 *
6 * An implementation of the TCP/IP protocol suite for the LINUX operating
7 * system. INET is implemented using the BSD Socket interface as the
8 * means of communication with the user level.
9 *
10 */
11
12#include <linux/module.h>
13#include <net/checksum.h>
14#include <asm/checksum.h>
15
16#ifdef CONFIG_IP_CHECKSUM_L1
17static unsigned short do_csum(const unsigned char *buff, int len)__attribute__((l1_text));
18#endif
19
20static unsigned short do_csum(const unsigned char *buff, int len)
21{
22 register unsigned long sum = 0;
23 int swappem = 0;
24
25 if (1 & (unsigned long)buff) {
26 sum = *buff << 8;
27 buff++;
28 len--;
29 ++swappem;
30 }
31
32 while (len > 1) {
33 sum += *(unsigned short *)buff;
34 buff += 2;
35 len -= 2;
36 }
37
38 if (len > 0)
39 sum += *buff;
40
41 /* Fold 32-bit sum to 16 bits */
42 while (sum >> 16)
43 sum = (sum & 0xffff) + (sum >> 16);
44
45 if (swappem)
46 sum = ((sum & 0xff00) >> 8) + ((sum & 0x00ff) << 8);
47
48 return sum;
49
50}
51
52/*
53 * This is a version of ip_compute_csum() optimized for IP headers,
54 * which always checksum on 4 octet boundaries.
55 */
56__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl)
57{
58 return (__force __sum16)~do_csum(iph, ihl * 4);
59}
60EXPORT_SYMBOL(ip_fast_csum);
61
62/*
63 * computes the checksum of a memory block at buff, length len,
64 * and adds in "sum" (32-bit)
65 *
66 * returns a 32-bit number suitable for feeding into itself
67 * or csum_tcpudp_magic
68 *
69 * this function must be called with even lengths, except
70 * for the last fragment, which may be odd
71 *
72 * it's best to have buff aligned on a 32-bit boundary
73 */
74__wsum csum_partial(const void *buff, int len, __wsum sum)
75{
76 /*
77 * Just in case we get nasty checksum data...
78 * Like 0xffff6ec3 in the case of our IPv6 multicast header.
79 * We fold to begin with, as well as at the end.
80 */
81 sum = (sum & 0xffff) + (sum >> 16);
82
83 sum += do_csum(buff, len);
84
85 sum = (sum & 0xffff) + (sum >> 16);
86
87 return sum;
88}
89EXPORT_SYMBOL(csum_partial);
90
91/*
92 * this routine is used for miscellaneous IP-like checksums, mainly
93 * in icmp.c
94 */
95__sum16 ip_compute_csum(const void *buff, int len)
96{
97 return (__force __sum16)~do_csum(buff, len);
98}
99EXPORT_SYMBOL(ip_compute_csum);
100
101/*
102 * copy from fs while checksumming, otherwise like csum_partial
103 */
104
105__wsum
106csum_partial_copy_from_user(const void __user *src, void *dst,
107 int len, __wsum sum, int *csum_err)
108{
109 if (csum_err)
110 *csum_err = 0;
111 memcpy(dst, (__force void *)src, len);
112 return csum_partial(dst, len, sum);
113}
114EXPORT_SYMBOL(csum_partial_copy_from_user);
115
116/*
117 * copy from ds while checksumming, otherwise like csum_partial
118 */
119
120__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
121{
122 memcpy(dst, src, len);
123 return csum_partial(dst, len, sum);
124}
125EXPORT_SYMBOL(csum_partial_copy);
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 4c76fefb7a3b..4ab2d166c832 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -1,3 +1,7 @@
1config BF51x
2 def_bool y
3 depends on (BF512 || BF514 || BF516 || BF518)
4
1if (BF51x) 5if (BF51x)
2 6
3source "arch/blackfin/mach-bf518/boards/Kconfig" 7source "arch/blackfin/mach-bf518/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 6cfb246aebec..9053462be4b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -58,10 +58,4 @@
58#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 58#define OFFSET_SCR 0x1C /* SCR Scratch Register */
59#define OFFSET_GCTL 0x24 /* Global Control Register */ 59#define OFFSET_GCTL 0x24 /* Global Control Register */
60 60
61/* PLL_DIV Masks */
62#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
63#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
64#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
65#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
66
67#endif 61#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index e1d99911025d..108fa4bde277 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF514_H 7#ifndef _CDEF_BF514_H
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF514.h" 11#include "defBF514.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF514 is BF512 + RSI */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF512.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
22 15
23/* Removable Storage Interface Registers */ 16/* Removable Storage Interface Registers */
24 17
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 6b364eda4947..2751592ef1c1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF516_H 7#ifndef _CDEF_BF516_H
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF516.h" 11#include "defBF516.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF516 is BF514 + EMAC */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF514.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
22 15
23/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 16/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
24 17
@@ -185,71 +178,4 @@
185#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) 178#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
186#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) 179#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
187 180
188/* Removable Storage Interface Registers */
189
190#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
191#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
192#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
193#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
194#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
195#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
196#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
197#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
198#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
199#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
200#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
201#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
202#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
203#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
204#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
205#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
206#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
207#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
208#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
209#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
210#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
211#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
212#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
213#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
214#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
215#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
216#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
217#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
218#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
219#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
220#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
221#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
222#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
223#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
224#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
225#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
226#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
227#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
228#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
229#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
230#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
231#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
232#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
233#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
234#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
235#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
236#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
237#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
238#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
239#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
240#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
241#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
242#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
243#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
244#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
245#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
246#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
247#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
248#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
249#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
250#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
251#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
252#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
253#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
254
255#endif /* _CDEF_BF516_H */ 181#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 929b90650bd4..7fb7f0eab990 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF518_H 7#ifndef _CDEF_BF518_H
@@ -10,181 +10,10 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF518.h" 11#include "defBF518.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF518 is BF516 + IEEE-1588 */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF516.h"
15 15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ 16/* PTP TSYNC Registers */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
22
23
24/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
25
26#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
27#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
28#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
29#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
30#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
31#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
32#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
33#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
34#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
35#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
36#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
37#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
38#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
39#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
40#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
41#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
42#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
43#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
44#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
45#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
46#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
47#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
48#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
49#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
50#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
51#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
52#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
53#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
54#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
55#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
56#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
57#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
58#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
59#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
60#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
61#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
62#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
63#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
64
65#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
66#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
67#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
68#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
69#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
70#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
71#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
72#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
73#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
74#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
75#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
76#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
77#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
78#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
79#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
80#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
81
82#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
83#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
84#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
85#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
86#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
87#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
88#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
89#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
90#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
91#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
92
93#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
94#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
95#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
96#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
97#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
98#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
99#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
100#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
101#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
102#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
103#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
104#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
105#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
106#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
107#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
108#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
109#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
110#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
111#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
112#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
113#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
114#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
115#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
116#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
117#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
118#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
119#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
120#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
121#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
122#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
123#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
124#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
125#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
126#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
127#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
128#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
129#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
130#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
131#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
132#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
133#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
134#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
135#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
136#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
137#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
138#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
139#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
140#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
141
142#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
143#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
144#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
145#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
146#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
147#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
148#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
149#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
150#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
151#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
152#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
153#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
154#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
155#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
156#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
157#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
158#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
159#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
160#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
161#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
162#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
163#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
164#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
165#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
166#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
167#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
168#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
169#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
170#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
171#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
172#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
173#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
174#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
175#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
176#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
177#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
178#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
179#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
180#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
181#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
182#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
183#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
184#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
185#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
186#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
187#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
188 17
189#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) 18#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
190#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) 19#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
@@ -227,72 +56,4 @@
227#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) 56#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
228#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) 57#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
229 58
230/* Removable Storage Interface Registers */
231
232#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
233#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
234#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
235#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
236#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
237#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
238#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
239#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
240#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
241#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
242#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
243#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
244#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
245#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
246#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
247#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
248#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
249#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
250#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
251#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
252#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
253#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
254#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
255#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
256#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
257#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
258#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
259#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
260#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
261#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
262#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
263#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
264#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
265#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
266#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
267#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
268#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
269#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
270#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
271#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
272#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
273#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
274#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
275#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
276#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
277#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
278#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
279#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
280#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
281#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
282#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
283#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
284#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
285#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
286#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
287#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
288#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
289#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
290#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
291#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
292#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
293#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
294#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
295#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
296
297
298#endif /* _CDEF_BF518_H */ 59#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 1d970df7aee9..e548e9d1d6fa 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -131,23 +131,6 @@
131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) 131#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
132 132
133 133
134/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
135#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
136#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
137#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
138#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
139#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
140#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
141#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
142#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
143#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
144#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
145#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
146#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
147#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
148#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
149
150
151/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ 134/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
152#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 135#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
153#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) 136#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
@@ -844,6 +827,7 @@
844#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 827#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
845#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 828#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
846#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) 829#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
830#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
847#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) 831#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
848#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) 832#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
849#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) 833#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
@@ -1062,17 +1046,6 @@
1062#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1046#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1063#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1047#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1064 1048
1065/* OTP/FUSE Registers */
1066
1067#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1068#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1069#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1070#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1071#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1072#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1073#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1074#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1075
1076/* Security Registers */ 1049/* Security Registers */
1077 1050
1078#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1051#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -1082,52 +1055,6 @@
1082#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1055#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1083#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1056#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1084 1057
1085/* OTP Read/Write Data Buffer Registers */
1086
1087#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1088#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1089#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1090#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1091#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1092#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1093#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1094#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1095
1096/* NFC Registers */
1097
1098#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1099#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1100#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1101#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1102#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1103#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1104#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1105#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1106#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1107#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1108#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1109#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1110#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1111#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1112#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1113#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1114#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1115#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1116#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1117#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1118#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1119#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1120#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1121#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1122#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1123#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1124#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1125#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1126#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1127#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1128#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1129#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1130
1131/* These need to be last due to the cdef/linux inter-dependencies */ 1058/* These need to be last due to the cdef/linux inter-dependencies */
1132#include <asm/irq.h> 1059#include <asm/irq.h>
1133 1060
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index b5adca23a788..92e950d6e996 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -7,49 +7,8 @@
7#ifndef _DEF_BF514_H 7#ifndef _DEF_BF514_H
8#define _DEF_BF514_H 8#define _DEF_BF514_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF514 is BF512 + RSI */
11#include <asm/def_LPBlackfin.h> 11#include "defBF512.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17
18/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
19
20/* SDH Registers */
21
22#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
23#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
24#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
25#define SDH_COMMAND 0xFFC0390C /* SDH Command */
26#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
27#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
28#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
29#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
30#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
31#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
32#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
33#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
34#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
35#define SDH_STATUS 0xFFC03934 /* SDH Status */
36#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
37#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
38#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
39#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
40#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
41#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
42#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
43#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
44#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
45#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
46#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
47#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
48#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
49#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
50#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
51#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
52#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
53 12
54/* Removable Storage Interface Registers */ 13/* Removable Storage Interface Registers */
55 14
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 7eb18774d727..22a3aa0d2629 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -7,13 +7,8 @@
7#ifndef _DEF_BF516_H 7#ifndef _DEF_BF516_H
8#define _DEF_BF516_H 8#define _DEF_BF516_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF516 is BF514 + EMAC */
11#include <asm/def_LPBlackfin.h> 11#include "defBF514.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17 12
18/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ 13/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
19/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
@@ -394,208 +389,4 @@
394#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ 389#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ 390#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
396 391
397/* SDH Registers */
398
399#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
400#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
401#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
402#define SDH_COMMAND 0xFFC0390C /* SDH Command */
403#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
404#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
405#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
406#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
407#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
408#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
409#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
410#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
411#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
412#define SDH_STATUS 0xFFC03934 /* SDH Status */
413#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
414#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
415#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
416#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
417#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
418#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
419#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
420#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
421#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
422#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
423#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
424#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
425#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
426#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
427#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
428#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
429#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
430
431/* Removable Storage Interface Registers */
432
433#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
434#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
435#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
436#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
437#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
438#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
439#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
440#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
441#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
442#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
443#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
444#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
445#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
446#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
447#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
448#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
449#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
450#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
451#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
452#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
453#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
454#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
455#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
456#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
457#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
458#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
459#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
460#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
461#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
462#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
463#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
464#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
465
466/* ********************************************************** */
467/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
468/* and MULTI BIT READ MACROS */
469/* ********************************************************** */
470
471/* Bit masks for SDH_COMMAND */
472
473#define CMD_IDX 0x3f /* Command Index */
474#define CMD_RSP 0x40 /* Response */
475#define CMD_L_RSP 0x80 /* Long Response */
476#define CMD_INT_E 0x100 /* Command Interrupt */
477#define CMD_PEND_E 0x200 /* Command Pending */
478#define CMD_E 0x400 /* Command Enable */
479
480/* Bit masks for SDH_PWR_CTL */
481
482#define PWR_ON 0x3 /* Power On */
483#if 0
484#define TBD 0x3c /* TBD */
485#endif
486#define SD_CMD_OD 0x40 /* Open Drain Output */
487#define ROD_CTL 0x80 /* Rod Control */
488
489/* Bit masks for SDH_CLK_CTL */
490
491#define CLKDIV 0xff /* MC_CLK Divisor */
492#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
493#define PWR_SV_E 0x200 /* Power Save Enable */
494#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
495#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
496
497/* Bit masks for SDH_RESP_CMD */
498
499#define RESP_CMD 0x3f /* Response Command */
500
501/* Bit masks for SDH_DATA_CTL */
502
503#define DTX_E 0x1 /* Data Transfer Enable */
504#define DTX_DIR 0x2 /* Data Transfer Direction */
505#define DTX_MODE 0x4 /* Data Transfer Mode */
506#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
507#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
508
509/* Bit masks for SDH_STATUS */
510
511#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
512#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
513#define CMD_TIME_OUT 0x4 /* CMD Time Out */
514#define DAT_TIME_OUT 0x8 /* Data Time Out */
515#define TX_UNDERRUN 0x10 /* Transmit Underrun */
516#define RX_OVERRUN 0x20 /* Receive Overrun */
517#define CMD_RESP_END 0x40 /* CMD Response End */
518#define CMD_SENT 0x80 /* CMD Sent */
519#define DAT_END 0x100 /* Data End */
520#define START_BIT_ERR 0x200 /* Start Bit Error */
521#define DAT_BLK_END 0x400 /* Data Block End */
522#define CMD_ACT 0x800 /* CMD Active */
523#define TX_ACT 0x1000 /* Transmit Active */
524#define RX_ACT 0x2000 /* Receive Active */
525#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
526#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
527#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
528#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
529#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
530#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
531#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
532#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
533
534/* Bit masks for SDH_STATUS_CLR */
535
536#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
537#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
538#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
539#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
540#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
541#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
542#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
543#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
544#define DAT_END_STAT 0x100 /* Data End Status */
545#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
546#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
547
548/* Bit masks for SDH_MASK0 */
549
550#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
551#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
552#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
553#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
554#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
555#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
556#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
557#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
558#define DAT_END_MASK 0x100 /* Data End Mask */
559#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
560#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
561#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
562#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
563#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
564#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
565#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
566#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
567#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
568#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
569#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
570#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
571#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
572
573/* Bit masks for SDH_FIFO_CNT */
574
575#define FIFO_COUNT 0x7fff /* FIFO Count */
576
577/* Bit masks for SDH_E_STATUS */
578
579#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
580#define SD_CARD_DET 0x10 /* SD Card Detect */
581
582/* Bit masks for SDH_E_MASK */
583
584#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
585#define SCD_MSK 0x40 /* Mask Card Detect */
586
587/* Bit masks for SDH_CFG */
588
589#define CLKS_EN 0x1 /* Clocks Enable */
590#define SD4E 0x4 /* SDIO 4-Bit Enable */
591#define MWE 0x8 /* Moving Window Enable */
592#define SD_RST 0x10 /* SDMMC Reset */
593#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
594#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
595#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
596
597/* Bit masks for SDH_RD_WAIT_EN */
598
599#define RWR 0x1 /* Read Wait Request */
600
601#endif /* _DEF_BF516_H */ 392#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index 794cf06eb5ba..cb18270e55c2 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -7,461 +7,8 @@
7#ifndef _DEF_BF518_H 7#ifndef _DEF_BF518_H
8#define _DEF_BF518_H 8#define _DEF_BF518_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF518 is BF516 + IEEE-1588 */
11#include <asm/def_LPBlackfin.h> 11#include "defBF516.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17
18/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
19/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
20
21#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
22#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
23#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
24#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
25#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
26#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
27#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
28#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
29#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
30#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
31#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
32#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
33#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
34#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
35#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
36#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
37#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
38#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
39#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
40
41#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
42#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
43#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
44#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
45#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
46#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
47#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
48#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
49
50#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
51#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
52#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
53#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
54#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
55
56#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
57#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
58#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
59#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
60#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
61#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
62#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
63#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
64#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
65#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
66#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
67#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
68#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
69#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
70#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
71#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
72#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
73#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
74#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
75#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
76#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
77#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
78#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
79#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
80
81#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
82#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
83#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
84#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
85#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
86#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
87#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
88#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
89#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
90#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
91#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
92#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
93#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
94#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
95#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
96#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
97#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
98#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
99#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
100#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
101#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
102#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
103#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
104
105/* Listing for IEEE-Supported Count Registers */
106
107#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
108#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
109#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
110#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
111#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
112#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
113#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
114#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
115#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
116#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
117#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
118#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
119#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
120#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
121#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
122#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
123#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
124#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
125#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
126#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
127#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
128#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
129#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
130#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
131
132#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
133#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
134#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
135#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
136#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
137#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
138#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
139#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
140#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
141#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
142#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
143#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
144#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
145#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
146#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
147#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
148#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
149#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
150#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
151#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
152#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
153#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
154#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
155
156/***********************************************************************************
157** System MMR Register Bits And Macros
158**
159** Disclaimer: All macros are intended to make C and Assembly code more readable.
160** Use these macros carefully, as any that do left shifts for field
161** depositing will result in the lower order bits being destroyed. Any
162** macro that shifts left to properly position the bit-field should be
163** used as part of an OR to initialize a register and NOT as a dynamic
164** modifier UNLESS the lower order bits are saved and ORed back in when
165** the macro is used.
166*************************************************************************************/
167
168/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
169
170/* EMAC_OPMODE Masks */
171
172#define RE 0x00000001 /* Receiver Enable */
173#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
174#define HU 0x00000010 /* Hash Filter Unicast Address */
175#define HM 0x00000020 /* Hash Filter Multicast Address */
176#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
177#define PR 0x00000080 /* Promiscuous Mode Enable */
178#define IFE 0x00000100 /* Inverse Filtering Enable */
179#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
180#define PBF 0x00000400 /* Pass Bad Frames Enable */
181#define PSF 0x00000800 /* Pass Short Frames Enable */
182#define RAF 0x00001000 /* Receive-All Mode */
183#define TE 0x00010000 /* Transmitter Enable */
184#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
185#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
186#define DC 0x00080000 /* Deferral Check */
187#define BOLMT 0x00300000 /* Back-Off Limit */
188#define BOLMT_10 0x00000000 /* 10-bit range */
189#define BOLMT_8 0x00100000 /* 8-bit range */
190#define BOLMT_4 0x00200000 /* 4-bit range */
191#define BOLMT_1 0x00300000 /* 1-bit range */
192#define DRTY 0x00400000 /* Disable TX Retry On Collision */
193#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
194#define RMII 0x01000000 /* RMII/MII* Mode */
195#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
196#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
197#define LB 0x08000000 /* Internal Loopback Enable */
198#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
199
200/* EMAC_STAADD Masks */
201
202#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
203#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
204#define STADISPRE 0x00000004 /* Disable Preamble Generation */
205#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
206#define REGAD 0x000007C0 /* STA Register Address */
207#define PHYAD 0x0000F800 /* PHY Device Address */
208
209#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
210#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
211
212/* EMAC_STADAT Mask */
213
214#define STADATA 0x0000FFFF /* Station Management Data */
215
216/* EMAC_FLC Masks */
217
218#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
219#define FLCE 0x00000002 /* Flow Control Enable */
220#define PCF 0x00000004 /* Pass Control Frames */
221#define BKPRSEN 0x00000008 /* Enable Backpressure */
222#define FLCPAUSE 0xFFFF0000 /* Pause Time */
223
224#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
225
226/* EMAC_WKUP_CTL Masks */
227
228#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
229#define MPKE 0x00000002 /* Magic Packet Enable */
230#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
231#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
232#define MPKS 0x00000020 /* Magic Packet Received Status */
233#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
234
235/* EMAC_WKUP_FFCMD Masks */
236
237#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
238#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
239#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
240#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
241#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
242#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
243#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
244#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
245
246/* EMAC_WKUP_FFOFF Masks */
247
248#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
249#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
250#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
251#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
252
253#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
254#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
255#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
256#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
257/* Set ALL Offsets */
258#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
259
260/* EMAC_WKUP_FFCRC0 Masks */
261
262#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
263#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
264
265#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
266#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
267
268/* EMAC_WKUP_FFCRC1 Masks */
269
270#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
271#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
272
273#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
274#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
275
276/* EMAC_SYSCTL Masks */
277
278#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
279#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
280#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
281#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
282#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
283
284#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
285
286/* EMAC_SYSTAT Masks */
287
288#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
289#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
290#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
291#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
292#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
293#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
294#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
295#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
296
297/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
298
299#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
300#define RX_COMP 0x00001000 /* RX Frame Complete */
301#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
302#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
303#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
304#define RX_CRC 0x00010000 /* RX Frame CRC Error */
305#define RX_LEN 0x00020000 /* RX Frame Length Error */
306#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
307#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
308#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
309#define RX_PHY 0x00200000 /* RX Frame PHY Error */
310#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
311#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
312#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
313#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
314#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
315#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
316#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
317#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
318#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
319#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
320
321/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
322
323#define TX_COMP 0x00000001 /* TX Frame Complete */
324#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
325#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
326#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
327#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
328#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
329#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
330#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
331#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
332#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
333#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
334#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
335#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
336#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
337#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
338
339/* EMAC_MMC_CTL Masks */
340#define RSTC 0x00000001 /* Reset All Counters */
341#define CROLL 0x00000002 /* Counter Roll-Over Enable */
342#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
343#define MMCE 0x00000008 /* Enable MMC Counter Operation */
344
345/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
346#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
347#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
348#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
349#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
350#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
351#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
352#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
353#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
354#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
355#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
356#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
357#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
358#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
359#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
360#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
361#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
362#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
363#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
364#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
365#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
366#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
367#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
368#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
369#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
370
371/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
372
373#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
374#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
375#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
376#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
377#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
378#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
379#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
380#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
381#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
382#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
383#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
384#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
385#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
386#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
387#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
388#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
389#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
390#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
391#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
392#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
393#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
394#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
396
397/* SDH Registers */
398
399#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
400#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
401#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
402#define SDH_COMMAND 0xFFC0390C /* SDH Command */
403#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
404#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
405#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
406#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
407#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
408#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
409#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
410#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
411#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
412#define SDH_STATUS 0xFFC03934 /* SDH Status */
413#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
414#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
415#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
416#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
417#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
418#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
419#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
420#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
421#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
422#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
423#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
424#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
425#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
426#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
427#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
428#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
429#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
430
431/* Removable Storage Interface Registers */
432
433#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
434#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
435#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
436#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
437#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
438#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
439#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
440#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
441#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
442#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
443#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
444#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
445#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
446#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
447#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
448#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
449#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
450#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
451#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
452#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
453#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
454#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
455#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
456#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
457#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
458#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
459#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
460#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
461#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
462#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
463#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
464#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
465 12
466/* PTP TSYNC Registers */ 13/* PTP TSYNC Registers */
467 14
@@ -489,141 +36,6 @@
489#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ 36#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
490#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ 37#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
491 38
492/* ********************************************************** */
493/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
494/* and MULTI BIT READ MACROS */
495/* ********************************************************** */
496
497/* Bit masks for SDH_COMMAND */
498
499#define CMD_IDX 0x3f /* Command Index */
500#define CMD_RSP 0x40 /* Response */
501#define CMD_L_RSP 0x80 /* Long Response */
502#define CMD_INT_E 0x100 /* Command Interrupt */
503#define CMD_PEND_E 0x200 /* Command Pending */
504#define CMD_E 0x400 /* Command Enable */
505
506/* Bit masks for SDH_PWR_CTL */
507
508#define PWR_ON 0x3 /* Power On */
509#if 0
510#define TBD 0x3c /* TBD */
511#endif
512#define SD_CMD_OD 0x40 /* Open Drain Output */
513#define ROD_CTL 0x80 /* Rod Control */
514
515/* Bit masks for SDH_CLK_CTL */
516
517#define CLKDIV 0xff /* MC_CLK Divisor */
518#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
519#define PWR_SV_E 0x200 /* Power Save Enable */
520#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
521#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
522
523/* Bit masks for SDH_RESP_CMD */
524
525#define RESP_CMD 0x3f /* Response Command */
526
527/* Bit masks for SDH_DATA_CTL */
528
529#define DTX_E 0x1 /* Data Transfer Enable */
530#define DTX_DIR 0x2 /* Data Transfer Direction */
531#define DTX_MODE 0x4 /* Data Transfer Mode */
532#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
533#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
534
535/* Bit masks for SDH_STATUS */
536
537#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
538#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
539#define CMD_TIME_OUT 0x4 /* CMD Time Out */
540#define DAT_TIME_OUT 0x8 /* Data Time Out */
541#define TX_UNDERRUN 0x10 /* Transmit Underrun */
542#define RX_OVERRUN 0x20 /* Receive Overrun */
543#define CMD_RESP_END 0x40 /* CMD Response End */
544#define CMD_SENT 0x80 /* CMD Sent */
545#define DAT_END 0x100 /* Data End */
546#define START_BIT_ERR 0x200 /* Start Bit Error */
547#define DAT_BLK_END 0x400 /* Data Block End */
548#define CMD_ACT 0x800 /* CMD Active */
549#define TX_ACT 0x1000 /* Transmit Active */
550#define RX_ACT 0x2000 /* Receive Active */
551#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
552#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
553#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
554#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
555#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
556#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
557#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
558#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
559
560/* Bit masks for SDH_STATUS_CLR */
561
562#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
563#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
564#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
565#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
566#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
567#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
568#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
569#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
570#define DAT_END_STAT 0x100 /* Data End Status */
571#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
572#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
573
574/* Bit masks for SDH_MASK0 */
575
576#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
577#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
578#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
579#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
580#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
581#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
582#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
583#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
584#define DAT_END_MASK 0x100 /* Data End Mask */
585#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
586#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
587#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
588#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
589#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
590#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
591#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
592#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
593#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
594#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
595#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
596#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
597#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
598
599/* Bit masks for SDH_FIFO_CNT */
600
601#define FIFO_COUNT 0x7fff /* FIFO Count */
602
603/* Bit masks for SDH_E_STATUS */
604
605#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
606#define SD_CARD_DET 0x10 /* SD Card Detect */
607
608/* Bit masks for SDH_E_MASK */
609
610#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
611#define SCD_MSK 0x40 /* Mask Card Detect */
612
613/* Bit masks for SDH_CFG */
614
615#define CLKS_EN 0x1 /* Clocks Enable */
616#define SD4E 0x4 /* SDIO 4-Bit Enable */
617#define MWE 0x8 /* Moving Window Enable */
618#define SD_RST 0x10 /* SDMMC Reset */
619#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
620#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
621#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
622
623/* Bit masks for SDH_RD_WAIT_EN */
624
625#define RWR 0x1 /* Read Wait Request */
626
627/* Bit masks for EMAC_PTP_CTL */ 39/* Bit masks for EMAC_PTP_CTL */
628 40
629#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */ 41#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index f9fd2b2a2956..9241205fb992 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -585,58 +585,6 @@
585** modifier UNLESS the lower order bits are saved and ORed back in when 585** modifier UNLESS the lower order bits are saved and ORed back in when
586** the macro is used. 586** the macro is used.
587*************************************************************************************/ 587*************************************************************************************/
588/*
589** ********************* PLL AND RESET MASKS ****************************************/
590/* PLL_CTL Masks */
591#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
592#define PLL_OFF 0x0002 /* PLL Not Powered */
593#define STOPCK 0x0008 /* Core Clock Off */
594#define PDWN 0x0020 /* Enter Deep Sleep Mode */
595#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
596#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
597#define BYPASS 0x0100 /* Bypass the PLL */
598#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
599/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
600#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
601
602/* PLL_DIV Masks */
603#define SSEL 0x000F /* System Select */
604#define CSEL 0x0030 /* Core Select */
605#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
606#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
607#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
608#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
609/* PLL_DIV Macros */
610#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
611
612/* VR_CTL Masks */
613#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
614#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
615
616#define VLEV 0x00F0 /* Internal Voltage Level */
617#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
618#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
619#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
620#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
621#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
622#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
623#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
624#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
625#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
626#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
627
628#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
629#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
630#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
631#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
632#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
633#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
634
635/* PLL_STAT Masks */
636#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
637#define FULL_ON 0x0002 /* Processor In Full On Mode */
638#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
639#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
640 588
641/* CHIPID Masks */ 589/* CHIPID Masks */
642#define CHIPID_VERSION 0xF0000000 590#define CHIPID_VERSION 0xF0000000
@@ -756,66 +704,6 @@
756#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
757 705
758 706
759/* ********* WATCHDOG TIMER MASKS ******************** */
760
761/* Watchdog Timer WDOG_CTL Register Masks */
762
763#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
764#define WDEV_RESET 0x0000 /* generate reset event on roll over */
765#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
766#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
767#define WDEV_NONE 0x0006 /* no event on roll over */
768#define WDEN 0x0FF0 /* enable watchdog */
769#define WDDIS 0x0AD0 /* disable watchdog */
770#define WDRO 0x8000 /* watchdog rolled over latch */
771
772/* depreciated WDOG_CTL Register Masks for legacy code */
773
774
775#define ICTL WDEV
776#define ENABLE_RESET WDEV_RESET
777#define WDOG_RESET WDEV_RESET
778#define ENABLE_NMI WDEV_NMI
779#define WDOG_NMI WDEV_NMI
780#define ENABLE_GPI WDEV_GPI
781#define WDOG_GPI WDEV_GPI
782#define DISABLE_EVT WDEV_NONE
783#define WDOG_NONE WDEV_NONE
784
785#define TMR_EN WDEN
786#define TMR_DIS WDDIS
787#define TRO WDRO
788#define ICTL_P0 0x01
789 #define ICTL_P1 0x02
790#define TRO_P 0x0F
791
792
793
794/* *************** REAL TIME CLOCK MASKS **************************/
795/* RTC_STAT and RTC_ALARM Masks */
796#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
797#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
798#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
799#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
800
801/* RTC_ALARM Macro z=day y=hr x=min w=sec */
802#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
803
804/* RTC_ICTL and RTC_ISTAT Masks */
805#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
806#define ALARM 0x0002 /* Alarm Interrupt Enable */
807#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
808#define MINUTE 0x0008 /* Minutes Interrupt Enable */
809#define HOUR 0x0010 /* Hours Interrupt Enable */
810#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
811#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
812#define WRITE_PENDING 0x4000 /* Write Pending Status */
813#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
814
815/* RTC_FAST / RTC_PREN Mask */
816#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
817
818
819/* ************** UART CONTROLLER MASKS *************************/ 707/* ************** UART CONTROLLER MASKS *************************/
820/* UARTx_LCR Masks */ 708/* UARTx_LCR Masks */
821#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
@@ -1372,33 +1260,6 @@
1372 1260
1373 1261
1374/* ************************** DMA CONTROLLER MASKS ********************************/ 1262/* ************************** DMA CONTROLLER MASKS ********************************/
1375/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1376#define DMAEN 0x0001 /* DMA Channel Enable */
1377#define WNR 0x0002 /* Channel Direction (W/R*) */
1378#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1379#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1380#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1381#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1382#define RESTART 0x0020 /* DMA Buffer Clear */
1383#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1384#define DI_EN 0x0080 /* Data Interrupt Enable */
1385#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1386#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1387#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1388#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1389#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1390#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1391#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1392#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1393#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1394#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1395#define NDSIZE 0x0900 /* Next Descriptor Size */
1396#define DMAFLOW 0x7000 /* Flow Control */
1397#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1398#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1399#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1400#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1401#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1402 1263
1403/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1264/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1404#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ 1265#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
@@ -1416,13 +1277,6 @@
1416#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ 1277#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1417#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ 1278#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1418 1279
1419/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1420#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1421#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1422#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1423#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1424
1425
1426/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ 1280/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1427/* PPI_CONTROL Masks */ 1281/* PPI_CONTROL Masks */
1428#define PORT_EN 0x0001 /* PPI Port Enable */ 1282#define PORT_EN 0x0001 /* PPI Port Enable */
@@ -1830,46 +1684,6 @@
1830#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 1684#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1831#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ 1685#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1832 1686
1833/* Bit masks for OTP_CONTROL */
1834
1835#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1836#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1837#define nFIEN 0x0
1838#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1839#define nFTESTDEC 0x0
1840#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1841#define nFWRTEST 0x0
1842#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1843#define nFRDEN 0x0
1844#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1845#define nFWREN 0x0
1846
1847/* Bit masks for OTP_BEN */
1848
1849#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1850
1851/* Bit masks for OTP_STATUS */
1852
1853#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1854#define nFCOMP 0x0
1855#define FERROR 0x2 /* OTP/Fuse Access Error */
1856#define nFERROR 0x0
1857#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1858#define nMMRGLOAD 0x0
1859#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1860#define nMMRGLOCK 0x0
1861#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1862#define nFPGMEN 0x0
1863
1864/* Bit masks for OTP_TIMING */
1865
1866#define USECDIV 0xff /* Micro Second Divider */
1867#define READACC 0x7f00 /* Read Access Time */
1868#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1869#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1870#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1871#define PGMTIME 0xff000000 /* Program Time */
1872
1873/* Bit masks for SECURE_SYSSWT */ 1687/* Bit masks for SECURE_SYSSWT */
1874 1688
1875#define EMUDABL 0x1 /* Emulation Disable. */ 1689#define EMUDABL 0x1 /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 848ac6f86823..1f8cbe9d6b9a 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -1,3 +1,7 @@
1config BF52x
2 def_bool y
3 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
4
1if (BF52x) 5if (BF52x)
2 6
3source "arch/blackfin/mach-bf527/boards/Kconfig" 7source "arch/blackfin/mach-bf527/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index f1996b13a3da..7ab0800e2914 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -15,9 +15,6 @@
15#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h> 16#include <linux/spi/flash.h>
17#include <linux/etherdevice.h> 17#include <linux/etherdevice.h>
18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
19#include <linux/usb/isp1362.h>
20#endif
21#include <linux/i2c.h> 18#include <linux/i2c.h>
22#include <linux/irq.h> 19#include <linux/irq.h>
23#include <linux/interrupt.h> 20#include <linux/interrupt.h>
@@ -65,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = {
65}; 62};
66 63
67static struct platform_device bfin_isp1760_device = { 64static struct platform_device bfin_isp1760_device = {
68 .name = "isp1760-hcd", 65 .name = "isp1760",
69 .id = 0, 66 .id = 0,
70 .dev = { 67 .dev = {
71 .platform_data = &isp1760_priv, 68 .platform_data = &isp1760_priv,
@@ -317,45 +314,6 @@ static struct platform_device sl811_hcd_device = {
317}; 314};
318#endif 315#endif
319 316
320#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
321static struct resource isp1362_hcd_resources[] = {
322 {
323 .start = 0x20360000,
324 .end = 0x20360000,
325 .flags = IORESOURCE_MEM,
326 }, {
327 .start = 0x20360004,
328 .end = 0x20360004,
329 .flags = IORESOURCE_MEM,
330 }, {
331 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
332 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
333 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
334 },
335};
336
337static struct isp1362_platform_data isp1362_priv = {
338 .sel15Kres = 1,
339 .clknotstop = 0,
340 .oc_enable = 0,
341 .int_act_high = 0,
342 .int_edge_triggered = 0,
343 .remote_wakeup_connected = 0,
344 .no_power_switching = 1,
345 .power_switching_mode = 0,
346};
347
348static struct platform_device isp1362_hcd_device = {
349 .name = "isp1362-hcd",
350 .id = 0,
351 .dev = {
352 .platform_data = &isp1362_priv,
353 },
354 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
355 .resource = isp1362_hcd_resources,
356};
357#endif
358
359#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 317#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
360static struct platform_device bfin_mii_bus = { 318static struct platform_device bfin_mii_bus = {
361 .name = "bfin_mii_bus", 319 .name = "bfin_mii_bus",
@@ -841,10 +799,6 @@ static struct platform_device *cmbf527_devices[] __initdata = {
841 &sl811_hcd_device, 799 &sl811_hcd_device,
842#endif 800#endif
843 801
844#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
845 &isp1362_hcd_device,
846#endif
847
848#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 802#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
849 &bfin_isp1760_device, 803 &bfin_isp1760_device,
850#endif 804#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index f09665f74ba0..5294fdd20732 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -13,9 +13,6 @@
13#include <linux/mtd/physmap.h> 13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h> 15#include <linux/spi/flash.h>
16#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
17#include <linux/usb/isp1362.h>
18#endif
19#include <linux/i2c.h> 16#include <linux/i2c.h>
20#include <linux/irq.h> 17#include <linux/irq.h>
21#include <linux/interrupt.h> 18#include <linux/interrupt.h>
@@ -63,7 +60,7 @@ static struct isp1760_platform_data isp1760_priv = {
63}; 60};
64 61
65static struct platform_device bfin_isp1760_device = { 62static struct platform_device bfin_isp1760_device = {
66 .name = "isp1760-hcd", 63 .name = "isp1760",
67 .id = 0, 64 .id = 0,
68 .dev = { 65 .dev = {
69 .platform_data = &isp1760_priv, 66 .platform_data = &isp1760_priv,
@@ -373,45 +370,6 @@ static struct platform_device sl811_hcd_device = {
373}; 370};
374#endif 371#endif
375 372
376#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
377static struct resource isp1362_hcd_resources[] = {
378 {
379 .start = 0x20360000,
380 .end = 0x20360000,
381 .flags = IORESOURCE_MEM,
382 }, {
383 .start = 0x20360004,
384 .end = 0x20360004,
385 .flags = IORESOURCE_MEM,
386 }, {
387 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
388 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
389 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
390 },
391};
392
393static struct isp1362_platform_data isp1362_priv = {
394 .sel15Kres = 1,
395 .clknotstop = 0,
396 .oc_enable = 0,
397 .int_act_high = 0,
398 .int_edge_triggered = 0,
399 .remote_wakeup_connected = 0,
400 .no_power_switching = 1,
401 .power_switching_mode = 0,
402};
403
404static struct platform_device isp1362_hcd_device = {
405 .name = "isp1362-hcd",
406 .id = 0,
407 .dev = {
408 .platform_data = &isp1362_priv,
409 },
410 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
411 .resource = isp1362_hcd_resources,
412};
413#endif
414
415#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 373#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
416static struct platform_device bfin_mii_bus = { 374static struct platform_device bfin_mii_bus = {
417 .name = "bfin_mii_bus", 375 .name = "bfin_mii_bus",
@@ -688,12 +646,6 @@ static struct platform_device bfin_spi0_device = {
688}; 646};
689#endif /* spi master and devices */ 647#endif /* spi master and devices */
690 648
691#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
692static struct platform_device bfin_fb_device = {
693 .name = "bf537-lq035",
694};
695#endif
696
697#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 649#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
698static struct resource bfin_uart_resources[] = { 650static struct resource bfin_uart_resources[] = {
699#ifdef CONFIG_SERIAL_BFIN_UART0 651#ifdef CONFIG_SERIAL_BFIN_UART0
@@ -850,7 +802,7 @@ static struct platform_device bfin_device_gpiokeys = {
850}; 802};
851#endif 803#endif
852 804
853#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) 805#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
854#include <linux/input.h> 806#include <linux/input.h>
855#include <asm/bfin_rotary.h> 807#include <asm/bfin_rotary.h>
856 808
@@ -924,10 +876,6 @@ static struct platform_device *stamp_devices[] __initdata = {
924 &sl811_hcd_device, 876 &sl811_hcd_device,
925#endif 877#endif
926 878
927#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
928 &isp1362_hcd_device,
929#endif
930
931#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 879#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
932 &bfin_isp1760_device, 880 &bfin_isp1760_device,
933#endif 881#endif
@@ -957,10 +905,6 @@ static struct platform_device *stamp_devices[] __initdata = {
957 &bfin_spi0_device, 905 &bfin_spi0_device,
958#endif 906#endif
959 907
960#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
961 &bfin_fb_device,
962#endif
963
964#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE) 908#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
965 &bf52x_t350mcqb_device, 909 &bf52x_t350mcqb_device,
966#endif 910#endif
@@ -991,7 +935,7 @@ static struct platform_device *stamp_devices[] __initdata = {
991 &bfin_device_gpiokeys, 935 &bfin_device_gpiokeys,
992#endif 936#endif
993 937
994#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) 938#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
995 &bfin_rotary_device, 939 &bfin_rotary_device,
996#endif 940#endif
997 941
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index e7d6034f268f..f714c5de3073 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -46,10 +46,4 @@
46#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 46#define OFFSET_SCR 0x1C /* SCR Scratch Register */
47#define OFFSET_GCTL 0x24 /* Global Control Register */ 47#define OFFSET_GCTL 0x24 /* Global Control Register */
48 48
49/* PLL_DIV Masks */
50#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
51#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
52#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
53#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
54
55#endif 49#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index dc3119e9f663..d7e2751c6bcc 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF525.h" 11#include "defBF525.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF525 is BF522 + USB */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF522.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
17
18/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
19#include "cdefBF52x_base.h"
20
21/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
22 15
23/* USB Control Registers */ 16/* USB Control Registers */
24 17
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index d6579449ee46..c7ba544d50b6 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF527.h" 11#include "defBF527.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF527 is BF525 + EMAC */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF525.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
17
18/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
19#include "cdefBF52x_base.h"
20
21/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
22 15
23/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 16/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
24 17
@@ -185,417 +178,4 @@
185#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) 178#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
186#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) 179#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
187 180
188/* USB Control Registers */
189
190#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
191#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
192#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
193#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
194#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
195#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
196#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
197#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
198#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
199#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
200#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
201#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
202#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
203#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
204#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
205#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
206#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
207#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
208#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
209#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
210#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
211#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
212#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
213#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
214#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
215#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
216
217/* USB Packet Control Registers */
218
219#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
220#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
221#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
222#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
223#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
224#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
225#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
226#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
227#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
228#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
229#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
230#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
231#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
232#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
233#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
234#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
235#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
236#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
237#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
238#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
239#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
240#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
241#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
242#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
243#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
244#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
245
246/* USB Endpoint FIFO Registers */
247
248#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
249#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
250#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
251#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
252#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
253#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
254#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
255#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
256#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
257#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
258#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
259#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
260#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
261#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
262#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
263#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
264
265/* USB OTG Control Registers */
266
267#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
268#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
269#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
270#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
271#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
272#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
273
274/* USB Phy Control Registers */
275
276#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
277#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
278#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
279#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
280#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
281#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
282#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
283#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
284#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
285#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
286
287/* (APHY_CNTRL is for ADI usage only) */
288
289#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
290#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
291
292/* (APHY_CALIB is for ADI usage only) */
293
294#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
295#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
296
297#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
298#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
299
300/* (PHY_TEST is for ADI usage only) */
301
302#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
303#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
304
305#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
306#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
307#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
308#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
309
310/* USB Endpoint 0 Control Registers */
311
312#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
313#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
314#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
315#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
316#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
317#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
318#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
319#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
320#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
321#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
322#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
323#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
324#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
325#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
326#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
327#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
328#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
329#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
330#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
331#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
332
333/* USB Endpoint 1 Control Registers */
334
335#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
336#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
337#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
338#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
339#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
340#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
341#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
342#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
343#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
344#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
345#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
346#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
347#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
348#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
349#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
350#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
351#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
352#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
353#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
354#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
355
356/* USB Endpoint 2 Control Registers */
357
358#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
359#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
360#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
361#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
362#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
363#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
364#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
365#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
366#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
367#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
368#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
369#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
370#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
371#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
372#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
373#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
374#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
375#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
376#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
377#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
378
379/* USB Endpoint 3 Control Registers */
380
381#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
382#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
383#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
384#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
385#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
386#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
387#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
388#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
389#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
390#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
391#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
392#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
393#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
394#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
395#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
396#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
397#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
398#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
399#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
400#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
401
402/* USB Endpoint 4 Control Registers */
403
404#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
405#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
406#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
407#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
408#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
409#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
410#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
411#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
412#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
413#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
414#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
415#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
416#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
417#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
418#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
419#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
420#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
421#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
422#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
423#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
424
425/* USB Endpoint 5 Control Registers */
426
427#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
428#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
429#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
430#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
431#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
432#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
433#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
434#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
435#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
436#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
437#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
438#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
439#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
440#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
441#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
442#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
443#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
444#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
445#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
446#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
447
448/* USB Endpoint 6 Control Registers */
449
450#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
451#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
452#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
453#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
454#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
455#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
456#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
457#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
458#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
459#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
460#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
461#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
462#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
463#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
464#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
465#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
466#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
467#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
468#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
469#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
470
471/* USB Endpoint 7 Control Registers */
472
473#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
474#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
475#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
476#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
477#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
478#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
479#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
480#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
481#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
482#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
483#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
484#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
485#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
486#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
487#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
488#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
489#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
490#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
491#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
492#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
493
494#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
495#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
496
497/* USB Channel 0 Config Registers */
498
499#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
500#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
501#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
502#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
503#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
504#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
505#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
506#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
507#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
508#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
509
510/* USB Channel 1 Config Registers */
511
512#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
513#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
514#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
515#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
516#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
517#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
518#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
519#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
520#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
521#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
522
523/* USB Channel 2 Config Registers */
524
525#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
526#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
527#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
528#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
529#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
530#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
531#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
532#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
533#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
534#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
535
536/* USB Channel 3 Config Registers */
537
538#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
539#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
540#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
541#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
542#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
543#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
544#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
545#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
546#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
547#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
548
549/* USB Channel 4 Config Registers */
550
551#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
552#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
553#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
554#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
555#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
556#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
557#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
558#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
559#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
560#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
561
562/* USB Channel 5 Config Registers */
563
564#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
565#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
566#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
567#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
568#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
569#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
570#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
571#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
572#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
573#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
574
575/* USB Channel 6 Config Registers */
576
577#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
578#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
579#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
580#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
581#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
582#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
583#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
584#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
585#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
586#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
587
588/* USB Channel 7 Config Registers */
589
590#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
591#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
592#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
593#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
594#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
595#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
596#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
597#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
598#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
599#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
600
601#endif /* _CDEF_BF527_H */ 181#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 7014dde10dd6..12f2ad45314e 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -844,6 +844,7 @@
844#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 844#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
845#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 845#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
846#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) 846#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
847#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
847#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) 848#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
848#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) 849#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
849#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) 850#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
@@ -1062,17 +1063,6 @@
1062#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1063#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1063#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1064#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1064 1065
1065/* OTP/FUSE Registers */
1066
1067#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1068#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1069#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1070#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1071#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1072#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1073#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1074#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1075
1076/* Security Registers */ 1066/* Security Registers */
1077 1067
1078#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1068#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -1082,17 +1072,6 @@
1082#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1072#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1083#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1073#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1084 1074
1085/* OTP Read/Write Data Buffer Registers */
1086
1087#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1088#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1089#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1090#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1091#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1092#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1093#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1094#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1095
1096/* NFC Registers */ 1075/* NFC Registers */
1097 1076
1098#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) 1077#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index 82abefc1ef6c..c136f7032962 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -7,15 +7,8 @@
7#ifndef _DEF_BF525_H 7#ifndef _DEF_BF525_H
8#define _DEF_BF525_H 8#define _DEF_BF525_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF525 is BF522 + USB */
11#include <asm/def_LPBlackfin.h> 11#include "defBF522.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
14
15/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
16#include "defBF52x_base.h"
17
18/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
19 12
20/* USB Control Registers */ 13/* USB Control Registers */
21 14
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 570a125df025..4dd58fb33156 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -7,15 +7,9 @@
7#ifndef _DEF_BF527_H 7#ifndef _DEF_BF527_H
8#define _DEF_BF527_H 8#define _DEF_BF527_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF527 is BF525 + EMAC */
11#include <asm/def_LPBlackfin.h> 11#include "defBF525.h"
12 12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
14
15/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
16#include "defBF52x_base.h"
17
18/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
19/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 13/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
20 14
21#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ 15#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
@@ -394,673 +388,4 @@
394#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ 388#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ 389#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
396 390
397/* USB Control Registers */
398
399#define USB_FADDR 0xffc03800 /* Function address register */
400#define USB_POWER 0xffc03804 /* Power management register */
401#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
402#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
403#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
404#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
405#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
406#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
407#define USB_FRAME 0xffc03820 /* USB frame number */
408#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
409#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
410#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
411#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
412
413/* USB Packet Control Registers */
414
415#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
416#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
417#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
418#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
419#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
420#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
421#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
422#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
423#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
424#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
425#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
426#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
427#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
428
429/* USB Endpoint FIFO Registers */
430
431#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
432#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
433#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
434#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
435#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
436#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
437#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
438#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
439
440/* USB OTG Control Registers */
441
442#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
443#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
444#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
445
446/* USB Phy Control Registers */
447
448#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
449#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
450#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
451#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
452#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
453
454/* (APHY_CNTRL is for ADI usage only) */
455
456#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
457
458/* (APHY_CALIB is for ADI usage only) */
459
460#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
461
462#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
463
464/* (PHY_TEST is for ADI usage only) */
465
466#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
467
468#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
469#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
470
471/* USB Endpoint 0 Control Registers */
472
473#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
474#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
475#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
476#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
477#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
478#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
479#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
480#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
481#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
482#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
483
484/* USB Endpoint 1 Control Registers */
485
486#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
487#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
488#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
489#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
490#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
491#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
492#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
493#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
494#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
495#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
496
497/* USB Endpoint 2 Control Registers */
498
499#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
500#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
501#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
502#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
503#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
504#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
505#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
506#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
507#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
508#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
509
510/* USB Endpoint 3 Control Registers */
511
512#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
513#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
514#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
515#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
516#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
517#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
518#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
519#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
520#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
521#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
522
523/* USB Endpoint 4 Control Registers */
524
525#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
526#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
527#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
528#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
529#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
530#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
531#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
532#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
533#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
534#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
535
536/* USB Endpoint 5 Control Registers */
537
538#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
539#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
540#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
541#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
542#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
543#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
544#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
545#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
546#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
547#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
548
549/* USB Endpoint 6 Control Registers */
550
551#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
552#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
553#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
554#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
555#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
556#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
557#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
558#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
559#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
560#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
561
562/* USB Endpoint 7 Control Registers */
563
564#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
565#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
566#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
567#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
568#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
569#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
570#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
571#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
572#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
573#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
574
575#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
576
577/* USB Channel 0 Config Registers */
578
579#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
580#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
581#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
582#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
583#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
584
585/* USB Channel 1 Config Registers */
586
587#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
588#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
589#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
590#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
591#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
592
593/* USB Channel 2 Config Registers */
594
595#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
596#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
597#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
598#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
599#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
600
601/* USB Channel 3 Config Registers */
602
603#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
604#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
605#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
606#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
607#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
608
609/* USB Channel 4 Config Registers */
610
611#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
612#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
613#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
614#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
615#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
616
617/* USB Channel 5 Config Registers */
618
619#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
620#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
621#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
622#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
623#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
624
625/* USB Channel 6 Config Registers */
626
627#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
628#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
629#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
630#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
631#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
632
633/* USB Channel 7 Config Registers */
634
635#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
636#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
637#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
638#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
639#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
640
641/* Bit masks for USB_FADDR */
642
643#define FUNCTION_ADDRESS 0x7f /* Function address */
644
645/* Bit masks for USB_POWER */
646
647#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
648#define nENABLE_SUSPENDM 0x0
649#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
650#define nSUSPEND_MODE 0x0
651#define RESUME_MODE 0x4 /* DMA Mode */
652#define nRESUME_MODE 0x0
653#define RESET 0x8 /* Reset indicator */
654#define nRESET 0x0
655#define HS_MODE 0x10 /* High Speed mode indicator */
656#define nHS_MODE 0x0
657#define HS_ENABLE 0x20 /* high Speed Enable */
658#define nHS_ENABLE 0x0
659#define SOFT_CONN 0x40 /* Soft connect */
660#define nSOFT_CONN 0x0
661#define ISO_UPDATE 0x80 /* Isochronous update */
662#define nISO_UPDATE 0x0
663
664/* Bit masks for USB_INTRTX */
665
666#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
667#define nEP0_TX 0x0
668#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
669#define nEP1_TX 0x0
670#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
671#define nEP2_TX 0x0
672#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
673#define nEP3_TX 0x0
674#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
675#define nEP4_TX 0x0
676#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
677#define nEP5_TX 0x0
678#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
679#define nEP6_TX 0x0
680#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
681#define nEP7_TX 0x0
682
683/* Bit masks for USB_INTRRX */
684
685#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
686#define nEP1_RX 0x0
687#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
688#define nEP2_RX 0x0
689#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
690#define nEP3_RX 0x0
691#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
692#define nEP4_RX 0x0
693#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
694#define nEP5_RX 0x0
695#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
696#define nEP6_RX 0x0
697#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
698#define nEP7_RX 0x0
699
700/* Bit masks for USB_INTRTXE */
701
702#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
703#define nEP0_TX_E 0x0
704#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
705#define nEP1_TX_E 0x0
706#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
707#define nEP2_TX_E 0x0
708#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
709#define nEP3_TX_E 0x0
710#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
711#define nEP4_TX_E 0x0
712#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
713#define nEP5_TX_E 0x0
714#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
715#define nEP6_TX_E 0x0
716#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
717#define nEP7_TX_E 0x0
718
719/* Bit masks for USB_INTRRXE */
720
721#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
722#define nEP1_RX_E 0x0
723#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
724#define nEP2_RX_E 0x0
725#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
726#define nEP3_RX_E 0x0
727#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
728#define nEP4_RX_E 0x0
729#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
730#define nEP5_RX_E 0x0
731#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
732#define nEP6_RX_E 0x0
733#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
734#define nEP7_RX_E 0x0
735
736/* Bit masks for USB_INTRUSB */
737
738#define SUSPEND_B 0x1 /* Suspend indicator */
739#define nSUSPEND_B 0x0
740#define RESUME_B 0x2 /* Resume indicator */
741#define nRESUME_B 0x0
742#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
743#define nRESET_OR_BABLE_B 0x0
744#define SOF_B 0x8 /* Start of frame */
745#define nSOF_B 0x0
746#define CONN_B 0x10 /* Connection indicator */
747#define nCONN_B 0x0
748#define DISCON_B 0x20 /* Disconnect indicator */
749#define nDISCON_B 0x0
750#define SESSION_REQ_B 0x40 /* Session Request */
751#define nSESSION_REQ_B 0x0
752#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
753#define nVBUS_ERROR_B 0x0
754
755/* Bit masks for USB_INTRUSBE */
756
757#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
758#define nSUSPEND_BE 0x0
759#define RESUME_BE 0x2 /* Resume indicator int enable */
760#define nRESUME_BE 0x0
761#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
762#define nRESET_OR_BABLE_BE 0x0
763#define SOF_BE 0x8 /* Start of frame int enable */
764#define nSOF_BE 0x0
765#define CONN_BE 0x10 /* Connection indicator int enable */
766#define nCONN_BE 0x0
767#define DISCON_BE 0x20 /* Disconnect indicator int enable */
768#define nDISCON_BE 0x0
769#define SESSION_REQ_BE 0x40 /* Session Request int enable */
770#define nSESSION_REQ_BE 0x0
771#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
772#define nVBUS_ERROR_BE 0x0
773
774/* Bit masks for USB_FRAME */
775
776#define FRAME_NUMBER 0x7ff /* Frame number */
777
778/* Bit masks for USB_INDEX */
779
780#define SELECTED_ENDPOINT 0xf /* selected endpoint */
781
782/* Bit masks for USB_GLOBAL_CTL */
783
784#define GLOBAL_ENA 0x1 /* enables USB module */
785#define nGLOBAL_ENA 0x0
786#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
787#define nEP1_TX_ENA 0x0
788#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
789#define nEP2_TX_ENA 0x0
790#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
791#define nEP3_TX_ENA 0x0
792#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
793#define nEP4_TX_ENA 0x0
794#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
795#define nEP5_TX_ENA 0x0
796#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
797#define nEP6_TX_ENA 0x0
798#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
799#define nEP7_TX_ENA 0x0
800#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
801#define nEP1_RX_ENA 0x0
802#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
803#define nEP2_RX_ENA 0x0
804#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
805#define nEP3_RX_ENA 0x0
806#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
807#define nEP4_RX_ENA 0x0
808#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
809#define nEP5_RX_ENA 0x0
810#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
811#define nEP6_RX_ENA 0x0
812#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
813#define nEP7_RX_ENA 0x0
814
815/* Bit masks for USB_OTG_DEV_CTL */
816
817#define SESSION 0x1 /* session indicator */
818#define nSESSION 0x0
819#define HOST_REQ 0x2 /* Host negotiation request */
820#define nHOST_REQ 0x0
821#define HOST_MODE 0x4 /* indicates USBDRC is a host */
822#define nHOST_MODE 0x0
823#define VBUS0 0x8 /* Vbus level indicator[0] */
824#define nVBUS0 0x0
825#define VBUS1 0x10 /* Vbus level indicator[1] */
826#define nVBUS1 0x0
827#define LSDEV 0x20 /* Low-speed indicator */
828#define nLSDEV 0x0
829#define FSDEV 0x40 /* Full or High-speed indicator */
830#define nFSDEV 0x0
831#define B_DEVICE 0x80 /* A' or 'B' device indicator */
832#define nB_DEVICE 0x0
833
834/* Bit masks for USB_OTG_VBUS_IRQ */
835
836#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
837#define nDRIVE_VBUS_ON 0x0
838#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
839#define nDRIVE_VBUS_OFF 0x0
840#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
841#define nCHRG_VBUS_START 0x0
842#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
843#define nCHRG_VBUS_END 0x0
844#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
845#define nDISCHRG_VBUS_START 0x0
846#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
847#define nDISCHRG_VBUS_END 0x0
848
849/* Bit masks for USB_OTG_VBUS_MASK */
850
851#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
852#define nDRIVE_VBUS_ON_ENA 0x0
853#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
854#define nDRIVE_VBUS_OFF_ENA 0x0
855#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
856#define nCHRG_VBUS_START_ENA 0x0
857#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
858#define nCHRG_VBUS_END_ENA 0x0
859#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
860#define nDISCHRG_VBUS_START_ENA 0x0
861#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
862#define nDISCHRG_VBUS_END_ENA 0x0
863
864/* Bit masks for USB_CSR0 */
865
866#define RXPKTRDY 0x1 /* data packet receive indicator */
867#define nRXPKTRDY 0x0
868#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
869#define nTXPKTRDY 0x0
870#define STALL_SENT 0x4 /* STALL handshake sent */
871#define nSTALL_SENT 0x0
872#define DATAEND 0x8 /* Data end indicator */
873#define nDATAEND 0x0
874#define SETUPEND 0x10 /* Setup end */
875#define nSETUPEND 0x0
876#define SENDSTALL 0x20 /* Send STALL handshake */
877#define nSENDSTALL 0x0
878#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
879#define nSERVICED_RXPKTRDY 0x0
880#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
881#define nSERVICED_SETUPEND 0x0
882#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
883#define nFLUSHFIFO 0x0
884#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
885#define nSTALL_RECEIVED_H 0x0
886#define SETUPPKT_H 0x8 /* send Setup token host mode */
887#define nSETUPPKT_H 0x0
888#define ERROR_H 0x10 /* timeout error indicator host mode */
889#define nERROR_H 0x0
890#define REQPKT_H 0x20 /* Request an IN transaction host mode */
891#define nREQPKT_H 0x0
892#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
893#define nSTATUSPKT_H 0x0
894#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
895#define nNAK_TIMEOUT_H 0x0
896
897/* Bit masks for USB_COUNT0 */
898
899#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
900
901/* Bit masks for USB_NAKLIMIT0 */
902
903#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
904
905/* Bit masks for USB_TX_MAX_PACKET */
906
907#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
908
909/* Bit masks for USB_RX_MAX_PACKET */
910
911#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
912
913/* Bit masks for USB_TXCSR */
914
915#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
916#define nTXPKTRDY_T 0x0
917#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
918#define nFIFO_NOT_EMPTY_T 0x0
919#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
920#define nUNDERRUN_T 0x0
921#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
922#define nFLUSHFIFO_T 0x0
923#define STALL_SEND_T 0x10 /* issue a Stall handshake */
924#define nSTALL_SEND_T 0x0
925#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
926#define nSTALL_SENT_T 0x0
927#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
928#define nCLEAR_DATATOGGLE_T 0x0
929#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
930#define nINCOMPTX_T 0x0
931#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
932#define nDMAREQMODE_T 0x0
933#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
934#define nFORCE_DATATOGGLE_T 0x0
935#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
936#define nDMAREQ_ENA_T 0x0
937#define ISO_T 0x4000 /* enable Isochronous transfers */
938#define nISO_T 0x0
939#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
940#define nAUTOSET_T 0x0
941#define ERROR_TH 0x4 /* error condition host mode */
942#define nERROR_TH 0x0
943#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
944#define nSTALL_RECEIVED_TH 0x0
945#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
946#define nNAK_TIMEOUT_TH 0x0
947
948/* Bit masks for USB_TXCOUNT */
949
950#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
951
952/* Bit masks for USB_RXCSR */
953
954#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
955#define nRXPKTRDY_R 0x0
956#define FIFO_FULL_R 0x2 /* FIFO not empty */
957#define nFIFO_FULL_R 0x0
958#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
959#define nOVERRUN_R 0x0
960#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
961#define nDATAERROR_R 0x0
962#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
963#define nFLUSHFIFO_R 0x0
964#define STALL_SEND_R 0x20 /* issue a Stall handshake */
965#define nSTALL_SEND_R 0x0
966#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
967#define nSTALL_SENT_R 0x0
968#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
969#define nCLEAR_DATATOGGLE_R 0x0
970#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
971#define nINCOMPRX_R 0x0
972#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
973#define nDMAREQMODE_R 0x0
974#define DISNYET_R 0x1000 /* disable Nyet handshakes */
975#define nDISNYET_R 0x0
976#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
977#define nDMAREQ_ENA_R 0x0
978#define ISO_R 0x4000 /* enable Isochronous transfers */
979#define nISO_R 0x0
980#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
981#define nAUTOCLEAR_R 0x0
982#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
983#define nERROR_RH 0x0
984#define REQPKT_RH 0x20 /* request an IN transaction host mode */
985#define nREQPKT_RH 0x0
986#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
987#define nSTALL_RECEIVED_RH 0x0
988#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
989#define nINCOMPRX_RH 0x0
990#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
991#define nDMAREQMODE_RH 0x0
992#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
993#define nAUTOREQ_RH 0x0
994
995/* Bit masks for USB_RXCOUNT */
996
997#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
998
999/* Bit masks for USB_TXTYPE */
1000
1001#define TARGET_EP_NO_T 0xf /* EP number */
1002#define PROTOCOL_T 0xc /* transfer type */
1003
1004/* Bit masks for USB_TXINTERVAL */
1005
1006#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1007
1008/* Bit masks for USB_RXTYPE */
1009
1010#define TARGET_EP_NO_R 0xf /* EP number */
1011#define PROTOCOL_R 0xc /* transfer type */
1012
1013/* Bit masks for USB_RXINTERVAL */
1014
1015#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1016
1017/* Bit masks for USB_DMA_INTERRUPT */
1018
1019#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1020#define nDMA0_INT 0x0
1021#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1022#define nDMA1_INT 0x0
1023#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1024#define nDMA2_INT 0x0
1025#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1026#define nDMA3_INT 0x0
1027#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1028#define nDMA4_INT 0x0
1029#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1030#define nDMA5_INT 0x0
1031#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1032#define nDMA6_INT 0x0
1033#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1034#define nDMA7_INT 0x0
1035
1036/* Bit masks for USB_DMAxCONTROL */
1037
1038#define DMA_ENA 0x1 /* DMA enable */
1039#define nDMA_ENA 0x0
1040#define DIRECTION 0x2 /* direction of DMA transfer */
1041#define nDIRECTION 0x0
1042#define MODE 0x4 /* DMA Bus error */
1043#define nMODE 0x0
1044#define INT_ENA 0x8 /* Interrupt enable */
1045#define nINT_ENA 0x0
1046#define EPNUM 0xf0 /* EP number */
1047#define BUSERROR 0x100 /* DMA Bus error */
1048#define nBUSERROR 0x0
1049
1050/* Bit masks for USB_DMAxADDRHIGH */
1051
1052#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1053
1054/* Bit masks for USB_DMAxADDRLOW */
1055
1056#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1057
1058/* Bit masks for USB_DMAxCOUNTHIGH */
1059
1060#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1061
1062/* Bit masks for USB_DMAxCOUNTLOW */
1063
1064#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1065
1066#endif /* _DEF_BF527_H */ 391#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index b9dbb73d7ef0..8b18b5359210 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -586,58 +586,6 @@
586** modifier UNLESS the lower order bits are saved and ORed back in when 586** modifier UNLESS the lower order bits are saved and ORed back in when
587** the macro is used. 587** the macro is used.
588*************************************************************************************/ 588*************************************************************************************/
589/*
590** ********************* PLL AND RESET MASKS ****************************************/
591/* PLL_CTL Masks */
592#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
593#define PLL_OFF 0x0002 /* PLL Not Powered */
594#define STOPCK 0x0008 /* Core Clock Off */
595#define PDWN 0x0020 /* Enter Deep Sleep Mode */
596#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
597#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
598#define BYPASS 0x0100 /* Bypass the PLL */
599#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
600/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
601#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
602
603/* PLL_DIV Masks */
604#define SSEL 0x000F /* System Select */
605#define CSEL 0x0030 /* Core Select */
606#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
607#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
608#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
609#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
610/* PLL_DIV Macros */
611#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
612
613/* VR_CTL Masks */
614#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
615#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
616
617#define VLEV 0x00F0 /* Internal Voltage Level */
618#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
619#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
620#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
621#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
622#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
623#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
624#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
625#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
626#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
627#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
628
629#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
630#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
631#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
632#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
633#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
634#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
635
636/* PLL_STAT Masks */
637#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
638#define FULL_ON 0x0002 /* Processor In Full On Mode */
639#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
640#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
641 589
642/* CHIPID Masks */ 590/* CHIPID Masks */
643#define CHIPID_VERSION 0xF0000000 591#define CHIPID_VERSION 0xF0000000
@@ -757,66 +705,6 @@
757#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 705#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
758 706
759 707
760/* ********* WATCHDOG TIMER MASKS ******************** */
761
762/* Watchdog Timer WDOG_CTL Register Masks */
763
764#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
765#define WDEV_RESET 0x0000 /* generate reset event on roll over */
766#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
767#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
768#define WDEV_NONE 0x0006 /* no event on roll over */
769#define WDEN 0x0FF0 /* enable watchdog */
770#define WDDIS 0x0AD0 /* disable watchdog */
771#define WDRO 0x8000 /* watchdog rolled over latch */
772
773/* depreciated WDOG_CTL Register Masks for legacy code */
774
775
776#define ICTL WDEV
777#define ENABLE_RESET WDEV_RESET
778#define WDOG_RESET WDEV_RESET
779#define ENABLE_NMI WDEV_NMI
780#define WDOG_NMI WDEV_NMI
781#define ENABLE_GPI WDEV_GPI
782#define WDOG_GPI WDEV_GPI
783#define DISABLE_EVT WDEV_NONE
784#define WDOG_NONE WDEV_NONE
785
786#define TMR_EN WDEN
787#define TMR_DIS WDDIS
788#define TRO WDRO
789#define ICTL_P0 0x01
790 #define ICTL_P1 0x02
791#define TRO_P 0x0F
792
793
794
795/* *************** REAL TIME CLOCK MASKS **************************/
796/* RTC_STAT and RTC_ALARM Masks */
797#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
798#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
799#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
800#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
801
802/* RTC_ALARM Macro z=day y=hr x=min w=sec */
803#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
804
805/* RTC_ICTL and RTC_ISTAT Masks */
806#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
807#define ALARM 0x0002 /* Alarm Interrupt Enable */
808#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
809#define MINUTE 0x0008 /* Minutes Interrupt Enable */
810#define HOUR 0x0010 /* Hours Interrupt Enable */
811#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
812#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
813#define WRITE_PENDING 0x4000 /* Write Pending Status */
814#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
815
816/* RTC_FAST / RTC_PREN Mask */
817#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
818
819
820/* ************** UART CONTROLLER MASKS *************************/ 708/* ************** UART CONTROLLER MASKS *************************/
821/* UARTx_LCR Masks */ 709/* UARTx_LCR Masks */
822#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 710#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
@@ -1381,33 +1269,6 @@
1381 1269
1382 1270
1383/* ************************** DMA CONTROLLER MASKS ********************************/ 1271/* ************************** DMA CONTROLLER MASKS ********************************/
1384/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1385#define DMAEN 0x0001 /* DMA Channel Enable */
1386#define WNR 0x0002 /* Channel Direction (W/R*) */
1387#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1388#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1389#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1390#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1391#define RESTART 0x0020 /* DMA Buffer Clear */
1392#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1393#define DI_EN 0x0080 /* Data Interrupt Enable */
1394#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1395#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1396#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1397#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1398#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1399#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1400#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1401#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1402#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1403#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1404#define NDSIZE 0x0900 /* Next Descriptor Size */
1405#define DMAFLOW 0x7000 /* Flow Control */
1406#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1407#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1408#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1409#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1410#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1411 1272
1412/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1273/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1413#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ 1274#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
@@ -1425,13 +1286,6 @@
1425#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ 1286#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1426#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ 1287#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1427 1288
1428/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1429#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1430#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1431#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1432#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1433
1434
1435/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ 1289/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1436/* PPI_CONTROL Masks */ 1290/* PPI_CONTROL Masks */
1437#define PORT_EN 0x0001 /* PPI Port Enable */ 1291#define PORT_EN 0x0001 /* PPI Port Enable */
@@ -1843,46 +1697,6 @@
1843#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 1697#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1844#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ 1698#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1845 1699
1846/* Bit masks for OTP_CONTROL */
1847
1848#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1849#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1850#define nFIEN 0x0
1851#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1852#define nFTESTDEC 0x0
1853#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1854#define nFWRTEST 0x0
1855#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1856#define nFRDEN 0x0
1857#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1858#define nFWREN 0x0
1859
1860/* Bit masks for OTP_BEN */
1861
1862#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1863
1864/* Bit masks for OTP_STATUS */
1865
1866#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1867#define nFCOMP 0x0
1868#define FERROR 0x2 /* OTP/Fuse Access Error */
1869#define nFERROR 0x0
1870#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1871#define nMMRGLOAD 0x0
1872#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1873#define nMMRGLOCK 0x0
1874#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1875#define nFPGMEN 0x0
1876
1877/* Bit masks for OTP_TIMING */
1878
1879#define USECDIV 0xff /* Micro Second Divider */
1880#define READACC 0x7f00 /* Read Access Time */
1881#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1882#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1883#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1884#define PGMTIME 0xff000000 /* Program Time */
1885
1886/* Bit masks for SECURE_SYSSWT */ 1700/* Bit masks for SECURE_SYSSWT */
1887 1701
1888#define EMUDABL 0x1 /* Emulation Disable. */ 1702#define EMUDABL 0x1 /* Emulation Disable. */
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 43f43a095a99..4adceb0bdb6d 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -166,7 +166,6 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
166#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) 166#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
167/* SPI ADC chip */ 167/* SPI ADC chip */
168static struct bfin5xx_spi_chip spi_adc_chip_info = { 168static struct bfin5xx_spi_chip spi_adc_chip_info = {
169 .ctl_reg = 0x1000,
170 .enable_dma = 1, /* use dma transfer with this chip*/ 169 .enable_dma = 1, /* use dma transfer with this chip*/
171 .bits_per_word = 16, 170 .bits_per_word = 16,
172}; 171};
@@ -174,7 +173,6 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
174 173
175#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) 174#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
176static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 175static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
177 .ctl_reg = 0x1000,
178 .enable_dma = 0, 176 .enable_dma = 0,
179 .bits_per_word = 16, 177 .bits_per_word = 16,
180}; 178};
@@ -258,12 +256,6 @@ static struct platform_device bfin_spi0_device = {
258}; 256};
259#endif /* spi master and devices */ 257#endif /* spi master and devices */
260 258
261#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
262static struct platform_device bfin_fb_device = {
263 .name = "bf537-fb",
264};
265#endif
266
267#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 259#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
268static struct resource bfin_uart_resources[] = { 260static struct resource bfin_uart_resources[] = {
269 { 261 {
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 644be5e5ab6f..8ec42ba35b9e 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -20,6 +20,7 @@
20#endif 20#endif
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/bfin5xx_spi.h> 22#include <asm/bfin5xx_spi.h>
23#include <asm/portmux.h>
23 24
24/* 25/*
25 * Name the Board for the /proc/cpuinfo 26 * Name the Board for the /proc/cpuinfo
@@ -107,20 +108,6 @@ static struct platform_device dm9000_device2 = {
107 108
108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 109#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip mmc_spi_chip_info = { 110static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110/*
111 * CPOL (Clock Polarity)
112 * 0 - Active high SCK
113 * 1 - Active low SCK
114 * CPHA (Clock Phase) Selects transfer format and operation mode
115 * 0 - SCLK toggles from middle of the first data bit, slave select
116 * pins controlled by hardware.
117 * 1 - SCLK toggles from beginning of first data bit, slave select
118 * pins controller by user software.
119 * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
120 * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
121 * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
122 */
123 .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
124 .enable_dma = 0, /* if 1 - block!!! */ 111 .enable_dma = 0, /* if 1 - block!!! */
125 .bits_per_word = 8, 112 .bits_per_word = 8,
126}; 113};
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 82f70efd66e7..6d68dcfa2da2 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -321,12 +321,6 @@ static struct platform_device bfin_spi0_device = {
321}; 321};
322#endif /* spi master and devices */ 322#endif /* spi master and devices */
323 323
324#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
325static struct platform_device bfin_fb_device = {
326 .name = "bf537-fb",
327};
328#endif
329
330#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 324#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
331static struct resource bfin_uart_resources[] = { 325static struct resource bfin_uart_resources[] = {
332 { 326 {
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 02b328eb0e07..e9ff491c0953 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -370,72 +370,6 @@
370/* System MMR Register Bits */ 370/* System MMR Register Bits */
371/******************************************************************************* */ 371/******************************************************************************* */
372 372
373/* ********************* PLL AND RESET MASKS ************************ */
374
375/* PLL_CTL Masks */
376#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
377#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
378#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
379#define PLL_OFF 0x0002 /* Shut off PLL clocks */
380#define STOPCK_OFF 0x0008 /* Core clock off */
381#define STOPCK 0x0008 /* Core Clock Off */
382#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
383#if !defined(__ADSPBF538__)
384/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
385# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
386# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
387#endif
388#define BYPASS 0x0100 /* Bypass the PLL */
389/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
390#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
391
392/* PLL_DIV Masks */
393#define SSEL 0x000F /* System Select */
394#define CSEL 0x0030 /* Core Select */
395
396#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
397
398#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
399#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
400#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
401#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
402/* PLL_DIV Macros */
403#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
404
405/* PLL_STAT Masks */
406#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
407#define FULL_ON 0x0002 /* Processor In Full On Mode */
408#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
409#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
410
411/* VR_CTL Masks */
412#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
413#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
414#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
415#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
416#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
417
418#define GAIN 0x000C /* Voltage Level Gain */
419#define GAIN_5 0x0000 /* GAIN = 5 */
420#define GAIN_10 0x0004 /* GAIN = 10 */
421#define GAIN_20 0x0008 /* GAIN = 20 */
422#define GAIN_50 0x000C /* GAIN = 50 */
423
424#define VLEV 0x00F0 /* Internal Voltage Level */
425#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
426#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
427#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
428#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
429#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
430#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
431#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
432#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
433#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
434#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
435
436#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
437#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
438
439/* CHIPID Masks */ 373/* CHIPID Masks */
440#define CHIPID_VERSION 0xF0000000 374#define CHIPID_VERSION 0xF0000000
441#define CHIPID_FAMILY 0x0FFFF000 375#define CHIPID_FAMILY 0x0FFFF000
@@ -703,54 +637,7 @@
703 637
704/* ********** DMA CONTROLLER MASKS *********************8 */ 638/* ********** DMA CONTROLLER MASKS *********************8 */
705 639
706/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */ 640/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
707#define DMAEN 0x00000001 /* Channel Enable */
708#define WNR 0x00000002 /* Channel Direction (W/R*) */
709#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
710#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
711#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
712#define DMA2D 0x00000010 /* 2D/1D* Mode */
713#define RESTART 0x00000020 /* Restart */
714#define DI_SEL 0x00000040 /* Data Interrupt Select */
715#define DI_EN 0x00000080 /* Data Interrupt Enable */
716#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
717#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
718#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
719#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
720#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
721#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
722#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
723#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
724#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
725#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
726#define NDSIZE 0x00000900 /* Next Descriptor Size */
727#define DMAFLOW 0x00007000 /* Flow Control */
728#define DMAFLOW_STOP 0x0000 /* Stop Mode */
729#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
730#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
731#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
732#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
733
734#define DMAEN_P 0 /* Channel Enable */
735#define WNR_P 1 /* Channel Direction (W/R*) */
736#define DMA2D_P 4 /* 2D/1D* Mode */
737#define RESTART_P 5 /* Restart */
738#define DI_SEL_P 6 /* Data Interrupt Select */
739#define DI_EN_P 7 /* Data Interrupt Enable */
740
741/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
742
743#define DMA_DONE 0x00000001 /* DMA Done Indicator */
744#define DMA_ERR 0x00000002 /* DMA Error Indicator */
745#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
746#define DMA_RUN 0x00000008 /* DMA Running Indicator */
747
748#define DMA_DONE_P 0 /* DMA Done Indicator */
749#define DMA_ERR_P 1 /* DMA Error Indicator */
750#define DFETCH_P 2 /* Descriptor Fetch Indicator */
751#define DMA_RUN_P 3 /* DMA Running Indicator */
752
753/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
754 641
755#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ 642#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
756#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ 643#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 9ba290466b56..4e0afda472ab 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -13,9 +13,6 @@
13#include <linux/mtd/partitions.h> 13#include <linux/mtd/partitions.h>
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h> 15#include <linux/spi/flash.h>
16#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
17#include <linux/usb/isp1362.h>
18#endif
19#include <linux/irq.h> 16#include <linux/irq.h>
20#include <asm/dma.h> 17#include <asm/dma.h>
21#include <asm/bfin5xx_spi.h> 18#include <asm/bfin5xx_spi.h>
@@ -147,45 +144,6 @@ static struct platform_device sl811_hcd_device = {
147}; 144};
148#endif 145#endif
149 146
150#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
151static struct resource isp1362_hcd_resources[] = {
152 {
153 .start = 0x20360000,
154 .end = 0x20360000,
155 .flags = IORESOURCE_MEM,
156 }, {
157 .start = 0x20360004,
158 .end = 0x20360004,
159 .flags = IORESOURCE_MEM,
160 }, {
161 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
162 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
163 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
164 },
165};
166
167static struct isp1362_platform_data isp1362_priv = {
168 .sel15Kres = 1,
169 .clknotstop = 0,
170 .oc_enable = 0,
171 .int_act_high = 0,
172 .int_edge_triggered = 0,
173 .remote_wakeup_connected = 0,
174 .no_power_switching = 1,
175 .power_switching_mode = 0,
176};
177
178static struct platform_device isp1362_hcd_device = {
179 .name = "isp1362-hcd",
180 .id = 0,
181 .dev = {
182 .platform_data = &isp1362_priv,
183 },
184 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
185 .resource = isp1362_hcd_resources,
186};
187#endif
188
189#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 147#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
190static struct platform_device bfin_mii_bus = { 148static struct platform_device bfin_mii_bus = {
191 .name = "bfin_mii_bus", 149 .name = "bfin_mii_bus",
@@ -492,10 +450,6 @@ static struct platform_device *stamp_devices[] __initdata = {
492 &sl811_hcd_device, 450 &sl811_hcd_device,
493#endif 451#endif
494 452
495#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
496 &isp1362_hcd_device,
497#endif
498
499#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 453#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
500 &smc91x_device, 454 &smc91x_device,
501#endif 455#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index c46baa5e6d9b..ac9b52e0087c 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -9,6 +9,7 @@
9#include <linux/device.h> 9#include <linux/device.h>
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/io.h>
12#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
13#include <linux/mtd/nand.h> 14#include <linux/mtd/nand.h>
14#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
@@ -25,6 +26,8 @@
25#include <linux/i2c.h> 26#include <linux/i2c.h>
26#include <linux/usb/sl811.h> 27#include <linux/usb/sl811.h>
27#include <linux/spi/mmc_spi.h> 28#include <linux/spi/mmc_spi.h>
29#include <linux/leds.h>
30#include <linux/input.h>
28#include <asm/dma.h> 31#include <asm/dma.h>
29#include <asm/bfin5xx_spi.h> 32#include <asm/bfin5xx_spi.h>
30#include <asm/reboot.h> 33#include <asm/reboot.h>
@@ -65,7 +68,7 @@ static struct isp1760_platform_data isp1760_priv = {
65}; 68};
66 69
67static struct platform_device bfin_isp1760_device = { 70static struct platform_device bfin_isp1760_device = {
68 .name = "isp1760-hcd", 71 .name = "isp1760",
69 .id = 0, 72 .id = 0,
70 .dev = { 73 .dev = {
71 .platform_data = &isp1760_priv, 74 .platform_data = &isp1760_priv,
@@ -76,7 +79,6 @@ static struct platform_device bfin_isp1760_device = {
76#endif 79#endif
77 80
78#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 81#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
79#include <linux/input.h>
80#include <linux/gpio_keys.h> 82#include <linux/gpio_keys.h>
81 83
82static struct gpio_keys_button bfin_gpio_keys_table[] = { 84static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -195,28 +197,6 @@ static struct platform_device dm9000_device = {
195}; 197};
196#endif 198#endif
197 199
198#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
199static struct resource ax88180_resources[] = {
200 [0] = {
201 .start = 0x20300000,
202 .end = 0x20300000 + 0x8000,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = IRQ_PF7,
207 .end = IRQ_PF7,
208 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
209 },
210};
211
212static struct platform_device ax88180_device = {
213 .name = "ax88180",
214 .id = -1,
215 .num_resources = ARRAY_SIZE(ax88180_resources),
216 .resource = ax88180_resources,
217};
218#endif
219
220#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) 200#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
221static struct resource sl811_hcd_resources[] = { 201static struct resource sl811_hcd_resources[] = {
222 { 202 {
@@ -272,8 +252,8 @@ static struct resource isp1362_hcd_resources[] = {
272 .end = 0x20360004, 252 .end = 0x20360004,
273 .flags = IORESOURCE_MEM, 253 .flags = IORESOURCE_MEM,
274 }, { 254 }, {
275 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 255 .start = IRQ_PF3,
276 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 256 .end = IRQ_PF3,
277 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 257 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
278 }, 258 },
279}; 259};
@@ -300,6 +280,44 @@ static struct platform_device isp1362_hcd_device = {
300}; 280};
301#endif 281#endif
302 282
283#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
284unsigned short bfin_can_peripherals[] = {
285 P_CAN0_RX, P_CAN0_TX, 0
286};
287
288static struct resource bfin_can_resources[] = {
289 {
290 .start = 0xFFC02A00,
291 .end = 0xFFC02FFF,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = IRQ_CAN_RX,
296 .end = IRQ_CAN_RX,
297 .flags = IORESOURCE_IRQ,
298 },
299 {
300 .start = IRQ_CAN_TX,
301 .end = IRQ_CAN_TX,
302 .flags = IORESOURCE_IRQ,
303 },
304 {
305 .start = IRQ_CAN_ERROR,
306 .end = IRQ_CAN_ERROR,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct platform_device bfin_can_device = {
312 .name = "bfin_can",
313 .num_resources = ARRAY_SIZE(bfin_can_resources),
314 .resource = bfin_can_resources,
315 .dev = {
316 .platform_data = &bfin_can_peripherals, /* Passed to driver */
317 },
318};
319#endif
320
303#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 321#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
304static struct platform_device bfin_mii_bus = { 322static struct platform_device bfin_mii_bus = {
305 .name = "bfin_mii_bus", 323 .name = "bfin_mii_bus",
@@ -514,15 +532,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
514}; 532};
515#endif 533#endif
516 534
517#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) 535#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
518#include <linux/input.h>
519#include <linux/input/ad714x.h> 536#include <linux/input/ad714x.h>
520static struct bfin5xx_spi_chip ad7147_spi_chip_info = { 537static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
521 .enable_dma = 0, 538 .enable_dma = 0,
522 .bits_per_word = 16, 539 .bits_per_word = 16,
523}; 540};
524 541
525static struct ad714x_slider_plat slider_plat[] = { 542static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
526 { 543 {
527 .start_stage = 0, 544 .start_stage = 0,
528 .end_stage = 7, 545 .end_stage = 7,
@@ -530,7 +547,7 @@ static struct ad714x_slider_plat slider_plat[] = {
530 }, 547 },
531}; 548};
532 549
533static struct ad714x_button_plat button_plat[] = { 550static struct ad714x_button_plat ad7147_spi_button_plat[] = {
534 { 551 {
535 .keycode = BTN_FORWARD, 552 .keycode = BTN_FORWARD,
536 .l_mask = 0, 553 .l_mask = 0,
@@ -557,11 +574,11 @@ static struct ad714x_button_plat button_plat[] = {
557 .h_mask = 0x400, 574 .h_mask = 0x400,
558 }, 575 },
559}; 576};
560static struct ad714x_platform_data ad7147_platfrom_data = { 577static struct ad714x_platform_data ad7147_spi_platform_data = {
561 .slider_num = 1, 578 .slider_num = 1,
562 .button_num = 5, 579 .button_num = 5,
563 .slider = slider_plat, 580 .slider = ad7147_spi_slider_plat,
564 .button = button_plat, 581 .button = ad7147_spi_button_plat,
565 .stage_cfg_reg = { 582 .stage_cfg_reg = {
566 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, 583 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
567 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, 584 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
@@ -580,10 +597,9 @@ static struct ad714x_platform_data ad7147_platfrom_data = {
580}; 597};
581#endif 598#endif
582 599
583#if defined(CONFIG_INPUT_EVAL_AD7142EB) 600#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
584#include <linux/input.h>
585#include <linux/input/ad714x.h> 601#include <linux/input/ad714x.h>
586static struct ad714x_button_plat button_plat[] = { 602static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
587 { 603 {
588 .keycode = BTN_1, 604 .keycode = BTN_1,
589 .l_mask = 0, 605 .l_mask = 0,
@@ -605,9 +621,9 @@ static struct ad714x_button_plat button_plat[] = {
605 .h_mask = 0x8, 621 .h_mask = 0x8,
606 }, 622 },
607}; 623};
608static struct ad714x_platform_data ad7142_platfrom_data = { 624static struct ad714x_platform_data ad7142_i2c_platform_data = {
609 .button_num = 4, 625 .button_num = 4,
610 .button = button_plat, 626 .button = ad7142_i2c_button_plat,
611 .stage_cfg_reg = { 627 .stage_cfg_reg = {
612 /* fixme: figure out right setting for all comoponent according 628 /* fixme: figure out right setting for all comoponent according
613 * to hardware feature of EVAL-AD7142EB board */ 629 * to hardware feature of EVAL-AD7142EB board */
@@ -696,8 +712,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
696#endif 712#endif
697 713
698#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) 714#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
699#include <linux/input.h> 715#include <linux/input/adxl34x.h>
700#include <linux/spi/adxl34x.h>
701static const struct adxl34x_platform_data adxl34x_info = { 716static const struct adxl34x_platform_data adxl34x_info = {
702 .x_axis_offset = 0, 717 .x_axis_offset = 0,
703 .y_axis_offset = 0, 718 .y_axis_offset = 0,
@@ -721,9 +736,7 @@ static const struct adxl34x_platform_data adxl34x_info = {
721 .ev_code_y = ABS_Y, /* EV_REL */ 736 .ev_code_y = ABS_Y, /* EV_REL */
722 .ev_code_z = ABS_Z, /* EV_REL */ 737 .ev_code_z = ABS_Z, /* EV_REL */
723 738
724 .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ 739 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
725 .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
726 .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
727 740
728/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ 741/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
729/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ 742/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
@@ -761,6 +774,47 @@ static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
761}; 774};
762#endif 775#endif
763 776
777#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
778static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
779 .bits_per_word = 16,
780 .cs_gpio = GPIO_PF10,
781};
782
783#include <linux/spi/adf702x.h>
784#define TXREG 0x0160A470
785static const u32 adf7021_regs[] = {
786 0x09608FA0,
787 0x00575011,
788 0x00A7F092,
789 0x2B141563,
790 0x81F29E94,
791 0x00003155,
792 0x050A4F66,
793 0x00000007,
794 0x00000008,
795 0x000231E9,
796 0x3296354A,
797 0x891A2B3B,
798 0x00000D9C,
799 0x0000000D,
800 0x0000000E,
801 0x0000000F,
802};
803
804static struct adf702x_platform_data adf7021_platform_data = {
805 .regs_base = (void *)SPORT1_TCR1,
806 .dma_ch_rx = CH_SPORT1_RX,
807 .dma_ch_tx = CH_SPORT1_TX,
808 .irq_sport_err = IRQ_SPORT1_ERROR,
809 .gpio_int_rfs = GPIO_PF8,
810 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
811 P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
812 .adf702x_model = MODEL_ADF7021,
813 .adf702x_regs = adf7021_regs,
814 .tx_reg = TXREG,
815};
816#endif
817
764#if defined(CONFIG_MTD_DATAFLASH) \ 818#if defined(CONFIG_MTD_DATAFLASH) \
765 || defined(CONFIG_MTD_DATAFLASH_MODULE) 819 || defined(CONFIG_MTD_DATAFLASH_MODULE)
766 820
@@ -794,6 +848,13 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
794}; 848};
795#endif 849#endif
796 850
851#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
852static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
853 .enable_dma = 0, /* use dma transfer with this chip*/
854 .bits_per_word = 8,
855};
856#endif
857
797static struct spi_board_info bfin_spi_board_info[] __initdata = { 858static struct spi_board_info bfin_spi_board_info[] __initdata = {
798#if defined(CONFIG_MTD_M25P80) \ 859#if defined(CONFIG_MTD_M25P80) \
799 || defined(CONFIG_MTD_M25P80_MODULE) 860 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -855,7 +916,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
855 }, 916 },
856#endif 917#endif
857 918
858#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) 919#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
859 { 920 {
860 .modalias = "ad714x_captouch", 921 .modalias = "ad714x_captouch",
861 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ 922 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
@@ -863,7 +924,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
863 .bus_num = 0, 924 .bus_num = 0,
864 .chip_select = 5, 925 .chip_select = 5,
865 .mode = SPI_MODE_3, 926 .mode = SPI_MODE_3,
866 .platform_data = &ad7147_platfrom_data, 927 .platform_data = &ad7147_spi_platform_data,
867 .controller_data = &ad7147_spi_chip_info, 928 .controller_data = &ad7147_spi_chip_info,
868 }, 929 },
869#endif 930#endif
@@ -932,6 +993,30 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
932 .mode = SPI_MODE_0, 993 .mode = SPI_MODE_0,
933 }, 994 },
934#endif 995#endif
996#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
997 {
998 .modalias = "adxl34x",
999 .platform_data = &adxl34x_info,
1000 .irq = IRQ_PF6,
1001 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1002 .bus_num = 0,
1003 .chip_select = 2,
1004 .controller_data = &spi_adxl34x_chip_info,
1005 .mode = SPI_MODE_3,
1006 },
1007#endif
1008#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
1009 {
1010 .modalias = "adf702x",
1011 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1012 .bus_num = 0,
1013 .chip_select = 0, /* GPIO controlled SSEL */
1014 .controller_data = &adf7021_spi_chip_info,
1015 .platform_data = &adf7021_platform_data,
1016 .mode = SPI_MODE_0,
1017 },
1018#endif
1019
935}; 1020};
936 1021
937#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 1022#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -1175,7 +1260,6 @@ static struct platform_device i2c_bfin_twi_device = {
1175#endif 1260#endif
1176 1261
1177#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) 1262#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
1178#include <linux/input.h>
1179#include <linux/i2c/adp5588.h> 1263#include <linux/i2c/adp5588.h>
1180static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { 1264static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
1181 [0] = KEY_GRAVE, 1265 [0] = KEY_GRAVE,
@@ -1268,35 +1352,33 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1268 * ADP5520/5501 Backlight Data 1352 * ADP5520/5501 Backlight Data
1269 */ 1353 */
1270 1354
1271static struct adp5520_backlight_platfrom_data adp5520_backlight_data = { 1355static struct adp5520_backlight_platform_data adp5520_backlight_data = {
1272 .fade_in = FADE_T_1200ms, 1356 .fade_in = ADP5520_FADE_T_1200ms,
1273 .fade_out = FADE_T_1200ms, 1357 .fade_out = ADP5520_FADE_T_1200ms,
1274 .fade_led_law = BL_LAW_LINEAR, 1358 .fade_led_law = ADP5520_BL_LAW_LINEAR,
1275 .en_ambl_sens = 1, 1359 .en_ambl_sens = 1,
1276 .abml_filt = BL_AMBL_FILT_640ms, 1360 .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
1277 .l1_daylight_max = BL_CUR_mA(15), 1361 .l1_daylight_max = ADP5520_BL_CUR_mA(15),
1278 .l1_daylight_dim = BL_CUR_mA(0), 1362 .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
1279 .l2_office_max = BL_CUR_mA(7), 1363 .l2_office_max = ADP5520_BL_CUR_mA(7),
1280 .l2_office_dim = BL_CUR_mA(0), 1364 .l2_office_dim = ADP5520_BL_CUR_mA(0),
1281 .l3_dark_max = BL_CUR_mA(3), 1365 .l3_dark_max = ADP5520_BL_CUR_mA(3),
1282 .l3_dark_dim = BL_CUR_mA(0), 1366 .l3_dark_dim = ADP5520_BL_CUR_mA(0),
1283 .l2_trip = L2_COMP_CURR_uA(700), 1367 .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
1284 .l2_hyst = L2_COMP_CURR_uA(50), 1368 .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
1285 .l3_trip = L3_COMP_CURR_uA(80), 1369 .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
1286 .l3_hyst = L3_COMP_CURR_uA(20), 1370 .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
1287}; 1371};
1288 1372
1289 /* 1373 /*
1290 * ADP5520/5501 LEDs Data 1374 * ADP5520/5501 LEDs Data
1291 */ 1375 */
1292 1376
1293#include <linux/leds.h>
1294
1295static struct led_info adp5520_leds[] = { 1377static struct led_info adp5520_leds[] = {
1296 { 1378 {
1297 .name = "adp5520-led1", 1379 .name = "adp5520-led1",
1298 .default_trigger = "none", 1380 .default_trigger = "none",
1299 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms, 1381 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
1300 }, 1382 },
1301#ifdef ADP5520_EN_ALL_LEDS 1383#ifdef ADP5520_EN_ALL_LEDS
1302 { 1384 {
@@ -1312,51 +1394,50 @@ static struct led_info adp5520_leds[] = {
1312#endif 1394#endif
1313}; 1395};
1314 1396
1315static struct adp5520_leds_platfrom_data adp5520_leds_data = { 1397static struct adp5520_leds_platform_data adp5520_leds_data = {
1316 .num_leds = ARRAY_SIZE(adp5520_leds), 1398 .num_leds = ARRAY_SIZE(adp5520_leds),
1317 .leds = adp5520_leds, 1399 .leds = adp5520_leds,
1318 .fade_in = FADE_T_600ms, 1400 .fade_in = ADP5520_FADE_T_600ms,
1319 .fade_out = FADE_T_600ms, 1401 .fade_out = ADP5520_FADE_T_600ms,
1320 .led_on_time = LED_ONT_600ms, 1402 .led_on_time = ADP5520_LED_ONT_600ms,
1321}; 1403};
1322 1404
1323 /* 1405 /*
1324 * ADP5520 GPIO Data 1406 * ADP5520 GPIO Data
1325 */ 1407 */
1326 1408
1327static struct adp5520_gpio_platfrom_data adp5520_gpio_data = { 1409static struct adp5520_gpio_platform_data adp5520_gpio_data = {
1328 .gpio_start = 50, 1410 .gpio_start = 50,
1329 .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, 1411 .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
1330 .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, 1412 .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
1331}; 1413};
1332 1414
1333 /* 1415 /*
1334 * ADP5520 Keypad Data 1416 * ADP5520 Keypad Data
1335 */ 1417 */
1336 1418
1337#include <linux/input.h>
1338static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { 1419static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
1339 [KEY(0, 0)] = KEY_GRAVE, 1420 [ADP5520_KEY(0, 0)] = KEY_GRAVE,
1340 [KEY(0, 1)] = KEY_1, 1421 [ADP5520_KEY(0, 1)] = KEY_1,
1341 [KEY(0, 2)] = KEY_2, 1422 [ADP5520_KEY(0, 2)] = KEY_2,
1342 [KEY(0, 3)] = KEY_3, 1423 [ADP5520_KEY(0, 3)] = KEY_3,
1343 [KEY(1, 0)] = KEY_4, 1424 [ADP5520_KEY(1, 0)] = KEY_4,
1344 [KEY(1, 1)] = KEY_5, 1425 [ADP5520_KEY(1, 1)] = KEY_5,
1345 [KEY(1, 2)] = KEY_6, 1426 [ADP5520_KEY(1, 2)] = KEY_6,
1346 [KEY(1, 3)] = KEY_7, 1427 [ADP5520_KEY(1, 3)] = KEY_7,
1347 [KEY(2, 0)] = KEY_8, 1428 [ADP5520_KEY(2, 0)] = KEY_8,
1348 [KEY(2, 1)] = KEY_9, 1429 [ADP5520_KEY(2, 1)] = KEY_9,
1349 [KEY(2, 2)] = KEY_0, 1430 [ADP5520_KEY(2, 2)] = KEY_0,
1350 [KEY(2, 3)] = KEY_MINUS, 1431 [ADP5520_KEY(2, 3)] = KEY_MINUS,
1351 [KEY(3, 0)] = KEY_EQUAL, 1432 [ADP5520_KEY(3, 0)] = KEY_EQUAL,
1352 [KEY(3, 1)] = KEY_BACKSLASH, 1433 [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
1353 [KEY(3, 2)] = KEY_BACKSPACE, 1434 [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
1354 [KEY(3, 3)] = KEY_ENTER, 1435 [ADP5520_KEY(3, 3)] = KEY_ENTER,
1355}; 1436};
1356 1437
1357static struct adp5520_keys_platfrom_data adp5520_keys_data = { 1438static struct adp5520_keys_platform_data adp5520_keys_data = {
1358 .rows_en_mask = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0, 1439 .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
1359 .cols_en_mask = COL_C3 | COL_C2 | COL_C1 | COL_C0, 1440 .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
1360 .keymap = adp5520_keymap, 1441 .keymap = adp5520_keymap,
1361 .keymapsize = ARRAY_SIZE(adp5520_keymap), 1442 .keymapsize = ARRAY_SIZE(adp5520_keymap),
1362 .repeat = 0, 1443 .repeat = 0,
@@ -1366,50 +1447,81 @@ static struct adp5520_keys_platfrom_data adp5520_keys_data = {
1366 * ADP5520/5501 Multifuction Device Init Data 1447 * ADP5520/5501 Multifuction Device Init Data
1367 */ 1448 */
1368 1449
1369static struct adp5520_subdev_info adp5520_subdevs[] = {
1370 {
1371 .name = "adp5520-backlight",
1372 .id = ID_ADP5520,
1373 .platform_data = &adp5520_backlight_data,
1374 },
1375 {
1376 .name = "adp5520-led",
1377 .id = ID_ADP5520,
1378 .platform_data = &adp5520_leds_data,
1379 },
1380 {
1381 .name = "adp5520-gpio",
1382 .id = ID_ADP5520,
1383 .platform_data = &adp5520_gpio_data,
1384 },
1385 {
1386 .name = "adp5520-keys",
1387 .id = ID_ADP5520,
1388 .platform_data = &adp5520_keys_data,
1389 },
1390};
1391
1392static struct adp5520_platform_data adp5520_pdev_data = { 1450static struct adp5520_platform_data adp5520_pdev_data = {
1393 .num_subdevs = ARRAY_SIZE(adp5520_subdevs), 1451 .backlight = &adp5520_backlight_data,
1394 .subdevs = adp5520_subdevs, 1452 .leds = &adp5520_leds_data,
1453 .gpio = &adp5520_gpio_data,
1454 .keys = &adp5520_keys_data,
1395}; 1455};
1396 1456
1397#endif 1457#endif
1398 1458
1399#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE) 1459#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
1400#include <linux/i2c/adp5588.h> 1460#include <linux/i2c/adp5588.h>
1401static struct adp5588_gpio_platfrom_data adp5588_gpio_data = { 1461static struct adp5588_gpio_platform_data adp5588_gpio_data = {
1402 .gpio_start = 50, 1462 .gpio_start = 50,
1403 .pullup_dis_mask = 0, 1463 .pullup_dis_mask = 0,
1404}; 1464};
1405#endif 1465#endif
1406 1466
1467#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
1468#include <linux/i2c/adp8870.h>
1469static struct led_info adp8870_leds[] = {
1470 {
1471 .name = "adp8870-led7",
1472 .default_trigger = "none",
1473 .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
1474 },
1475};
1476
1477
1478static struct adp8870_backlight_platform_data adp8870_pdata = {
1479 .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
1480 ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
1481 .pwm_assign = 0, /* 1 = Enables PWM mode */
1482
1483 .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
1484 .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
1485 .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
1486
1487 .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
1488 .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
1489
1490 .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1491 .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1492 .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1493 .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1494 .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1495 .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1496 .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1497 .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1498 .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
1499 .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
1500
1501 .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
1502 .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
1503 .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
1504 .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
1505 .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
1506 .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
1507 .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
1508 .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
1509
1510 .leds = adp8870_leds,
1511 .num_leds = ARRAY_SIZE(adp8870_leds),
1512 .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
1513 .led_fade_in = ADP8870_FADE_T_600ms,
1514 .led_fade_out = ADP8870_FADE_T_600ms,
1515 .led_on_time = ADP8870_LED_ONT_200ms,
1516};
1517#endif
1518
1407static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 1519static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1408#if defined(CONFIG_INPUT_EVAL_AD7142EB) 1520#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
1409 { 1521 {
1410 I2C_BOARD_INFO("ad7142_captouch", 0x2C), 1522 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
1411 .irq = IRQ_PG5, 1523 .irq = IRQ_PG5,
1412 .platform_data = (void *)&ad7142_platfrom_data, 1524 .platform_data = (void *)&ad7142_i2c_platform_data,
1413 }, 1525 },
1414#endif 1526#endif
1415#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 1527#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
@@ -1462,6 +1574,32 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
1462 I2C_BOARD_INFO("bfin-adv7393", 0x2B), 1574 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
1463 }, 1575 },
1464#endif 1576#endif
1577#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1578 {
1579 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C),
1580 },
1581#endif
1582#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
1583 {
1584 I2C_BOARD_INFO("adp8870", 0x2B),
1585 .platform_data = (void *)&adp8870_pdata,
1586 },
1587#endif
1588#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
1589 {
1590 I2C_BOARD_INFO("adau1371", 0x1A),
1591 },
1592#endif
1593#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1594 {
1595 I2C_BOARD_INFO("adau1761", 0x38),
1596 },
1597#endif
1598#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
1599 {
1600 I2C_BOARD_INFO("ad5258", 0x18),
1601 },
1602#endif
1465}; 1603};
1466 1604
1467#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 1605#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -1602,8 +1740,8 @@ static struct platform_device *stamp_devices[] __initdata = {
1602 &dm9000_device, 1740 &dm9000_device,
1603#endif 1741#endif
1604 1742
1605#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) 1743#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1606 &ax88180_device, 1744 &bfin_can_device,
1607#endif 1745#endif
1608 1746
1609#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1747#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
index 17fab4474669..8b291418ca32 100644
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -9,16 +9,6 @@
9#ifndef __MACH_BF537_H__ 9#ifndef __MACH_BF537_H__
10#define __MACH_BF537_H__ 10#define __MACH_BF537_H__
11 11
12/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
13
14#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
15#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
16#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
17#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
18#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
19#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
20#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
21
22#define OFFSET_(x) ((x) & 0x0000FFFF) 12#define OFFSET_(x) ((x) & 0x0000FFFF)
23 13
24/*some misc defines*/ 14/*some misc defines*/
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index eab006d260c5..a12d4b6a221d 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -40,10 +40,4 @@
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */ 41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 42
43/* PLL_DIV Masks */
44#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
45#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
46#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
47#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
48
49#endif 43#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index a6d20ca57683..066d5c261f47 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -958,67 +958,6 @@
958** modifier UNLESS the lower order bits are saved and ORed back in when 958** modifier UNLESS the lower order bits are saved and ORed back in when
959** the macro is used. 959** the macro is used.
960*************************************************************************************/ 960*************************************************************************************/
961/*
962** ********************* PLL AND RESET MASKS ****************************************/
963/* PLL_CTL Masks */
964#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
965#define PLL_OFF 0x0002 /* PLL Not Powered */
966#define STOPCK 0x0008 /* Core Clock Off */
967#define PDWN 0x0020 /* Enter Deep Sleep Mode */
968#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
969#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
970#define BYPASS 0x0100 /* Bypass the PLL */
971#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
972/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
973#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
974
975/* PLL_DIV Masks */
976#define SSEL 0x000F /* System Select */
977#define CSEL 0x0030 /* Core Select */
978#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
979#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
980#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
981#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
982/* PLL_DIV Macros */
983#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
984
985/* VR_CTL Masks */
986#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
987#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
988#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
989#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
990#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
991
992#define GAIN 0x000C /* Voltage Level Gain */
993#define GAIN_5 0x0000 /* GAIN = 5 */
994#define GAIN_10 0x0004 /* GAIN = 10 */
995#define GAIN_20 0x0008 /* GAIN = 20 */
996#define GAIN_50 0x000C /* GAIN = 50 */
997
998#define VLEV 0x00F0 /* Internal Voltage Level */
999#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1000#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1001#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1002#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1003#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1004#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1005#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1006#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1007#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1008#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1009
1010#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1011#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1012#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1013#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1014#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1015#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1016
1017/* PLL_STAT Masks */
1018#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1019#define FULL_ON 0x0002 /* Processor In Full On Mode */
1020#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1021#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1022 961
1023/* CHIPID Masks */ 962/* CHIPID Masks */
1024#define CHIPID_VERSION 0xF0000000 963#define CHIPID_VERSION 0xF0000000
@@ -1645,34 +1584,6 @@
1645#define BGSTAT 0x0020 /* Bus Grant Status */ 1584#define BGSTAT 0x0020 /* Bus Grant Status */
1646 1585
1647/* ************************** DMA CONTROLLER MASKS ********************************/ 1586/* ************************** DMA CONTROLLER MASKS ********************************/
1648/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1649#define DMAEN 0x0001 /* DMA Channel Enable */
1650#define WNR 0x0002 /* Channel Direction (W/R*) */
1651#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1652#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1653#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1654#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1655#define RESTART 0x0020 /* DMA Buffer Clear */
1656#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1657#define DI_EN 0x0080 /* Data Interrupt Enable */
1658#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1659#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1660#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1661#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1662#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1663#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1664#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1665#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1666#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1667#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1668#define NDSIZE 0x0900 /* Next Descriptor Size */
1669
1670#define DMAFLOW 0x7000 /* Flow Control */
1671#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1672#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1673#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1674#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1675#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1676 1587
1677/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1588/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1678#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ 1589#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
@@ -1690,12 +1601,6 @@
1690#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ 1601#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1691#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ 1602#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1692 1603
1693/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1694#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1695#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1696#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1697#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1698
1699/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ 1604/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1700/* PPI_CONTROL Masks */ 1605/* PPI_CONTROL Masks */
1701#define PORT_EN 0x0001 /* PPI Port Enable */ 1606#define PORT_EN 0x0001 /* PPI Port Enable */
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
index 8cd2719684db..c0be54f2cd2b 100644
--- a/arch/blackfin/mach-bf538/Makefile
+++ b/arch/blackfin/mach-bf538/Makefile
@@ -3,3 +3,4 @@
3# 3#
4 4
5obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
6obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 14af5c2088d4..c296bb1ed503 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -151,6 +151,44 @@ static struct platform_device bfin_sir2_device = {
151#endif 151#endif
152#endif 152#endif
153 153
154#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
155unsigned short bfin_can_peripherals[] = {
156 P_CAN0_RX, P_CAN0_TX, 0
157};
158
159static struct resource bfin_can_resources[] = {
160 {
161 .start = 0xFFC02A00,
162 .end = 0xFFC02FFF,
163 .flags = IORESOURCE_MEM,
164 },
165 {
166 .start = IRQ_CAN_RX,
167 .end = IRQ_CAN_RX,
168 .flags = IORESOURCE_IRQ,
169 },
170 {
171 .start = IRQ_CAN_TX,
172 .end = IRQ_CAN_TX,
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .start = IRQ_CAN_ERROR,
177 .end = IRQ_CAN_ERROR,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device bfin_can_device = {
183 .name = "bfin_can",
184 .num_resources = ARRAY_SIZE(bfin_can_resources),
185 .resource = bfin_can_resources,
186 .dev = {
187 .platform_data = &bfin_can_peripherals, /* Passed to driver */
188 },
189};
190#endif
191
154/* 192/*
155 * USB-LAN EzExtender board 193 * USB-LAN EzExtender board
156 * Driver needs to know address, irq and flag pin. 194 * Driver needs to know address, irq and flag pin.
@@ -610,6 +648,10 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
610#endif 648#endif
611#endif 649#endif
612 650
651#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
652 &bfin_can_device,
653#endif
654
613#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 655#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
614 &smc91x_device, 656 &smc91x_device,
615#endif 657#endif
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
new file mode 100644
index 000000000000..180b1252679f
--- /dev/null
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -0,0 +1,123 @@
1/*
2 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
3 *
4 * Copyright 2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/err.h>
11#include <asm/blackfin.h>
12#include <asm/gpio.h>
13#include <asm/portmux.h>
14
15#define DEFINE_REG(reg, off) \
16static inline u16 read_##reg(void __iomem *port) \
17 { return bfin_read16(port + off); } \
18static inline void write_##reg(void __iomem *port, u16 v) \
19 { bfin_write16(port + off, v); }
20
21DEFINE_REG(PORTIO, 0x00)
22DEFINE_REG(PORTIO_CLEAR, 0x10)
23DEFINE_REG(PORTIO_SET, 0x20)
24DEFINE_REG(PORTIO_DIR, 0x40)
25DEFINE_REG(PORTIO_INEN, 0x50)
26
27static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
28{
29 switch (chip->base) {
30 default: /* not really needed, but keeps gcc happy */
31 case GPIO_PC0: return (void __iomem *)PORTCIO;
32 case GPIO_PD0: return (void __iomem *)PORTDIO;
33 case GPIO_PE0: return (void __iomem *)PORTEIO;
34 }
35}
36
37static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
38{
39 void __iomem *port = gpio_chip_to_mmr(chip);
40 return !!(read_PORTIO(port) & (1u << gpio));
41}
42
43static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
44{
45 void __iomem *port = gpio_chip_to_mmr(chip);
46 if (value)
47 write_PORTIO_SET(port, (1u << gpio));
48 else
49 write_PORTIO_CLEAR(port, (1u << gpio));
50}
51
52static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
53{
54 void __iomem *port = gpio_chip_to_mmr(chip);
55 write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
56 write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
57 return 0;
58}
59
60static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
61{
62 void __iomem *port = gpio_chip_to_mmr(chip);
63 write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
64 bf538_gpio_set_value(port, gpio, value);
65 write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
66 return 0;
67}
68
69static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
70{
71 return bfin_special_gpio_request(chip->base + gpio, chip->label);
72}
73
74static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
75{
76 return bfin_special_gpio_free(chip->base + gpio);
77}
78
79/* We don't set the irq fields as these banks cannot generate interrupts */
80
81static struct gpio_chip bf538_portc_chip = {
82 .label = "GPIO-PC",
83 .direction_input = bf538_gpio_direction_input,
84 .get = bf538_gpio_get_value,
85 .direction_output = bf538_gpio_direction_output,
86 .set = bf538_gpio_set_value,
87 .request = bf538_gpio_request,
88 .free = bf538_gpio_free,
89 .base = GPIO_PC0,
90 .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
91};
92
93static struct gpio_chip bf538_portd_chip = {
94 .label = "GPIO-PD",
95 .direction_input = bf538_gpio_direction_input,
96 .get = bf538_gpio_get_value,
97 .direction_output = bf538_gpio_direction_output,
98 .set = bf538_gpio_set_value,
99 .request = bf538_gpio_request,
100 .free = bf538_gpio_free,
101 .base = GPIO_PD0,
102 .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
103};
104
105static struct gpio_chip bf538_porte_chip = {
106 .label = "GPIO-PE",
107 .direction_input = bf538_gpio_direction_input,
108 .get = bf538_gpio_get_value,
109 .direction_output = bf538_gpio_direction_output,
110 .set = bf538_gpio_set_value,
111 .request = bf538_gpio_request,
112 .free = bf538_gpio_free,
113 .base = GPIO_PE0,
114 .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
115};
116
117static int __init bf538_extgpio_setup(void)
118{
119 return gpiochip_add(&bf538_portc_chip) |
120 gpiochip_add(&bf538_portd_chip) |
121 gpiochip_add(&bf538_porte_chip);
122}
123arch_initcall(bf538_extgpio_setup);
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 278e8942eef2..08b5eabb1ed5 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -37,10 +37,4 @@
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */ 38#define OFFSET_GCTL 0x24 /* Global Control Register */
39 39
40/* PLL_DIV Masks */
41#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
42#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
43#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
44#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
45
46#endif 40#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5f6c34dfd08e..fac563e6f62f 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -468,31 +468,31 @@
468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ 468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
469 469
470/* GPIO Port C Register Names */ 470/* GPIO Port C Register Names */
471#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ 471#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
472#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ 472#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
473#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ 473#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
474#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ 474#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
475#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ 475#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
476#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ 476#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
477#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ 477#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
478 478
479/* GPIO Port D Register Names */ 479/* GPIO Port D Register Names */
480#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ 480#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
481#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ 481#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
482#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ 482#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
483#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ 483#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
484#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ 484#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
485#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ 485#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
486#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ 486#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
487 487
488/* GPIO Port E Register Names */ 488/* GPIO Port E Register Names */
489#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ 489#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
490#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ 490#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
491#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ 491#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
492#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ 492#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
493#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ 493#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
494#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ 494#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
495#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ 495#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
496 496
497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ 497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
498 498
@@ -1422,81 +1422,6 @@
1422/* System MMR Register Bits and Macros */ 1422/* System MMR Register Bits and Macros */
1423/******************************************************************************* */ 1423/******************************************************************************* */
1424 1424
1425/* ********************* PLL AND RESET MASKS ************************ */
1426/* PLL_CTL Masks */
1427#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
1428#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
1429#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1430#define PLL_OFF 0x0002 /* Shut off PLL clocks */
1431
1432#define STOPCK 0x0008 /* Core Clock Off */
1433#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
1434#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
1435#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
1436#define BYPASS 0x0100 /* Bypass the PLL */
1437#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
1438
1439/* PLL_CTL Macros */
1440#ifdef _MISRA_RULES
1441#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1442#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
1443#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
1444#else
1445#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1446#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
1447#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
1448#endif /* _MISRA_RULES */
1449
1450/* PLL_DIV Masks */
1451#define SSEL 0x000F /* System Select */
1452#define CSEL 0x0030 /* Core Select */
1453#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1454#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1455#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1456#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1457
1458#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
1459
1460/* PLL_DIV Macros */
1461#ifdef _MISRA_RULES
1462#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1463#else
1464#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1465#endif /* _MISRA_RULES */
1466
1467/* PLL_STAT Masks */
1468#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1469#define FULL_ON 0x0002 /* Processor In Full On Mode */
1470#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1471#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1472
1473/* VR_CTL Masks */
1474#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1475#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1476#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1477#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1478#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1479
1480#define GAIN 0x000C /* Voltage Level Gain */
1481#define GAIN_5 0x0000 /* GAIN = 5 */
1482#define GAIN_10 0x0004 /* GAIN = 10 */
1483#define GAIN_20 0x0008 /* GAIN = 20 */
1484#define GAIN_50 0x000C /* GAIN = 50 */
1485
1486#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1487#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1488#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1489#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1490#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1491#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1492#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1493#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1494
1495#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1496#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1497#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
1498#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
1499
1500/* SWRST Mask */ 1425/* SWRST Mask */
1501#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1426#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1502#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1427#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
@@ -1609,91 +1534,6 @@
1609#endif /* _MISRA_RULES */ 1534#endif /* _MISRA_RULES */
1610 1535
1611 1536
1612/* ********* WATCHDOG TIMER MASKS ******************** */
1613/* Watchdog Timer WDOG_CTL Register Masks */
1614#ifdef _MISRA_RULES
1615#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
1616#else
1617#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
1618#endif /* _MISRA_RULES */
1619#define WDEV_RESET 0x0000 /* generate reset event on roll over */
1620#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
1621#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
1622#define WDEV_NONE 0x0006 /* no event on roll over */
1623#define WDEN 0x0FF0 /* enable watchdog */
1624#define WDDIS 0x0AD0 /* disable watchdog */
1625#define WDRO 0x8000 /* watchdog rolled over latch */
1626
1627/* deprecated WDOG_CTL Register Masks for legacy code */
1628#define ICTL WDEV
1629#define ENABLE_RESET WDEV_RESET
1630#define WDOG_RESET WDEV_RESET
1631#define ENABLE_NMI WDEV_NMI
1632#define WDOG_NMI WDEV_NMI
1633#define ENABLE_GPI WDEV_GPI
1634#define WDOG_GPI WDEV_GPI
1635#define DISABLE_EVT WDEV_NONE
1636#define WDOG_NONE WDEV_NONE
1637
1638#define TMR_EN WDEN
1639#define WDOG_DISABLE WDDIS
1640#define TRO WDRO
1641
1642#define ICTL_P0 0x01
1643#define ICTL_P1 0x02
1644#define TRO_P 0x0F
1645
1646
1647/* *************** REAL TIME CLOCK MASKS **************************/
1648/* RTC_STAT and RTC_ALARM register */
1649#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
1650#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
1651#define RTHR 0x0001F000 /* Real-Time Clock Hours */
1652#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
1653
1654/* RTC_ICTL register */
1655#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
1656#define AIE 0x0002 /* Alarm Interrupt Enable */
1657#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
1658#define MIE 0x0008 /* Minutes Interrupt Enable */
1659#define HIE 0x0010 /* Hours Interrupt Enable */
1660#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
1661#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1662#define WCIE 0x8000 /* Write Complete Interrupt Enable */
1663
1664/* RTC_ISTAT register */
1665#define SWEF 0x0001 /* Stopwatch Event Flag */
1666#define AEF 0x0002 /* Alarm Event Flag */
1667#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
1668#define MEF 0x0008 /* Minutes Event Flag */
1669#define HEF 0x0010 /* Hours Event Flag */
1670#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
1671#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
1672#define WPS 0x4000 /* Write Pending Status (RO) */
1673#define WCOM 0x8000 /* Write Complete */
1674
1675/* RTC_FAST Mask (RTC_PREN Mask) */
1676#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
1677#define PREN 0x00000001
1678 /* ** Must be set after power-up for proper operation of RTC */
1679
1680/* Deprecated RTC_STAT and RTC_ALARM Masks */
1681#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
1682#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
1683#define RTC_HR RTHR /* Real-Time Clock Hours */
1684#define RTC_DAY RTDAY /* Real-Time Clock Days */
1685
1686/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
1687#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
1688#define ALARM AIE /* Alarm Interrupt Enable */
1689#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
1690#define MINUTE MIE /* Minutes Interrupt Enable */
1691#define HOUR HIE /* Hours Interrupt Enable */
1692#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
1693#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1694#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
1695
1696
1697/* ***************************** UART CONTROLLER MASKS ********************** */ 1537/* ***************************** UART CONTROLLER MASKS ********************** */
1698/* UARTx_LCR Register */ 1538/* UARTx_LCR Register */
1699#ifdef _MISRA_RULES 1539#ifdef _MISRA_RULES
@@ -1917,52 +1757,6 @@
1917 1757
1918 1758
1919/* ********** DMA CONTROLLER MASKS ***********************/ 1759/* ********** DMA CONTROLLER MASKS ***********************/
1920/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1921#define DMAEN 0x0001 /* Channel Enable */
1922#define WNR 0x0002 /* Channel Direction (W/R*) */
1923#define WDSIZE_8 0x0000 /* Word Size 8 bits */
1924#define WDSIZE_16 0x0004 /* Word Size 16 bits */
1925#define WDSIZE_32 0x0008 /* Word Size 32 bits */
1926#define DMA2D 0x0010 /* 2D/1D* Mode */
1927#define RESTART 0x0020 /* Restart */
1928#define DI_SEL 0x0040 /* Data Interrupt Select */
1929#define DI_EN 0x0080 /* Data Interrupt Enable */
1930#define NDSIZE 0x0900 /* Next Descriptor Size */
1931#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1932#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1933#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1934#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1935#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1936#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1937#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1938#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1939#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1940#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1941
1942#define DMAFLOW 0x7000 /* Flow Control */
1943#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1944#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1945#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1946#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1947#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1948
1949#define DMAEN_P 0x0 /* Channel Enable */
1950#define WNR_P 0x1 /* Channel Direction (W/R*) */
1951#define DMA2D_P 0x4 /* 2D/1D* Mode */
1952#define RESTART_P 0x5 /* Restart */
1953#define DI_SEL_P 0x6 /* Data Interrupt Select */
1954#define DI_EN_P 0x7 /* Data Interrupt Enable */
1955
1956/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1957#define DMA_DONE 0x0001 /* DMA Done Indicator */
1958#define DMA_ERR 0x0002 /* DMA Error Indicator */
1959#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
1960#define DMA_RUN 0x0008 /* DMA Running Indicator */
1961
1962#define DMA_DONE_P 0x0 /* DMA Done Indicator */
1963#define DMA_ERR_P 0x1 /* DMA Error Indicator */
1964#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
1965#define DMA_RUN_P 0x3 /* DMA Running Indicator */
1966 1760
1967/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1761/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1968 1762
@@ -2625,1019 +2419,6 @@
2625#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 2419#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2626 2420
2627 2421
2628/********************************* MXVR MASKS ****************************************/
2629
2630/* MXVR_CONFIG Masks */
2631
2632#define MXVREN 0x00000001lu
2633#define MMSM 0x00000002lu
2634#define ACTIVE 0x00000004lu
2635#define SDELAY 0x00000008lu
2636#define NCMRXEN 0x00000010lu
2637#define RWRRXEN 0x00000020lu
2638#define MTXEN 0x00000040lu
2639#define MTXON 0x00000080lu /*legacy*/
2640#define MTXONB 0x00000080lu
2641#define EPARITY 0x00000100lu
2642#define MSB 0x00001E00lu
2643#define APRXEN 0x00002000lu
2644#define WAKEUP 0x00004000lu
2645#define LMECH 0x00008000lu
2646
2647#ifdef _MISRA_RULES
2648#define SET_MSB(x) (((x)&0xFu) << 0x9)
2649#else
2650#define SET_MSB(x) (((x)&0xF) << 0x9)
2651#endif /* _MISRA_RULES */
2652
2653
2654/* MXVR_PLL_CTL_0 Masks */
2655
2656#define MXTALCEN 0x00000001lu
2657#define MXTALFEN 0x00000002lu
2658#define MPLLMS 0x00000008lu
2659#define MXTALMUL 0x00000030lu
2660#define MPLLEN 0x00000040lu
2661#define MPLLEN0 0x00000040lu /* legacy */
2662#define MPLLEN1 0x00000080lu /* legacy */
2663#define MMCLKEN 0x00000100lu
2664#define MMCLKMUL 0x00001E00lu
2665#define MPLLRSTB 0x00002000lu
2666#define MPLLRSTB0 0x00002000lu /* legacy */
2667#define MPLLRSTB1 0x00004000lu /* legacy */
2668#define MBCLKEN 0x00010000lu
2669#define MBCLKDIV 0x001E0000lu
2670#define MPLLCDR 0x00200000lu
2671#define MPLLCDR0 0x00200000lu /* legacy */
2672#define MPLLCDR1 0x00400000lu /* legacy */
2673#define INVRX 0x00800000lu
2674#define MFSEN 0x01000000lu
2675#define MFSDIV 0x1E000000lu
2676#define MFSSEL 0x60000000lu
2677#define MFSSYNC 0x80000000lu
2678
2679#define MXTALMUL_256FS 0x00000000lu /* legacy */
2680#define MXTALMUL_384FS 0x00000010lu /* legacy */
2681#define MXTALMUL_512FS 0x00000020lu /* legacy */
2682#define MXTALMUL_1024FS 0x00000030lu
2683
2684#define MMCLKMUL_1024FS 0x00000000lu
2685#define MMCLKMUL_512FS 0x00000200lu
2686#define MMCLKMUL_256FS 0x00000400lu
2687#define MMCLKMUL_128FS 0x00000600lu
2688#define MMCLKMUL_64FS 0x00000800lu
2689#define MMCLKMUL_32FS 0x00000A00lu
2690#define MMCLKMUL_16FS 0x00000C00lu
2691#define MMCLKMUL_8FS 0x00000E00lu
2692#define MMCLKMUL_4FS 0x00001000lu
2693#define MMCLKMUL_2FS 0x00001200lu
2694#define MMCLKMUL_1FS 0x00001400lu
2695#define MMCLKMUL_1536FS 0x00001A00lu
2696#define MMCLKMUL_768FS 0x00001C00lu
2697#define MMCLKMUL_384FS 0x00001E00lu
2698
2699#define MBCLKDIV_DIV2 0x00020000lu
2700#define MBCLKDIV_DIV4 0x00040000lu
2701#define MBCLKDIV_DIV8 0x00060000lu
2702#define MBCLKDIV_DIV16 0x00080000lu
2703#define MBCLKDIV_DIV32 0x000A0000lu
2704#define MBCLKDIV_DIV64 0x000C0000lu
2705#define MBCLKDIV_DIV128 0x000E0000lu
2706#define MBCLKDIV_DIV256 0x00100000lu
2707#define MBCLKDIV_DIV512 0x00120000lu
2708#define MBCLKDIV_DIV1024 0x00140000lu
2709
2710#define MFSDIV_DIV2 0x02000000lu
2711#define MFSDIV_DIV4 0x04000000lu
2712#define MFSDIV_DIV8 0x06000000lu
2713#define MFSDIV_DIV16 0x08000000lu
2714#define MFSDIV_DIV32 0x0A000000lu
2715#define MFSDIV_DIV64 0x0C000000lu
2716#define MFSDIV_DIV128 0x0E000000lu
2717#define MFSDIV_DIV256 0x10000000lu
2718#define MFSDIV_DIV512 0x12000000lu
2719#define MFSDIV_DIV1024 0x14000000lu
2720
2721#define MFSSEL_CLOCK 0x00000000lu
2722#define MFSSEL_PULSE_HI 0x20000000lu
2723#define MFSSEL_PULSE_LO 0x40000000lu
2724
2725
2726/* MXVR_PLL_CTL_1 Masks */
2727
2728#define MSTO 0x00000001lu
2729#define MSTO0 0x00000001lu /* legacy */
2730#define MHOGGD 0x00000004lu
2731#define MHOGGD0 0x00000004lu /* legacy */
2732#define MHOGGD1 0x00000008lu /* legacy */
2733#define MSHAPEREN 0x00000010lu
2734#define MSHAPEREN0 0x00000010lu /* legacy */
2735#define MSHAPEREN1 0x00000020lu /* legacy */
2736#define MPLLCNTEN 0x00008000lu
2737#define MPLLCNT 0xFFFF0000lu
2738
2739#ifdef _MISRA_RULES
2740#define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10)
2741#else
2742#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
2743#endif /* _MISRA_RULES */
2744
2745
2746/* MXVR_PLL_CTL_2 Masks */
2747
2748#define MSHAPERSEL 0x00000007lu
2749#define MCPSEL 0x000000E0lu
2750
2751/* MXVR_INT_STAT_0 Masks */
2752
2753#define NI2A 0x00000001lu
2754#define NA2I 0x00000002lu
2755#define SBU2L 0x00000004lu
2756#define SBL2U 0x00000008lu
2757#define PRU 0x00000010lu
2758#define MPRU 0x00000020lu
2759#define DRU 0x00000040lu
2760#define MDRU 0x00000080lu
2761#define SBU 0x00000100lu
2762#define ATU 0x00000200lu
2763#define FCZ0 0x00000400lu
2764#define FCZ1 0x00000800lu
2765#define PERR 0x00001000lu
2766#define MH2L 0x00002000lu
2767#define ML2H 0x00004000lu
2768#define WUP 0x00008000lu
2769#define FU2L 0x00010000lu
2770#define FL2U 0x00020000lu
2771#define BU2L 0x00040000lu
2772#define BL2U 0x00080000lu
2773#define PCZ 0x00400000lu
2774#define FERR 0x00800000lu
2775#define CMR 0x01000000lu
2776#define CMROF 0x02000000lu
2777#define CMTS 0x04000000lu
2778#define CMTC 0x08000000lu
2779#define RWRC 0x10000000lu
2780#define BCZ 0x20000000lu
2781#define BMERR 0x40000000lu
2782#define DERR 0x80000000lu
2783
2784
2785/* MXVR_INT_EN_0 Masks */
2786
2787#define NI2AEN NI2A
2788#define NA2IEN NA2I
2789#define SBU2LEN SBU2L
2790#define SBL2UEN SBL2U
2791#define PRUEN PRU
2792#define MPRUEN MPRU
2793#define DRUEN DRU
2794#define MDRUEN MDRU
2795#define SBUEN SBU
2796#define ATUEN ATU
2797#define FCZ0EN FCZ0
2798#define FCZ1EN FCZ1
2799#define PERREN PERR
2800#define MH2LEN MH2L
2801#define ML2HEN ML2H
2802#define WUPEN WUP
2803#define FU2LEN FU2L
2804#define FL2UEN FL2U
2805#define BU2LEN BU2L
2806#define BL2UEN BL2U
2807#define PCZEN PCZ
2808#define FERREN FERR
2809#define CMREN CMR
2810#define CMROFEN CMROF
2811#define CMTSEN CMTS
2812#define CMTCEN CMTC
2813#define RWRCEN RWRC
2814#define BCZEN BCZ
2815#define BMERREN BMERR
2816#define DERREN DERR
2817
2818
2819/* MXVR_INT_STAT_1 Masks */
2820
2821#define APR 0x00000004lu
2822#define APROF 0x00000008lu
2823#define APTS 0x00000040lu
2824#define APTC 0x00000080lu
2825#define APRCE 0x00000400lu
2826#define APRPE 0x00000800lu
2827
2828#define HDONE0 0x00000001lu
2829#define DONE0 0x00000002lu
2830#define HDONE1 0x00000010lu
2831#define DONE1 0x00000020lu
2832#define HDONE2 0x00000100lu
2833#define DONE2 0x00000200lu
2834#define HDONE3 0x00001000lu
2835#define DONE3 0x00002000lu
2836#define HDONE4 0x00010000lu
2837#define DONE4 0x00020000lu
2838#define HDONE5 0x00100000lu
2839#define DONE5 0x00200000lu
2840#define HDONE6 0x01000000lu
2841#define DONE6 0x02000000lu
2842#define HDONE7 0x10000000lu
2843#define DONE7 0x20000000lu
2844
2845#define DONEX(x) (0x00000002 << (4 * (x)))
2846#define HDONEX(x) (0x00000001 << (4 * (x)))
2847
2848
2849/* MXVR_INT_EN_1 Masks */
2850
2851#define APREN APR
2852#define APROFEN APROF
2853#define APTSEN APTS
2854#define APTCEN APTC
2855#define APRCEEN APRCE
2856#define APRPEEN APRPE
2857
2858#define HDONEEN0 HDONE0
2859#define DONEEN0 DONE0
2860#define HDONEEN1 HDONE1
2861#define DONEEN1 DONE1
2862#define HDONEEN2 HDONE2
2863#define DONEEN2 DONE2
2864#define HDONEEN3 HDONE3
2865#define DONEEN3 DONE3
2866#define HDONEEN4 HDONE4
2867#define DONEEN4 DONE4
2868#define HDONEEN5 HDONE5
2869#define DONEEN5 DONE5
2870#define HDONEEN6 HDONE6
2871#define DONEEN6 DONE6
2872#define HDONEEN7 HDONE7
2873#define DONEEN7 DONE7
2874
2875#define DONEENX(x) (0x00000002 << (4 * (x)))
2876#define HDONEENX(x) (0x00000001 << (4 * (x)))
2877
2878
2879/* MXVR_STATE_0 Masks */
2880
2881#define NACT 0x00000001lu
2882#define SBLOCK 0x00000002lu
2883#define PFDLOCK 0x00000004lu
2884#define PFDLOCK0 0x00000004lu /* legacy */
2885#define PDD 0x00000008lu
2886#define PDD0 0x00000008lu /* legacy */
2887#define PVCO 0x00000010lu
2888#define PVCO0 0x00000010lu /* legacy */
2889#define PFDLOCK1 0x00000020lu /* legacy */
2890#define PDD1 0x00000040lu /* legacy */
2891#define PVCO1 0x00000080lu /* legacy */
2892#define APBSY 0x00000100lu
2893#define APARB 0x00000200lu
2894#define APTX 0x00000400lu
2895#define APRX 0x00000800lu
2896#define CMBSY 0x00001000lu
2897#define CMARB 0x00002000lu
2898#define CMTX 0x00004000lu
2899#define CMRX 0x00008000lu
2900#define MRXONB 0x00010000lu
2901#define RGSIP 0x00020000lu
2902#define DALIP 0x00040000lu
2903#define ALIP 0x00080000lu
2904#define RRDIP 0x00100000lu
2905#define RWRIP 0x00200000lu
2906#define FLOCK 0x00400000lu
2907#define BLOCK 0x00800000lu
2908#define RSB 0x0F000000lu
2909#define DERRNUM 0xF0000000lu
2910
2911
2912/* MXVR_STATE_1 Masks */
2913
2914#define STXNUMB 0x0000000Flu
2915#define SRXNUMB 0x000000F0lu
2916#define APCONT 0x00000100lu
2917#define DMAACTIVEX 0x00FF0000lu
2918#define DMAACTIVE0 0x00010000lu
2919#define DMAACTIVE1 0x00020000lu
2920#define DMAACTIVE2 0x00040000lu
2921#define DMAACTIVE3 0x00080000lu
2922#define DMAACTIVE4 0x00100000lu
2923#define DMAACTIVE5 0x00200000lu
2924#define DMAACTIVE6 0x00400000lu
2925#define DMAACTIVE7 0x00800000lu
2926#define DMAPMENX 0xFF000000lu
2927#define DMAPMEN0 0x01000000lu
2928#define DMAPMEN1 0x02000000lu
2929#define DMAPMEN2 0x04000000lu
2930#define DMAPMEN3 0x08000000lu
2931#define DMAPMEN4 0x10000000lu
2932#define DMAPMEN5 0x20000000lu
2933#define DMAPMEN6 0x40000000lu
2934#define DMAPMEN7 0x80000000lu
2935
2936
2937/* MXVR_POSITION Masks */
2938
2939#define PVALID 0x8000
2940#define POSITION 0x003F
2941
2942
2943/* MXVR_MAX_POSITION Masks */
2944
2945#define MPVALID 0x8000
2946#define MPOSITION 0x003F
2947
2948
2949/* MXVR_DELAY Masks */
2950
2951#define DVALID 0x8000
2952#define DELAY 0x003F
2953
2954
2955/* MXVR_MAX_DELAY Masks */
2956
2957#define MDVALID 0x8000
2958#define MDELAY 0x003F
2959
2960
2961/* MXVR_LADDR Masks */
2962
2963#define LVALID 0x80000000lu
2964#define LADDR 0x0000FFFFlu
2965
2966
2967/* MXVR_GADDR Masks */
2968
2969#define GVALID 0x8000
2970#define GADDRL 0x00FF
2971
2972
2973/* MXVR_AADDR Masks */
2974
2975#define AVALID 0x80000000lu
2976#define AADDR 0x0000FFFFlu
2977
2978
2979/* MXVR_ALLOC_0 Masks */
2980
2981#define CIU0 0x00000080lu
2982#define CIU1 0x00008000lu
2983#define CIU2 0x00800000lu
2984#define CIU3 0x80000000lu
2985
2986#define CL0 0x0000007Flu
2987#define CL1 0x00007F00lu
2988#define CL2 0x007F0000lu
2989#define CL3 0x7F000000lu
2990
2991
2992/* MXVR_ALLOC_1 Masks */
2993
2994#define CIU4 0x00000080lu
2995#define CIU5 0x00008000lu
2996#define CIU6 0x00800000lu
2997#define CIU7 0x80000000lu
2998
2999#define CL4 0x0000007Flu
3000#define CL5 0x00007F00lu
3001#define CL6 0x007F0000lu
3002#define CL7 0x7F000000lu
3003
3004
3005/* MXVR_ALLOC_2 Masks */
3006
3007#define CIU8 0x00000080lu
3008#define CIU9 0x00008000lu
3009#define CIU10 0x00800000lu
3010#define CIU11 0x80000000lu
3011
3012#define CL8 0x0000007Flu
3013#define CL9 0x00007F00lu
3014#define CL10 0x007F0000lu
3015#define CL11 0x7F000000lu
3016
3017
3018/* MXVR_ALLOC_3 Masks */
3019
3020#define CIU12 0x00000080lu
3021#define CIU13 0x00008000lu
3022#define CIU14 0x00800000lu
3023#define CIU15 0x80000000lu
3024
3025#define CL12 0x0000007Flu
3026#define CL13 0x00007F00lu
3027#define CL14 0x007F0000lu
3028#define CL15 0x7F000000lu
3029
3030
3031/* MXVR_ALLOC_4 Masks */
3032
3033#define CIU16 0x00000080lu
3034#define CIU17 0x00008000lu
3035#define CIU18 0x00800000lu
3036#define CIU19 0x80000000lu
3037
3038#define CL16 0x0000007Flu
3039#define CL17 0x00007F00lu
3040#define CL18 0x007F0000lu
3041#define CL19 0x7F000000lu
3042
3043
3044/* MXVR_ALLOC_5 Masks */
3045
3046#define CIU20 0x00000080lu
3047#define CIU21 0x00008000lu
3048#define CIU22 0x00800000lu
3049#define CIU23 0x80000000lu
3050
3051#define CL20 0x0000007Flu
3052#define CL21 0x00007F00lu
3053#define CL22 0x007F0000lu
3054#define CL23 0x7F000000lu
3055
3056
3057/* MXVR_ALLOC_6 Masks */
3058
3059#define CIU24 0x00000080lu
3060#define CIU25 0x00008000lu
3061#define CIU26 0x00800000lu
3062#define CIU27 0x80000000lu
3063
3064#define CL24 0x0000007Flu
3065#define CL25 0x00007F00lu
3066#define CL26 0x007F0000lu
3067#define CL27 0x7F000000lu
3068
3069
3070/* MXVR_ALLOC_7 Masks */
3071
3072#define CIU28 0x00000080lu
3073#define CIU29 0x00008000lu
3074#define CIU30 0x00800000lu
3075#define CIU31 0x80000000lu
3076
3077#define CL28 0x0000007Flu
3078#define CL29 0x00007F00lu
3079#define CL30 0x007F0000lu
3080#define CL31 0x7F000000lu
3081
3082
3083/* MXVR_ALLOC_8 Masks */
3084
3085#define CIU32 0x00000080lu
3086#define CIU33 0x00008000lu
3087#define CIU34 0x00800000lu
3088#define CIU35 0x80000000lu
3089
3090#define CL32 0x0000007Flu
3091#define CL33 0x00007F00lu
3092#define CL34 0x007F0000lu
3093#define CL35 0x7F000000lu
3094
3095
3096/* MXVR_ALLOC_9 Masks */
3097
3098#define CIU36 0x00000080lu
3099#define CIU37 0x00008000lu
3100#define CIU38 0x00800000lu
3101#define CIU39 0x80000000lu
3102
3103#define CL36 0x0000007Flu
3104#define CL37 0x00007F00lu
3105#define CL38 0x007F0000lu
3106#define CL39 0x7F000000lu
3107
3108
3109/* MXVR_ALLOC_10 Masks */
3110
3111#define CIU40 0x00000080lu
3112#define CIU41 0x00008000lu
3113#define CIU42 0x00800000lu
3114#define CIU43 0x80000000lu
3115
3116#define CL40 0x0000007Flu
3117#define CL41 0x00007F00lu
3118#define CL42 0x007F0000lu
3119#define CL43 0x7F000000lu
3120
3121
3122/* MXVR_ALLOC_11 Masks */
3123
3124#define CIU44 0x00000080lu
3125#define CIU45 0x00008000lu
3126#define CIU46 0x00800000lu
3127#define CIU47 0x80000000lu
3128
3129#define CL44 0x0000007Flu
3130#define CL45 0x00007F00lu
3131#define CL46 0x007F0000lu
3132#define CL47 0x7F000000lu
3133
3134
3135/* MXVR_ALLOC_12 Masks */
3136
3137#define CIU48 0x00000080lu
3138#define CIU49 0x00008000lu
3139#define CIU50 0x00800000lu
3140#define CIU51 0x80000000lu
3141
3142#define CL48 0x0000007Flu
3143#define CL49 0x00007F00lu
3144#define CL50 0x007F0000lu
3145#define CL51 0x7F000000lu
3146
3147
3148/* MXVR_ALLOC_13 Masks */
3149
3150#define CIU52 0x00000080lu
3151#define CIU53 0x00008000lu
3152#define CIU54 0x00800000lu
3153#define CIU55 0x80000000lu
3154
3155#define CL52 0x0000007Flu
3156#define CL53 0x00007F00lu
3157#define CL54 0x007F0000lu
3158#define CL55 0x7F000000lu
3159
3160
3161/* MXVR_ALLOC_14 Masks */
3162
3163#define CIU56 0x00000080lu
3164#define CIU57 0x00008000lu
3165#define CIU58 0x00800000lu
3166#define CIU59 0x80000000lu
3167
3168#define CL56 0x0000007Flu
3169#define CL57 0x00007F00lu
3170#define CL58 0x007F0000lu
3171#define CL59 0x7F000000lu
3172
3173
3174/* MXVR_SYNC_LCHAN_0 Masks */
3175
3176#define LCHANPC0 0x0000000Flu
3177#define LCHANPC1 0x000000F0lu
3178#define LCHANPC2 0x00000F00lu
3179#define LCHANPC3 0x0000F000lu
3180#define LCHANPC4 0x000F0000lu
3181#define LCHANPC5 0x00F00000lu
3182#define LCHANPC6 0x0F000000lu
3183#define LCHANPC7 0xF0000000lu
3184
3185
3186/* MXVR_SYNC_LCHAN_1 Masks */
3187
3188#define LCHANPC8 0x0000000Flu
3189#define LCHANPC9 0x000000F0lu
3190#define LCHANPC10 0x00000F00lu
3191#define LCHANPC11 0x0000F000lu
3192#define LCHANPC12 0x000F0000lu
3193#define LCHANPC13 0x00F00000lu
3194#define LCHANPC14 0x0F000000lu
3195#define LCHANPC15 0xF0000000lu
3196
3197
3198/* MXVR_SYNC_LCHAN_2 Masks */
3199
3200#define LCHANPC16 0x0000000Flu
3201#define LCHANPC17 0x000000F0lu
3202#define LCHANPC18 0x00000F00lu
3203#define LCHANPC19 0x0000F000lu
3204#define LCHANPC20 0x000F0000lu
3205#define LCHANPC21 0x00F00000lu
3206#define LCHANPC22 0x0F000000lu
3207#define LCHANPC23 0xF0000000lu
3208
3209
3210/* MXVR_SYNC_LCHAN_3 Masks */
3211
3212#define LCHANPC24 0x0000000Flu
3213#define LCHANPC25 0x000000F0lu
3214#define LCHANPC26 0x00000F00lu
3215#define LCHANPC27 0x0000F000lu
3216#define LCHANPC28 0x000F0000lu
3217#define LCHANPC29 0x00F00000lu
3218#define LCHANPC30 0x0F000000lu
3219#define LCHANPC31 0xF0000000lu
3220
3221
3222/* MXVR_SYNC_LCHAN_4 Masks */
3223
3224#define LCHANPC32 0x0000000Flu
3225#define LCHANPC33 0x000000F0lu
3226#define LCHANPC34 0x00000F00lu
3227#define LCHANPC35 0x0000F000lu
3228#define LCHANPC36 0x000F0000lu
3229#define LCHANPC37 0x00F00000lu
3230#define LCHANPC38 0x0F000000lu
3231#define LCHANPC39 0xF0000000lu
3232
3233
3234/* MXVR_SYNC_LCHAN_5 Masks */
3235
3236#define LCHANPC40 0x0000000Flu
3237#define LCHANPC41 0x000000F0lu
3238#define LCHANPC42 0x00000F00lu
3239#define LCHANPC43 0x0000F000lu
3240#define LCHANPC44 0x000F0000lu
3241#define LCHANPC45 0x00F00000lu
3242#define LCHANPC46 0x0F000000lu
3243#define LCHANPC47 0xF0000000lu
3244
3245
3246/* MXVR_SYNC_LCHAN_6 Masks */
3247
3248#define LCHANPC48 0x0000000Flu
3249#define LCHANPC49 0x000000F0lu
3250#define LCHANPC50 0x00000F00lu
3251#define LCHANPC51 0x0000F000lu
3252#define LCHANPC52 0x000F0000lu
3253#define LCHANPC53 0x00F00000lu
3254#define LCHANPC54 0x0F000000lu
3255#define LCHANPC55 0xF0000000lu
3256
3257
3258/* MXVR_SYNC_LCHAN_7 Masks */
3259
3260#define LCHANPC56 0x0000000Flu
3261#define LCHANPC57 0x000000F0lu
3262#define LCHANPC58 0x00000F00lu
3263#define LCHANPC59 0x0000F000lu
3264
3265
3266/* MXVR_DMAx_CONFIG Masks */
3267
3268#define MDMAEN 0x00000001lu
3269#define DD 0x00000002lu
3270#define LCHAN 0x000003C0lu
3271#define BITSWAPEN 0x00000400lu
3272#define BYSWAPEN 0x00000800lu
3273#define MFLOW 0x00007000lu
3274#define FIXEDPM 0x00080000lu
3275#define STARTPAT 0x00300000lu
3276#define STOPPAT 0x00C00000lu
3277#define COUNTPOS 0x1C000000lu
3278
3279#define DD_TX 0x00000000lu
3280#define DD_RX 0x00000002lu
3281
3282#define LCHAN_0 0x00000000lu
3283#define LCHAN_1 0x00000040lu
3284#define LCHAN_2 0x00000080lu
3285#define LCHAN_3 0x000000C0lu
3286#define LCHAN_4 0x00000100lu
3287#define LCHAN_5 0x00000140lu
3288#define LCHAN_6 0x00000180lu
3289#define LCHAN_7 0x000001C0lu
3290
3291#define MFLOW_STOP 0x00000000lu
3292#define MFLOW_AUTO 0x00001000lu
3293#define MFLOW_PVC 0x00002000lu
3294#define MFLOW_PSS 0x00003000lu
3295#define MFLOW_PFC 0x00004000lu
3296
3297#define STARTPAT_0 0x00000000lu
3298#define STARTPAT_1 0x00100000lu
3299
3300#define STOPPAT_0 0x00000000lu
3301#define STOPPAT_1 0x00400000lu
3302
3303#define COUNTPOS_0 0x00000000lu
3304#define COUNTPOS_1 0x04000000lu
3305#define COUNTPOS_2 0x08000000lu
3306#define COUNTPOS_3 0x0C000000lu
3307#define COUNTPOS_4 0x10000000lu
3308#define COUNTPOS_5 0x14000000lu
3309#define COUNTPOS_6 0x18000000lu
3310#define COUNTPOS_7 0x1C000000lu
3311
3312
3313/* MXVR_AP_CTL Masks */
3314
3315#define STARTAP 0x00000001lu
3316#define CANCELAP 0x00000002lu
3317#define RESETAP 0x00000004lu
3318#define APRBE0 0x00004000lu
3319#define APRBE1 0x00008000lu
3320#define APRBEX 0x0000C000lu
3321
3322
3323/* MXVR_CM_CTL Masks */
3324
3325#define STARTCM 0x00000001lu
3326#define CANCELCM 0x00000002lu
3327#define CMRBEX 0xFFFF0000lu
3328#define CMRBE0 0x00010000lu
3329#define CMRBE1 0x00020000lu
3330#define CMRBE2 0x00040000lu
3331#define CMRBE3 0x00080000lu
3332#define CMRBE4 0x00100000lu
3333#define CMRBE5 0x00200000lu
3334#define CMRBE6 0x00400000lu
3335#define CMRBE7 0x00800000lu
3336#define CMRBE8 0x01000000lu
3337#define CMRBE9 0x02000000lu
3338#define CMRBE10 0x04000000lu
3339#define CMRBE11 0x08000000lu
3340#define CMRBE12 0x10000000lu
3341#define CMRBE13 0x20000000lu
3342#define CMRBE14 0x40000000lu
3343#define CMRBE15 0x80000000lu
3344
3345
3346/* MXVR_PAT_DATA_x Masks */
3347
3348#define MATCH_DATA_0 0x000000FFlu
3349#define MATCH_DATA_1 0x0000FF00lu
3350#define MATCH_DATA_2 0x00FF0000lu
3351#define MATCH_DATA_3 0xFF000000lu
3352
3353
3354
3355/* MXVR_PAT_EN_x Masks */
3356
3357#define MATCH_EN_0_0 0x00000001lu
3358#define MATCH_EN_0_1 0x00000002lu
3359#define MATCH_EN_0_2 0x00000004lu
3360#define MATCH_EN_0_3 0x00000008lu
3361#define MATCH_EN_0_4 0x00000010lu
3362#define MATCH_EN_0_5 0x00000020lu
3363#define MATCH_EN_0_6 0x00000040lu
3364#define MATCH_EN_0_7 0x00000080lu
3365
3366#define MATCH_EN_1_0 0x00000100lu
3367#define MATCH_EN_1_1 0x00000200lu
3368#define MATCH_EN_1_2 0x00000400lu
3369#define MATCH_EN_1_3 0x00000800lu
3370#define MATCH_EN_1_4 0x00001000lu
3371#define MATCH_EN_1_5 0x00002000lu
3372#define MATCH_EN_1_6 0x00004000lu
3373#define MATCH_EN_1_7 0x00008000lu
3374
3375#define MATCH_EN_2_0 0x00010000lu
3376#define MATCH_EN_2_1 0x00020000lu
3377#define MATCH_EN_2_2 0x00040000lu
3378#define MATCH_EN_2_3 0x00080000lu
3379#define MATCH_EN_2_4 0x00100000lu
3380#define MATCH_EN_2_5 0x00200000lu
3381#define MATCH_EN_2_6 0x00400000lu
3382#define MATCH_EN_2_7 0x00800000lu
3383
3384#define MATCH_EN_3_0 0x01000000lu
3385#define MATCH_EN_3_1 0x02000000lu
3386#define MATCH_EN_3_2 0x04000000lu
3387#define MATCH_EN_3_3 0x08000000lu
3388#define MATCH_EN_3_4 0x10000000lu
3389#define MATCH_EN_3_5 0x20000000lu
3390#define MATCH_EN_3_6 0x40000000lu
3391#define MATCH_EN_3_7 0x80000000lu
3392
3393
3394/* MXVR_ROUTING_0 Masks */
3395
3396#define MUTE_CH0 0x00000080lu
3397#define MUTE_CH1 0x00008000lu
3398#define MUTE_CH2 0x00800000lu
3399#define MUTE_CH3 0x80000000lu
3400
3401#define TX_CH0 0x0000007Flu
3402#define TX_CH1 0x00007F00lu
3403#define TX_CH2 0x007F0000lu
3404#define TX_CH3 0x7F000000lu
3405
3406
3407/* MXVR_ROUTING_1 Masks */
3408
3409#define MUTE_CH4 0x00000080lu
3410#define MUTE_CH5 0x00008000lu
3411#define MUTE_CH6 0x00800000lu
3412#define MUTE_CH7 0x80000000lu
3413
3414#define TX_CH4 0x0000007Flu
3415#define TX_CH5 0x00007F00lu
3416#define TX_CH6 0x007F0000lu
3417#define TX_CH7 0x7F000000lu
3418
3419
3420/* MXVR_ROUTING_2 Masks */
3421
3422#define MUTE_CH8 0x00000080lu
3423#define MUTE_CH9 0x00008000lu
3424#define MUTE_CH10 0x00800000lu
3425#define MUTE_CH11 0x80000000lu
3426
3427#define TX_CH8 0x0000007Flu
3428#define TX_CH9 0x00007F00lu
3429#define TX_CH10 0x007F0000lu
3430#define TX_CH11 0x7F000000lu
3431
3432/* MXVR_ROUTING_3 Masks */
3433
3434#define MUTE_CH12 0x00000080lu
3435#define MUTE_CH13 0x00008000lu
3436#define MUTE_CH14 0x00800000lu
3437#define MUTE_CH15 0x80000000lu
3438
3439#define TX_CH12 0x0000007Flu
3440#define TX_CH13 0x00007F00lu
3441#define TX_CH14 0x007F0000lu
3442#define TX_CH15 0x7F000000lu
3443
3444
3445/* MXVR_ROUTING_4 Masks */
3446
3447#define MUTE_CH16 0x00000080lu
3448#define MUTE_CH17 0x00008000lu
3449#define MUTE_CH18 0x00800000lu
3450#define MUTE_CH19 0x80000000lu
3451
3452#define TX_CH16 0x0000007Flu
3453#define TX_CH17 0x00007F00lu
3454#define TX_CH18 0x007F0000lu
3455#define TX_CH19 0x7F000000lu
3456
3457
3458/* MXVR_ROUTING_5 Masks */
3459
3460#define MUTE_CH20 0x00000080lu
3461#define MUTE_CH21 0x00008000lu
3462#define MUTE_CH22 0x00800000lu
3463#define MUTE_CH23 0x80000000lu
3464
3465#define TX_CH20 0x0000007Flu
3466#define TX_CH21 0x00007F00lu
3467#define TX_CH22 0x007F0000lu
3468#define TX_CH23 0x7F000000lu
3469
3470
3471/* MXVR_ROUTING_6 Masks */
3472
3473#define MUTE_CH24 0x00000080lu
3474#define MUTE_CH25 0x00008000lu
3475#define MUTE_CH26 0x00800000lu
3476#define MUTE_CH27 0x80000000lu
3477
3478#define TX_CH24 0x0000007Flu
3479#define TX_CH25 0x00007F00lu
3480#define TX_CH26 0x007F0000lu
3481#define TX_CH27 0x7F000000lu
3482
3483
3484/* MXVR_ROUTING_7 Masks */
3485
3486#define MUTE_CH28 0x00000080lu
3487#define MUTE_CH29 0x00008000lu
3488#define MUTE_CH30 0x00800000lu
3489#define MUTE_CH31 0x80000000lu
3490
3491#define TX_CH28 0x0000007Flu
3492#define TX_CH29 0x00007F00lu
3493#define TX_CH30 0x007F0000lu
3494#define TX_CH31 0x7F000000lu
3495
3496
3497/* MXVR_ROUTING_8 Masks */
3498
3499#define MUTE_CH32 0x00000080lu
3500#define MUTE_CH33 0x00008000lu
3501#define MUTE_CH34 0x00800000lu
3502#define MUTE_CH35 0x80000000lu
3503
3504#define TX_CH32 0x0000007Flu
3505#define TX_CH33 0x00007F00lu
3506#define TX_CH34 0x007F0000lu
3507#define TX_CH35 0x7F000000lu
3508
3509
3510/* MXVR_ROUTING_9 Masks */
3511
3512#define MUTE_CH36 0x00000080lu
3513#define MUTE_CH37 0x00008000lu
3514#define MUTE_CH38 0x00800000lu
3515#define MUTE_CH39 0x80000000lu
3516
3517#define TX_CH36 0x0000007Flu
3518#define TX_CH37 0x00007F00lu
3519#define TX_CH38 0x007F0000lu
3520#define TX_CH39 0x7F000000lu
3521
3522
3523/* MXVR_ROUTING_10 Masks */
3524
3525#define MUTE_CH40 0x00000080lu
3526#define MUTE_CH41 0x00008000lu
3527#define MUTE_CH42 0x00800000lu
3528#define MUTE_CH43 0x80000000lu
3529
3530#define TX_CH40 0x0000007Flu
3531#define TX_CH41 0x00007F00lu
3532#define TX_CH42 0x007F0000lu
3533#define TX_CH43 0x7F000000lu
3534
3535
3536/* MXVR_ROUTING_11 Masks */
3537
3538#define MUTE_CH44 0x00000080lu
3539#define MUTE_CH45 0x00008000lu
3540#define MUTE_CH46 0x00800000lu
3541#define MUTE_CH47 0x80000000lu
3542
3543#define TX_CH44 0x0000007Flu
3544#define TX_CH45 0x00007F00lu
3545#define TX_CH46 0x007F0000lu
3546#define TX_CH47 0x7F000000lu
3547
3548
3549/* MXVR_ROUTING_12 Masks */
3550
3551#define MUTE_CH48 0x00000080lu
3552#define MUTE_CH49 0x00008000lu
3553#define MUTE_CH50 0x00800000lu
3554#define MUTE_CH51 0x80000000lu
3555
3556#define TX_CH48 0x0000007Flu
3557#define TX_CH49 0x00007F00lu
3558#define TX_CH50 0x007F0000lu
3559#define TX_CH51 0x7F000000lu
3560
3561
3562/* MXVR_ROUTING_13 Masks */
3563
3564#define MUTE_CH52 0x00000080lu
3565#define MUTE_CH53 0x00008000lu
3566#define MUTE_CH54 0x00800000lu
3567#define MUTE_CH55 0x80000000lu
3568
3569#define TX_CH52 0x0000007Flu
3570#define TX_CH53 0x00007F00lu
3571#define TX_CH54 0x007F0000lu
3572#define TX_CH55 0x7F000000lu
3573
3574
3575/* MXVR_ROUTING_14 Masks */
3576
3577#define MUTE_CH56 0x00000080lu
3578#define MUTE_CH57 0x00008000lu
3579#define MUTE_CH58 0x00800000lu
3580#define MUTE_CH59 0x80000000lu
3581
3582#define TX_CH56 0x0000007Flu
3583#define TX_CH57 0x00007F00lu
3584#define TX_CH58 0x007F0000lu
3585#define TX_CH59 0x7F000000lu
3586
3587
3588/* Control Message Receive Buffer (CMRB) Address Offsets */
3589
3590#define CMRB_STRIDE 0x00000016lu
3591
3592#define CMRB_DST_OFFSET 0x00000000lu
3593#define CMRB_SRC_OFFSET 0x00000002lu
3594#define CMRB_DATA_OFFSET 0x00000005lu
3595
3596
3597/* Control Message Transmit Buffer (CMTB) Address Offsets */
3598
3599#define CMTB_PRIO_OFFSET 0x00000000lu
3600#define CMTB_DST_OFFSET 0x00000002lu
3601#define CMTB_SRC_OFFSET 0x00000004lu
3602#define CMTB_TYPE_OFFSET 0x00000006lu
3603#define CMTB_DATA_OFFSET 0x00000007lu
3604
3605#define CMTB_ANSWER_OFFSET 0x0000000Alu
3606
3607#define CMTB_STAT_N_OFFSET 0x00000018lu
3608#define CMTB_STAT_A_OFFSET 0x00000016lu
3609#define CMTB_STAT_D_OFFSET 0x0000000Elu
3610#define CMTB_STAT_R_OFFSET 0x00000014lu
3611#define CMTB_STAT_W_OFFSET 0x00000014lu
3612#define CMTB_STAT_G_OFFSET 0x00000014lu
3613
3614
3615/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
3616
3617#define APRB_STRIDE 0x00000400lu
3618
3619#define APRB_DST_OFFSET 0x00000000lu
3620#define APRB_LEN_OFFSET 0x00000002lu
3621#define APRB_SRC_OFFSET 0x00000004lu
3622#define APRB_DATA_OFFSET 0x00000006lu
3623
3624
3625/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
3626
3627#define APTB_PRIO_OFFSET 0x00000000lu
3628#define APTB_DST_OFFSET 0x00000002lu
3629#define APTB_LEN_OFFSET 0x00000004lu
3630#define APTB_SRC_OFFSET 0x00000006lu
3631#define APTB_DATA_OFFSET 0x00000008lu
3632
3633
3634/* Remote Read Buffer (RRDB) Address Offsets */
3635
3636#define RRDB_WADDR_OFFSET 0x00000100lu
3637#define RRDB_WLEN_OFFSET 0x00000101lu
3638
3639
3640
3641/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ 2422/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
3642/* CAN_CONTROL Masks */ 2423/* CAN_CONTROL Masks */
3643#define SRS 0x0001 /* Software Reset */ 2424#define SRS 0x0001 /* Software Reset */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 295c78a465c2..0c346fba9619 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Analog Devices Inc. 2 * Copyright (C) 2008-2009 Analog Devices Inc.
3 * Licensed under the GPL-2 or later. 3 * Licensed under the GPL-2 or later.
4 */ 4 */
5 5
@@ -7,11 +7,8 @@
7#ifndef _MACH_GPIO_H_ 7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10 /* FIXME:
11 * For now only support PORTF GPIOs.
12 * PORT C,D and E are for peripheral usage only
13 */
14#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11#define BFIN_SPECIAL_GPIO_BANKS 3
15 12
16#define GPIO_PF0 0 /* PF */ 13#define GPIO_PF0 0 /* PF */
17#define GPIO_PF1 1 14#define GPIO_PF1 1
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
index 6121cf8b5872..0083ba13ee9e 100644
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES 64
11 11
12#define P_TMR2 (P_DONTCARE) 12#define P_TMR2 (P_DONTCARE)
13#define P_TMR1 (P_DONTCARE) 13#define P_TMR1 (P_DONTCARE)
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index a09623dfd550..70189a0d1a19 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -1,3 +1,27 @@
1config BF542
2 def_bool y
3 depends on BF542_std || BF542M
4config BF544
5 def_bool y
6 depends on BF544_std || BF544M
7config BF547
8 def_bool y
9 depends on BF547_std || BF547M
10config BF548
11 def_bool y
12 depends on BF548_std || BF548M
13config BF549
14 def_bool y
15 depends on BF549_std || BF549M
16
17config BF54xM
18 def_bool y
19 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
20
21config BF54x
22 def_bool y
23 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
24
1if (BF54x) 25if (BF54x)
2 26
3source "arch/blackfin/mach-bf548/boards/Kconfig" 27source "arch/blackfin/mach-bf548/boards/Kconfig"
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 1a5286bbb3fa..60193f72777c 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -62,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = {
62}; 62};
63 63
64static struct platform_device bfin_isp1760_device = { 64static struct platform_device bfin_isp1760_device = {
65 .name = "isp1760-hcd", 65 .name = "isp1760",
66 .id = 0, 66 .id = 0,
67 .dev = { 67 .dev = {
68 .platform_data = &isp1760_priv, 68 .platform_data = &isp1760_priv,
@@ -154,7 +154,7 @@ static struct platform_device bf54x_kpad_device = {
154}; 154};
155#endif 155#endif
156 156
157#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) 157#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
158#include <asm/bfin_rotary.h> 158#include <asm/bfin_rotary.h>
159 159
160static struct bfin_rotary_platform_data bfin_rotary_data = { 160static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -186,7 +186,7 @@ static struct platform_device bfin_rotary_device = {
186#endif 186#endif
187 187
188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) 188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
189#include <linux/spi/adxl34x.h> 189#include <linux/input/adxl34x.h>
190static const struct adxl34x_platform_data adxl34x_info = { 190static const struct adxl34x_platform_data adxl34x_info = {
191 .x_axis_offset = 0, 191 .x_axis_offset = 0,
192 .y_axis_offset = 0, 192 .y_axis_offset = 0,
@@ -210,14 +210,17 @@ static const struct adxl34x_platform_data adxl34x_info = {
210 .ev_code_y = ABS_Y, /* EV_REL */ 210 .ev_code_y = ABS_Y, /* EV_REL */
211 .ev_code_z = ABS_Z, /* EV_REL */ 211 .ev_code_z = ABS_Z, /* EV_REL */
212 212
213 .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ 213 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
214 .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */
215 .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */
216 214
217/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ 215/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
218/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ 216/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
219 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, 217 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
220 .fifo_mode = ADXL_FIFO_STREAM, 218 .fifo_mode = ADXL_FIFO_STREAM,
219 .orientation_enable = ADXL_EN_ORIENTATION_3D,
220 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
221 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
222 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
223 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
221}; 224};
222#endif 225#endif
223 226
@@ -461,6 +464,44 @@ static struct platform_device musb_device = {
461}; 464};
462#endif 465#endif
463 466
467#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
468unsigned short bfin_can_peripherals[] = {
469 P_CAN0_RX, P_CAN0_TX, 0
470};
471
472static struct resource bfin_can_resources[] = {
473 {
474 .start = 0xFFC02A00,
475 .end = 0xFFC02FFF,
476 .flags = IORESOURCE_MEM,
477 },
478 {
479 .start = IRQ_CAN0_RX,
480 .end = IRQ_CAN0_RX,
481 .flags = IORESOURCE_IRQ,
482 },
483 {
484 .start = IRQ_CAN0_TX,
485 .end = IRQ_CAN0_TX,
486 .flags = IORESOURCE_IRQ,
487 },
488 {
489 .start = IRQ_CAN0_ERROR,
490 .end = IRQ_CAN0_ERROR,
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
495static struct platform_device bfin_can_device = {
496 .name = "bfin_can",
497 .num_resources = ARRAY_SIZE(bfin_can_resources),
498 .resource = bfin_can_resources,
499 .dev = {
500 .platform_data = &bfin_can_peripherals, /* Passed to driver */
501 },
502};
503#endif
504
464#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 505#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
465static struct resource bfin_atapi_resources[] = { 506static struct resource bfin_atapi_resources[] = {
466 { 507 {
@@ -953,6 +994,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
953 &bfin_isp1760_device, 994 &bfin_isp1760_device,
954#endif 995#endif
955 996
997#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
998 &bfin_can_device,
999#endif
1000
956#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 1001#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
957 &bfin_atapi_device, 1002 &bfin_atapi_device,
958#endif 1003#endif
@@ -974,7 +1019,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
974 &bf54x_kpad_device, 1019 &bf54x_kpad_device,
975#endif 1020#endif
976 1021
977#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) 1022#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
978 &bfin_rotary_device, 1023 &bfin_rotary_device,
979#endif 1024#endif
980 1025
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index 7bead5ce0f3b..751e5e11ecf8 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -81,18 +81,6 @@
81 81
82#define AMGCTLVAL (V_AMBEN | V_AMCKEN) 82#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
83 83
84#if defined(CONFIG_BF542M)
85# define CONFIG_BF542
86#elif defined(CONFIG_BF544M)
87# define CONFIG_BF544
88#elif defined(CONFIG_BF547M)
89# define CONFIG_BF547
90#elif defined(CONFIG_BF548M)
91# define CONFIG_BF548
92#elif defined(CONFIG_BF549M)
93# define CONFIG_BF549
94#endif
95
96#if defined(CONFIG_BF542) 84#if defined(CONFIG_BF542)
97# define CPU "BF542" 85# define CPU "BF542"
98# define CPUID 0x27de 86# define CPUID 0x27de
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 13302b67857a..5684030ccc21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -64,10 +64,4 @@
64#define OFFSET_THR 0x28 /* Transmit Holding register */ 64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */ 65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66 66
67/* PLL_DIV Masks */
68#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
69#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
70#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
71#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
72
73#endif 67#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index 423421515134..bc650e6ea482 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -4,21 +4,21 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _CDEF_BF548_H 7#ifndef _CDEF_BF547_H
8#define _CDEF_BF548_H 8#define _CDEF_BF547_H
9 9
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF548.h" 11#include "defBF547.h"
12 12
13/* include core sbfin_read_()ecific register pointer definitions */ 13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h> 14#include <asm/cdef_LPBlackfin.h>
15 15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ 16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
17 17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 19#include "cdefBF54x_base.h"
20 20
21/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 21/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
22 22
23/* Timer Registers */ 23/* Timer Registers */
24 24
@@ -805,4 +805,4 @@
805#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 805#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
806#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) 806#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
807 807
808#endif /* _CDEF_BF548_H */ 808#endif /* _CDEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index df84180410c4..3523e08f7968 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -18,165 +18,8 @@
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 19#include "cdefBF54x_base.h"
20 20
21/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 21/* The BF548 is like the BF547, but has additional CANs */
22 22#include "cdefBF547.h"
23/* Timer Registers */
24
25#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
26#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
27#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
28#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
29#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
30#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
31#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
32#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
33#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
34#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
35#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
36#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
37#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
38#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
39#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
40#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
41#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
42#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
43#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
44#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
45#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
46#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
47#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
48#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
49
50/* Timer Groubfin_read_() of 3 */
51
52#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
53#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
54#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
55#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
56#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
57#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
58
59/* SPORT0 Registers */
60
61#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
62#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
63#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
64#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
65#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
66#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
67#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
68#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
69#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
70#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
71#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
72#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
73#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
74#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
75#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
76#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
77#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
78#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
79#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
80#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
81#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
82#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
83#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
84#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
85#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
86#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
87#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
88#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
89#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
90#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
91#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
92#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
93#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
94#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
95#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
96#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
97#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
98#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
99#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
100#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
101#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
102#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
103#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
104#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
105
106/* EPPI0 Registers */
107
108#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
109#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
110#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
111#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
112#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
113#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
114#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
115#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
116#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
117#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
118#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
119#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
120#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
121#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
122#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
123#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
124#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
125#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
126#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
127#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
128#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
129#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
130#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
131#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
132#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
133#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
134#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
135#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
136
137/* UART2 Registers */
138
139#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
140#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
141#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
142#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
143#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
144#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
145#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
146#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
147#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
148#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
149#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
150#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
151#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
152#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
153#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
154#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
155#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
156#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
157#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
158#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
159#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
160#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
161
162/* Two Wire Interface Registers (TWI1) */
163
164/* SPI2 Registers */
165
166#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
167#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
168#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
169#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
170#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
171#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
172#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
173#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
174#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
175#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
176#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
177#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
178#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
179#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
180 23
181/* CAN Controller 1 Config 1 Registers */ 24/* CAN Controller 1 Config 1 Registers */
182 25
@@ -923,631 +766,4 @@
923#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) 766#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
924#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) 767#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
925 768
926/* ATAPI Registers */
927
928#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
929#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
930#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
931#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
932#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
933#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
934#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
935#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
936#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
937#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
938#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
939#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
940#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
941#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
942#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
943#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
944#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
945#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
946#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
947#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
948#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
949#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
950#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
951#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
952#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
953#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
954#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
955#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
956#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
957#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
958#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
959#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
960#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
961#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
962#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
963#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
964#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
965#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
966#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
967#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
968#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
969#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
970#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
971#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
972#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
973#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
974#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
975#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
976#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
977#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
978
979/* SDH Registers */
980
981#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
982#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
983#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
984#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
985#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
986#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
987#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
988#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
989#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
990#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
991#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
992#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
993#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
994#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
995#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
996#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
997#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
998#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
999#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1000#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1001#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1002#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1003#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1004#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1005#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1006#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1007#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1008#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1009#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1010#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1011#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1012#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1013#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1014#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1015#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1016#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1017#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1018#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1019#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1020#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1021#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1022#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1023#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1024#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1025#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1026#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1027#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1028#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1029#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1030#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1031#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1032#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1033#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1034#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1035#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1036#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1037#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1038#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1039#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1040#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1041#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1042#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1043
1044/* HOST Port Registers */
1045
1046#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1047#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1048#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1049#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1050#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1051#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1052
1053/* USB Control Registers */
1054
1055#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1056#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1057#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1058#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1059#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1060#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1061#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1062#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1063#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1064#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1065#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1066#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1067#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1068#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1069#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1070#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1071#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1072#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1073#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1074#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1075#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1076#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1077#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1078#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1079#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1080#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1081
1082/* USB Packet Control Registers */
1083
1084#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1085#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1086#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1087#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1088#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1089#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1090#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1091#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1092#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1093#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1094#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1095#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1096#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1097#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1098#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1099#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1100#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1101#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1102#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1103#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1104#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1105#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1106#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1107#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1108#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1109#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1110
1111/* USB Endbfin_read_()oint FIFO Registers */
1112
1113#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1114#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1115#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1116#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1117#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1118#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1119#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1120#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1121#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1122#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1123#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1124#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1125#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1126#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1127#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1128#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1129
1130/* USB OTG Control Registers */
1131
1132#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1133#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1134#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1135#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1136#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1137#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1138
1139/* USB Phy Control Registers */
1140
1141#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1142#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1143#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1144#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1145#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1146#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1147#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1148#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1149#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1150#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1151
1152/* (APHY_CNTRL is for ADI usage only) */
1153
1154#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1155#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1156
1157/* (APHY_CALIB is for ADI usage only) */
1158
1159#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1160#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1161#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1162#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1163
1164/* (PHY_TEST is for ADI usage only) */
1165
1166#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1167#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1168#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1169#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1170#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1171#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1172
1173/* USB Endbfin_read_()oint 0 Control Registers */
1174
1175#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1176#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1177#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1178#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1179#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1180#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1181#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1182#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1183#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1184#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1185#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1186#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1187#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1188#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1189#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1190#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1191#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1192#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1193
1194/* USB Endbfin_read_()oint 1 Control Registers */
1195
1196#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1197#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1198#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1199#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1200#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1201#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1202#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1203#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1204#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1205#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1206#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1207#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1208#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1209#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1210#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1211#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1212#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1213#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1214#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1215#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1216
1217/* USB Endbfin_read_()oint 2 Control Registers */
1218
1219#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1220#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1221#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1222#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1223#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1224#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1225#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1226#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1227#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1228#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1229#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1230#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1231#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1232#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1233#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1234#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1235#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1236#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1237#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1238#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1239
1240/* USB Endbfin_read_()oint 3 Control Registers */
1241
1242#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1243#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1244#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1245#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1246#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1247#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1248#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1249#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1250#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1251#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1252#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1253#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1254#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1255#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1256#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1257#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1258#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1259#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1260#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1261#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1262
1263/* USB Endbfin_read_()oint 4 Control Registers */
1264
1265#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1266#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1267#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1268#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1269#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1270#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1271#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1272#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1273#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1274#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1275#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1276#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1277#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1278#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1279#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1280#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1281#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1282#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1283#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1284#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1285
1286/* USB Endbfin_read_()oint 5 Control Registers */
1287
1288#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1289#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1290#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1291#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1292#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1293#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1294#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1295#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1296#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1297#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1298#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1299#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1300#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1301#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1302#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1303#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1304#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1305#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1306#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1307#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1308
1309/* USB Endbfin_read_()oint 6 Control Registers */
1310
1311#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1312#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1313#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1314#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1315#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1316#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1317#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1318#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1319#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1320#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1321#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1322#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1323#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1324#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1325#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1326#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1327#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1328#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1329#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1330#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1331
1332/* USB Endbfin_read_()oint 7 Control Registers */
1333
1334#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1335#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1336#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1337#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1338#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1339#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1340#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1341#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1342#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1343#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1344#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1345#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1346#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1347#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1348#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1349#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1350#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1351#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1352#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1353#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1354#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1355#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1356#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1357#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1358
1359/* USB Channel 0 Config Registers */
1360
1361#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1362#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1363#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1364#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1365#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1366#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1367#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1368#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1369#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1370#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1371
1372/* USB Channel 1 Config Registers */
1373
1374#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1375#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1376#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1377#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1378#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1379#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1380#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1381#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1382#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1383#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1384
1385/* USB Channel 2 Config Registers */
1386
1387#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1388#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1389#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1390#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1391#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1392#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1393#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1394#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1395#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1396#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1397
1398/* USB Channel 3 Config Registers */
1399
1400#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1401#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1402#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1403#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1404#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1405#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1406#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1407#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1408#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1409#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1410
1411/* USB Channel 4 Config Registers */
1412
1413#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1414#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1415#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1416#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1417#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1418#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1419#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1420#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1421#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1422#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1423
1424/* USB Channel 5 Config Registers */
1425
1426#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1427#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1428#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1429#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1430#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1431#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1432#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1433#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1434#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1435#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1436
1437/* USB Channel 6 Config Registers */
1438
1439#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1440#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1441#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1442#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1443#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1444#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1445#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1446#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1447#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1448#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1449
1450/* USB Channel 7 Config Registers */
1451
1452#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1453#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1454#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1455#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1456#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1457#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1458#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1459#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1460#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1461#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1462
1463/* Keybfin_read_()ad Registers */
1464
1465#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1466#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1467#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1468#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1469#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1470#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1471#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1472#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1473#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1474#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1475#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1476#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1477
1478/* Pixel Combfin_read_()ositor (PIXC) Registers */
1479
1480#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1481#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1482#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1483#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1484#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1485#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1486#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1487#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1488#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1489#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1490#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1491#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1492#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1493#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1494#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1495#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1496#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1497#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1498#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1499#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1500#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1501#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1502#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1503#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1504#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1505#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1506#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1507#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1508#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1509#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1510#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1511#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1512#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1513#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1514#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1515#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1516#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1517#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1518
1519/* Handshake MDMA 0 Registers */
1520
1521#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1522#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1523#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1524#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1525#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1526#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1527#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1528#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1529#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1530#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1531#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1532#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1533#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1534#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1535
1536/* Handshake MDMA 1 Registers */
1537
1538#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1539#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1540#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1541#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1542#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1543#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1544#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1545#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1546#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1547#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1548#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1549#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1550#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1551#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1552
1553#endif /* _CDEF_BF548_H */ 769#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 34c84c7fb256..80201ed41f80 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -18,165 +18,8 @@
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 19#include "cdefBF54x_base.h"
20 20
21/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ 21/* The BF549 is like the BF544, but has MXVR */
22 22#include "cdefBF547.h"
23/* Timer Registers */
24
25#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
26#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
27#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
28#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
29#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
30#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
31#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
32#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
33#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
34#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
35#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
36#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
37#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
38#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
39#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
40#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
41#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
42#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
43#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
44#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
45#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
46#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
47#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
48#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
49
50/* Timer Groubfin_read_() of 3 */
51
52#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
53#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
54#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
55#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
56#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
57#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
58
59/* SPORT0 Registers */
60
61#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
62#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
63#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
64#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
65#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
66#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
67#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
68#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
69#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
70#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
71#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
72#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
73#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
74#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
75#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
76#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
77#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
78#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
79#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
80#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
81#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
82#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
83#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
84#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
85#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
86#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
87#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
88#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
89#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
90#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
91#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
92#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
93#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
94#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
95#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
96#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
97#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
98#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
99#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
100#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
101#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
102#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
103#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
104#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
105
106/* EPPI0 Registers */
107
108#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
109#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
110#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
111#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
112#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
113#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
114#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
115#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
116#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
117#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
118#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
119#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
120#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
121#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
122#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
123#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
124#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
125#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
126#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
127#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
128#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
129#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
130#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
131#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
132#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
133#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
134#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
135#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
136
137/* UART2 Registers */
138
139#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
140#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
141#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
142#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
143#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
144#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
145#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
146#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
147#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
148#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
149#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
150#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
151#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
152#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
153#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
154#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
155#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
156#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
157#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
158#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
159#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
160#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
161
162/* Two Wire Interface Registers (TWI1) */
163
164/* SPI2 Registers */
165
166#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
167#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
168#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
169#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
170#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
171#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
172#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
173#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
174#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
175#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
176#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
177#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
178#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
179#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
180 23
181/* MXVR Registers */ 24/* MXVR Registers */
182 25
@@ -464,1376 +307,4 @@
464#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) 307#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
465#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) 308#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
466 309
467/* CAN Controller 1 Config 1 Registers */
468
469#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
470#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
471#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
472#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
473#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
474#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
475#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
476#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
477#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
478#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
479#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
480#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
481#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
482#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
483#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
484#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
485#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
486#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
487#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
488#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
489#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
490#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
491#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
492#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
493#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
494#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
495
496/* CAN Controller 1 Config 2 Registers */
497
498#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
499#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
500#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
501#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
502#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
503#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
504#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
505#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
506#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
507#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
508#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
509#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
510#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
511#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
512#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
513#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
514#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
515#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
516#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
517#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
518#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
519#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
520#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
521#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
522#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
523#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
524
525/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
526
527#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
528#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
529#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
530#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
531#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
532#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
533#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
534#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
535#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
536#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
537#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
538#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
539#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
540#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
541#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
542#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
543#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
544#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
545#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
546#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
547#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
548#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
549#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
550#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
551#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
552#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
553#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
554#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
555#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
556#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
557#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
558#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
559
560/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
561
562#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
563#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
564#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
565#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
566#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
567#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
568#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
569#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
570#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
571#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
572#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
573#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
574#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
575#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
576#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
577#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
578#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
579#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
580#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
581#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
582#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
583#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
584#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
585#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
586#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
587#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
588#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
589#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
590#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
591#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
592#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
593#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
594#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
595#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
596#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
597#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
598#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
599#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
600#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
601#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
602#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
603#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
604#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
605#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
606#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
607#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
608#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
609#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
610#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
611#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
612#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
613#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
614#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
615#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
616#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
617#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
618#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
619#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
620#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
621#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
622#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
623#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
624#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
625#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
626
627/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
628
629#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
630#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
631#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
632#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
633#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
634#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
635#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
636#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
637#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
638#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
639#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
640#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
641#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
642#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
643#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
644#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
645#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
646#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
647#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
648#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
649#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
650#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
651#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
652#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
653#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
654#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
655#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
656#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
657#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
658#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
659#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
660#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
661#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
662#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
663#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
664#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
665#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
666#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
667#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
668#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
669#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
670#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
671#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
672#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
673#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
674#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
675#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
676#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
677#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
678#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
679#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
680#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
681#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
682#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
683#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
684#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
685#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
686#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
687#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
688#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
689#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
690#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
691#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
692#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
693
694/* CAN Controller 1 Mailbox Data Registers */
695
696#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
697#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
698#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
699#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
700#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
701#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
702#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
703#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
704#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
705#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
706#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
707#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
708#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
709#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
710#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
711#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
712#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
713#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
714#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
715#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
716#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
717#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
718#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
719#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
720#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
721#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
722#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
723#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
724#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
725#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
726#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
727#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
728#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
729#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
730#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
731#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
732#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
733#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
734#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
735#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
736#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
737#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
738#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
739#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
740#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
741#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
742#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
743#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
744#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
745#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
746#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
747#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
748#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
749#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
750#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
751#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
752#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
753#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
754#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
755#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
756#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
757#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
758#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
759#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
760#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
761#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
762#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
763#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
764#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
765#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
766#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
767#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
768#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
769#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
770#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
771#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
772#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
773#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
774#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
775#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
776#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
777#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
778#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
779#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
780#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
781#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
782#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
783#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
784#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
785#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
786#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
787#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
788#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
789#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
790#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
791#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
792#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
793#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
794#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
795#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
796#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
797#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
798#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
799#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
800#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
801#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
802#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
803#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
804#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
805#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
806#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
807#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
808#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
809#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
810#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
811#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
812#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
813#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
814#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
815#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
816#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
817#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
818#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
819#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
820#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
821#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
822#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
823#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
824#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
825#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
826#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
827#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
828#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
829#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
830#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
831#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
832#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
833#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
834#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
835#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
836#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
837#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
838#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
839#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
840#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
841#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
842#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
843#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
844#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
845#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
846#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
847#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
848#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
849#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
850#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
851#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
852#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
853#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
854#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
855#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
856#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
857#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
858#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
859#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
860#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
861#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
862#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
863#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
864#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
865#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
866#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
867#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
868#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
869#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
870#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
871#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
872#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
873#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
874#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
875#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
876#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
877#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
878#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
879#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
880#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
881#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
882#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
883#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
884#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
885#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
886#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
887#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
888#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
889#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
890#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
891#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
892#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
893#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
894#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
895#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
896#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
897#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
898#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
899#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
900#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
901#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
902#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
903#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
904#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
905#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
906#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
907#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
908#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
909#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
910#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
911#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
912#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
913#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
914#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
915#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
916#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
917#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
918#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
919#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
920#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
921#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
922#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
923#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
924#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
925#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
926#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
927#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
928#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
929#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
930#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
931#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
932#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
933#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
934#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
935#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
936#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
937#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
938#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
939#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
940#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
941#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
942#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
943#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
944#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
945#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
946#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
947#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
948#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
949#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
950#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
951#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
952
953/* CAN Controller 1 Mailbox Data Registers */
954
955#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
956#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
957#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
958#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
959#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
960#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
961#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
962#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
963#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
964#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
965#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
966#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
967#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
968#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
969#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
970#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
971#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
972#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
973#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
974#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
975#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
976#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
977#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
978#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
979#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
980#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
981#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
982#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
983#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
984#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
985#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
986#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
987#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
988#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
989#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
990#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
991#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
992#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
993#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
994#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
995#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
996#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
997#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
998#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
999#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
1000#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
1001#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
1002#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
1003#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
1004#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
1005#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
1006#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
1007#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
1008#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
1009#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
1010#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
1011#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
1012#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
1013#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
1014#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
1015#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
1016#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
1017#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
1018#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
1019#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
1020#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
1021#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
1022#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
1023#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
1024#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
1025#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
1026#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
1027#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
1028#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
1029#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
1030#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
1031#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
1032#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
1033#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
1034#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
1035#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
1036#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
1037#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
1038#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
1039#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
1040#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
1041#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
1042#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
1043#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
1044#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
1045#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
1046#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
1047#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
1048#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
1049#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
1050#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
1051#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
1052#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
1053#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
1054#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
1055#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
1056#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
1057#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
1058#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
1059#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
1060#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
1061#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
1062#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
1063#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
1064#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
1065#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
1066#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
1067#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
1068#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
1069#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
1070#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
1071#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
1072#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
1073#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
1074#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
1075#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
1076#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
1077#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
1078#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
1079#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
1080#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
1081#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
1082#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
1083#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
1084#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
1085#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
1086#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
1087#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
1088#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
1089#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
1090#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
1091#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
1092#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
1093#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
1094#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
1095#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
1096#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
1097#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
1098#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
1099#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
1100#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
1101#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
1102#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
1103#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
1104#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
1105#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
1106#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
1107#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
1108#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
1109#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
1110#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
1111#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
1112#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
1113#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
1114#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
1115#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
1116#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
1117#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
1118#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
1119#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
1120#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
1121#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
1122#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
1123#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
1124#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
1125#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
1126#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
1127#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
1128#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
1129#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
1130#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
1131#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
1132#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
1133#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
1134#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
1135#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
1136#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
1137#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
1138#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
1139#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
1140#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
1141#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
1142#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
1143#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
1144#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
1145#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
1146#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
1147#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
1148#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
1149#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
1150#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
1151#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
1152#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
1153#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
1154#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
1155#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
1156#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
1157#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
1158#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
1159#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
1160#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
1161#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
1162#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
1163#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
1164#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
1165#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
1166#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
1167#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
1168#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
1169#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
1170#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
1171#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
1172#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
1173#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
1174#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
1175#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
1176#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
1177#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
1178#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
1179#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
1180#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
1181#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
1182#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
1183#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
1184#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
1185#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
1186#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
1187#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
1188#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
1189#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
1190#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
1191#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
1192#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
1193#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
1194#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
1195#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
1196#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
1197#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
1198#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
1199#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
1200#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
1201#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
1202#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
1203#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
1204#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
1205#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
1206#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
1207#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
1208#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
1209#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
1210#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
1211
1212/* ATAPI Registers */
1213
1214#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
1215#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
1216#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
1217#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
1218#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
1219#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
1220#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
1221#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
1222#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
1223#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
1224#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
1225#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
1226#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
1227#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
1228#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1229#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1230#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1231#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1232#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1233#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1234#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1235#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1236#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1237#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1238#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1239#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1240#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1241#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1242#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1243#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1244#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1245#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1246#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1247#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1248#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1249#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1250#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1251#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1252#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1253#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1254#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1255#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1256#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1257#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1258#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1259#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1260#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1261#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1262#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1263#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1264
1265/* SDH Registers */
1266
1267#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1268#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1269#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1270#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1271#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1272#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1273#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1274#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1275#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1276#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1277#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1278#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1279#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1280#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1281#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1282#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1283#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1284#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1285#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1286#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1287#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1288#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1289#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1290#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1291#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1292#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1293#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1294#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1295#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1296#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1297#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1298#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1299#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1300#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1301#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1302#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1303#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1304#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1305#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1306#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1307#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1308#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1309#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1310#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1311#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1312#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1313#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1314#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1315#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1316#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1317#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1318#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1319#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1320#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1321#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1322#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1323#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1324#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1325#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1326#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1327#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1328#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1329
1330/* HOST Port Registers */
1331
1332#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1333#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1334#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1335#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1336#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1337#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1338
1339/* USB Control Registers */
1340
1341#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1342#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1343#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1344#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1345#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1346#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1347#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1348#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1349#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1350#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1351#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1352#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1353#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1354#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1355#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1356#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1357#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1358#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1359#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1360#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1361#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1362#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1363#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1364#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1365#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1366#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1367
1368/* USB Packet Control Registers */
1369
1370#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1371#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1372#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1373#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1374#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1375#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1376#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1377#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1378#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1379#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1380#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1381#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1382#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1383#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1384#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1385#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1386#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1387#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1388#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1389#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1390#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1391#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1392#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1393#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1394#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1395#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1396
1397/* USB Endbfin_read_()oint FIFO Registers */
1398
1399#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1400#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1401#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1402#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1403#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1404#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1405#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1406#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1407#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1408#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1409#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1410#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1411#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1412#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1413#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1414#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1415
1416/* USB OTG Control Registers */
1417
1418#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1419#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1420#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1421#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1422#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1423#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1424
1425/* USB Phy Control Registers */
1426
1427#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1428#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1429#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1430#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1431#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1432#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1433#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1434#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1435#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1436#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1437
1438/* (APHY_CNTRL is for ADI usage only) */
1439
1440#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1441#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1442
1443/* (APHY_CALIB is for ADI usage only) */
1444
1445#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1446#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1447#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1448#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1449
1450/* (PHY_TEST is for ADI usage only) */
1451
1452#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1453#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1454#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1455#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1456#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1457#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1458
1459/* USB Endbfin_read_()oint 0 Control Registers */
1460
1461#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1462#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1463#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1464#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1465#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1466#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1467#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1468#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1469#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1470#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1471#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1472#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1473#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1474#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1475#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1476#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1477#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1478#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1479
1480/* USB Endbfin_read_()oint 1 Control Registers */
1481
1482#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1483#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1484#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1485#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1486#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1487#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1488#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1489#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1490#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1491#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1492#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1493#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1494#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1495#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1496#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1497#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1498#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1499#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1500#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1501#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1502
1503/* USB Endbfin_read_()oint 2 Control Registers */
1504
1505#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1506#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1507#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1508#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1509#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1510#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1511#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1512#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1513#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1514#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1515#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1516#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1517#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1518#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1519#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1520#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1521#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1522#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1523#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1524#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1525
1526/* USB Endbfin_read_()oint 3 Control Registers */
1527
1528#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1529#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1530#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1531#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1532#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1533#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1534#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1535#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1536#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1537#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1538#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1539#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1540#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1541#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1542#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1543#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1544#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1545#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1546#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1547#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1548
1549/* USB Endbfin_read_()oint 4 Control Registers */
1550
1551#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1552#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1553#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1554#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1555#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1556#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1557#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1558#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1559#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1560#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1561#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1562#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1563#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1564#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1565#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1566#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1567#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1568#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1569#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1570#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1571
1572/* USB Endbfin_read_()oint 5 Control Registers */
1573
1574#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1575#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1576#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1577#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1578#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1579#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1580#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1581#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1582#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1583#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1584#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1585#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1586#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1587#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1588#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1589#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1590#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1591#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1592#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1593#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1594
1595/* USB Endbfin_read_()oint 6 Control Registers */
1596
1597#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1598#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1599#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1600#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1601#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1602#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1603#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1604#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1605#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1606#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1607#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1608#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1609#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1610#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1611#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1612#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1613#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1614#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1615#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1616#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1617
1618/* USB Endbfin_read_()oint 7 Control Registers */
1619
1620#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1621#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1622#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1623#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1624#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1625#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1626#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1627#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1628#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1629#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1630#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1631#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1632#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1633#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1634#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1635#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1636#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1637#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1638#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1639#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1640#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1641#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1642#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1643#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1644
1645/* USB Channel 0 Config Registers */
1646
1647#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1648#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1649#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1650#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1651#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1652#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1653#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1654#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1655#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1656#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1657
1658/* USB Channel 1 Config Registers */
1659
1660#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1661#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1662#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1663#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1664#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1665#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1666#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1667#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1668#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1669#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1670
1671/* USB Channel 2 Config Registers */
1672
1673#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1674#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1675#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1676#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1677#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1678#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1679#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1680#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1681#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1682#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1683
1684/* USB Channel 3 Config Registers */
1685
1686#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1687#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1688#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1689#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1690#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1691#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1692#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1693#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1694#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1695#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1696
1697/* USB Channel 4 Config Registers */
1698
1699#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1700#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1701#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1702#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1703#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1704#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1705#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1706#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1707#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1708#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1709
1710/* USB Channel 5 Config Registers */
1711
1712#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1713#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1714#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1715#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1716#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1717#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1718#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1719#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1720#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1721#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1722
1723/* USB Channel 6 Config Registers */
1724
1725#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1726#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1727#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1728#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1729#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1730#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1731#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1732#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1733#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1734#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1735
1736/* USB Channel 7 Config Registers */
1737
1738#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1739#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1740#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1741#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1742#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1743#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1744#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1745#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1746#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1747#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1748
1749/* Keybfin_read_()ad Registers */
1750
1751#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1752#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1753#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1754#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1755#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1756#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1757#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1758#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1759#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1760#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1761#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1762#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1763
1764/* Pixel Combfin_read_()ositor (PIXC) Registers */
1765
1766#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1767#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1768#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1769#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1770#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1771#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1772#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1773#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1774#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1775#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1776#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1777#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1778#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1779#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1780#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1781#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1782#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1783#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1784#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1785#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1786#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1787#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1788#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1789#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1790#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1791#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1792#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1793#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1794#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1795#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1796#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1797#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1798#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1799#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1800#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1801#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1802#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1803#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1804
1805/* Handshake MDMA 0 Registers */
1806
1807#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1808#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1809#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1810#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1811#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1812#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1813#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1814#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1815#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1816#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1817#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1818#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1819#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1820#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1821
1822/* Handshake MDMA 1 Registers */
1823
1824#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1825#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1826#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1827#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1828#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1829#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1830#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1831#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1832#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1833#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1834#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1835#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1836#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1837#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1838
1839#endif /* _CDEF_BF549_H */ 310#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index a2e9d9849eba..32f71e6a7c15 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2615,17 +2615,6 @@
2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 2615#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 2616#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2617 2617
2618/* OTP/FUSE Registers */
2619
2620#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2621#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2622#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2623#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2624#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2625#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2626#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2627#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2628
2629/* Security Registers */ 2618/* Security Registers */
2630 2619
2631#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 2620#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
@@ -2640,17 +2629,6 @@
2640#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) 2629#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2641#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) 2630#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2642 2631
2643/* OTP Read/Write Data Buffer Registers */
2644
2645#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2646#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2647#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2648#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2649#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2650#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2651#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2652#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2653
2654/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ 2632/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2655 2633
2656/* legacy definitions */ 2634/* legacy definitions */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index 39f588dcd382..f916c52a148a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -624,9 +624,9 @@
624#define DMA_READY 0x1 /* DMA Ready */ 624#define DMA_READY 0x1 /* DMA Ready */
625#define FIFOFULL 0x2 /* FIFO Full */ 625#define FIFOFULL 0x2 /* FIFO Full */
626#define FIFOEMPTY 0x4 /* FIFO Empty */ 626#define FIFOEMPTY 0x4 /* FIFO Empty */
627#define COMPLETE 0x8 /* DMA Complete */ 627#define DMA_COMPLETE 0x8 /* DMA Complete */
628#define HSHK 0x10 /* Host Handshake */ 628#define HSHK 0x10 /* Host Handshake */
629#define TIMEOUT 0x20 /* Host Timeout */ 629#define HSTIMEOUT 0x20 /* Host Timeout */
630#define HIRQ 0x40 /* Host Interrupt Request */ 630#define HIRQ 0x40 /* Host Interrupt Request */
631#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 631#define ALLOW_CNFG 0x80 /* Allow New Configuration */
632#define DMA_DIR 0x100 /* DMA Direction */ 632#define DMA_DIR 0x100 /* DMA Direction */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index c4dcf302d9f5..72c343646b2a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -4,18 +4,18 @@
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF548_H 7#ifndef _DEF_BF547_H
8#define _DEF_BF548_H 8#define _DEF_BF547_H
9 9
10/* Include all Core registers and bit definitions */ 10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h> 11#include <asm/def_LPBlackfin.h>
12 12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ 13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
14 14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 16#include "defBF54x_base.h"
17 17
18/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 18/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
19 19
20/* Timer Registers */ 20/* Timer Registers */
21 21
@@ -1217,4 +1217,4 @@
1217/* ******************************************* */ 1217/* ******************************************* */
1218 1218
1219 1219
1220#endif /* _DEF_BF548_H */ 1220#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index a5079980968c..3fb33b040ab7 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -15,115 +15,8 @@
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 16#include "defBF54x_base.h"
17 17
18/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 18/* The BF548 is like the BF547, but has additional CANs */
19 19#include "defBF547.h"
20/* Timer Registers */
21
22#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
23#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
24#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
25#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
26#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
27#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
28#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
29#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
30#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
31#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
32#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
33#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
34
35/* Timer Group of 3 Registers */
36
37#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
38#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
39#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
40
41/* SPORT0 Registers */
42
43#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
44#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
45#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
46#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
47#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
48#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
49#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
50#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
51#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
52#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
53#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
54#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
55#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
56#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
57#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
58#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
59#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
60#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
61#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
62#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
63#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
64#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
65
66/* EPPI0 Registers */
67
68#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
69#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
70#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
71#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
72#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
73#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
74#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
75#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
76#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
77#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
78#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
79#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
80#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
81#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
82
83/* UART2 Registers */
84
85#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
86#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
87#define UART2_GCTL 0xffc02108 /* Global Control Register */
88#define UART2_LCR 0xffc0210c /* Line Control Register */
89#define UART2_MCR 0xffc02110 /* Modem Control Register */
90#define UART2_LSR 0xffc02114 /* Line Status Register */
91#define UART2_MSR 0xffc02118 /* Modem Status Register */
92#define UART2_SCR 0xffc0211c /* Scratch Register */
93#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
94#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
95#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
96
97/* Two Wire Interface Registers (TWI1) */
98
99#define TWI1_REGBASE 0xffc02200
100#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
101#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
102#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
103#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
104#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
105#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
106#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
107#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
108#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
109#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
110#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
111#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
112#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
113#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
114#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
115#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
116
117/* SPI2 Registers */
118
119#define SPI2_REGBASE 0xffc02400
120#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
121#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
122#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
123#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
124#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
125#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
126#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
127 20
128/* CAN Controller 1 Config 1 Registers */ 21/* CAN Controller 1 Config 1 Registers */
129 22
@@ -508,1096 +401,4 @@
508#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ 401#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
509#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ 402#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
510 403
511/* ATAPI Registers */
512
513#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
514#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
515#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
516#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
517#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
518#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
519#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
520#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
521#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
522#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
523#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
524#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
525#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
526#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
527#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
528#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
529#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
530#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
531#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
532#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
533#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
534#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
535#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
536#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
537#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
538
539/* SDH Registers */
540
541#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
542#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
543#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
544#define SDH_COMMAND 0xffc0390c /* SDH Command */
545#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
546#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
547#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
548#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
549#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
550#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
551#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
552#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
553#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
554#define SDH_STATUS 0xffc03934 /* SDH Status */
555#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
556#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
557#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
558#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
559#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
560#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
561#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
562#define SDH_CFG 0xffc039c8 /* SDH Configuration */
563#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
564#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
565#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
566#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
567#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
568#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
569#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
570#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
571#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
572
573/* HOST Port Registers */
574
575#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
576#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
577#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
578
579/* USB Control Registers */
580
581#define USB_FADDR 0xffc03c00 /* Function address register */
582#define USB_POWER 0xffc03c04 /* Power management register */
583#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
584#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
585#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
586#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
587#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
588#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
589#define USB_FRAME 0xffc03c20 /* USB frame number */
590#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
591#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
592#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
593#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
594
595/* USB Packet Control Registers */
596
597#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
598#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
599#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
600#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
601#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
602#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
603#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
604#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
605#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
606#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
607#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
608#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
609#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
610
611/* USB Endpoint FIFO Registers */
612
613#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
614#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
615#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
616#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
617#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
618#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
619#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
620#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
621
622/* USB OTG Control Registers */
623
624#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
625#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
626#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
627
628/* USB Phy Control Registers */
629
630#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
631#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
632#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
633#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
634#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
635
636/* (APHY_CNTRL is for ADI usage only) */
637
638#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
639
640/* (APHY_CALIB is for ADI usage only) */
641
642#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
643#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
644
645/* (PHY_TEST is for ADI usage only) */
646
647#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
648#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
649#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
650
651/* USB Endpoint 0 Control Registers */
652
653#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
654#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
655#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
656#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
657#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
658#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
659#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
660#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
661#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
662
663/* USB Endpoint 1 Control Registers */
664
665#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
666#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
667#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
668#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
669#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
670#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
671#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
672#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
673#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
674#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
675
676/* USB Endpoint 2 Control Registers */
677
678#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
679#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
680#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
681#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
682#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
683#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
684#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
685#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
686#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
687#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
688
689/* USB Endpoint 3 Control Registers */
690
691#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
692#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
693#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
694#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
695#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
696#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
697#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
698#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
699#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
700#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
701
702/* USB Endpoint 4 Control Registers */
703
704#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
705#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
706#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
707#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
708#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
709#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
710#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
711#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
712#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
713#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
714
715/* USB Endpoint 5 Control Registers */
716
717#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
718#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
719#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
720#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
721#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
722#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
723#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
724#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
725#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
726#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
727
728/* USB Endpoint 6 Control Registers */
729
730#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
731#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
732#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
733#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
734#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
735#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
736#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
737#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
738#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
739#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
740
741/* USB Endpoint 7 Control Registers */
742
743#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
744#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
745#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
746#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
747#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
748#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
749#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
750#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
751#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
752#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
753#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
754#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
755
756/* USB Channel 0 Config Registers */
757
758#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
759#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
760#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
761#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
762#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
763
764/* USB Channel 1 Config Registers */
765
766#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
767#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
768#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
769#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
770#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
771
772/* USB Channel 2 Config Registers */
773
774#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
775#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
776#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
777#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
778#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
779
780/* USB Channel 3 Config Registers */
781
782#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
783#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
784#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
785#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
786#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
787
788/* USB Channel 4 Config Registers */
789
790#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
791#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
792#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
793#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
794#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
795
796/* USB Channel 5 Config Registers */
797
798#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
799#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
800#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
801#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
802#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
803
804/* USB Channel 6 Config Registers */
805
806#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
807#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
808#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
809#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
810#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
811
812/* USB Channel 7 Config Registers */
813
814#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
815#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
816#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
817#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
818#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
819
820/* Keypad Registers */
821
822#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
823#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
824#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
825#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
826#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
827#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
828
829/* Pixel Compositor (PIXC) Registers */
830
831#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
832#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
833#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
834#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
835#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
836#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
837#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
838#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
839#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
840#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
841#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
842#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
843#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
844#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
845#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
846#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
847#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
848#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
849#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
850
851/* Handshake MDMA 0 Registers */
852
853#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
854#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
855#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
856#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
857#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
858#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
859#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
860
861/* Handshake MDMA 1 Registers */
862
863#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
864#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
865#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
866#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
867#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
868#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
869#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
870
871
872/* ********************************************************** */
873/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
874/* and MULTI BIT READ MACROS */
875/* ********************************************************** */
876
877/* Bit masks for PIXC_CTL */
878
879#define PIXC_EN 0x1 /* Pixel Compositor Enable */
880#define OVR_A_EN 0x2 /* Overlay A Enable */
881#define OVR_B_EN 0x4 /* Overlay B Enable */
882#define IMG_FORM 0x8 /* Image Data Format */
883#define OVR_FORM 0x10 /* Overlay Data Format */
884#define OUT_FORM 0x20 /* Output Data Format */
885#define UDS_MOD 0x40 /* Resampling Mode */
886#define TC_EN 0x80 /* Transparent Color Enable */
887#define IMG_STAT 0x300 /* Image FIFO Status */
888#define OVR_STAT 0xc00 /* Overlay FIFO Status */
889#define WM_LVL 0x3000 /* FIFO Watermark Level */
890
891/* Bit masks for PIXC_AHSTART */
892
893#define A_HSTART 0xfff /* Horizontal Start Coordinates */
894
895/* Bit masks for PIXC_AHEND */
896
897#define A_HEND 0xfff /* Horizontal End Coordinates */
898
899/* Bit masks for PIXC_AVSTART */
900
901#define A_VSTART 0x3ff /* Vertical Start Coordinates */
902
903/* Bit masks for PIXC_AVEND */
904
905#define A_VEND 0x3ff /* Vertical End Coordinates */
906
907/* Bit masks for PIXC_ATRANSP */
908
909#define A_TRANSP 0xf /* Transparency Value */
910
911/* Bit masks for PIXC_BHSTART */
912
913#define B_HSTART 0xfff /* Horizontal Start Coordinates */
914
915/* Bit masks for PIXC_BHEND */
916
917#define B_HEND 0xfff /* Horizontal End Coordinates */
918
919/* Bit masks for PIXC_BVSTART */
920
921#define B_VSTART 0x3ff /* Vertical Start Coordinates */
922
923/* Bit masks for PIXC_BVEND */
924
925#define B_VEND 0x3ff /* Vertical End Coordinates */
926
927/* Bit masks for PIXC_BTRANSP */
928
929#define B_TRANSP 0xf /* Transparency Value */
930
931/* Bit masks for PIXC_INTRSTAT */
932
933#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
934#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
935#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
936#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
937
938/* Bit masks for PIXC_RYCON */
939
940#define A11 0x3ff /* A11 in the Coefficient Matrix */
941#define A12 0xffc00 /* A12 in the Coefficient Matrix */
942#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
943#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
944
945/* Bit masks for PIXC_GUCON */
946
947#define A21 0x3ff /* A21 in the Coefficient Matrix */
948#define A22 0xffc00 /* A22 in the Coefficient Matrix */
949#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
950#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
951
952/* Bit masks for PIXC_BVCON */
953
954#define A31 0x3ff /* A31 in the Coefficient Matrix */
955#define A32 0xffc00 /* A32 in the Coefficient Matrix */
956#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
957#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
958
959/* Bit masks for PIXC_CCBIAS */
960
961#define A14 0x3ff /* A14 in the Bias Vector */
962#define A24 0xffc00 /* A24 in the Bias Vector */
963#define A34 0x3ff00000 /* A34 in the Bias Vector */
964
965/* Bit masks for PIXC_TC */
966
967#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
968#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
969#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
970
971/* Bit masks for HOST_CONTROL */
972
973#define HOST_EN 0x1 /* Host Enable */
974#define HOST_END 0x2 /* Host Endianess */
975#define DATA_SIZE 0x4 /* Data Size */
976#define HOST_RST 0x8 /* Host Reset */
977#define HRDY_OVR 0x20 /* Host Ready Override */
978#define INT_MODE 0x40 /* Interrupt Mode */
979#define BT_EN 0x80 /* Bus Timeout Enable */
980#define EHW 0x100 /* Enable Host Write */
981#define EHR 0x200 /* Enable Host Read */
982#define BDR 0x400 /* Burst DMA Requests */
983
984/* Bit masks for HOST_STATUS */
985
986#define DMA_READY 0x1 /* DMA Ready */
987#define FIFOFULL 0x2 /* FIFO Full */
988#define FIFOEMPTY 0x4 /* FIFO Empty */
989#define DMA_COMPLETE 0x8 /* DMA Complete */
990#define HSHK 0x10 /* Host Handshake */
991#define HSTIMEOUT 0x20 /* Host Timeout */
992#define HIRQ 0x40 /* Host Interrupt Request */
993#define ALLOW_CNFG 0x80 /* Allow New Configuration */
994#define DMA_DIR 0x100 /* DMA Direction */
995#define BTE 0x200 /* Bus Timeout Enabled */
996
997/* Bit masks for HOST_TIMEOUT */
998
999#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1000
1001/* Bit masks for KPAD_CTL */
1002
1003#define KPAD_EN 0x1 /* Keypad Enable */
1004#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1005#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1006#define KPAD_COLEN 0xe000 /* Column Enable Width */
1007
1008/* Bit masks for KPAD_PRESCALE */
1009
1010#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1011
1012/* Bit masks for KPAD_MSEL */
1013
1014#define DBON_SCALE 0xff /* Debounce Scale Value */
1015#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1016
1017/* Bit masks for KPAD_ROWCOL */
1018
1019#define KPAD_ROW 0xff /* Rows Pressed */
1020#define KPAD_COL 0xff00 /* Columns Pressed */
1021
1022/* Bit masks for KPAD_STAT */
1023
1024#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1025#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1026#define KPAD_PRESSED 0x8 /* Key press current status */
1027
1028/* Bit masks for KPAD_SOFTEVAL */
1029
1030#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1031
1032/* Bit masks for SDH_COMMAND */
1033
1034#define CMD_IDX 0x3f /* Command Index */
1035#define CMD_RSP 0x40 /* Response */
1036#define CMD_L_RSP 0x80 /* Long Response */
1037#define CMD_INT_E 0x100 /* Command Interrupt */
1038#define CMD_PEND_E 0x200 /* Command Pending */
1039#define CMD_E 0x400 /* Command Enable */
1040
1041/* Bit masks for SDH_PWR_CTL */
1042
1043#define PWR_ON 0x3 /* Power On */
1044#if 0
1045#define TBD 0x3c /* TBD */
1046#endif
1047#define SD_CMD_OD 0x40 /* Open Drain Output */
1048#define ROD_CTL 0x80 /* Rod Control */
1049
1050/* Bit masks for SDH_CLK_CTL */
1051
1052#define CLKDIV 0xff /* MC_CLK Divisor */
1053#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1054#define PWR_SV_E 0x200 /* Power Save Enable */
1055#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1056#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1057
1058/* Bit masks for SDH_RESP_CMD */
1059
1060#define RESP_CMD 0x3f /* Response Command */
1061
1062/* Bit masks for SDH_DATA_CTL */
1063
1064#define DTX_E 0x1 /* Data Transfer Enable */
1065#define DTX_DIR 0x2 /* Data Transfer Direction */
1066#define DTX_MODE 0x4 /* Data Transfer Mode */
1067#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1068#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1069
1070/* Bit masks for SDH_STATUS */
1071
1072#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1073#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1074#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1075#define DAT_TIME_OUT 0x8 /* Data Time Out */
1076#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1077#define RX_OVERRUN 0x20 /* Receive Overrun */
1078#define CMD_RESP_END 0x40 /* CMD Response End */
1079#define CMD_SENT 0x80 /* CMD Sent */
1080#define DAT_END 0x100 /* Data End */
1081#define START_BIT_ERR 0x200 /* Start Bit Error */
1082#define DAT_BLK_END 0x400 /* Data Block End */
1083#define CMD_ACT 0x800 /* CMD Active */
1084#define TX_ACT 0x1000 /* Transmit Active */
1085#define RX_ACT 0x2000 /* Receive Active */
1086#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1087#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1088#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1089#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1090#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1091#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1092#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1093#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1094
1095/* Bit masks for SDH_STATUS_CLR */
1096
1097#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1098#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1099#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1100#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1101#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1102#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1103#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1104#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1105#define DAT_END_STAT 0x100 /* Data End Status */
1106#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1107#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1108
1109/* Bit masks for SDH_MASK0 */
1110
1111#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1112#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1113#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1114#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1115#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1116#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1117#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1118#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1119#define DAT_END_MASK 0x100 /* Data End Mask */
1120#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1121#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1122#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1123#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1124#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1125#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1126#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1127#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1128#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1129#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1130#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1131#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1132#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1133
1134/* Bit masks for SDH_FIFO_CNT */
1135
1136#define FIFO_COUNT 0x7fff /* FIFO Count */
1137
1138/* Bit masks for SDH_E_STATUS */
1139
1140#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1141#define SD_CARD_DET 0x10 /* SD Card Detect */
1142
1143/* Bit masks for SDH_E_MASK */
1144
1145#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1146#define SCD_MSK 0x40 /* Mask Card Detect */
1147
1148/* Bit masks for SDH_CFG */
1149
1150#define CLKS_EN 0x1 /* Clocks Enable */
1151#define SD4E 0x4 /* SDIO 4-Bit Enable */
1152#define MWE 0x8 /* Moving Window Enable */
1153#define SD_RST 0x10 /* SDMMC Reset */
1154#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1155#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1156#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1157
1158/* Bit masks for SDH_RD_WAIT_EN */
1159
1160#define RWR 0x1 /* Read Wait Request */
1161
1162/* Bit masks for ATAPI_CONTROL */
1163
1164#define PIO_START 0x1 /* Start PIO/Reg Op */
1165#define MULTI_START 0x2 /* Start Multi-DMA Op */
1166#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1167#define XFER_DIR 0x8 /* Transfer Direction */
1168#define IORDY_EN 0x10 /* IORDY Enable */
1169#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1170#define SOFT_RST 0x40 /* Soft Reset */
1171#define DEV_RST 0x80 /* Device Reset */
1172#define TFRCNT_RST 0x100 /* Trans Count Reset */
1173#define END_ON_TERM 0x200 /* End/Terminate Select */
1174#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1175#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1176
1177/* Bit masks for ATAPI_STATUS */
1178
1179#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1180#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1181#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1182#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1183
1184/* Bit masks for ATAPI_DEV_ADDR */
1185
1186#define DEV_ADDR 0x1f /* Device Address */
1187
1188/* Bit masks for ATAPI_INT_MASK */
1189
1190#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1191#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1192#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1193#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1194#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1195#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1196#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1197#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1198#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1199
1200/* Bit masks for ATAPI_INT_STATUS */
1201
1202#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1203#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1204#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1205#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1206#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1207#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1208#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1209#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1210#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1211
1212/* Bit masks for ATAPI_LINE_STATUS */
1213
1214#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1215#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1216#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1217#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1218#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1219#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1220#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1221#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1222#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1223#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1224
1225/* Bit masks for ATAPI_SM_STATE */
1226
1227#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1228#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1229#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1230#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1231
1232/* Bit masks for ATAPI_TERMINATE */
1233
1234#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1235
1236/* Bit masks for ATAPI_REG_TIM_0 */
1237
1238#define T2_REG 0xff /* End of cycle time for register access transfers */
1239#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1240
1241/* Bit masks for ATAPI_PIO_TIM_0 */
1242
1243#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1244#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1245#define T4_REG 0xf000 /* DIOW data hold */
1246
1247/* Bit masks for ATAPI_PIO_TIM_1 */
1248
1249#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1250
1251/* Bit masks for ATAPI_MULTI_TIM_0 */
1252
1253#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1254#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1255
1256/* Bit masks for ATAPI_MULTI_TIM_1 */
1257
1258#define TKW 0xff /* Selects DIOW negated pulsewidth */
1259#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1260
1261/* Bit masks for ATAPI_MULTI_TIM_2 */
1262
1263#define TH 0xff /* Selects DIOW data hold */
1264#define TEOC 0xff00 /* Selects end of cycle for DMA */
1265
1266/* Bit masks for ATAPI_ULTRA_TIM_0 */
1267
1268#define TACK 0xff /* Selects setup and hold times for TACK */
1269#define TENV 0xff00 /* Selects envelope time */
1270
1271/* Bit masks for ATAPI_ULTRA_TIM_1 */
1272
1273#define TDVS 0xff /* Selects data valid setup time */
1274#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1275
1276/* Bit masks for ATAPI_ULTRA_TIM_2 */
1277
1278#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1279#define TMLI 0xff00 /* Selects interlock time */
1280
1281/* Bit masks for ATAPI_ULTRA_TIM_3 */
1282
1283#define TZAH 0xff /* Selects minimum delay required for output */
1284#define READY_PAUSE 0xff00 /* Selects ready to pause */
1285
1286/* Bit masks for TIMER_ENABLE1 */
1287
1288#define TIMEN8 0x1 /* Timer 8 Enable */
1289#define TIMEN9 0x2 /* Timer 9 Enable */
1290#define TIMEN10 0x4 /* Timer 10 Enable */
1291
1292/* Bit masks for TIMER_DISABLE1 */
1293
1294#define TIMDIS8 0x1 /* Timer 8 Disable */
1295#define TIMDIS9 0x2 /* Timer 9 Disable */
1296#define TIMDIS10 0x4 /* Timer 10 Disable */
1297
1298/* Bit masks for TIMER_STATUS1 */
1299
1300#define TIMIL8 0x1 /* Timer 8 Interrupt */
1301#define TIMIL9 0x2 /* Timer 9 Interrupt */
1302#define TIMIL10 0x4 /* Timer 10 Interrupt */
1303#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1304#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1305#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1306#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1307#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1308#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1309
1310/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1311
1312/* Bit masks for USB_FADDR */
1313
1314#define FUNCTION_ADDRESS 0x7f /* Function address */
1315
1316/* Bit masks for USB_POWER */
1317
1318#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1319#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1320#define RESUME_MODE 0x4 /* DMA Mode */
1321#define RESET 0x8 /* Reset indicator */
1322#define HS_MODE 0x10 /* High Speed mode indicator */
1323#define HS_ENABLE 0x20 /* high Speed Enable */
1324#define SOFT_CONN 0x40 /* Soft connect */
1325#define ISO_UPDATE 0x80 /* Isochronous update */
1326
1327/* Bit masks for USB_INTRTX */
1328
1329#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1330#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1331#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1332#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1333#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1334#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1335#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1336#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1337
1338/* Bit masks for USB_INTRRX */
1339
1340#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1341#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1342#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1343#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1344#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1345#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1346#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1347
1348/* Bit masks for USB_INTRTXE */
1349
1350#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1351#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1352#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1353#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1354#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1355#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1356#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1357#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1358
1359/* Bit masks for USB_INTRRXE */
1360
1361#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1362#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1363#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1364#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1365#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1366#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1367#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1368
1369/* Bit masks for USB_INTRUSB */
1370
1371#define SUSPEND_B 0x1 /* Suspend indicator */
1372#define RESUME_B 0x2 /* Resume indicator */
1373#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1374#define SOF_B 0x8 /* Start of frame */
1375#define CONN_B 0x10 /* Connection indicator */
1376#define DISCON_B 0x20 /* Disconnect indicator */
1377#define SESSION_REQ_B 0x40 /* Session Request */
1378#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1379
1380/* Bit masks for USB_INTRUSBE */
1381
1382#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1383#define RESUME_BE 0x2 /* Resume indicator int enable */
1384#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1385#define SOF_BE 0x8 /* Start of frame int enable */
1386#define CONN_BE 0x10 /* Connection indicator int enable */
1387#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1388#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1389#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1390
1391/* Bit masks for USB_FRAME */
1392
1393#define FRAME_NUMBER 0x7ff /* Frame number */
1394
1395/* Bit masks for USB_INDEX */
1396
1397#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1398
1399/* Bit masks for USB_GLOBAL_CTL */
1400
1401#define GLOBAL_ENA 0x1 /* enables USB module */
1402#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1403#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1404#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1405#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1406#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1407#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1408#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1409#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1410#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1411#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1412#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1413#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1414#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1415#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1416
1417/* Bit masks for USB_OTG_DEV_CTL */
1418
1419#define SESSION 0x1 /* session indicator */
1420#define HOST_REQ 0x2 /* Host negotiation request */
1421#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1422#define VBUS0 0x8 /* Vbus level indicator[0] */
1423#define VBUS1 0x10 /* Vbus level indicator[1] */
1424#define LSDEV 0x20 /* Low-speed indicator */
1425#define FSDEV 0x40 /* Full or High-speed indicator */
1426#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1427
1428/* Bit masks for USB_OTG_VBUS_IRQ */
1429
1430#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1431#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1432#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1433#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1434#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1435#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1436
1437/* Bit masks for USB_OTG_VBUS_MASK */
1438
1439#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1440#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1441#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1442#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1443#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1444#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1445
1446/* Bit masks for USB_CSR0 */
1447
1448#define RXPKTRDY 0x1 /* data packet receive indicator */
1449#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1450#define STALL_SENT 0x4 /* STALL handshake sent */
1451#define DATAEND 0x8 /* Data end indicator */
1452#define SETUPEND 0x10 /* Setup end */
1453#define SENDSTALL 0x20 /* Send STALL handshake */
1454#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1455#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1456#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1457#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1458#define SETUPPKT_H 0x8 /* send Setup token host mode */
1459#define ERROR_H 0x10 /* timeout error indicator host mode */
1460#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1461#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1462#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1463
1464/* Bit masks for USB_COUNT0 */
1465
1466#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1467
1468/* Bit masks for USB_NAKLIMIT0 */
1469
1470#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1471
1472/* Bit masks for USB_TX_MAX_PACKET */
1473
1474#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1475
1476/* Bit masks for USB_RX_MAX_PACKET */
1477
1478#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1479
1480/* Bit masks for USB_TXCSR */
1481
1482#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1483#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1484#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1485#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1486#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1487#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1488#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1489#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1490#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1491#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1492#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1493#define ISO_T 0x4000 /* enable Isochronous transfers */
1494#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1495#define ERROR_TH 0x4 /* error condition host mode */
1496#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1497#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1498
1499/* Bit masks for USB_TXCOUNT */
1500
1501#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1502
1503/* Bit masks for USB_RXCSR */
1504
1505#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1506#define FIFO_FULL_R 0x2 /* FIFO not empty */
1507#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1508#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1509#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1510#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1511#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1512#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1513#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1514#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1515#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1516#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1517#define ISO_R 0x4000 /* enable Isochronous transfers */
1518#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1519#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1520#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1521#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1522#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1523#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1524#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1525
1526/* Bit masks for USB_RXCOUNT */
1527
1528#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1529
1530/* Bit masks for USB_TXTYPE */
1531
1532#define TARGET_EP_NO_T 0xf /* EP number */
1533#define PROTOCOL_T 0xc /* transfer type */
1534
1535/* Bit masks for USB_TXINTERVAL */
1536
1537#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1538
1539/* Bit masks for USB_RXTYPE */
1540
1541#define TARGET_EP_NO_R 0xf /* EP number */
1542#define PROTOCOL_R 0xc /* transfer type */
1543
1544/* Bit masks for USB_RXINTERVAL */
1545
1546#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1547
1548/* Bit masks for USB_DMA_INTERRUPT */
1549
1550#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1551#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1552#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1553#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1554#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1555#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1556#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1557#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1558
1559/* Bit masks for USB_DMAxCONTROL */
1560
1561#define DMA_ENA 0x1 /* DMA enable */
1562#define DIRECTION 0x2 /* direction of DMA transfer */
1563#define MODE 0x4 /* DMA Bus error */
1564#define INT_ENA 0x8 /* Interrupt enable */
1565#define EPNUM 0xf0 /* EP number */
1566#define BUSERROR 0x100 /* DMA Bus error */
1567
1568/* Bit masks for USB_DMAxADDRHIGH */
1569
1570#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1571
1572/* Bit masks for USB_DMAxADDRLOW */
1573
1574#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1575
1576/* Bit masks for USB_DMAxCOUNTHIGH */
1577
1578#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1579
1580/* Bit masks for USB_DMAxCOUNTLOW */
1581
1582#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1583
1584/* Bit masks for HMDMAx_CONTROL */
1585
1586#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1587#define REP 0x2 /* Handshake MDMA Request Polarity */
1588#define UTE 0x8 /* Urgency Threshold Enable */
1589#define OIE 0x10 /* Overflow Interrupt Enable */
1590#define BDIE 0x20 /* Block Done Interrupt Enable */
1591#define MBDI 0x40 /* Mask Block Done Interrupt */
1592#define DRQ 0x300 /* Handshake MDMA Request Type */
1593#define RBC 0x1000 /* Force Reload of BCOUNT */
1594#define PS 0x2000 /* Pin Status */
1595#define OI 0x4000 /* Overflow Interrupt Generated */
1596#define BDI 0x8000 /* Block Done Interrupt Generated */
1597
1598/* ******************************************* */
1599/* MULTI BIT MACRO ENUMERATIONS */
1600/* ******************************************* */
1601
1602
1603#endif /* _DEF_BF548_H */ 404#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index f7f043560c6f..5a04e6d4017e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -10,121 +10,13 @@
10/* Include all Core registers and bit definitions */ 10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h> 11#include <asm/def_LPBlackfin.h>
12 12
13
14/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ 13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
15 14
16/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
17#include "defBF54x_base.h" 16#include "defBF54x_base.h"
18 17
19/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ 18/* The BF549 is like the BF544, but has MXVR */
20 19#include "defBF547.h"
21/* Timer Registers */
22
23#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
24#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
25#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
26#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
27#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
28#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
29#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
30#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
31#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
32#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
33#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
34#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
35
36/* Timer Group of 3 Registers */
37
38#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
39#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
40#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
41
42/* SPORT0 Registers */
43
44#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
45#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
46#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
47#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
48#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
49#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
50#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
51#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
52#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
53#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
54#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
55#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
56#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
57#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
58#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
59#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
60#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
61#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
62#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
63#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
64#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
65#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
66
67/* EPPI0 Registers */
68
69#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
70#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
71#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
72#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
73#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
74#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
75#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
76#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
77#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
78#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
79#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
80#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
81#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
82#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
83
84/* UART2 Registers */
85
86#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
87#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
88#define UART2_GCTL 0xffc02108 /* Global Control Register */
89#define UART2_LCR 0xffc0210c /* Line Control Register */
90#define UART2_MCR 0xffc02110 /* Modem Control Register */
91#define UART2_LSR 0xffc02114 /* Line Status Register */
92#define UART2_MSR 0xffc02118 /* Modem Status Register */
93#define UART2_SCR 0xffc0211c /* Scratch Register */
94#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
95#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
96#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
97
98/* Two Wire Interface Registers (TWI1) */
99
100#define TWI1_REGBASE 0xffc02200
101#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
102#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
103#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
104#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
105#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
106#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
107#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
108#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
109#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
110#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
111#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
112#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
113#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
114#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
115#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
116#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
117
118/* SPI2 Registers */
119
120#define SPI2_REGBASE 0xffc02400
121#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
122#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
123#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
124#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
125#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
126#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
127#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
128 20
129/* MXVR Registers */ 21/* MXVR Registers */
130 22
@@ -296,2418 +188,4 @@
296#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ 188#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
297#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ 189#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
298 190
299/* CAN Controller 1 Config 1 Registers */
300
301#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
302#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
303#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
304#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
305#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
306#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
307#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
308#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
309#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
310#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
311#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
312#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
313#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
314
315/* CAN Controller 1 Config 2 Registers */
316
317#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
318#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
319#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
320#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
321#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
322#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
323#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
324#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
325#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
326#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
327#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
328#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
329#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
330
331/* CAN Controller 1 Clock/Interrupt/Counter Registers */
332
333#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
334#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
335#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
336#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
337#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
338#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
339#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
340#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
341#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
342#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
343#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
344#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
345#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
346#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
347#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
348#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
349
350/* CAN Controller 1 Mailbox Acceptance Registers */
351
352#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
353#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
354#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
355#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
356#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
357#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
358#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
359#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
360#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
361#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
362#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
363#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
364#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
365#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
366#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
367#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
368#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
369#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
370#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
371#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
372#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
373#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
374#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
375#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
376#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
377#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
378#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
379#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
380#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
381#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
382#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
383#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
384
385/* CAN Controller 1 Mailbox Acceptance Registers */
386
387#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
388#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
389#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
390#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
391#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
392#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
393#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
394#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
395#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
396#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
397#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
398#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
399#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
400#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
401#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
402#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
403#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
404#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
405#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
406#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
407#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
408#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
409#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
410#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
411#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
412#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
413#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
414#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
415#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
416#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
417#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
418#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
419
420/* CAN Controller 1 Mailbox Data Registers */
421
422#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
423#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
424#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
425#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
426#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
427#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
428#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
429#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
430#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
431#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
432#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
433#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
434#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
435#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
436#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
437#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
438#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
439#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
440#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
441#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
442#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
443#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
444#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
445#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
446#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
447#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
448#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
449#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
450#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
451#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
452#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
453#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
454#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
455#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
456#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
457#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
458#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
459#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
460#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
461#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
462#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
463#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
464#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
465#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
466#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
467#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
468#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
469#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
470#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
471#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
472#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
473#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
474#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
475#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
476#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
477#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
478#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
479#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
480#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
481#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
482#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
483#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
484#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
485#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
486#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
487#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
488#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
489#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
490#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
491#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
492#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
493#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
494#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
495#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
496#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
497#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
498#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
499#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
500#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
501#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
502#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
503#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
504#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
505#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
506#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
507#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
508#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
509#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
510#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
511#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
512#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
513#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
514#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
515#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
516#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
517#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
518#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
519#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
520#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
521#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
522#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
523#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
524#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
525#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
526#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
527#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
528#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
529#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
530#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
531#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
532#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
533#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
534#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
535#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
536#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
537#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
538#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
539#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
540#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
541#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
542#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
543#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
544#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
545#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
546#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
547#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
548#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
549#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
550
551/* CAN Controller 1 Mailbox Data Registers */
552
553#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
554#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
555#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
556#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
557#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
558#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
559#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
560#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
561#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
562#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
563#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
564#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
565#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
566#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
567#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
568#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
569#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
570#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
571#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
572#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
573#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
574#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
575#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
576#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
577#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
578#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
579#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
580#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
581#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
582#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
583#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
584#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
585#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
586#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
587#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
588#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
589#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
590#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
591#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
592#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
593#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
594#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
595#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
596#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
597#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
598#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
599#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
600#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
601#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
602#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
603#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
604#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
605#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
606#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
607#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
608#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
609#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
610#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
611#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
612#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
613#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
614#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
615#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
616#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
617#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
618#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
619#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
620#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
621#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
622#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
623#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
624#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
625#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
626#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
627#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
628#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
629#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
630#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
631#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
632#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
633#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
634#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
635#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
636#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
637#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
638#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
639#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
640#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
641#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
642#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
643#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
644#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
645#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
646#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
647#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
648#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
649#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
650#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
651#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
652#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
653#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
654#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
655#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
656#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
657#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
658#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
659#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
660#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
661#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
662#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
663#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
664#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
665#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
666#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
667#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
668#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
669#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
670#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
671#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
672#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
673#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
674#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
675#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
676#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
677#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
678#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
679#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
680#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
681
682/* ATAPI Registers */
683
684#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
685#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
686#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
687#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
688#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
689#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
690#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
691#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
692#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
693#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
694#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
695#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
696#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
697#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
698#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
699#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
700#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
701#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
702#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
703#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
704#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
705#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
706#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
707#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
708#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
709
710/* SDH Registers */
711
712#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
713#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
714#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
715#define SDH_COMMAND 0xffc0390c /* SDH Command */
716#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
717#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
718#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
719#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
720#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
721#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
722#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
723#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
724#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
725#define SDH_STATUS 0xffc03934 /* SDH Status */
726#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
727#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
728#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
729#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
730#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
731#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
732#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
733#define SDH_CFG 0xffc039c8 /* SDH Configuration */
734#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
735#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
736#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
737#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
738#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
739#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
740#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
741#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
742#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
743
744/* HOST Port Registers */
745
746#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
747#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
748#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
749
750/* USB Control Registers */
751
752#define USB_FADDR 0xffc03c00 /* Function address register */
753#define USB_POWER 0xffc03c04 /* Power management register */
754#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
755#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
756#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
757#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
758#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
759#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
760#define USB_FRAME 0xffc03c20 /* USB frame number */
761#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
762#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
763#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
764#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
765
766/* USB Packet Control Registers */
767
768#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
769#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
770#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
771#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
772#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
773#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
774#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
775#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
776#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
777#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
778#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
779#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
780#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
781
782/* USB Endpoint FIFO Registers */
783
784#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
785#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
786#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
787#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
788#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
789#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
790#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
791#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
792
793/* USB OTG Control Registers */
794
795#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
796#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
797#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
798
799/* USB Phy Control Registers */
800
801#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
802#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
803#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
804#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
805#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
806
807/* (APHY_CNTRL is for ADI usage only) */
808
809#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
810
811/* (APHY_CALIB is for ADI usage only) */
812
813#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
814#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
815
816/* (PHY_TEST is for ADI usage only) */
817
818#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
819#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
820#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
821
822/* USB Endpoint 0 Control Registers */
823
824#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
825#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
826#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
827#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
828#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
829#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
830#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
831#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
832#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
833
834/* USB Endpoint 1 Control Registers */
835
836#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
837#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
838#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
839#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
840#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
841#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
842#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
843#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
844#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
845#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
846
847/* USB Endpoint 2 Control Registers */
848
849#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
850#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
851#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
852#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
853#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
854#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
855#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
856#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
857#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
858#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
859
860/* USB Endpoint 3 Control Registers */
861
862#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
863#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
864#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
865#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
866#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
867#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
868#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
869#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
870#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
871#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
872
873/* USB Endpoint 4 Control Registers */
874
875#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
876#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
877#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
878#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
879#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
880#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
881#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
882#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
883#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
884#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
885
886/* USB Endpoint 5 Control Registers */
887
888#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
889#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
890#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
891#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
892#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
893#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
894#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
895#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
896#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
897#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
898
899/* USB Endpoint 6 Control Registers */
900
901#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
902#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
903#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
904#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
905#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
906#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
907#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
908#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
909#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
910#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
911
912/* USB Endpoint 7 Control Registers */
913
914#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
915#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
916#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
917#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
918#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
919#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
920#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
921#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
922#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
923#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
924#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
925#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
926
927/* USB Channel 0 Config Registers */
928
929#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
930#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
931#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
932#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
933#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
934
935/* USB Channel 1 Config Registers */
936
937#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
938#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
939#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
940#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
941#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
942
943/* USB Channel 2 Config Registers */
944
945#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
946#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
947#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
948#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
949#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
950
951/* USB Channel 3 Config Registers */
952
953#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
954#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
955#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
956#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
957#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
958
959/* USB Channel 4 Config Registers */
960
961#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
962#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
963#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
964#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
965#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
966
967/* USB Channel 5 Config Registers */
968
969#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
970#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
971#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
972#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
973#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
974
975/* USB Channel 6 Config Registers */
976
977#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
978#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
979#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
980#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
981#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
982
983/* USB Channel 7 Config Registers */
984
985#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
986#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
987#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
988#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
989#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
990
991/* Keypad Registers */
992
993#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
994#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
995#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
996#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
997#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
998#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
999
1000/* Pixel Compositor (PIXC) Registers */
1001
1002#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1003#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
1004#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
1005#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
1006#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
1007#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
1008#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
1009#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
1010#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
1011#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
1012#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
1013#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
1014#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
1015#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
1016#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1017#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1018#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1019#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
1020#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
1021
1022/* Handshake MDMA 0 Registers */
1023
1024#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1025#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1026#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1027#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
1028#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1029#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1030#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
1031
1032/* Handshake MDMA 1 Registers */
1033
1034#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1035#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1036#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1037#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
1038#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1039#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1040#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
1041
1042
1043/* ********************************************************** */
1044/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1045/* and MULTI BIT READ MACROS */
1046/* ********************************************************** */
1047
1048/* Bit masks for PIXC_CTL */
1049
1050#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1051#define OVR_A_EN 0x2 /* Overlay A Enable */
1052#define OVR_B_EN 0x4 /* Overlay B Enable */
1053#define IMG_FORM 0x8 /* Image Data Format */
1054#define OVR_FORM 0x10 /* Overlay Data Format */
1055#define OUT_FORM 0x20 /* Output Data Format */
1056#define UDS_MOD 0x40 /* Resampling Mode */
1057#define TC_EN 0x80 /* Transparent Color Enable */
1058#define IMG_STAT 0x300 /* Image FIFO Status */
1059#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1060#define WM_LVL 0x3000 /* FIFO Watermark Level */
1061
1062/* Bit masks for PIXC_AHSTART */
1063
1064#define A_HSTART 0xfff /* Horizontal Start Coordinates */
1065
1066/* Bit masks for PIXC_AHEND */
1067
1068#define A_HEND 0xfff /* Horizontal End Coordinates */
1069
1070/* Bit masks for PIXC_AVSTART */
1071
1072#define A_VSTART 0x3ff /* Vertical Start Coordinates */
1073
1074/* Bit masks for PIXC_AVEND */
1075
1076#define A_VEND 0x3ff /* Vertical End Coordinates */
1077
1078/* Bit masks for PIXC_ATRANSP */
1079
1080#define A_TRANSP 0xf /* Transparency Value */
1081
1082/* Bit masks for PIXC_BHSTART */
1083
1084#define B_HSTART 0xfff /* Horizontal Start Coordinates */
1085
1086/* Bit masks for PIXC_BHEND */
1087
1088#define B_HEND 0xfff /* Horizontal End Coordinates */
1089
1090/* Bit masks for PIXC_BVSTART */
1091
1092#define B_VSTART 0x3ff /* Vertical Start Coordinates */
1093
1094/* Bit masks for PIXC_BVEND */
1095
1096#define B_VEND 0x3ff /* Vertical End Coordinates */
1097
1098/* Bit masks for PIXC_BTRANSP */
1099
1100#define B_TRANSP 0xf /* Transparency Value */
1101
1102/* Bit masks for PIXC_INTRSTAT */
1103
1104#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1105#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1106#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1107#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1108
1109/* Bit masks for PIXC_RYCON */
1110
1111#define A11 0x3ff /* A11 in the Coefficient Matrix */
1112#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1113#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1114#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1115
1116/* Bit masks for PIXC_GUCON */
1117
1118#define A21 0x3ff /* A21 in the Coefficient Matrix */
1119#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1120#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1121#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1122
1123/* Bit masks for PIXC_BVCON */
1124
1125#define A31 0x3ff /* A31 in the Coefficient Matrix */
1126#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1127#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1128#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1129
1130/* Bit masks for PIXC_CCBIAS */
1131
1132#define A14 0x3ff /* A14 in the Bias Vector */
1133#define A24 0xffc00 /* A24 in the Bias Vector */
1134#define A34 0x3ff00000 /* A34 in the Bias Vector */
1135
1136/* Bit masks for PIXC_TC */
1137
1138#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1139#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1140#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1141
1142/* Bit masks for HOST_CONTROL */
1143
1144#define HOST_EN 0x1 /* Host Enable */
1145#define HOST_END 0x2 /* Host Endianess */
1146#define DATA_SIZE 0x4 /* Data Size */
1147#define HOST_RST 0x8 /* Host Reset */
1148#define HRDY_OVR 0x20 /* Host Ready Override */
1149#define INT_MODE 0x40 /* Interrupt Mode */
1150#define BT_EN 0x80 /* Bus Timeout Enable */
1151#define EHW 0x100 /* Enable Host Write */
1152#define EHR 0x200 /* Enable Host Read */
1153#define BDR 0x400 /* Burst DMA Requests */
1154
1155/* Bit masks for HOST_STATUS */
1156
1157#define DMA_READY 0x1 /* DMA Ready */
1158#define FIFOFULL 0x2 /* FIFO Full */
1159#define FIFOEMPTY 0x4 /* FIFO Empty */
1160#define DMA_COMPLETE 0x8 /* DMA Complete */
1161#define HSHK 0x10 /* Host Handshake */
1162#define TIMEOUT 0x20 /* Host Timeout */
1163#define HIRQ 0x40 /* Host Interrupt Request */
1164#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1165#define DMA_DIR 0x100 /* DMA Direction */
1166#define BTE 0x200 /* Bus Timeout Enabled */
1167
1168/* Bit masks for HOST_TIMEOUT */
1169
1170#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1171
1172/* Bit masks for MXVR_CONFIG */
1173
1174#define MXVREN 0x1 /* MXVR Enable */
1175#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1176#define ACTIVE 0x4 /* Active Mode */
1177#define SDELAY 0x8 /* Synchronous Data Delay */
1178#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1179#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1180#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1181#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1182#define EPARITY 0x100 /* Even Parity Select */
1183#define MSB 0x1e00 /* Master Synchronous Boundary */
1184#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1185#define WAKEUP 0x4000 /* Wake-Up */
1186#define LMECH 0x8000 /* Lock Mechanism Select */
1187
1188/* Bit masks for MXVR_STATE_0 */
1189
1190#define NACT 0x1 /* Network Activity */
1191#define SBLOCK 0x2 /* Super Block Lock */
1192#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1193#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1194#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1195#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1196#define APTX 0x400 /* Asynchronous Packet Transmitting */
1197#define APRX 0x800 /* Receiving Asynchronous Packet */
1198#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1199#define CMARB 0x2000 /* Control Message Arbitrating */
1200#define CMTX 0x4000 /* Control Message Transmitting */
1201#define CMRX 0x8000 /* Receiving Control Message */
1202#define MRXONB 0x10000 /* MRXONB Pin State */
1203#define RGSIP 0x20000 /* Remote Get Source In Progress */
1204#define DALIP 0x40000 /* Resource Deallocate In Progress */
1205#define ALIP 0x80000 /* Resource Allocate In Progress */
1206#define RRDIP 0x100000 /* Remote Read In Progress */
1207#define RWRIP 0x200000 /* Remote Write In Progress */
1208#define FLOCK 0x400000 /* Frame Lock */
1209#define BLOCK 0x800000 /* Block Lock */
1210#define RSB 0xf000000 /* Received Synchronous Boundary */
1211#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1212
1213/* Bit masks for MXVR_STATE_1 */
1214
1215#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1216#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1217#define APCONT 0x100 /* Asynchronous Packet Continuation */
1218#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1219#define DMAACTIVE0 0x10000 /* DMA0 Active */
1220#define DMAACTIVE1 0x20000 /* DMA1 Active */
1221#define DMAACTIVE2 0x40000 /* DMA2 Active */
1222#define DMAACTIVE3 0x80000 /* DMA3 Active */
1223#define DMAACTIVE4 0x100000 /* DMA4 Active */
1224#define DMAACTIVE5 0x200000 /* DMA5 Active */
1225#define DMAACTIVE6 0x400000 /* DMA6 Active */
1226#define DMAACTIVE7 0x800000 /* DMA7 Active */
1227#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1228#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1229#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1230#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1231#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1232#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1233#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1234#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1235
1236/* Bit masks for MXVR_INT_STAT_0 */
1237
1238#define NI2A 0x1 /* Network Inactive to Active */
1239#define NA2I 0x2 /* Network Active to Inactive */
1240#define SBU2L 0x4 /* Super Block Unlock to Lock */
1241#define SBL2U 0x8 /* Super Block Lock to Unlock */
1242#define PRU 0x10 /* Position Register Updated */
1243#define MPRU 0x20 /* Maximum Position Register Updated */
1244#define DRU 0x40 /* Delay Register Updated */
1245#define MDRU 0x80 /* Maximum Delay Register Updated */
1246#define SBU 0x100 /* Synchronous Boundary Updated */
1247#define ATU 0x200 /* Allocation Table Updated */
1248#define FCZ0 0x400 /* Frame Counter 0 Zero */
1249#define FCZ1 0x800 /* Frame Counter 1 Zero */
1250#define PERR 0x1000 /* Parity Error */
1251#define MH2L 0x2000 /* MRXONB High to Low */
1252#define ML2H 0x4000 /* MRXONB Low to High */
1253#define WUP 0x8000 /* Wake-Up Preamble Received */
1254#define FU2L 0x10000 /* Frame Unlock to Lock */
1255#define FL2U 0x20000 /* Frame Lock to Unlock */
1256#define BU2L 0x40000 /* Block Unlock to Lock */
1257#define BL2U 0x80000 /* Block Lock to Unlock */
1258#define OBERR 0x100000 /* DMA Out of Bounds Error */
1259#define PFL 0x200000 /* PLL Frequency Locked */
1260#define SCZ 0x400000 /* System Clock Counter Zero */
1261#define FERR 0x800000 /* FIFO Error */
1262#define CMR 0x1000000 /* Control Message Received */
1263#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1264#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1265#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1266#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1267#define BCZ 0x20000000 /* Block Counter Zero */
1268#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1269#define DERR 0x80000000 /* DMA Error */
1270
1271/* Bit masks for MXVR_INT_STAT_1 */
1272
1273#define HDONE0 0x1 /* DMA0 Half Done */
1274#define DONE0 0x2 /* DMA0 Done */
1275#define APR 0x4 /* Asynchronous Packet Received */
1276#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1277#define HDONE1 0x10 /* DMA1 Half Done */
1278#define DONE1 0x20 /* DMA1 Done */
1279#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1280#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1281#define HDONE2 0x100 /* DMA2 Half Done */
1282#define DONE2 0x200 /* DMA2 Done */
1283#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1284#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1285#define HDONE3 0x1000 /* DMA3 Half Done */
1286#define DONE3 0x2000 /* DMA3 Done */
1287#define HDONE4 0x10000 /* DMA4 Half Done */
1288#define DONE4 0x20000 /* DMA4 Done */
1289#define HDONE5 0x100000 /* DMA5 Half Done */
1290#define DONE5 0x200000 /* DMA5 Done */
1291#define HDONE6 0x1000000 /* DMA6 Half Done */
1292#define DONE6 0x2000000 /* DMA6 Done */
1293#define HDONE7 0x10000000 /* DMA7 Half Done */
1294#define DONE7 0x20000000 /* DMA7 Done */
1295
1296/* Bit masks for MXVR_INT_EN_0 */
1297
1298#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1299#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1300#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1301#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1302#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1303#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1304#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1305#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1306#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1307#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1308#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1309#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1310#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1311#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1312#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1313#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1314#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1315#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1316#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1317#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1318#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1319#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1320#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1321#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1322#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1323#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1324#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1325#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1326#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1327#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1328#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1329#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1330
1331/* Bit masks for MXVR_INT_EN_1 */
1332
1333#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1334#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1335#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1336#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1337#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1338#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1339#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1340#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1341#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1342#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1343#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1344#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1345#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1346#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1347#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1348#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1349#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1350#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1351#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1352#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1353#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1354#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1355
1356/* Bit masks for MXVR_POSITION */
1357
1358#define POSITION 0x3f /* Node Position */
1359#define PVALID 0x8000 /* Node Position Valid */
1360
1361/* Bit masks for MXVR_MAX_POSITION */
1362
1363#define MPOSITION 0x3f /* Maximum Node Position */
1364#define MPVALID 0x8000 /* Maximum Node Position Valid */
1365
1366/* Bit masks for MXVR_DELAY */
1367
1368#define DELAY 0x3f /* Node Frame Delay */
1369#define DVALID 0x8000 /* Node Frame Delay Valid */
1370
1371/* Bit masks for MXVR_MAX_DELAY */
1372
1373#define MDELAY 0x3f /* Maximum Node Frame Delay */
1374#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1375
1376/* Bit masks for MXVR_LADDR */
1377
1378#define LADDR 0xffff /* Logical Address */
1379#define LVALID 0x80000000 /* Logical Address Valid */
1380
1381/* Bit masks for MXVR_GADDR */
1382
1383#define GADDRL 0xff /* Group Address Lower Byte */
1384#define GVALID 0x8000 /* Group Address Valid */
1385
1386/* Bit masks for MXVR_AADDR */
1387
1388#define AADDR 0xffff /* Alternate Address */
1389#define AVALID 0x80000000 /* Alternate Address Valid */
1390
1391/* Bit masks for MXVR_ALLOC_0 */
1392
1393#define CL0 0x7f /* Channel 0 Connection Label */
1394#define CIU0 0x80 /* Channel 0 In Use */
1395#define CL1 0x7f00 /* Channel 0 Connection Label */
1396#define CIU1 0x8000 /* Channel 0 In Use */
1397#define CL2 0x7f0000 /* Channel 0 Connection Label */
1398#define CIU2 0x800000 /* Channel 0 In Use */
1399#define CL3 0x7f000000 /* Channel 0 Connection Label */
1400#define CIU3 0x80000000 /* Channel 0 In Use */
1401
1402/* Bit masks for MXVR_ALLOC_1 */
1403
1404#define CL4 0x7f /* Channel 4 Connection Label */
1405#define CIU4 0x80 /* Channel 4 In Use */
1406#define CL5 0x7f00 /* Channel 5 Connection Label */
1407#define CIU5 0x8000 /* Channel 5 In Use */
1408#define CL6 0x7f0000 /* Channel 6 Connection Label */
1409#define CIU6 0x800000 /* Channel 6 In Use */
1410#define CL7 0x7f000000 /* Channel 7 Connection Label */
1411#define CIU7 0x80000000 /* Channel 7 In Use */
1412
1413/* Bit masks for MXVR_ALLOC_2 */
1414
1415#define CL8 0x7f /* Channel 8 Connection Label */
1416#define CIU8 0x80 /* Channel 8 In Use */
1417#define CL9 0x7f00 /* Channel 9 Connection Label */
1418#define CIU9 0x8000 /* Channel 9 In Use */
1419#define CL10 0x7f0000 /* Channel 10 Connection Label */
1420#define CIU10 0x800000 /* Channel 10 In Use */
1421#define CL11 0x7f000000 /* Channel 11 Connection Label */
1422#define CIU11 0x80000000 /* Channel 11 In Use */
1423
1424/* Bit masks for MXVR_ALLOC_3 */
1425
1426#define CL12 0x7f /* Channel 12 Connection Label */
1427#define CIU12 0x80 /* Channel 12 In Use */
1428#define CL13 0x7f00 /* Channel 13 Connection Label */
1429#define CIU13 0x8000 /* Channel 13 In Use */
1430#define CL14 0x7f0000 /* Channel 14 Connection Label */
1431#define CIU14 0x800000 /* Channel 14 In Use */
1432#define CL15 0x7f000000 /* Channel 15 Connection Label */
1433#define CIU15 0x80000000 /* Channel 15 In Use */
1434
1435/* Bit masks for MXVR_ALLOC_4 */
1436
1437#define CL16 0x7f /* Channel 16 Connection Label */
1438#define CIU16 0x80 /* Channel 16 In Use */
1439#define CL17 0x7f00 /* Channel 17 Connection Label */
1440#define CIU17 0x8000 /* Channel 17 In Use */
1441#define CL18 0x7f0000 /* Channel 18 Connection Label */
1442#define CIU18 0x800000 /* Channel 18 In Use */
1443#define CL19 0x7f000000 /* Channel 19 Connection Label */
1444#define CIU19 0x80000000 /* Channel 19 In Use */
1445
1446/* Bit masks for MXVR_ALLOC_5 */
1447
1448#define CL20 0x7f /* Channel 20 Connection Label */
1449#define CIU20 0x80 /* Channel 20 In Use */
1450#define CL21 0x7f00 /* Channel 21 Connection Label */
1451#define CIU21 0x8000 /* Channel 21 In Use */
1452#define CL22 0x7f0000 /* Channel 22 Connection Label */
1453#define CIU22 0x800000 /* Channel 22 In Use */
1454#define CL23 0x7f000000 /* Channel 23 Connection Label */
1455#define CIU23 0x80000000 /* Channel 23 In Use */
1456
1457/* Bit masks for MXVR_ALLOC_6 */
1458
1459#define CL24 0x7f /* Channel 24 Connection Label */
1460#define CIU24 0x80 /* Channel 24 In Use */
1461#define CL25 0x7f00 /* Channel 25 Connection Label */
1462#define CIU25 0x8000 /* Channel 25 In Use */
1463#define CL26 0x7f0000 /* Channel 26 Connection Label */
1464#define CIU26 0x800000 /* Channel 26 In Use */
1465#define CL27 0x7f000000 /* Channel 27 Connection Label */
1466#define CIU27 0x80000000 /* Channel 27 In Use */
1467
1468/* Bit masks for MXVR_ALLOC_7 */
1469
1470#define CL28 0x7f /* Channel 28 Connection Label */
1471#define CIU28 0x80 /* Channel 28 In Use */
1472#define CL29 0x7f00 /* Channel 29 Connection Label */
1473#define CIU29 0x8000 /* Channel 29 In Use */
1474#define CL30 0x7f0000 /* Channel 30 Connection Label */
1475#define CIU30 0x800000 /* Channel 30 In Use */
1476#define CL31 0x7f000000 /* Channel 31 Connection Label */
1477#define CIU31 0x80000000 /* Channel 31 In Use */
1478
1479/* Bit masks for MXVR_ALLOC_8 */
1480
1481#define CL32 0x7f /* Channel 32 Connection Label */
1482#define CIU32 0x80 /* Channel 32 In Use */
1483#define CL33 0x7f00 /* Channel 33 Connection Label */
1484#define CIU33 0x8000 /* Channel 33 In Use */
1485#define CL34 0x7f0000 /* Channel 34 Connection Label */
1486#define CIU34 0x800000 /* Channel 34 In Use */
1487#define CL35 0x7f000000 /* Channel 35 Connection Label */
1488#define CIU35 0x80000000 /* Channel 35 In Use */
1489
1490/* Bit masks for MXVR_ALLOC_9 */
1491
1492#define CL36 0x7f /* Channel 36 Connection Label */
1493#define CIU36 0x80 /* Channel 36 In Use */
1494#define CL37 0x7f00 /* Channel 37 Connection Label */
1495#define CIU37 0x8000 /* Channel 37 In Use */
1496#define CL38 0x7f0000 /* Channel 38 Connection Label */
1497#define CIU38 0x800000 /* Channel 38 In Use */
1498#define CL39 0x7f000000 /* Channel 39 Connection Label */
1499#define CIU39 0x80000000 /* Channel 39 In Use */
1500
1501/* Bit masks for MXVR_ALLOC_10 */
1502
1503#define CL40 0x7f /* Channel 40 Connection Label */
1504#define CIU40 0x80 /* Channel 40 In Use */
1505#define CL41 0x7f00 /* Channel 41 Connection Label */
1506#define CIU41 0x8000 /* Channel 41 In Use */
1507#define CL42 0x7f0000 /* Channel 42 Connection Label */
1508#define CIU42 0x800000 /* Channel 42 In Use */
1509#define CL43 0x7f000000 /* Channel 43 Connection Label */
1510#define CIU43 0x80000000 /* Channel 43 In Use */
1511
1512/* Bit masks for MXVR_ALLOC_11 */
1513
1514#define CL44 0x7f /* Channel 44 Connection Label */
1515#define CIU44 0x80 /* Channel 44 In Use */
1516#define CL45 0x7f00 /* Channel 45 Connection Label */
1517#define CIU45 0x8000 /* Channel 45 In Use */
1518#define CL46 0x7f0000 /* Channel 46 Connection Label */
1519#define CIU46 0x800000 /* Channel 46 In Use */
1520#define CL47 0x7f000000 /* Channel 47 Connection Label */
1521#define CIU47 0x80000000 /* Channel 47 In Use */
1522
1523/* Bit masks for MXVR_ALLOC_12 */
1524
1525#define CL48 0x7f /* Channel 48 Connection Label */
1526#define CIU48 0x80 /* Channel 48 In Use */
1527#define CL49 0x7f00 /* Channel 49 Connection Label */
1528#define CIU49 0x8000 /* Channel 49 In Use */
1529#define CL50 0x7f0000 /* Channel 50 Connection Label */
1530#define CIU50 0x800000 /* Channel 50 In Use */
1531#define CL51 0x7f000000 /* Channel 51 Connection Label */
1532#define CIU51 0x80000000 /* Channel 51 In Use */
1533
1534/* Bit masks for MXVR_ALLOC_13 */
1535
1536#define CL52 0x7f /* Channel 52 Connection Label */
1537#define CIU52 0x80 /* Channel 52 In Use */
1538#define CL53 0x7f00 /* Channel 53 Connection Label */
1539#define CIU53 0x8000 /* Channel 53 In Use */
1540#define CL54 0x7f0000 /* Channel 54 Connection Label */
1541#define CIU54 0x800000 /* Channel 54 In Use */
1542#define CL55 0x7f000000 /* Channel 55 Connection Label */
1543#define CIU55 0x80000000 /* Channel 55 In Use */
1544
1545/* Bit masks for MXVR_ALLOC_14 */
1546
1547#define CL56 0x7f /* Channel 56 Connection Label */
1548#define CIU56 0x80 /* Channel 56 In Use */
1549#define CL57 0x7f00 /* Channel 57 Connection Label */
1550#define CIU57 0x8000 /* Channel 57 In Use */
1551#define CL58 0x7f0000 /* Channel 58 Connection Label */
1552#define CIU58 0x800000 /* Channel 58 In Use */
1553#define CL59 0x7f000000 /* Channel 59 Connection Label */
1554#define CIU59 0x80000000 /* Channel 59 In Use */
1555
1556/* MXVR_SYNC_LCHAN_0 Masks */
1557
1558#define LCHANPC0 0x0000000Flu
1559#define LCHANPC1 0x000000F0lu
1560#define LCHANPC2 0x00000F00lu
1561#define LCHANPC3 0x0000F000lu
1562#define LCHANPC4 0x000F0000lu
1563#define LCHANPC5 0x00F00000lu
1564#define LCHANPC6 0x0F000000lu
1565#define LCHANPC7 0xF0000000lu
1566
1567
1568/* MXVR_SYNC_LCHAN_1 Masks */
1569
1570#define LCHANPC8 0x0000000Flu
1571#define LCHANPC9 0x000000F0lu
1572#define LCHANPC10 0x00000F00lu
1573#define LCHANPC11 0x0000F000lu
1574#define LCHANPC12 0x000F0000lu
1575#define LCHANPC13 0x00F00000lu
1576#define LCHANPC14 0x0F000000lu
1577#define LCHANPC15 0xF0000000lu
1578
1579
1580/* MXVR_SYNC_LCHAN_2 Masks */
1581
1582#define LCHANPC16 0x0000000Flu
1583#define LCHANPC17 0x000000F0lu
1584#define LCHANPC18 0x00000F00lu
1585#define LCHANPC19 0x0000F000lu
1586#define LCHANPC20 0x000F0000lu
1587#define LCHANPC21 0x00F00000lu
1588#define LCHANPC22 0x0F000000lu
1589#define LCHANPC23 0xF0000000lu
1590
1591
1592/* MXVR_SYNC_LCHAN_3 Masks */
1593
1594#define LCHANPC24 0x0000000Flu
1595#define LCHANPC25 0x000000F0lu
1596#define LCHANPC26 0x00000F00lu
1597#define LCHANPC27 0x0000F000lu
1598#define LCHANPC28 0x000F0000lu
1599#define LCHANPC29 0x00F00000lu
1600#define LCHANPC30 0x0F000000lu
1601#define LCHANPC31 0xF0000000lu
1602
1603
1604/* MXVR_SYNC_LCHAN_4 Masks */
1605
1606#define LCHANPC32 0x0000000Flu
1607#define LCHANPC33 0x000000F0lu
1608#define LCHANPC34 0x00000F00lu
1609#define LCHANPC35 0x0000F000lu
1610#define LCHANPC36 0x000F0000lu
1611#define LCHANPC37 0x00F00000lu
1612#define LCHANPC38 0x0F000000lu
1613#define LCHANPC39 0xF0000000lu
1614
1615
1616/* MXVR_SYNC_LCHAN_5 Masks */
1617
1618#define LCHANPC40 0x0000000Flu
1619#define LCHANPC41 0x000000F0lu
1620#define LCHANPC42 0x00000F00lu
1621#define LCHANPC43 0x0000F000lu
1622#define LCHANPC44 0x000F0000lu
1623#define LCHANPC45 0x00F00000lu
1624#define LCHANPC46 0x0F000000lu
1625#define LCHANPC47 0xF0000000lu
1626
1627
1628/* MXVR_SYNC_LCHAN_6 Masks */
1629
1630#define LCHANPC48 0x0000000Flu
1631#define LCHANPC49 0x000000F0lu
1632#define LCHANPC50 0x00000F00lu
1633#define LCHANPC51 0x0000F000lu
1634#define LCHANPC52 0x000F0000lu
1635#define LCHANPC53 0x00F00000lu
1636#define LCHANPC54 0x0F000000lu
1637#define LCHANPC55 0xF0000000lu
1638
1639
1640/* MXVR_SYNC_LCHAN_7 Masks */
1641
1642#define LCHANPC56 0x0000000Flu
1643#define LCHANPC57 0x000000F0lu
1644#define LCHANPC58 0x00000F00lu
1645#define LCHANPC59 0x0000F000lu
1646
1647/* Bit masks for MXVR_DMAx_CONFIG */
1648
1649#define MDMAEN 0x1 /* DMA Channel Enable */
1650#define DMADD 0x2 /* DMA Channel Direction */
1651#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1652#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1653#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1654#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1655#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1656#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1657#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1658#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1659#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
1660
1661/* Bit masks for MXVR_AP_CTL */
1662
1663#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1664#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1665#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1666#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1667#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1668
1669/* Bit masks for MXVR_APRB_START_ADDR */
1670
1671#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1672
1673/* Bit masks for MXVR_APRB_CURR_ADDR */
1674
1675#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1676
1677/* Bit masks for MXVR_APTB_START_ADDR */
1678
1679#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1680
1681/* Bit masks for MXVR_APTB_CURR_ADDR */
1682
1683#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1684
1685/* Bit masks for MXVR_CM_CTL */
1686
1687#define STARTCM 0x1 /* Start Control Message Transmission */
1688#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1689#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1690#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1691#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1692#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1693#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1694#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1695#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1696#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1697#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1698#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
1699#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
1700#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
1701#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
1702#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
1703#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
1704#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
1705
1706/* Bit masks for MXVR_CMRB_START_ADDR */
1707
1708#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
1709
1710/* Bit masks for MXVR_CMRB_CURR_ADDR */
1711
1712#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
1713
1714/* Bit masks for MXVR_CMTB_START_ADDR */
1715
1716#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
1717
1718/* Bit masks for MXVR_CMTB_CURR_ADDR */
1719
1720#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
1721
1722/* Bit masks for MXVR_RRDB_START_ADDR */
1723
1724#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
1725
1726/* Bit masks for MXVR_RRDB_CURR_ADDR */
1727
1728#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
1729
1730/* Bit masks for MXVR_PAT_DATAx */
1731
1732#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */
1733#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */
1734#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */
1735#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */
1736
1737/* Bit masks for MXVR_PAT_EN_0 */
1738
1739#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1740#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1741#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1742#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1743#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1744#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1745#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1746#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1747#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1748#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1749#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1750#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1751#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1752#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1753#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1754#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1755#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1756#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1757#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1758#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1759#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1760#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1761#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1762#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1763#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1764#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1765#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1766#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1767#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1768#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1769#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1770#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1771
1772/* Bit masks for MXVR_PAT_EN_1 */
1773
1774#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1775#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1776#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1777#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1778#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1779#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1780#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1781#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1782#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1783#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1784#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1785#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1786#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1787#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1788#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1789#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1790#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1791#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1792#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1793#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1794#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1795#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1796#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1797#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1798#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1799#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1800#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1801#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1802#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1803#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1804#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1805#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1806
1807/* Bit masks for MXVR_FRAME_CNT_0 */
1808
1809#define FCNT 0xffff /* Frame Count */
1810
1811/* Bit masks for MXVR_FRAME_CNT_1 */
1812
1813#define FCNT 0xffff /* Frame Count */
1814
1815/* Bit masks for MXVR_ROUTING_0 */
1816
1817#define TX_CH0 0x3f /* Transmit Channel 0 */
1818#define MUTE_CH0 0x80 /* Mute Channel 0 */
1819#define TX_CH1 0x3f00 /* Transmit Channel 0 */
1820#define MUTE_CH1 0x8000 /* Mute Channel 0 */
1821#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
1822#define MUTE_CH2 0x800000 /* Mute Channel 0 */
1823#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
1824#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
1825
1826/* Bit masks for MXVR_ROUTING_1 */
1827
1828#define TX_CH4 0x3f /* Transmit Channel 4 */
1829#define MUTE_CH4 0x80 /* Mute Channel 4 */
1830#define TX_CH5 0x3f00 /* Transmit Channel 5 */
1831#define MUTE_CH5 0x8000 /* Mute Channel 5 */
1832#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
1833#define MUTE_CH6 0x800000 /* Mute Channel 6 */
1834#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
1835#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
1836
1837/* Bit masks for MXVR_ROUTING_2 */
1838
1839#define TX_CH8 0x3f /* Transmit Channel 8 */
1840#define MUTE_CH8 0x80 /* Mute Channel 8 */
1841#define TX_CH9 0x3f00 /* Transmit Channel 9 */
1842#define MUTE_CH9 0x8000 /* Mute Channel 9 */
1843#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
1844#define MUTE_CH10 0x800000 /* Mute Channel 10 */
1845#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
1846#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
1847
1848/* Bit masks for MXVR_ROUTING_3 */
1849
1850#define TX_CH12 0x3f /* Transmit Channel 12 */
1851#define MUTE_CH12 0x80 /* Mute Channel 12 */
1852#define TX_CH13 0x3f00 /* Transmit Channel 13 */
1853#define MUTE_CH13 0x8000 /* Mute Channel 13 */
1854#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
1855#define MUTE_CH14 0x800000 /* Mute Channel 14 */
1856#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
1857#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
1858
1859/* Bit masks for MXVR_ROUTING_4 */
1860
1861#define TX_CH16 0x3f /* Transmit Channel 16 */
1862#define MUTE_CH16 0x80 /* Mute Channel 16 */
1863#define TX_CH17 0x3f00 /* Transmit Channel 17 */
1864#define MUTE_CH17 0x8000 /* Mute Channel 17 */
1865#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
1866#define MUTE_CH18 0x800000 /* Mute Channel 18 */
1867#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
1868#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
1869
1870/* Bit masks for MXVR_ROUTING_5 */
1871
1872#define TX_CH20 0x3f /* Transmit Channel 20 */
1873#define MUTE_CH20 0x80 /* Mute Channel 20 */
1874#define TX_CH21 0x3f00 /* Transmit Channel 21 */
1875#define MUTE_CH21 0x8000 /* Mute Channel 21 */
1876#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
1877#define MUTE_CH22 0x800000 /* Mute Channel 22 */
1878#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
1879#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
1880
1881/* Bit masks for MXVR_ROUTING_6 */
1882
1883#define TX_CH24 0x3f /* Transmit Channel 24 */
1884#define MUTE_CH24 0x80 /* Mute Channel 24 */
1885#define TX_CH25 0x3f00 /* Transmit Channel 25 */
1886#define MUTE_CH25 0x8000 /* Mute Channel 25 */
1887#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
1888#define MUTE_CH26 0x800000 /* Mute Channel 26 */
1889#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
1890#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
1891
1892/* Bit masks for MXVR_ROUTING_7 */
1893
1894#define TX_CH28 0x3f /* Transmit Channel 28 */
1895#define MUTE_CH28 0x80 /* Mute Channel 28 */
1896#define TX_CH29 0x3f00 /* Transmit Channel 29 */
1897#define MUTE_CH29 0x8000 /* Mute Channel 29 */
1898#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
1899#define MUTE_CH30 0x800000 /* Mute Channel 30 */
1900#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
1901#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
1902
1903/* Bit masks for MXVR_ROUTING_8 */
1904
1905#define TX_CH32 0x3f /* Transmit Channel 32 */
1906#define MUTE_CH32 0x80 /* Mute Channel 32 */
1907#define TX_CH33 0x3f00 /* Transmit Channel 33 */
1908#define MUTE_CH33 0x8000 /* Mute Channel 33 */
1909#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
1910#define MUTE_CH34 0x800000 /* Mute Channel 34 */
1911#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
1912#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
1913
1914/* Bit masks for MXVR_ROUTING_9 */
1915
1916#define TX_CH36 0x3f /* Transmit Channel 36 */
1917#define MUTE_CH36 0x80 /* Mute Channel 36 */
1918#define TX_CH37 0x3f00 /* Transmit Channel 37 */
1919#define MUTE_CH37 0x8000 /* Mute Channel 37 */
1920#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
1921#define MUTE_CH38 0x800000 /* Mute Channel 38 */
1922#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
1923#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
1924
1925/* Bit masks for MXVR_ROUTING_10 */
1926
1927#define TX_CH40 0x3f /* Transmit Channel 40 */
1928#define MUTE_CH40 0x80 /* Mute Channel 40 */
1929#define TX_CH41 0x3f00 /* Transmit Channel 41 */
1930#define MUTE_CH41 0x8000 /* Mute Channel 41 */
1931#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
1932#define MUTE_CH42 0x800000 /* Mute Channel 42 */
1933#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
1934#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
1935
1936/* Bit masks for MXVR_ROUTING_11 */
1937
1938#define TX_CH44 0x3f /* Transmit Channel 44 */
1939#define MUTE_CH44 0x80 /* Mute Channel 44 */
1940#define TX_CH45 0x3f00 /* Transmit Channel 45 */
1941#define MUTE_CH45 0x8000 /* Mute Channel 45 */
1942#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
1943#define MUTE_CH46 0x800000 /* Mute Channel 46 */
1944#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
1945#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
1946
1947/* Bit masks for MXVR_ROUTING_12 */
1948
1949#define TX_CH48 0x3f /* Transmit Channel 48 */
1950#define MUTE_CH48 0x80 /* Mute Channel 48 */
1951#define TX_CH49 0x3f00 /* Transmit Channel 49 */
1952#define MUTE_CH49 0x8000 /* Mute Channel 49 */
1953#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
1954#define MUTE_CH50 0x800000 /* Mute Channel 50 */
1955#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
1956#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
1957
1958/* Bit masks for MXVR_ROUTING_13 */
1959
1960#define TX_CH52 0x3f /* Transmit Channel 52 */
1961#define MUTE_CH52 0x80 /* Mute Channel 52 */
1962#define TX_CH53 0x3f00 /* Transmit Channel 53 */
1963#define MUTE_CH53 0x8000 /* Mute Channel 53 */
1964#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
1965#define MUTE_CH54 0x800000 /* Mute Channel 54 */
1966#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
1967#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
1968
1969/* Bit masks for MXVR_ROUTING_14 */
1970
1971#define TX_CH56 0x3f /* Transmit Channel 56 */
1972#define MUTE_CH56 0x80 /* Mute Channel 56 */
1973#define TX_CH57 0x3f00 /* Transmit Channel 57 */
1974#define MUTE_CH57 0x8000 /* Mute Channel 57 */
1975#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
1976#define MUTE_CH58 0x800000 /* Mute Channel 58 */
1977#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
1978#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
1979
1980/* Bit masks for MXVR_BLOCK_CNT */
1981
1982#define BCNT 0xffff /* Block Count */
1983
1984/* Bit masks for MXVR_CLK_CTL */
1985
1986#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
1987#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
1988#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
1989#define CLKX3SEL 0x80 /* Clock Generation Source Select */
1990#define MMCLKEN 0x100 /* Master Clock Enable */
1991#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
1992#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
1993#define MBCLKEN 0x10000 /* Bit Clock Enable */
1994#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
1995#define INVRX 0x800000 /* Invert Receive Data */
1996#define MFSEN 0x1000000 /* Frame Sync Enable */
1997#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
1998#define MFSSEL 0x60000000 /* Frame Sync Select */
1999#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2000
2001/* Bit masks for MXVR_CDRPLL_CTL */
2002
2003#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2004#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2005#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2006#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2007#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2008#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2009#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2010#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2011#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2012
2013/* Bit masks for MXVR_FMPLL_CTL */
2014
2015#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2016#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2017#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2018#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2019#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2020#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
2021
2022/* Bit masks for MXVR_PIN_CTL */
2023
2024#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2025#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2026#define MFSOE 0x10 /* MFS Output Enable */
2027#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2028#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2029
2030/* Bit masks for MXVR_SCLK_CNT */
2031
2032#define SCNT 0xffff /* System Clock Count */
2033
2034/* Bit masks for KPAD_CTL */
2035
2036#define KPAD_EN 0x1 /* Keypad Enable */
2037#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2038#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2039#define KPAD_COLEN 0xe000 /* Column Enable Width */
2040
2041/* Bit masks for KPAD_PRESCALE */
2042
2043#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
2044
2045/* Bit masks for KPAD_MSEL */
2046
2047#define DBON_SCALE 0xff /* Debounce Scale Value */
2048#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
2049
2050/* Bit masks for KPAD_ROWCOL */
2051
2052#define KPAD_ROW 0xff /* Rows Pressed */
2053#define KPAD_COL 0xff00 /* Columns Pressed */
2054
2055/* Bit masks for KPAD_STAT */
2056
2057#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2058#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2059#define KPAD_PRESSED 0x8 /* Key press current status */
2060
2061/* Bit masks for KPAD_SOFTEVAL */
2062
2063#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2064
2065/* Bit masks for SDH_COMMAND */
2066
2067#define CMD_IDX 0x3f /* Command Index */
2068#define CMD_RSP 0x40 /* Response */
2069#define CMD_L_RSP 0x80 /* Long Response */
2070#define CMD_INT_E 0x100 /* Command Interrupt */
2071#define CMD_PEND_E 0x200 /* Command Pending */
2072#define CMD_E 0x400 /* Command Enable */
2073
2074/* Bit masks for SDH_PWR_CTL */
2075
2076#define PWR_ON 0x3 /* Power On */
2077#if 0
2078#define TBD 0x3c /* TBD */
2079#endif
2080#define SD_CMD_OD 0x40 /* Open Drain Output */
2081#define ROD_CTL 0x80 /* Rod Control */
2082
2083/* Bit masks for SDH_CLK_CTL */
2084
2085#define CLKDIV 0xff /* MC_CLK Divisor */
2086#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2087#define PWR_SV_E 0x200 /* Power Save Enable */
2088#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2089#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2090
2091/* Bit masks for SDH_RESP_CMD */
2092
2093#define RESP_CMD 0x3f /* Response Command */
2094
2095/* Bit masks for SDH_DATA_CTL */
2096
2097#define DTX_E 0x1 /* Data Transfer Enable */
2098#define DTX_DIR 0x2 /* Data Transfer Direction */
2099#define DTX_MODE 0x4 /* Data Transfer Mode */
2100#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2101#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2102
2103/* Bit masks for SDH_STATUS */
2104
2105#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2106#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2107#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2108#define DAT_TIME_OUT 0x8 /* Data Time Out */
2109#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2110#define RX_OVERRUN 0x20 /* Receive Overrun */
2111#define CMD_RESP_END 0x40 /* CMD Response End */
2112#define CMD_SENT 0x80 /* CMD Sent */
2113#define DAT_END 0x100 /* Data End */
2114#define START_BIT_ERR 0x200 /* Start Bit Error */
2115#define DAT_BLK_END 0x400 /* Data Block End */
2116#define CMD_ACT 0x800 /* CMD Active */
2117#define TX_ACT 0x1000 /* Transmit Active */
2118#define RX_ACT 0x2000 /* Receive Active */
2119#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2120#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2121#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2122#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2123#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2124#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2125#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2126#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2127
2128/* Bit masks for SDH_STATUS_CLR */
2129
2130#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2131#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2132#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2133#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2134#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2135#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2136#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2137#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2138#define DAT_END_STAT 0x100 /* Data End Status */
2139#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2140#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2141
2142/* Bit masks for SDH_MASK0 */
2143
2144#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2145#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2146#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2147#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2148#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2149#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2150#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2151#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2152#define DAT_END_MASK 0x100 /* Data End Mask */
2153#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2154#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2155#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2156#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2157#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2158#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2159#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2160#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2161#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2162#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2163#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2164#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2165#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2166
2167/* Bit masks for SDH_FIFO_CNT */
2168
2169#define FIFO_COUNT 0x7fff /* FIFO Count */
2170
2171/* Bit masks for SDH_E_STATUS */
2172
2173#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2174#define SD_CARD_DET 0x10 /* SD Card Detect */
2175
2176/* Bit masks for SDH_E_MASK */
2177
2178#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2179#define SCD_MSK 0x40 /* Mask Card Detect */
2180
2181/* Bit masks for SDH_CFG */
2182
2183#define CLKS_EN 0x1 /* Clocks Enable */
2184#define SD4E 0x4 /* SDIO 4-Bit Enable */
2185#define MWE 0x8 /* Moving Window Enable */
2186#define SD_RST 0x10 /* SDMMC Reset */
2187#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2188#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2189#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2190
2191/* Bit masks for SDH_RD_WAIT_EN */
2192
2193#define RWR 0x1 /* Read Wait Request */
2194
2195/* Bit masks for ATAPI_CONTROL */
2196
2197#define PIO_START 0x1 /* Start PIO/Reg Op */
2198#define MULTI_START 0x2 /* Start Multi-DMA Op */
2199#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2200#define XFER_DIR 0x8 /* Transfer Direction */
2201#define IORDY_EN 0x10 /* IORDY Enable */
2202#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2203#define SOFT_RST 0x40 /* Soft Reset */
2204#define DEV_RST 0x80 /* Device Reset */
2205#define TFRCNT_RST 0x100 /* Trans Count Reset */
2206#define END_ON_TERM 0x200 /* End/Terminate Select */
2207#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2208#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2209
2210/* Bit masks for ATAPI_STATUS */
2211
2212#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2213#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2214#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2215#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2216
2217/* Bit masks for ATAPI_DEV_ADDR */
2218
2219#define DEV_ADDR 0x1f /* Device Address */
2220
2221/* Bit masks for ATAPI_INT_MASK */
2222
2223#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2224#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2225#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2226#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2227#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2228#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2229#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2230#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2231#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2232
2233/* Bit masks for ATAPI_INT_STATUS */
2234
2235#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2236#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2237#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2238#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2239#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2240#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2241#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2242#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2243#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2244
2245/* Bit masks for ATAPI_LINE_STATUS */
2246
2247#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2248#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2249#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2250#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2251#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2252#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2253#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2254#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2255#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2256#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2257
2258/* Bit masks for ATAPI_SM_STATE */
2259
2260#define PIO_CSTATE 0xf /* PIO mode state machine current state */
2261#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
2262#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
2263#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
2264
2265/* Bit masks for ATAPI_TERMINATE */
2266
2267#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2268
2269/* Bit masks for ATAPI_REG_TIM_0 */
2270
2271#define T2_REG 0xff /* End of cycle time for register access transfers */
2272#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
2273
2274/* Bit masks for ATAPI_PIO_TIM_0 */
2275
2276#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
2277#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
2278#define T4_REG 0xf000 /* DIOW data hold */
2279
2280/* Bit masks for ATAPI_PIO_TIM_1 */
2281
2282#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
2283
2284/* Bit masks for ATAPI_MULTI_TIM_0 */
2285
2286#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
2287#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
2288
2289/* Bit masks for ATAPI_MULTI_TIM_1 */
2290
2291#define TKW 0xff /* Selects DIOW negated pulsewidth */
2292#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
2293
2294/* Bit masks for ATAPI_MULTI_TIM_2 */
2295
2296#define TH 0xff /* Selects DIOW data hold */
2297#define TEOC 0xff00 /* Selects end of cycle for DMA */
2298
2299/* Bit masks for ATAPI_ULTRA_TIM_0 */
2300
2301#define TACK 0xff /* Selects setup and hold times for TACK */
2302#define TENV 0xff00 /* Selects envelope time */
2303
2304/* Bit masks for ATAPI_ULTRA_TIM_1 */
2305
2306#define TDVS 0xff /* Selects data valid setup time */
2307#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
2308
2309/* Bit masks for ATAPI_ULTRA_TIM_2 */
2310
2311#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
2312#define TMLI 0xff00 /* Selects interlock time */
2313
2314/* Bit masks for ATAPI_ULTRA_TIM_3 */
2315
2316#define TZAH 0xff /* Selects minimum delay required for output */
2317#define READY_PAUSE 0xff00 /* Selects ready to pause */
2318
2319/* Bit masks for TIMER_ENABLE1 */
2320
2321#define TIMEN8 0x1 /* Timer 8 Enable */
2322#define TIMEN9 0x2 /* Timer 9 Enable */
2323#define TIMEN10 0x4 /* Timer 10 Enable */
2324
2325/* Bit masks for TIMER_DISABLE1 */
2326
2327#define TIMDIS8 0x1 /* Timer 8 Disable */
2328#define TIMDIS9 0x2 /* Timer 9 Disable */
2329#define TIMDIS10 0x4 /* Timer 10 Disable */
2330
2331/* Bit masks for TIMER_STATUS1 */
2332
2333#define TIMIL8 0x1 /* Timer 8 Interrupt */
2334#define TIMIL9 0x2 /* Timer 9 Interrupt */
2335#define TIMIL10 0x4 /* Timer 10 Interrupt */
2336#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2337#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2338#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2339#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2340#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2341#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2342
2343/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2344
2345/* Bit masks for USB_FADDR */
2346
2347#define FUNCTION_ADDRESS 0x7f /* Function address */
2348
2349/* Bit masks for USB_POWER */
2350
2351#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2352#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2353#define RESUME_MODE 0x4 /* DMA Mode */
2354#define RESET 0x8 /* Reset indicator */
2355#define HS_MODE 0x10 /* High Speed mode indicator */
2356#define HS_ENABLE 0x20 /* high Speed Enable */
2357#define SOFT_CONN 0x40 /* Soft connect */
2358#define ISO_UPDATE 0x80 /* Isochronous update */
2359
2360/* Bit masks for USB_INTRTX */
2361
2362#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2363#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2364#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2365#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2366#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2367#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2368#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2369#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2370
2371/* Bit masks for USB_INTRRX */
2372
2373#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2374#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2375#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2376#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2377#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2378#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2379#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2380
2381/* Bit masks for USB_INTRTXE */
2382
2383#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
2384#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
2385#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
2386#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
2387#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
2388#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
2389#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
2390#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
2391
2392/* Bit masks for USB_INTRRXE */
2393
2394#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
2395#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
2396#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
2397#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
2398#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
2399#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
2400#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
2401
2402/* Bit masks for USB_INTRUSB */
2403
2404#define SUSPEND_B 0x1 /* Suspend indicator */
2405#define RESUME_B 0x2 /* Resume indicator */
2406#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
2407#define SOF_B 0x8 /* Start of frame */
2408#define CONN_B 0x10 /* Connection indicator */
2409#define DISCON_B 0x20 /* Disconnect indicator */
2410#define SESSION_REQ_B 0x40 /* Session Request */
2411#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
2412
2413/* Bit masks for USB_INTRUSBE */
2414
2415#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
2416#define RESUME_BE 0x2 /* Resume indicator int enable */
2417#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
2418#define SOF_BE 0x8 /* Start of frame int enable */
2419#define CONN_BE 0x10 /* Connection indicator int enable */
2420#define DISCON_BE 0x20 /* Disconnect indicator int enable */
2421#define SESSION_REQ_BE 0x40 /* Session Request int enable */
2422#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
2423
2424/* Bit masks for USB_FRAME */
2425
2426#define FRAME_NUMBER 0x7ff /* Frame number */
2427
2428/* Bit masks for USB_INDEX */
2429
2430#define SELECTED_ENDPOINT 0xf /* selected endpoint */
2431
2432/* Bit masks for USB_GLOBAL_CTL */
2433
2434#define GLOBAL_ENA 0x1 /* enables USB module */
2435#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
2436#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
2437#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
2438#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
2439#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
2440#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
2441#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
2442#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
2443#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
2444#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
2445#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
2446#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
2447#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
2448#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
2449
2450/* Bit masks for USB_OTG_DEV_CTL */
2451
2452#define SESSION 0x1 /* session indicator */
2453#define HOST_REQ 0x2 /* Host negotiation request */
2454#define HOST_MODE 0x4 /* indicates USBDRC is a host */
2455#define VBUS0 0x8 /* Vbus level indicator[0] */
2456#define VBUS1 0x10 /* Vbus level indicator[1] */
2457#define LSDEV 0x20 /* Low-speed indicator */
2458#define FSDEV 0x40 /* Full or High-speed indicator */
2459#define B_DEVICE 0x80 /* A' or 'B' device indicator */
2460
2461/* Bit masks for USB_OTG_VBUS_IRQ */
2462
2463#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
2464#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
2465#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
2466#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
2467#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
2468#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
2469
2470/* Bit masks for USB_OTG_VBUS_MASK */
2471
2472#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
2473#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
2474#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
2475#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
2476#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
2477#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
2478
2479/* Bit masks for USB_CSR0 */
2480
2481#define RXPKTRDY 0x1 /* data packet receive indicator */
2482#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
2483#define STALL_SENT 0x4 /* STALL handshake sent */
2484#define DATAEND 0x8 /* Data end indicator */
2485#define SETUPEND 0x10 /* Setup end */
2486#define SENDSTALL 0x20 /* Send STALL handshake */
2487#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
2488#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
2489#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
2490#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
2491#define SETUPPKT_H 0x8 /* send Setup token host mode */
2492#define ERROR_H 0x10 /* timeout error indicator host mode */
2493#define REQPKT_H 0x20 /* Request an IN transaction host mode */
2494#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
2495#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
2496
2497/* Bit masks for USB_COUNT0 */
2498
2499#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
2500
2501/* Bit masks for USB_NAKLIMIT0 */
2502
2503#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
2504
2505/* Bit masks for USB_TX_MAX_PACKET */
2506
2507#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
2508
2509/* Bit masks for USB_RX_MAX_PACKET */
2510
2511#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
2512
2513/* Bit masks for USB_TXCSR */
2514
2515#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
2516#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
2517#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
2518#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
2519#define STALL_SEND_T 0x10 /* issue a Stall handshake */
2520#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
2521#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
2522#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
2523#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
2524#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
2525#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
2526#define ISO_T 0x4000 /* enable Isochronous transfers */
2527#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
2528#define ERROR_TH 0x4 /* error condition host mode */
2529#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
2530#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
2531
2532/* Bit masks for USB_TXCOUNT */
2533
2534#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
2535
2536/* Bit masks for USB_RXCSR */
2537
2538#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
2539#define FIFO_FULL_R 0x2 /* FIFO not empty */
2540#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
2541#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
2542#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
2543#define STALL_SEND_R 0x20 /* issue a Stall handshake */
2544#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
2545#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
2546#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
2547#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
2548#define DISNYET_R 0x1000 /* disable Nyet handshakes */
2549#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
2550#define ISO_R 0x4000 /* enable Isochronous transfers */
2551#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
2552#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
2553#define REQPKT_RH 0x20 /* request an IN transaction host mode */
2554#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
2555#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
2556#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
2557#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
2558
2559/* Bit masks for USB_RXCOUNT */
2560
2561#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
2562
2563/* Bit masks for USB_TXTYPE */
2564
2565#define TARGET_EP_NO_T 0xf /* EP number */
2566#define PROTOCOL_T 0xc /* transfer type */
2567
2568/* Bit masks for USB_TXINTERVAL */
2569
2570#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
2571
2572/* Bit masks for USB_RXTYPE */
2573
2574#define TARGET_EP_NO_R 0xf /* EP number */
2575#define PROTOCOL_R 0xc /* transfer type */
2576
2577/* Bit masks for USB_RXINTERVAL */
2578
2579#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
2580
2581/* Bit masks for USB_DMA_INTERRUPT */
2582
2583#define DMA0_INT 0x1 /* DMA0 pending interrupt */
2584#define DMA1_INT 0x2 /* DMA1 pending interrupt */
2585#define DMA2_INT 0x4 /* DMA2 pending interrupt */
2586#define DMA3_INT 0x8 /* DMA3 pending interrupt */
2587#define DMA4_INT 0x10 /* DMA4 pending interrupt */
2588#define DMA5_INT 0x20 /* DMA5 pending interrupt */
2589#define DMA6_INT 0x40 /* DMA6 pending interrupt */
2590#define DMA7_INT 0x80 /* DMA7 pending interrupt */
2591
2592/* Bit masks for USB_DMAxCONTROL */
2593
2594#define DMA_ENA 0x1 /* DMA enable */
2595#define DIRECTION 0x2 /* direction of DMA transfer */
2596#define MODE 0x4 /* DMA Bus error */
2597#define INT_ENA 0x8 /* Interrupt enable */
2598#define EPNUM 0xf0 /* EP number */
2599#define BUSERROR 0x100 /* DMA Bus error */
2600
2601/* Bit masks for USB_DMAxADDRHIGH */
2602
2603#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
2604
2605/* Bit masks for USB_DMAxADDRLOW */
2606
2607#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
2608
2609/* Bit masks for USB_DMAxCOUNTHIGH */
2610
2611#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
2612
2613/* Bit masks for USB_DMAxCOUNTLOW */
2614
2615#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
2616
2617/* Bit masks for HMDMAx_CONTROL */
2618
2619#define HMDMAEN 0x1 /* Handshake MDMA Enable */
2620#define REP 0x2 /* Handshake MDMA Request Polarity */
2621#define UTE 0x8 /* Urgency Threshold Enable */
2622#define OIE 0x10 /* Overflow Interrupt Enable */
2623#define BDIE 0x20 /* Block Done Interrupt Enable */
2624#define MBDI 0x40 /* Mask Block Done Interrupt */
2625#define DRQ 0x300 /* Handshake MDMA Request Type */
2626#define RBC 0x1000 /* Force Reload of BCOUNT */
2627#define PS 0x2000 /* Pin Status */
2628#define OI 0x4000 /* Overflow Interrupt Generated */
2629#define BDI 0x8000 /* Block Done Interrupt Generated */
2630
2631/* ******************************************* */
2632/* MULTI BIT MACRO ENUMERATIONS */
2633/* ******************************************* */
2634
2635/* ************************ */
2636/* MXVR Address Offsets */
2637/* ************************ */
2638
2639/* Control Message Receive Buffer (CMRB) Address Offsets */
2640
2641#define CMRB_STRIDE 0x00000016lu
2642
2643#define CMRB_DST_OFFSET 0x00000000lu
2644#define CMRB_SRC_OFFSET 0x00000002lu
2645#define CMRB_DATA_OFFSET 0x00000005lu
2646
2647/* Control Message Transmit Buffer (CMTB) Address Offsets */
2648
2649#define CMTB_PRIO_OFFSET 0x00000000lu
2650#define CMTB_DST_OFFSET 0x00000002lu
2651#define CMTB_SRC_OFFSET 0x00000004lu
2652#define CMTB_TYPE_OFFSET 0x00000006lu
2653#define CMTB_DATA_OFFSET 0x00000007lu
2654
2655#define CMTB_ANSWER_OFFSET 0x0000000Alu
2656
2657#define CMTB_STAT_N_OFFSET 0x00000018lu
2658#define CMTB_STAT_A_OFFSET 0x00000016lu
2659#define CMTB_STAT_D_OFFSET 0x0000000Elu
2660#define CMTB_STAT_R_OFFSET 0x00000014lu
2661#define CMTB_STAT_W_OFFSET 0x00000014lu
2662#define CMTB_STAT_G_OFFSET 0x00000014lu
2663
2664/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
2665
2666#define APRB_STRIDE 0x00000400lu
2667
2668#define APRB_DST_OFFSET 0x00000000lu
2669#define APRB_LEN_OFFSET 0x00000002lu
2670#define APRB_SRC_OFFSET 0x00000004lu
2671#define APRB_DATA_OFFSET 0x00000006lu
2672
2673/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
2674
2675#define APTB_PRIO_OFFSET 0x00000000lu
2676#define APTB_DST_OFFSET 0x00000002lu
2677#define APTB_LEN_OFFSET 0x00000004lu
2678#define APTB_SRC_OFFSET 0x00000006lu
2679#define APTB_DATA_OFFSET 0x00000008lu
2680
2681/* Remote Read Buffer (RRDB) Address Offsets */
2682
2683#define RRDB_WADDR_OFFSET 0x00000100lu
2684#define RRDB_WLEN_OFFSET 0x00000101lu
2685
2686/* **************** */
2687/* MXVR Macros */
2688/* **************** */
2689
2690/* MXVR_CONFIG Macros */
2691
2692#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
2693
2694/* MXVR_INT_STAT_1 Macros */
2695
2696#define DONEX(x) (0x00000002 << (4 * (x)))
2697#define HDONEX(x) (0x00000001 << (4 * (x)))
2698
2699/* MXVR_INT_EN_1 Macros */
2700
2701#define DONEENX(x) (0x00000002 << (4 * (x)))
2702#define HDONEENX(x) (0x00000001 << (4 * (x)))
2703
2704/* MXVR_CDRPLL_CTL Macros */
2705
2706#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
2707
2708/* MXVR_FMPLL_CTL Macros */
2709
2710#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
2711#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
2712
2713#endif /* _DEF_BF549_H */ 191#endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 8590c8c78336..ab04d137fd8b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1609,44 +1609,6 @@
1609#define PINT2 0x40000000 /* Pin Interrupt 2 */ 1609#define PINT2 0x40000000 /* Pin Interrupt 2 */
1610#define PINT3 0x80000000 /* Pin Interrupt 3 */ 1610#define PINT3 0x80000000 /* Pin Interrupt 3 */
1611 1611
1612/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1613
1614#define DMAEN 0x1 /* DMA Channel Enable */
1615#define WNR 0x2 /* DMA Direction */
1616#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1617#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1618#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1619#define DMA2D 0x10 /* DMA Mode */
1620#define RESTART 0x20 /* Work Unit Transitions */
1621#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1622#define DI_EN 0x80 /* Data Interrupt Enable */
1623
1624#define NDSIZE 0xf00 /* Flex Descriptor Size */
1625#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1626#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1627#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1628#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1629#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1630#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1631#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1632#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1633#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1634#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1635
1636#define DMAFLOW 0xf000 /* Next Operation */
1637#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1638#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1639#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1640#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1641#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1642
1643/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1644
1645#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1646#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1647#define DFETCH 0x4 /* DMA Descriptor Fetch */
1648#define DMA_RUN 0x8 /* DMA Channel Running */
1649
1650/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1612/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1651 1613
1652#define CTYPE 0x40 /* DMA Channel Type */ 1614#define CTYPE 0x40 /* DMA Channel Type */
@@ -1815,10 +1777,6 @@
1815#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ 1777#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1816#define CORE_MERROR 0x80 /* Core Error (2nd) */ 1778#define CORE_MERROR 0x80 /* Core Error (2nd) */
1817 1779
1818/* Bit masks for EBIU_ERRADD */
1819
1820#define ERROR_ADDRESS 0xffffffff /* Error Address */
1821
1822/* Bit masks for EBIU_RSTCTL */ 1780/* Bit masks for EBIU_RSTCTL */
1823 1781
1824#define DDRSRESET 0x1 /* DDR soft reset */ 1782#define DDRSRESET 0x1 /* DDR soft reset */
@@ -1827,98 +1785,6 @@
1827#define SRACK 0x10 /* Self-refresh acknowledge */ 1785#define SRACK 0x10 /* Self-refresh acknowledge */
1828#define MDDRENABLE 0x20 /* Mobile DDR enable */ 1786#define MDDRENABLE 0x20 /* Mobile DDR enable */
1829 1787
1830/* Bit masks for EBIU_DDRBRC0 */
1831
1832#define BRC0 0xffffffff /* Count */
1833
1834/* Bit masks for EBIU_DDRBRC1 */
1835
1836#define BRC1 0xffffffff /* Count */
1837
1838/* Bit masks for EBIU_DDRBRC2 */
1839
1840#define BRC2 0xffffffff /* Count */
1841
1842/* Bit masks for EBIU_DDRBRC3 */
1843
1844#define BRC3 0xffffffff /* Count */
1845
1846/* Bit masks for EBIU_DDRBRC4 */
1847
1848#define BRC4 0xffffffff /* Count */
1849
1850/* Bit masks for EBIU_DDRBRC5 */
1851
1852#define BRC5 0xffffffff /* Count */
1853
1854/* Bit masks for EBIU_DDRBRC6 */
1855
1856#define BRC6 0xffffffff /* Count */
1857
1858/* Bit masks for EBIU_DDRBRC7 */
1859
1860#define BRC7 0xffffffff /* Count */
1861
1862/* Bit masks for EBIU_DDRBWC0 */
1863
1864#define BWC0 0xffffffff /* Count */
1865
1866/* Bit masks for EBIU_DDRBWC1 */
1867
1868#define BWC1 0xffffffff /* Count */
1869
1870/* Bit masks for EBIU_DDRBWC2 */
1871
1872#define BWC2 0xffffffff /* Count */
1873
1874/* Bit masks for EBIU_DDRBWC3 */
1875
1876#define BWC3 0xffffffff /* Count */
1877
1878/* Bit masks for EBIU_DDRBWC4 */
1879
1880#define BWC4 0xffffffff /* Count */
1881
1882/* Bit masks for EBIU_DDRBWC5 */
1883
1884#define BWC5 0xffffffff /* Count */
1885
1886/* Bit masks for EBIU_DDRBWC6 */
1887
1888#define BWC6 0xffffffff /* Count */
1889
1890/* Bit masks for EBIU_DDRBWC7 */
1891
1892#define BWC7 0xffffffff /* Count */
1893
1894/* Bit masks for EBIU_DDRACCT */
1895
1896#define ACCT 0xffffffff /* Count */
1897
1898/* Bit masks for EBIU_DDRTACT */
1899
1900#define TECT 0xffffffff /* Count */
1901
1902/* Bit masks for EBIU_DDRARCT */
1903
1904#define ARCT 0xffffffff /* Count */
1905
1906/* Bit masks for EBIU_DDRGC0 */
1907
1908#define GC0 0xffffffff /* Count */
1909
1910/* Bit masks for EBIU_DDRGC1 */
1911
1912#define GC1 0xffffffff /* Count */
1913
1914/* Bit masks for EBIU_DDRGC2 */
1915
1916#define GC2 0xffffffff /* Count */
1917
1918/* Bit masks for EBIU_DDRGC3 */
1919
1920#define GC3 0xffffffff /* Count */
1921
1922/* Bit masks for EBIU_DDRMCEN */ 1788/* Bit masks for EBIU_DDRMCEN */
1923 1789
1924#define B0WCENABLE 0x1 /* Bank 0 write count enable */ 1790#define B0WCENABLE 0x1 /* Bank 0 write count enable */
@@ -2092,12 +1958,6 @@
2092#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1958#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2093#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1959#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2094 1960
2095/* Bit masks for WDOG_CTL */
2096
2097#define WDEV 0x6 /* Watchdog Event */
2098#define WDEN 0xff0 /* Watchdog Enable */
2099#define WDRO 0x8000 /* Watchdog Rolled Over */
2100
2101/* Bit masks for CNT_CONFIG */ 1961/* Bit masks for CNT_CONFIG */
2102 1962
2103#define CNTE 0x1 /* Counter Enable */ 1963#define CNTE 0x1 /* Counter Enable */
@@ -2149,81 +2009,6 @@
2149 2009
2150#define DPRESCALE 0xf /* Load Counter Register */ 2010#define DPRESCALE 0xf /* Load Counter Register */
2151 2011
2152/* Bit masks for RTC_STAT */
2153
2154#define SECONDS 0x3f /* Seconds */
2155#define MINUTES 0xfc0 /* Minutes */
2156#define HOURS 0x1f000 /* Hours */
2157#define DAY_COUNTER 0xfffe0000 /* Day Counter */
2158
2159/* Bit masks for RTC_ICTL */
2160
2161#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2162#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2163#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2164#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2165#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2166#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2167#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2168#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2169
2170/* Bit masks for RTC_ISTAT */
2171
2172#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2173#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2174#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2175#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2176#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2177#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2178#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2179#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2180#define WRITE_COMPLETE 0x8000 /* Write Complete */
2181
2182/* Bit masks for RTC_SWCNT */
2183
2184#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
2185
2186/* Bit masks for RTC_ALARM */
2187
2188#define SECONDS 0x3f /* Seconds */
2189#define MINUTES 0xfc0 /* Minutes */
2190#define HOURS 0x1f000 /* Hours */
2191#define DAY 0xfffe0000 /* Day */
2192
2193/* Bit masks for RTC_PREN */
2194
2195#define PREN 0x1 /* Prescaler Enable */
2196
2197/* Bit masks for OTP_CONTROL */
2198
2199#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2200#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2201#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2202#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2203#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2204#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2205
2206/* Bit masks for OTP_BEN */
2207
2208#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2209
2210/* Bit masks for OTP_STATUS */
2211
2212#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2213#define FERROR 0x2 /* OTP/Fuse Access Error */
2214#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2215#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2216#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2217
2218/* Bit masks for OTP_TIMING */
2219
2220#define USECDIV 0xff /* Micro Second Divider */
2221#define READACC 0x7f00 /* Read Access Time */
2222#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2223#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2224#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2225#define PGMTIME 0xff000000 /* Program Time */
2226
2227/* Bit masks for SECURE_SYSSWT */ 2012/* Bit masks for SECURE_SYSSWT */
2228 2013
2229#define EMUDABL 0x1 /* Emulation Disable. */ 2014#define EMUDABL 0x1 /* Emulation Disable. */
@@ -2252,26 +2037,6 @@
2252#define AFEXIT 0x10 /* Authentication Firmware Exit */ 2037#define AFEXIT 0x10 /* Authentication Firmware Exit */
2253#define SECSTAT 0xe0 /* Secure Status */ 2038#define SECSTAT 0xe0 /* Secure Status */
2254 2039
2255/* Bit masks for PLL_DIV */
2256
2257#define CSEL 0x30 /* Core Select */
2258#define SSEL 0xf /* System Select */
2259#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2260#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2261#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2262#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2263
2264/* Bit masks for PLL_CTL */
2265
2266#define MSEL 0x7e00 /* Multiplier Select */
2267#define BYPASS 0x100 /* PLL Bypass Enable */
2268#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2269#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2270#define PDWN 0x20 /* Power Down */
2271#define STOPCK 0x8 /* Stop Clock */
2272#define PLL_OFF 0x2 /* Disable PLL */
2273#define DF 0x1 /* Divide Frequency */
2274
2275/* SWRST Masks */ 2040/* SWRST Masks */
2276#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 2041#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2277#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 2042#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
@@ -2279,52 +2044,6 @@
2279#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 2044#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2280#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 2045#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2281 2046
2282/* Bit masks for PLL_STAT */
2283
2284#define PLL_LOCKED 0x20 /* PLL Locked Status */
2285#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2286#define FULL_ON 0x2 /* Full-On Mode */
2287#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2288#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2289#define CANWS 0x800 /* CAN Wake-Up Status */
2290#define USBWS 0x2000 /* USB Wake-Up Status */
2291#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2292#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2293#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2294
2295/* Bit masks for VR_CTL */
2296
2297#define FREQ 0x3 /* Regulator Switching Frequency */
2298#define GAIN 0xc /* Voltage Output Level Gain */
2299#define VLEV 0xf0 /* Internal Voltage Level */
2300#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2301#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2302#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2303#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2304#define USBWE 0x800 /* USB Wake-Up Enable */
2305#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2306#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2307
2308#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2309#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2310#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2311
2312#define GAIN_5 0x0000 /* GAIN = 5*/
2313#define GAIN_10 0x0004 /* GAIN = 1*/
2314#define GAIN_20 0x0008 /* GAIN = 2*/
2315#define GAIN_50 0x000C /* GAIN = 5*/
2316
2317#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2318#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2319#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2320#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2321#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2322#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2323#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2324#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2325#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2326#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2327
2328/* Bit masks for NFC_CTL */ 2047/* Bit masks for NFC_CTL */
2329 2048
2330#define WR_DLY 0xf /* Write Strobe Delay */ 2049#define WR_DLY 0xf /* Write Strobe Delay */
@@ -2489,14 +2208,6 @@
2489#define UCCT 0x40 /* Universal Counter CAN Trigger */ 2208#define UCCT 0x40 /* Universal Counter CAN Trigger */
2490#define UCE 0x80 /* Universal Counter Enable */ 2209#define UCE 0x80 /* Universal Counter Enable */
2491 2210
2492/* Bit masks for CAN0_UCCNT */
2493
2494#define UCCNT 0xffff /* Universal Counter Count Value */
2495
2496/* Bit masks for CAN0_UCRC */
2497
2498#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
2499
2500/* Bit masks for CAN0_CEC */ 2211/* Bit masks for CAN0_CEC */
2501 2212
2502#define RXECNT 0xff /* Receive Error Counter */ 2213#define RXECNT 0xff /* Receive Error Counter */
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
index e4bc6d7c5a6a..1aa529b9f8bb 100644
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ b/arch/blackfin/mach-bf561/boards/Kconfig
@@ -19,4 +19,11 @@ config BFIN561_BLUETECHNIX_CM
19 help 19 help
20 CM-BF561 support for EVAL- and DEV-Board. 20 CM-BF561 support for EVAL- and DEV-Board.
21 21
22config BFIN561_ACVILON
23 bool "BF561-ACVILON"
24 help
25 BF561-ACVILON System On Module support (SO-DIMM 144).
26 For more information about Acvilon BF561 SoM
27 please go to http://www.niistt.ru/
28
22endchoice 29endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
index 3a152559e957..a5879f7857ad 100644
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -2,6 +2,7 @@
2# arch/blackfin/mach-bf561/boards/Makefile 2# arch/blackfin/mach-bf561/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
5obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o 6obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
6obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o 7obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
7obj-$(CONFIG_BFIN561_TEPLA) += tepla.o 8obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
new file mode 100644
index 000000000000..07e8dc8770da
--- /dev/null
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -0,0 +1,551 @@
1/*
2 * File: arch/blackfin/mach-bf561/acvilon.c
3 * Based on: arch/blackfin/mach-bf561/ezkit.c
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 * Copyright 2009 CJSC "NII STT"
12 *
13 * Bugs:
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 *
30 *
31 * For more information about Acvilon BF561 SoM please
32 * go to http://www.niistt.ru/
33 *
34 */
35
36#include <linux/device.h>
37#include <linux/platform_device.h>
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/partitions.h>
40#include <linux/mtd/physmap.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/plat-ram.h>
43#include <linux/spi/spi.h>
44#include <linux/spi/flash.h>
45#include <linux/irq.h>
46#include <linux/interrupt.h>
47#include <linux/i2c-pca-platform.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <asm/dma.h>
51#include <asm/bfin5xx_spi.h>
52#include <asm/portmux.h>
53#include <asm/dpmc.h>
54#include <asm/cacheflush.h>
55#include <linux/i2c.h>
56
57/*
58 * Name the Board for the /proc/cpuinfo
59 */
60const char bfin_board_name[] = "Acvilon board";
61
62#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
63#include <linux/usb/isp1760.h>
64static struct resource bfin_isp1760_resources[] = {
65 [0] = {
66 .start = 0x20000000,
67 .end = 0x20000000 + 0x000fffff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = IRQ_PF15,
72 .end = IRQ_PF15,
73 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
74 },
75};
76
77static struct isp1760_platform_data isp1760_priv = {
78 .is_isp1761 = 0,
79 .port1_disable = 0,
80 .bus_width_16 = 1,
81 .port1_otg = 0,
82 .analog_oc = 0,
83 .dack_polarity_high = 0,
84 .dreq_polarity_high = 0,
85};
86
87static struct platform_device bfin_isp1760_device = {
88 .name = "isp1760-hcd",
89 .id = 0,
90 .dev = {
91 .platform_data = &isp1760_priv,
92 },
93 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
94 .resource = bfin_isp1760_resources,
95};
96#endif
97
98static struct resource bfin_i2c_pca_resources[] = {
99 {
100 .name = "pca9564-regs",
101 .start = 0x2C000000,
102 .end = 0x2C000000 + 16,
103 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
104 }, {
105
106 .start = IRQ_PF8,
107 .end = IRQ_PF8,
108 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
109 },
110};
111
112struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
113 .gpio = -1,
114 .i2c_clock_speed = 330000,
115 .timeout = 10000
116};
117
118/* PCA9564 I2C Bus driver */
119static struct platform_device bfin_i2c_pca_device = {
120 .name = "i2c-pca-platform",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
123 .resource = bfin_i2c_pca_resources,
124 .dev = {
125 .platform_data = &pca9564_platform_data,
126 }
127};
128
129/* I2C devices fitted. */
130static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
131 {
132 I2C_BOARD_INFO("ds1339", 0x68),
133 },
134 {
135 I2C_BOARD_INFO("tcn75", 0x49),
136 },
137};
138
139#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
140static struct platdata_mtd_ram mtd_ram_data = {
141 .mapname = "rootfs(RAM)",
142 .bankwidth = 4,
143};
144
145static struct resource mtd_ram_resource = {
146 .start = 0x4000000,
147 .end = 0x5ffffff,
148 .flags = IORESOURCE_MEM,
149};
150
151static struct platform_device mtd_ram_device = {
152 .name = "mtd-ram",
153 .id = 0,
154 .dev = {
155 .platform_data = &mtd_ram_data,
156 },
157 .num_resources = 1,
158 .resource = &mtd_ram_resource,
159};
160#endif
161
162#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
163#include <linux/smsc911x.h>
164static struct resource smsc911x_resources[] = {
165 {
166 .name = "smsc911x-memory",
167 .start = 0x28000000,
168 .end = 0x28000000 + 0xFF,
169 .flags = IORESOURCE_MEM,
170 },
171 {
172 .start = IRQ_PF7,
173 .end = IRQ_PF7,
174 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
175 },
176};
177
178static struct smsc911x_platform_config smsc911x_config = {
179 .flags = SMSC911X_USE_32BIT,
180 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
181 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
182 .phy_interface = PHY_INTERFACE_MODE_MII,
183};
184
185static struct platform_device smsc911x_device = {
186 .name = "smsc911x",
187 .id = 0,
188 .num_resources = ARRAY_SIZE(smsc911x_resources),
189 .resource = smsc911x_resources,
190 .dev = {
191 .platform_data = &smsc911x_config,
192 },
193};
194#endif
195
196#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
197#ifdef CONFIG_SERIAL_BFIN_UART0
198static struct resource bfin_uart0_resources[] = {
199 {
200 .start = BFIN_UART_THR,
201 .end = BFIN_UART_GCTL + 2,
202 .flags = IORESOURCE_MEM,
203 },
204 {
205 .start = IRQ_UART_RX,
206 .end = IRQ_UART_RX + 1,
207 .flags = IORESOURCE_IRQ,
208 },
209 {
210 .start = IRQ_UART_ERROR,
211 .end = IRQ_UART_ERROR,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .start = CH_UART_TX,
216 .end = CH_UART_TX,
217 .flags = IORESOURCE_DMA,
218 },
219 {
220 .start = CH_UART_RX,
221 .end = CH_UART_RX,
222 .flags = IORESOURCE_DMA,
223 },
224};
225
226unsigned short bfin_uart0_peripherals[] = {
227 P_UART0_TX, P_UART0_RX, 0
228};
229
230static struct platform_device bfin_uart0_device = {
231 .name = "bfin-uart",
232 .id = 0,
233 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
234 .resource = bfin_uart0_resources,
235 .dev = {
236 /* Passed to driver */
237 .platform_data = &bfin_uart0_peripherals,
238 },
239};
240#endif
241#endif
242
243#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
244
245#ifdef CONFIG_MTD_PARTITIONS
246const char *part_probes[] = { "cmdlinepart", NULL };
247
248static struct mtd_partition bfin_plat_nand_partitions[] = {
249 {
250 .name = "params(nand)",
251 .size = 32 * 1024 * 1024,
252 .offset = 0,
253 }, {
254 .name = "userfs(nand)",
255 .size = MTDPART_SIZ_FULL,
256 .offset = MTDPART_OFS_APPEND,
257 },
258};
259#endif
260
261#define BFIN_NAND_PLAT_CLE 2
262#define BFIN_NAND_PLAT_ALE 3
263
264static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
265 unsigned int ctrl)
266{
267 struct nand_chip *this = mtd->priv;
268
269 if (cmd == NAND_CMD_NONE)
270 return;
271
272 if (ctrl & NAND_CLE)
273 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
274 else
275 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
276}
277
278#define BFIN_NAND_PLAT_READY GPIO_PF10
279static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
280{
281 return gpio_get_value(BFIN_NAND_PLAT_READY);
282}
283
284static struct platform_nand_data bfin_plat_nand_data = {
285 .chip = {
286 .chip_delay = 30,
287#ifdef CONFIG_MTD_PARTITIONS
288 .part_probe_types = part_probes,
289 .partitions = bfin_plat_nand_partitions,
290 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
291#endif
292 },
293 .ctrl = {
294 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
295 .dev_ready = bfin_plat_nand_dev_ready,
296 },
297};
298
299#define MAX(x, y) (x > y ? x : y)
300static struct resource bfin_plat_nand_resources = {
301 .start = 0x24000000,
302 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
303 .flags = IORESOURCE_IO,
304};
305
306static struct platform_device bfin_async_nand_device = {
307 .name = "gen_nand",
308 .id = -1,
309 .num_resources = 1,
310 .resource = &bfin_plat_nand_resources,
311 .dev = {
312 .platform_data = &bfin_plat_nand_data,
313 },
314};
315
316static void bfin_plat_nand_init(void)
317{
318 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
319}
320#else
321static void bfin_plat_nand_init(void)
322{
323}
324#endif
325
326#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
327static struct mtd_partition bfin_spi_dataflash_partitions[] = {
328 {
329 .name = "bootloader",
330 .size = 0x4200,
331 .offset = 0,
332 .mask_flags = MTD_CAP_ROM},
333 {
334 .name = "u-boot",
335 .size = 0x42000,
336 .offset = MTDPART_OFS_APPEND,
337 },
338 {
339 .name = "u-boot(params)",
340 .size = 0x4200,
341 .offset = MTDPART_OFS_APPEND,
342 },
343 {
344 .name = "kernel",
345 .size = 0x294000,
346 .offset = MTDPART_OFS_APPEND,
347 },
348 {
349 .name = "params",
350 .size = 0x42000,
351 .offset = MTDPART_OFS_APPEND,
352 },
353 {
354 .name = "rootfs",
355 .size = MTDPART_SIZ_FULL,
356 .offset = MTDPART_OFS_APPEND,
357 }
358};
359
360static struct flash_platform_data bfin_spi_dataflash_data = {
361 .name = "SPI Dataflash",
362 .parts = bfin_spi_dataflash_partitions,
363 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
364};
365
366/* DataFlash chip */
367static struct bfin5xx_spi_chip data_flash_chip_info = {
368 .enable_dma = 0, /* use dma transfer with this chip */
369 .bits_per_word = 8,
370};
371#endif
372
373#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
374static struct bfin5xx_spi_chip spidev_chip_info = {
375 .enable_dma = 0,
376 .bits_per_word = 8,
377};
378#endif
379
380#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
381/* SPI (0) */
382static struct resource bfin_spi0_resource[] = {
383 [0] = {
384 .start = SPI0_REGBASE,
385 .end = SPI0_REGBASE + 0xFF,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = CH_SPI,
390 .end = CH_SPI,
391 .flags = IORESOURCE_DMA,
392 },
393 [2] = {
394 .start = IRQ_SPI,
395 .end = IRQ_SPI,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
400/* SPI controller data */
401static struct bfin5xx_spi_master bfin_spi0_info = {
402 .num_chipselect = 8,
403 .enable_dma = 1, /* master has the ability to do dma transfer */
404 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
405};
406
407static struct platform_device bfin_spi0_device = {
408 .name = "bfin-spi",
409 .id = 0, /* Bus number */
410 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
411 .resource = bfin_spi0_resource,
412 .dev = {
413 .platform_data = &bfin_spi0_info, /* Passed to driver */
414 },
415};
416#endif
417
418static struct spi_board_info bfin_spi_board_info[] __initdata = {
419#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
420 {
421 .modalias = "spidev",
422 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
423 .bus_num = 0,
424 .chip_select = 3,
425 .controller_data = &spidev_chip_info,
426 },
427#endif
428#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
429 { /* DataFlash chip */
430 .modalias = "mtd_dataflash",
431 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
432 .bus_num = 0, /* Framework bus number */
433 .chip_select = 2, /* Framework chip select */
434 .platform_data = &bfin_spi_dataflash_data,
435 .controller_data = &data_flash_chip_info,
436 .mode = SPI_MODE_3,
437 },
438#endif
439};
440
441static struct resource bfin_gpios_resources = {
442 .start = 31,
443/* .end = MAX_BLACKFIN_GPIOS - 1, */
444 .end = 32,
445 .flags = IORESOURCE_IRQ,
446};
447
448static struct platform_device bfin_gpios_device = {
449 .name = "simple-gpio",
450 .id = -1,
451 .num_resources = 1,
452 .resource = &bfin_gpios_resources,
453};
454
455static const unsigned int cclk_vlev_datasheet[] = {
456 VRPAIR(VLEV_085, 250000000),
457 VRPAIR(VLEV_090, 300000000),
458 VRPAIR(VLEV_095, 313000000),
459 VRPAIR(VLEV_100, 350000000),
460 VRPAIR(VLEV_105, 400000000),
461 VRPAIR(VLEV_110, 444000000),
462 VRPAIR(VLEV_115, 450000000),
463 VRPAIR(VLEV_120, 475000000),
464 VRPAIR(VLEV_125, 500000000),
465 VRPAIR(VLEV_130, 600000000),
466};
467
468static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
469 .tuple_tab = cclk_vlev_datasheet,
470 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
471 .vr_settling_time = 25 /* us */ ,
472};
473
474static struct platform_device bfin_dpmc = {
475 .name = "bfin dpmc",
476 .dev = {
477 .platform_data = &bfin_dmpc_vreg_data,
478 },
479};
480
481static struct platform_device *acvilon_devices[] __initdata = {
482 &bfin_dpmc,
483
484#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
485 &bfin_spi0_device,
486#endif
487
488#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
489#ifdef CONFIG_SERIAL_BFIN_UART0
490 &bfin_uart0_device,
491#endif
492#endif
493
494 &bfin_gpios_device,
495
496#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
497 &smsc911x_device,
498#endif
499
500 &bfin_i2c_pca_device,
501
502#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
503 &bfin_async_nand_device,
504#endif
505
506#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
507 &mtd_ram_device,
508#endif
509
510};
511
512static int __init acvilon_init(void)
513{
514 int ret;
515
516 printk(KERN_INFO "%s(): registering device resources\n", __func__);
517
518 bfin_plat_nand_init();
519 ret =
520 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
521 if (ret < 0)
522 return ret;
523
524 i2c_register_board_info(0, acvilon_i2c_devs,
525 ARRAY_SIZE(acvilon_i2c_devs));
526
527 bfin_write_FIO0_FLAG_C(1 << 14);
528 msleep(5);
529 bfin_write_FIO0_FLAG_S(1 << 14);
530
531 spi_register_board_info(bfin_spi_board_info,
532 ARRAY_SIZE(bfin_spi_board_info));
533 return 0;
534}
535
536arch_initcall(acvilon_init);
537
538static struct platform_device *acvilon_early_devices[] __initdata = {
539#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
540#ifdef CONFIG_SERIAL_BFIN_UART0
541 &bfin_uart0_device,
542#endif
543#endif
544};
545
546void __init native_machine_early_platform_add_devices(void)
547{
548 printk(KERN_INFO "register early platform devices\n");
549 early_platform_add_devices(acvilon_early_devices,
550 ARRAY_SIZE(acvilon_early_devices));
551}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9e2d8cfba546..ffd3e6a80d1a 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -49,7 +49,7 @@ static struct isp1760_platform_data isp1760_priv = {
49}; 49};
50 50
51static struct platform_device bfin_isp1760_device = { 51static struct platform_device bfin_isp1760_device = {
52 .name = "isp1760-hcd", 52 .name = "isp1760",
53 .id = 0, 53 .id = 0,
54 .dev = { 54 .dev = {
55 .platform_data = &isp1760_priv, 55 .platform_data = &isp1760_priv,
@@ -159,28 +159,6 @@ static struct platform_device smc91x_device = {
159}; 159};
160#endif 160#endif
161 161
162#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
163static struct resource ax88180_resources[] = {
164 [0] = {
165 .start = 0x2c000000,
166 .end = 0x2c000000 + 0x8000,
167 .flags = IORESOURCE_MEM,
168 },
169 [1] = {
170 .start = IRQ_PF10,
171 .end = IRQ_PF10,
172 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
173 },
174};
175
176static struct platform_device ax88180_device = {
177 .name = "ax88180",
178 .id = -1,
179 .num_resources = ARRAY_SIZE(ax88180_resources),
180 .resource = ax88180_resources,
181};
182#endif
183
184#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 162#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
185static struct resource bfin_uart_resources[] = { 163static struct resource bfin_uart_resources[] = {
186 { 164 {
@@ -421,10 +399,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
421 &smc91x_device, 399 &smc91x_device,
422#endif 400#endif
423 401
424#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
425 &ax88180_device,
426#endif
427
428#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) 402#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
429 &net2272_bfin_device, 403 &net2272_bfin_device,
430#endif 404#endif
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 1e60a92dd602..deb2271d09a3 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -22,8 +22,8 @@
22#define CMD_COREB_STOP 3 22#define CMD_COREB_STOP 3
23#define CMD_COREB_RESET 4 23#define CMD_COREB_RESET 4
24 24
25static int 25static long
26coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 26coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
27{ 27{
28 int ret = 0; 28 int ret = 0;
29 29
@@ -49,8 +49,8 @@ coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned l
49} 49}
50 50
51static const struct file_operations coreb_fops = { 51static const struct file_operations coreb_fops = {
52 .owner = THIS_MODULE, 52 .owner = THIS_MODULE,
53 .ioctl = coreb_ioctl, 53 .unlocked_ioctl = coreb_ioctl,
54}; 54};
55 55
56static struct miscdevice coreb_dev = { 56static struct miscdevice coreb_dev = {
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index a31e509553fb..4c8e36b7fb33 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -884,65 +884,11 @@
884/* System MMR Register Bits */ 884/* System MMR Register Bits */
885/******************************************************************************* */ 885/******************************************************************************* */
886 886
887/* ********************* PLL AND RESET MASKS ************************ */
888
889/* PLL_CTL Masks */
890#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
891#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
892#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
893#define STOPCK_OFF 0x00000008 /* Core clock off */
894#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
895#define BYPASS 0x00000100 /* Bypass the PLL */
896
897/* CHIPID Masks */ 887/* CHIPID Masks */
898#define CHIPID_VERSION 0xF0000000 888#define CHIPID_VERSION 0xF0000000
899#define CHIPID_FAMILY 0x0FFFF000 889#define CHIPID_FAMILY 0x0FFFF000
900#define CHIPID_MANUFACTURE 0x00000FFE 890#define CHIPID_MANUFACTURE 0x00000FFE
901 891
902/* VR_CTL Masks */
903#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
904#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
905#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
906#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
907#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
908
909#define GAIN 0x000C /* Voltage Level Gain */
910#define GAIN_5 0x0000 /* GAIN = 5*/
911#define GAIN_10 0x0004 /* GAIN = 1*/
912#define GAIN_20 0x0008 /* GAIN = 2*/
913#define GAIN_50 0x000C /* GAIN = 5*/
914
915#define VLEV 0x00F0 /* Internal Voltage Level */
916#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
917#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
918#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
919#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
920#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
921#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
922#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
923#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
924#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
925#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
926
927#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
928#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
929
930/* PLL_DIV Masks */
931#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
932
933#define CSEL 0x30 /* Core Select */
934#define SSEL 0xf /* System Select */
935#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
936#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
937#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
938#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
939
940/* PLL_STAT Masks */
941#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
942#define FULL_ON 0x0002 /* Processor In Full On Mode */
943#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
944#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
945
946/* SICA_SYSCR Masks */ 892/* SICA_SYSCR Masks */
947#define COREB_SRAM_INIT 0x0020 893#define COREB_SRAM_INIT 0x0020
948 894
@@ -1150,53 +1096,6 @@
1150 1096
1151/* ********** DMA CONTROLLER MASKS *********************8 */ 1097/* ********** DMA CONTROLLER MASKS *********************8 */
1152 1098
1153/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
1154#define DMAEN 0x00000001 /* Channel Enable */
1155#define WNR 0x00000002 /* Channel Direction (W/R*) */
1156#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
1157#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
1158#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
1159#define DMA2D 0x00000010 /* 2D/1D* Mode */
1160#define RESTART 0x00000020 /* Restart */
1161#define DI_SEL 0x00000040 /* Data Interrupt Select */
1162#define DI_EN 0x00000080 /* Data Interrupt Enable */
1163#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1164#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1165#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1166#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1167#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1168#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1169#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1170#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1171#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1172#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1173#define NDSIZE 0x00000900 /* Next Descriptor Size */
1174#define DMAFLOW 0x00007000 /* Flow Control */
1175#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1176#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1177#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1178#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1179#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1180
1181#define DMAEN_P 0 /* Channel Enable */
1182#define WNR_P 1 /* Channel Direction (W/R*) */
1183#define DMA2D_P 4 /* 2D/1D* Mode */
1184#define RESTART_P 5 /* Restart */
1185#define DI_SEL_P 6 /* Data Interrupt Select */
1186#define DI_EN_P 7 /* Data Interrupt Enable */
1187
1188/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
1189
1190#define DMA_DONE 0x00000001 /* DMA Done Indicator */
1191#define DMA_ERR 0x00000002 /* DMA Error Indicator */
1192#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
1193#define DMA_RUN 0x00000008 /* DMA Running Indicator */
1194
1195#define DMA_DONE_P 0 /* DMA Done Indicator */
1196#define DMA_ERR_P 1 /* DMA Error Indicator */
1197#define DFETCH_P 2 /* Descriptor Fetch Indicator */
1198#define DMA_RUN_P 3 /* DMA Running Indicator */
1199
1200/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ 1099/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
1201 1100
1202#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ 1101#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 510f57641495..0192532e96a2 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -52,8 +52,6 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
52 52
53void __cpuinit platform_secondary_init(unsigned int cpu) 53void __cpuinit platform_secondary_init(unsigned int cpu)
54{ 54{
55 local_irq_disable();
56
57 /* Clone setup for peripheral interrupt sources from CoreA. */ 55 /* Clone setup for peripheral interrupt sources from CoreA. */
58 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); 56 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
59 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); 57 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
@@ -70,11 +68,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
70 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); 68 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
71 SSYNC(); 69 SSYNC();
72 70
73 local_irq_enable();
74
75 /* Calibrate loops per jiffy value. */
76 calibrate_delay();
77
78 /* Store CPU-private information to the cpu_data array. */ 71 /* Store CPU-private information to the cpu_data array. */
79 bfin_setup_cpudata(cpu); 72 bfin_setup_cpudata(cpu);
80 73
@@ -108,9 +101,13 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
108 barrier(); 101 barrier();
109 } 102 }
110 103
111 spin_unlock(&boot_lock); 104 if (cpu_isset(cpu, cpu_callin_map)) {
112 105 cpu_set(cpu, cpu_online_map);
113 return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS; 106 /* release the lock and let coreb run */
107 spin_unlock(&boot_lock);
108 return 0;
109 } else
110 panic("CPU%u: processor failed to boot\n", cpu);
114} 111}
115 112
116void __init platform_request_ipi(irq_handler_t handler) 113void __init platform_request_ipi(irq_handler_t handler)
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index ef6870e9eea6..d5cfe611b778 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -13,6 +13,7 @@
13#include <asm/dma.h> 13#include <asm/dma.h>
14#include <asm/clocks.h> 14#include <asm/clocks.h>
15#include <asm/mem_init.h> 15#include <asm/mem_init.h>
16#include <asm/dpmc.h>
16 17
17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 18#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
18#define PLL_CTL_VAL \ 19#define PLL_CTL_VAL \
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 01506504e6d0..777582897253 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -13,7 +13,7 @@
13#include <linux/fs.h> 13#include <linux/fs.h>
14#include <asm/blackfin.h> 14#include <asm/blackfin.h>
15#include <asm/time.h> 15#include <asm/time.h>
16 16#include <asm/dpmc.h>
17 17
18/* this is the table of CCLK frequencies, in Hz */ 18/* this is the table of CCLK frequencies, in Hz */
19/* .index is the entry in the auxillary dpm_state_table[] */ 19/* .index is the entry in the auxillary dpm_state_table[] */
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
138 dpm_state_table[index].tscale); 138 dpm_state_table[index].tscale);
139 } 139 }
140 140
141 policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000; 141 policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
142
142 /*Now ,only support one cpu */ 143 /*Now ,only support one cpu */
143 policy->cur = cclk; 144 policy->cur = cclk;
144 cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); 145 cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 8009a512fb11..b03716896051 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -404,6 +404,21 @@ ENTRY(_do_hibernate)
404 PM_SYS_PUSH(EBIU_FCTL) 404 PM_SYS_PUSH(EBIU_FCTL)
405#endif 405#endif
406 406
407#ifdef PORTCIO_FER
408 PM_SYS_PUSH16(PORTCIO_DIR)
409 PM_SYS_PUSH16(PORTCIO_INEN)
410 PM_SYS_PUSH16(PORTCIO)
411 PM_SYS_PUSH16(PORTCIO_FER)
412 PM_SYS_PUSH16(PORTDIO_DIR)
413 PM_SYS_PUSH16(PORTDIO_INEN)
414 PM_SYS_PUSH16(PORTDIO)
415 PM_SYS_PUSH16(PORTDIO_FER)
416 PM_SYS_PUSH16(PORTEIO_DIR)
417 PM_SYS_PUSH16(PORTEIO_INEN)
418 PM_SYS_PUSH16(PORTEIO)
419 PM_SYS_PUSH16(PORTEIO_FER)
420#endif
421
407 PM_SYS_PUSH16(SYSCR) 422 PM_SYS_PUSH16(SYSCR)
408 423
409 /* Save Core MMRs */ 424 /* Save Core MMRs */
@@ -716,6 +731,21 @@ ENTRY(_do_hibernate)
716 P0.L = lo(PLL_CTL); 731 P0.L = lo(PLL_CTL);
717 PM_SYS_POP16(SYSCR) 732 PM_SYS_POP16(SYSCR)
718 733
734#ifdef PORTCIO_FER
735 PM_SYS_POP16(PORTEIO_FER)
736 PM_SYS_POP16(PORTEIO)
737 PM_SYS_POP16(PORTEIO_INEN)
738 PM_SYS_POP16(PORTEIO_DIR)
739 PM_SYS_POP16(PORTDIO_FER)
740 PM_SYS_POP16(PORTDIO)
741 PM_SYS_POP16(PORTDIO_INEN)
742 PM_SYS_POP16(PORTDIO_DIR)
743 PM_SYS_POP16(PORTCIO_FER)
744 PM_SYS_POP16(PORTCIO)
745 PM_SYS_POP16(PORTCIO_INEN)
746 PM_SYS_POP16(PORTCIO_DIR)
747#endif
748
719#ifdef EBIU_FCTL 749#ifdef EBIU_FCTL
720 PM_SYS_POP(EBIU_FCTL) 750 PM_SYS_POP(EBIU_FCTL)
721 PM_SYS_POP(EBIU_MODE) 751 PM_SYS_POP(EBIU_MODE)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index f3f8bb46b517..b0ed0b487ff2 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -713,6 +713,8 @@ ENTRY(_system_call)
713 cc = BITTST(r7, TIF_RESTORE_SIGMASK); 713 cc = BITTST(r7, TIF_RESTORE_SIGMASK);
714 if cc jump .Lsyscall_do_signals; 714 if cc jump .Lsyscall_do_signals;
715 cc = BITTST(r7, TIF_SIGPENDING); 715 cc = BITTST(r7, TIF_SIGPENDING);
716 if cc jump .Lsyscall_do_signals;
717 cc = BITTST(r7, TIF_NOTIFY_RESUME);
716 if !cc jump .Lsyscall_really_exit; 718 if !cc jump .Lsyscall_really_exit;
717.Lsyscall_do_signals: 719.Lsyscall_do_signals:
718 /* Reenable interrupts. */ 720 /* Reenable interrupts. */
@@ -721,7 +723,7 @@ ENTRY(_system_call)
721 723
722 r0 = sp; 724 r0 = sp;
723 SP += -12; 725 SP += -12;
724 call _do_signal; 726 call _do_notify_resume;
725 SP += 12; 727 SP += 12;
726 728
727.Lsyscall_really_exit: 729.Lsyscall_really_exit:
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 660ea1bec54c..1873b2c1fede 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -25,11 +25,20 @@
25#include <asm/blackfin.h> 25#include <asm/blackfin.h>
26#include <asm/gpio.h> 26#include <asm/gpio.h>
27#include <asm/irq_handler.h> 27#include <asm/irq_handler.h>
28#include <asm/dpmc.h>
29#include <asm/bfin5xx_spi.h>
30#include <asm/bfin_sport.h>
28 31
29#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 32#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
30 33
31#ifdef BF537_FAMILY 34#ifdef BF537_FAMILY
32# define BF537_GENERIC_ERROR_INT_DEMUX 35# define BF537_GENERIC_ERROR_INT_DEMUX
36# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
37# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
38# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
39# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
40# define UART_ERR_MASK (0x6) /* UART_IIR */
41# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
33#else 42#else
34# undef BF537_GENERIC_ERROR_INT_DEMUX 43# undef BF537_GENERIC_ERROR_INT_DEMUX
35#endif 44#endif
@@ -324,11 +333,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
324 irq = IRQ_CAN_ERROR; 333 irq = IRQ_CAN_ERROR;
325 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) 334 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
326 irq = IRQ_SPI_ERROR; 335 irq = IRQ_SPI_ERROR;
327 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && 336 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
328 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
329 irq = IRQ_UART0_ERROR; 337 irq = IRQ_UART0_ERROR;
330 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && 338 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
331 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
332 irq = IRQ_UART1_ERROR; 339 irq = IRQ_UART1_ERROR;
333 340
334 if (irq) { 341 if (irq) {
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index d92b168c8328..369e687582b7 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -336,13 +336,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
336 336
337 ret = platform_boot_secondary(cpu, idle); 337 ret = platform_boot_secondary(cpu, idle);
338 338
339 if (ret) {
340 cpu_clear(cpu, cpu_present_map);
341 printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
342 free_task(idle);
343 } else
344 cpu_set(cpu, cpu_online_map);
345
346 secondary_stack = NULL; 339 secondary_stack = NULL;
347 340
348 return ret; 341 return ret;
@@ -418,9 +411,16 @@ void __cpuinit secondary_start_kernel(void)
418 411
419 setup_secondary(cpu); 412 setup_secondary(cpu);
420 413
414 platform_secondary_init(cpu);
415
421 local_irq_enable(); 416 local_irq_enable();
422 417
423 platform_secondary_init(cpu); 418 /*
419 * Calibrate loops per jiffy value.
420 * IRQs need to be enabled here - D-cache can be invalidated
421 * in timer irq handler, so core B can read correct jiffies.
422 */
423 calibrate_delay();
424 424
425 cpu_idle(); 425 cpu_idle();
426} 426}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 03:24:05 -0500