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authorSonic Zhang <sonic.zhang@analog.com>2012-07-02 06:05:20 -0400
committerBob Liu <lliubbo@gmail.com>2012-07-24 01:39:52 -0400
commit14c04e5755045a6a653b111d0ab5fc251155b9c6 (patch)
tree7d8ab000ff868d6f57f9826d64656b2deb87cbbd /arch/blackfin
parente0a593104d43dc98250984daa1b82f964835fcfa (diff)
bf60x: update bf60x anomaly list.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf609/include/mach/anomaly.h144
1 files changed, 56 insertions, 88 deletions
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index bdd39aefb565..13ed8ad7e58d 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -5,126 +5,94 @@
5 * and can be replaced with that version at any time 5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2012 Analog Devices Inc.
9 * Licensed under the Clear BSD license. 9 * Licensed under the Clear BSD license.
10 */ 10 */
11 11
12/* This file should be up to date with: 12/* This file should be up to date with:
13 * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
13 */ 14 */
14 15
15#if __SILICON_REVISION__ < 0 16#if __SILICON_REVISION__ < 0
16# error will not work on BF506 silicon version 17# error will not work on BF609 silicon version
17#endif 18#endif
18 19
19#ifndef _MACH_ANOMALY_H_ 20#ifndef _MACH_ANOMALY_H_
20#define _MACH_ANOMALY_H_ 21#define _MACH_ANOMALY_H_
21 22
22/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 23/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
23#define ANOMALY_05000074 (1) 24#define ANOMALY_16000003 (1)
24/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 25/* The EPPI Data Enable (DEN) Signal is Not Functional */
25#define ANOMALY_05000119 (1) 26#define ANOMALY_16000004 (1)
26/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 27/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
27#define ANOMALY_05000122 (1) 28#define ANOMALY_16000005 (1)
28/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 29/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
29#define ANOMALY_05000245 (1) 30#define ANOMALY_16000006 (1)
30/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 31/* DDR2 Memory Reads May Fail Intermittently */
31#define ANOMALY_05000254 (1) 32#define ANOMALY_16000007 (1)
32/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 33/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
33#define ANOMALY_05000265 (1) 34#define ANOMALY_16000008 (1)
34/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 35/* TestSET Instruction Cannot Be Interrupted */
35#define ANOMALY_05000310 (1) 36#define ANOMALY_16000009 (1)
36/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
37#define ANOMALY_05000366 (1)
38/* Speculative Fetches Can Cause Undesired External FIFO Operations */
39#define ANOMALY_05000416 (1)
40/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
41#define ANOMALY_05000426 (1)
42/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 37/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
43#define ANOMALY_05000443 (1) 38#define ANOMALY_16000010 (1)
44/* UART IrDA Receiver Fails on Extended Bit Pulses */
45#define ANOMALY_05000447 (1)
46/* False Hardware Error when RETI Points to Invalid Memory */ 39/* False Hardware Error when RETI Points to Invalid Memory */
47#define ANOMALY_05000461 (1) 40#define ANOMALY_16000011 (1)
48/* PLL Latches Incorrect Settings During Reset */ 41/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
49#define ANOMALY_05000469 (1) 42#define ANOMALY_16000012 (1)
50/* Incorrect Default MSEL Value in PLL_CTL */ 43/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
51#define ANOMALY_05000472 (1) 44#define ANOMALY_16000013 (1)
52/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ 45/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
53#define ANOMALY_05000473 (1) 46#define ANOMALY_16000014 (1)
54/* TESTSET Instruction Cannot Be Interrupted */ 47/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
55#define ANOMALY_05000477 (1) 48#define ANOMALY_16000015 (1)
56/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 49/* Speculative Fetches Can Cause Undesired External FIFO Operations */
57#define ANOMALY_05000481 (1) 50#define ANOMALY_16000017 (1)
58/* IFLUSH sucks at life */ 51/* RSI Boot Cleanup Routine Does Not Clear Registers */
59#define ANOMALY_05000491 (1) 52#define ANOMALY_16000018 (1)
60/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */ 53/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
61#define ANOMALY_05001001 (__SILICON_REVISION__ < 1) 54#define ANOMALY_16000019 (1)
55/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
56#define ANOMALY_16000020 (1)
57/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
58#define ANOMALY_16000021 (1)
59/* Boot Code Fails to Enable Parity Fault Detection */
60#define ANOMALY_16000022 (1)
61/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
62#define ANOMALY_16000027 (1)
63/* Interrupted Core Reads of MMRs May Cause Data Loss */
64#define ANOMALY_16000030 (1)
62 65
63/* Anomalies that don't exist on this proc */ 66/* Anomalies that don't exist on this proc */
64#define ANOMALY_05000099 (0)
65#define ANOMALY_05000120 (0)
66#define ANOMALY_05000125 (0)
67#define ANOMALY_05000149 (0)
68#define ANOMALY_05000158 (0) 67#define ANOMALY_05000158 (0)
69#define ANOMALY_05000171 (0)
70#define ANOMALY_05000179 (0)
71#define ANOMALY_05000182 (0)
72#define ANOMALY_05000183 (0)
73#define ANOMALY_05000189 (0) 68#define ANOMALY_05000189 (0)
74#define ANOMALY_05000198 (0) 69#define ANOMALY_05000198 (0)
75#define ANOMALY_05000202 (0)
76#define ANOMALY_05000215 (0)
77#define ANOMALY_05000219 (0)
78#define ANOMALY_05000220 (0)
79#define ANOMALY_05000227 (0)
80#define ANOMALY_05000230 (0) 70#define ANOMALY_05000230 (0)
81#define ANOMALY_05000231 (0) 71#define ANOMALY_05000231 (0)
82#define ANOMALY_05000233 (0)
83#define ANOMALY_05000234 (0)
84#define ANOMALY_05000242 (0)
85#define ANOMALY_05000244 (0) 72#define ANOMALY_05000244 (0)
86#define ANOMALY_05000248 (0)
87#define ANOMALY_05000250 (0)
88#define ANOMALY_05000257 (0)
89#define ANOMALY_05000261 (0)
90#define ANOMALY_05000263 (0) 73#define ANOMALY_05000263 (0)
91#define ANOMALY_05000266 (0)
92#define ANOMALY_05000273 (0) 74#define ANOMALY_05000273 (0)
93#define ANOMALY_05000274 (0) 75#define ANOMALY_05000274 (0)
94#define ANOMALY_05000278 (0) 76#define ANOMALY_05000278 (0)
95#define ANOMALY_05000281 (0) 77#define ANOMALY_05000281 (0)
96#define ANOMALY_05000283 (0)
97#define ANOMALY_05000285 (0)
98#define ANOMALY_05000287 (0) 78#define ANOMALY_05000287 (0)
99#define ANOMALY_05000301 (0)
100#define ANOMALY_05000305 (0)
101#define ANOMALY_05000307 (0)
102#define ANOMALY_05000311 (0) 79#define ANOMALY_05000311 (0)
103#define ANOMALY_05000312 (0) 80#define ANOMALY_05000312 (0)
104#define ANOMALY_05000315 (0)
105#define ANOMALY_05000323 (0) 81#define ANOMALY_05000323 (0)
106#define ANOMALY_05000353 (1)
107#define ANOMALY_05000357 (0)
108#define ANOMALY_05000362 (1)
109#define ANOMALY_05000363 (0) 82#define ANOMALY_05000363 (0)
110#define ANOMALY_05000364 (0)
111#define ANOMALY_05000371 (0)
112#define ANOMALY_05000380 (0)
113#define ANOMALY_05000386 (0)
114#define ANOMALY_05000389 (0)
115#define ANOMALY_05000400 (0)
116#define ANOMALY_05000402 (0)
117#define ANOMALY_05000412 (0)
118#define ANOMALY_05000432 (0)
119#define ANOMALY_05000440 (0)
120#define ANOMALY_05000448 (0)
121#define ANOMALY_05000456 (0)
122#define ANOMALY_05000450 (0)
123#define ANOMALY_05000465 (0)
124#define ANOMALY_05000467 (0)
125#define ANOMALY_05000474 (0)
126#define ANOMALY_05000475 (0)
127#define ANOMALY_05000480 (0) 83#define ANOMALY_05000480 (0)
128#define ANOMALY_05000485 (0) 84#define ANOMALY_05000481 (1)
85
86/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
87#define ANOMALY_05000491 ANOMALY_16000008
88#define ANOMALY_05000477 ANOMALY_16000009
89#define ANOMALY_05000443 ANOMALY_16000010
90#define ANOMALY_05000461 ANOMALY_16000011
91#define ANOMALY_05000426 ANOMALY_16000012
92#define ANOMALY_05000310 ANOMALY_16000013
93#define ANOMALY_05000245 ANOMALY_16000014
94#define ANOMALY_05000074 ANOMALY_16000015
95#define ANOMALY_05000416 ANOMALY_16000017
96
129 97
130#endif 98#endif