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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 12:22:30 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:59 -0400
commit43f2f1154aecce40e6ced16b46dab47fbb4de866 (patch)
treedba799998a5a78a9eab36f4eb731a71e8b6e9ecd /arch/blackfin/mach-common
parent1907d8be2d54de461c682ee2fac45d97c29fd5dd (diff)
bfin: Convert irq namespace
Convert to the new function names. Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: uclinux-dist-devel@blackfin.uclinux.org
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/ints-priority.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index cbfc88e11c12..43d9fb195c1e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -559,7 +559,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
559#ifdef CONFIG_IPIPE 559#ifdef CONFIG_IPIPE
560 handle = handle_level_irq; 560 handle = handle_level_irq;
561#endif 561#endif
562 __set_irq_handler_unlocked(irq, handle); 562 __irq_set_handler_locked(irq, handle);
563} 563}
564 564
565static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 565static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
@@ -1163,9 +1163,9 @@ int __init init_arch_irq(void)
1163 1163
1164 for (irq = 0; irq <= SYS_IRQS; irq++) { 1164 for (irq = 0; irq <= SYS_IRQS; irq++) {
1165 if (irq <= IRQ_CORETMR) 1165 if (irq <= IRQ_CORETMR)
1166 set_irq_chip(irq, &bfin_core_irqchip); 1166 irq_set_chip(irq, &bfin_core_irqchip);
1167 else 1167 else
1168 set_irq_chip(irq, &bfin_internal_irqchip); 1168 irq_set_chip(irq, &bfin_internal_irqchip);
1169 1169
1170 switch (irq) { 1170 switch (irq) {
1171#if defined(CONFIG_BF53x) 1171#if defined(CONFIG_BF53x)
@@ -1189,50 +1189,50 @@ int __init init_arch_irq(void)
1189#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 1189#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1190 case IRQ_PORTF_INTA: 1190 case IRQ_PORTF_INTA:
1191#endif 1191#endif
1192 set_irq_chained_handler(irq, 1192 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1193 bfin_demux_gpio_irq);
1194 break; 1193 break;
1195#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1194#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1196 case IRQ_GENERIC_ERROR: 1195 case IRQ_GENERIC_ERROR:
1197 set_irq_chained_handler(irq, bfin_demux_error_irq); 1196 irq_set_chained_handler(irq, bfin_demux_error_irq);
1198 break; 1197 break;
1199#endif 1198#endif
1200#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1199#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1201 case IRQ_MAC_ERROR: 1200 case IRQ_MAC_ERROR:
1202 set_irq_chained_handler(irq, bfin_demux_mac_status_irq); 1201 irq_set_chained_handler(irq,
1202 bfin_demux_mac_status_irq);
1203 break; 1203 break;
1204#endif 1204#endif
1205#ifdef CONFIG_SMP 1205#ifdef CONFIG_SMP
1206 case IRQ_SUPPLE_0: 1206 case IRQ_SUPPLE_0:
1207 case IRQ_SUPPLE_1: 1207 case IRQ_SUPPLE_1:
1208 set_irq_handler(irq, handle_percpu_irq); 1208 irq_set_handler(irq, handle_percpu_irq);
1209 break; 1209 break;
1210#endif 1210#endif
1211 1211
1212#ifdef CONFIG_TICKSOURCE_CORETMR 1212#ifdef CONFIG_TICKSOURCE_CORETMR
1213 case IRQ_CORETMR: 1213 case IRQ_CORETMR:
1214# ifdef CONFIG_SMP 1214# ifdef CONFIG_SMP
1215 set_irq_handler(irq, handle_percpu_irq); 1215 irq_set_handler(irq, handle_percpu_irq);
1216 break; 1216 break;
1217# else 1217# else
1218 set_irq_handler(irq, handle_simple_irq); 1218 irq_set_handler(irq, handle_simple_irq);
1219 break; 1219 break;
1220# endif 1220# endif
1221#endif 1221#endif
1222 1222
1223#ifdef CONFIG_TICKSOURCE_GPTMR0 1223#ifdef CONFIG_TICKSOURCE_GPTMR0
1224 case IRQ_TIMER0: 1224 case IRQ_TIMER0:
1225 set_irq_handler(irq, handle_simple_irq); 1225 irq_set_handler(irq, handle_simple_irq);
1226 break; 1226 break;
1227#endif 1227#endif
1228 1228
1229#ifdef CONFIG_IPIPE 1229#ifdef CONFIG_IPIPE
1230 default: 1230 default:
1231 set_irq_handler(irq, handle_level_irq); 1231 irq_set_handler(irq, handle_level_irq);
1232 break; 1232 break;
1233#else /* !CONFIG_IPIPE */ 1233#else /* !CONFIG_IPIPE */
1234 default: 1234 default:
1235 set_irq_handler(irq, handle_simple_irq); 1235 irq_set_handler(irq, handle_simple_irq);
1236 break; 1236 break;
1237#endif /* !CONFIG_IPIPE */ 1237#endif /* !CONFIG_IPIPE */
1238 } 1238 }
@@ -1240,22 +1240,22 @@ int __init init_arch_irq(void)
1240 1240
1241#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1241#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1242 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) 1242 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1243 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, 1243 irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
1244 handle_level_irq); 1244 handle_level_irq);
1245#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1245#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1246 set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); 1246 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1247#endif 1247#endif
1248#endif 1248#endif
1249 1249
1250#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1250#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1251 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) 1251 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1252 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, 1252 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1253 handle_level_irq); 1253 handle_level_irq);
1254#endif 1254#endif
1255 /* if configured as edge, then will be changed to do_edge_IRQ */ 1255 /* if configured as edge, then will be changed to do_edge_IRQ */
1256 for (irq = GPIO_IRQ_BASE; 1256 for (irq = GPIO_IRQ_BASE;
1257 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) 1257 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1258 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, 1258 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1259 handle_level_irq); 1259 handle_level_irq);
1260 1260
1261 bfin_write_IMASK(0); 1261 bfin_write_IMASK(0);