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authorMike Frysinger <vapier@gentoo.org>2011-04-15 03:08:20 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:43 -0400
commitf58c3276d3652b0d96654ba08f0afc87c013da57 (patch)
treea7276504d01d8a0a170f6b52eea80a2cbef6b225 /arch/blackfin/mach-common
parent6327a574f9ce85f0daab8693913003a456f27f1f (diff)
Blackfin: move bf537-specific irq code out of common code
The SIC interrupt line muxing that the bf537 does is specific to this CPU (thankfully), so rip it out of the common code and move it to a bf537-specific file. This tidies up the common code significantly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/ints-priority.c148
1 files changed, 10 insertions, 138 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 766e9f6d0627..e32cd6f11010 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -24,24 +24,9 @@
24#include <asm/gpio.h> 24#include <asm/gpio.h>
25#include <asm/irq_handler.h> 25#include <asm/irq_handler.h>
26#include <asm/dpmc.h> 26#include <asm/dpmc.h>
27#include <asm/bfin5xx_spi.h>
28#include <asm/bfin_sport.h>
29#include <asm/bfin_can.h>
30 27
31#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 28#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
32 29
33#ifdef BF537_FAMILY
34# define BF537_GENERIC_ERROR_INT_DEMUX
35# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
36# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
37# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
38# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
39# define UART_ERR_MASK (0x6) /* UART_IIR */
40# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
41#else
42# undef BF537_GENERIC_ERROR_INT_DEMUX
43#endif
44
45/* 30/*
46 * NOTES: 31 * NOTES:
47 * - we have separated the physical Hardware interrupt from the 32 * - we have separated the physical Hardware interrupt from the
@@ -119,7 +104,7 @@ static void __init search_IAR(void)
119 * This is for core internal IRQs 104 * This is for core internal IRQs
120 */ 105 */
121 106
122static void bfin_ack_noop(struct irq_data *d) 107void bfin_ack_noop(struct irq_data *d)
123{ 108{
124 /* Dummy function. */ 109 /* Dummy function. */
125} 110}
@@ -148,7 +133,7 @@ static void bfin_core_unmask_irq(struct irq_data *d)
148 return; 133 return;
149} 134}
150 135
151static void bfin_internal_mask_irq(unsigned int irq) 136void bfin_internal_mask_irq(unsigned int irq)
152{ 137{
153 unsigned long flags = hard_local_irq_save(); 138 unsigned long flags = hard_local_irq_save();
154 139
@@ -178,7 +163,7 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
178static void bfin_internal_unmask_irq_affinity(unsigned int irq, 163static void bfin_internal_unmask_irq_affinity(unsigned int irq,
179 const struct cpumask *affinity) 164 const struct cpumask *affinity)
180#else 165#else
181static void bfin_internal_unmask_irq(unsigned int irq) 166void bfin_internal_unmask_irq(unsigned int irq)
182#endif 167#endif
183{ 168{
184 unsigned long flags = hard_local_irq_save(); 169 unsigned long flags = hard_local_irq_save();
@@ -310,7 +295,7 @@ static struct irq_chip bfin_internal_irqchip = {
310 .irq_set_wake = bfin_internal_set_wake_chip, 295 .irq_set_wake = bfin_internal_set_wake_chip,
311}; 296};
312 297
313static void bfin_handle_irq(unsigned irq) 298void bfin_handle_irq(unsigned irq)
314{ 299{
315#ifdef CONFIG_IPIPE 300#ifdef CONFIG_IPIPE
316 struct pt_regs regs; /* Contents not used. */ 301 struct pt_regs regs; /* Contents not used. */
@@ -322,102 +307,6 @@ static void bfin_handle_irq(unsigned irq)
322#endif /* !CONFIG_IPIPE */ 307#endif /* !CONFIG_IPIPE */
323} 308}
324 309
325#ifdef BF537_GENERIC_ERROR_INT_DEMUX
326static int error_int_mask;
327
328static void bfin_generic_error_mask_irq(struct irq_data *d)
329{
330 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
331 if (!error_int_mask)
332 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
333}
334
335static void bfin_generic_error_unmask_irq(struct irq_data *d)
336{
337 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
338 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
339}
340
341static struct irq_chip bfin_generic_error_irqchip = {
342 .name = "ERROR",
343 .irq_ack = bfin_ack_noop,
344 .irq_mask_ack = bfin_generic_error_mask_irq,
345 .irq_mask = bfin_generic_error_mask_irq,
346 .irq_unmask = bfin_generic_error_unmask_irq,
347};
348
349static void bfin_demux_error_irq(unsigned int int_err_irq,
350 struct irq_desc *inta_desc)
351{
352 int irq = 0;
353
354#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
355 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
356 irq = IRQ_MAC_ERROR;
357 else
358#endif
359 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
360 irq = IRQ_SPORT0_ERROR;
361 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
362 irq = IRQ_SPORT1_ERROR;
363 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
364 irq = IRQ_PPI_ERROR;
365 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
366 irq = IRQ_CAN_ERROR;
367 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
368 irq = IRQ_SPI_ERROR;
369 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
370 irq = IRQ_UART0_ERROR;
371 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
372 irq = IRQ_UART1_ERROR;
373
374 if (irq) {
375 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
376 bfin_handle_irq(irq);
377 else {
378
379 switch (irq) {
380 case IRQ_PPI_ERROR:
381 bfin_write_PPI_STATUS(PPI_ERR_MASK);
382 break;
383#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
384 case IRQ_MAC_ERROR:
385 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
386 break;
387#endif
388 case IRQ_SPORT0_ERROR:
389 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
390 break;
391
392 case IRQ_SPORT1_ERROR:
393 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
394 break;
395
396 case IRQ_CAN_ERROR:
397 bfin_write_CAN_GIS(CAN_ERR_MASK);
398 break;
399
400 case IRQ_SPI_ERROR:
401 bfin_write_SPI_STAT(SPI_ERR_MASK);
402 break;
403
404 default:
405 break;
406 }
407
408 pr_debug("IRQ %d:"
409 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
410 irq);
411 }
412 } else
413 printk(KERN_ERR
414 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
415 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
416 __func__, __FILE__, __LINE__);
417
418}
419#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
420
421#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 310#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
422static int mac_stat_int_mask; 311static int mac_stat_int_mask;
423 312
@@ -458,7 +347,7 @@ static void bfin_mac_status_mask_irq(struct irq_data *d)
458 unsigned int irq = d->irq; 347 unsigned int irq = d->irq;
459 348
460 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); 349 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
461#ifdef BF537_GENERIC_ERROR_INT_DEMUX 350#ifdef BF537_FAMILY
462 switch (irq) { 351 switch (irq) {
463 case IRQ_MAC_PHYINT: 352 case IRQ_MAC_PHYINT:
464 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); 353 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
@@ -477,7 +366,7 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
477{ 366{
478 unsigned int irq = d->irq; 367 unsigned int irq = d->irq;
479 368
480#ifdef BF537_GENERIC_ERROR_INT_DEMUX 369#ifdef BF537_FAMILY
481 switch (irq) { 370 switch (irq) {
482 case IRQ_MAC_PHYINT: 371 case IRQ_MAC_PHYINT:
483 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); 372 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
@@ -495,7 +384,7 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
495#ifdef CONFIG_PM 384#ifdef CONFIG_PM
496int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) 385int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
497{ 386{
498#ifdef BF537_GENERIC_ERROR_INT_DEMUX 387#ifdef BF537_FAMILY
499 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); 388 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
500#else 389#else
501 return bfin_internal_set_wake(IRQ_MAC_ERROR, state); 390 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
@@ -514,8 +403,8 @@ static struct irq_chip bfin_mac_status_irqchip = {
514 .irq_set_wake = bfin_mac_status_set_wake, 403 .irq_set_wake = bfin_mac_status_set_wake,
515}; 404};
516 405
517static void bfin_demux_mac_status_irq(unsigned int int_err_irq, 406void bfin_demux_mac_status_irq(unsigned int int_err_irq,
518 struct irq_desc *inta_desc) 407 struct irq_desc *inta_desc)
519{ 408{
520 int i, irq = 0; 409 int i, irq = 0;
521 u32 status = bfin_read_EMAC_SYSTAT(); 410 u32 status = bfin_read_EMAC_SYSTAT();
@@ -1137,11 +1026,6 @@ int __init init_arch_irq(void)
1137 1026
1138 local_irq_disable(); 1027 local_irq_disable();
1139 1028
1140#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1141 /* Clear EMAC Interrupt Status bits so we can demux it later */
1142 bfin_write_EMAC_SYSTAT(-1);
1143#endif
1144
1145#ifdef CONFIG_BF54x 1029#ifdef CONFIG_BF54x
1146# ifdef CONFIG_PINTx_REASSIGN 1030# ifdef CONFIG_PINTx_REASSIGN
1147 pint[0]->assign = CONFIG_PINT0_ASSIGN; 1031 pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1183,11 +1067,6 @@ int __init init_arch_irq(void)
1183#endif 1067#endif
1184 irq_set_chained_handler(irq, bfin_demux_gpio_irq); 1068 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1185 break; 1069 break;
1186#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1187 case IRQ_GENERIC_ERROR:
1188 irq_set_chained_handler(irq, bfin_demux_error_irq);
1189 break;
1190#endif
1191#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1070#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1192 case IRQ_MAC_ERROR: 1071 case IRQ_MAC_ERROR:
1193 irq_set_chained_handler(irq, 1072 irq_set_chained_handler(irq,
@@ -1227,14 +1106,7 @@ int __init init_arch_irq(void)
1227 } 1106 }
1228 } 1107 }
1229 1108
1230#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1109 init_mach_irq();
1231 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1232 irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
1233 handle_level_irq);
1234#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1235 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1236#endif
1237#endif
1238 1110
1239#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1111#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1240 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) 1112 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)