aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-common
diff options
context:
space:
mode:
authorMichael Hennerich <michael.hennerich@analog.com>2008-08-06 05:55:32 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:55:32 -0400
commit56f5f59052bb662a77d5ffd6cbe5861a2ef2407c (patch)
tree4c645e253579fa7d3e912144bd317a0236f27a5a /arch/blackfin/mach-common
parent15b07536892284449ac5cd9488a8da1054b4295b (diff)
Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling
- Disable all bits in SIC_IWR unless we are going into a real (DPMC) power saving mode. Any Interrupt can wake the core form it's idle state. - Remove deep sleep mode as it is not going to be used anywhere: We support sleep, sleep deeper and hibernate. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S56
-rw-r--r--arch/blackfin/mach-common/ints-priority.c8
-rw-r--r--arch/blackfin/mach-common/pm.c8
3 files changed, 8 insertions, 64 deletions
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 5e3f1d8a4fb8..838b0b2ce9a5 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -78,62 +78,6 @@ ENTRY(_hibernate_mode)
78 jump .Lforever; 78 jump .Lforever;
79ENDPROC(_hibernate_mode) 79ENDPROC(_hibernate_mode)
80 80
81ENTRY(_deep_sleep)
82 [--SP] = ( R7:0, P5:0 );
83 [--SP] = RETS;
84
85 CLI R4;
86
87 R0 = IWR_ENABLE(0);
88 R1 = IWR_DISABLE_ALL;
89 R2 = IWR_DISABLE_ALL;
90
91 call _set_sic_iwr;
92
93 call _set_dram_srfs;
94
95 /* Clear all the interrupts,bits sticky */
96 R0 = 0xFFFF (Z);
97 call _set_rtc_istat
98
99 P0.H = hi(PLL_CTL);
100 P0.L = lo(PLL_CTL);
101 R0 = W[P0](z);
102 BITSET (R0, 5);
103 W[P0] = R0.L;
104
105 call _test_pll_locked;
106
107 SSYNC;
108 IDLE;
109
110 call _unset_dram_srfs;
111
112 call _test_pll_locked;
113
114 R0 = IWR_ENABLE(0);
115 R1 = IWR_DISABLE_ALL;
116 R2 = IWR_DISABLE_ALL;
117
118 call _set_sic_iwr;
119
120 P0.H = hi(PLL_CTL);
121 P0.L = lo(PLL_CTL);
122 R0 = w[p0](z);
123 BITCLR (R0, 3);
124 BITCLR (R0, 5);
125 BITCLR (R0, 8);
126 w[p0] = R0;
127 IDLE;
128 call _test_pll_locked;
129
130 STI R4;
131
132 RETS = [SP++];
133 ( R7:0, P5:0 ) = [SP++];
134 RTS;
135ENDPROC(_deep_sleep)
136
137ENTRY(_sleep_deeper) 81ENTRY(_sleep_deeper)
138 [--SP] = ( R7:0, P5:0 ); 82 [--SP] = ( R7:0, P5:0 );
139 [--SP] = RETS; 83 [--SP] = RETS;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index e713b9db867d..4271ef3f201a 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1068,13 +1068,13 @@ int __init init_arch_irq(void)
1068 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1068 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1069 1069
1070#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1070#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1071 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 1071 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1072 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 1072 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1073# ifdef CONFIG_BF54x 1073# ifdef CONFIG_BF54x
1074 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 1074 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1075# endif 1075# endif
1076#else 1076#else
1077 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 1077 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1078#endif 1078#endif
1079 1079
1080 return 0; 1080 return 0;
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 143134b852ea..a17ace3e0e41 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -83,13 +83,13 @@ void bfin_pm_suspend_standby_enter(void)
83 bfin_pm_standby_restore(); 83 bfin_pm_standby_restore();
84 84
85#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 85#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
86 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 86 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
87 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 87 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
88# ifdef CONFIG_BF54x 88# ifdef CONFIG_BF54x
89 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 89 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
90# endif 90# endif
91#else 91#else
92 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 92 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
93#endif 93#endif
94 94
95 local_irq_restore(flags); 95 local_irq_restore(flags);