diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-07-16 05:07:26 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-07-16 05:07:26 -0400 |
commit | 1a8caeebe3689ad4ef67d7ff5d4143f7748deedd (patch) | |
tree | 9d32926a0ab37ce21dff30dbb5a046cbde997dec /arch/blackfin/mach-common | |
parent | 7dee62ac5a3e3f5aa7cc5069fa2d32cec5117229 (diff) |
Blackfin arch: use local labels and ENDPROC() markings
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 46ee77afed20..5e3f1d8a4fb8 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S | |||
@@ -51,6 +51,7 @@ ENTRY(_sleep_mode) | |||
51 | RETS = [SP++]; | 51 | RETS = [SP++]; |
52 | ( R7:0, P5:0 ) = [SP++]; | 52 | ( R7:0, P5:0 ) = [SP++]; |
53 | RTS; | 53 | RTS; |
54 | ENDPROC(_sleep_mode) | ||
54 | 55 | ||
55 | ENTRY(_hibernate_mode) | 56 | ENTRY(_hibernate_mode) |
56 | [--SP] = ( R7:0, P5:0 ); | 57 | [--SP] = ( R7:0, P5:0 ); |
@@ -75,6 +76,7 @@ ENTRY(_hibernate_mode) | |||
75 | IDLE; | 76 | IDLE; |
76 | .Lforever: | 77 | .Lforever: |
77 | jump .Lforever; | 78 | jump .Lforever; |
79 | ENDPROC(_hibernate_mode) | ||
78 | 80 | ||
79 | ENTRY(_deep_sleep) | 81 | ENTRY(_deep_sleep) |
80 | [--SP] = ( R7:0, P5:0 ); | 82 | [--SP] = ( R7:0, P5:0 ); |
@@ -130,6 +132,7 @@ ENTRY(_deep_sleep) | |||
130 | RETS = [SP++]; | 132 | RETS = [SP++]; |
131 | ( R7:0, P5:0 ) = [SP++]; | 133 | ( R7:0, P5:0 ) = [SP++]; |
132 | RTS; | 134 | RTS; |
135 | ENDPROC(_deep_sleep) | ||
133 | 136 | ||
134 | ENTRY(_sleep_deeper) | 137 | ENTRY(_sleep_deeper) |
135 | [--SP] = ( R7:0, P5:0 ); | 138 | [--SP] = ( R7:0, P5:0 ); |
@@ -231,7 +234,7 @@ ENTRY(_sleep_deeper) | |||
231 | RETS = [SP++]; | 234 | RETS = [SP++]; |
232 | ( R7:0, P5:0 ) = [SP++]; | 235 | ( R7:0, P5:0 ) = [SP++]; |
233 | RTS; | 236 | RTS; |
234 | 237 | ENDPROC(_sleep_deeper) | |
235 | 238 | ||
236 | ENTRY(_set_dram_srfs) | 239 | ENTRY(_set_dram_srfs) |
237 | /* set the dram to self refresh mode */ | 240 | /* set the dram to self refresh mode */ |
@@ -270,7 +273,7 @@ ENTRY(_set_dram_srfs) | |||
270 | [P0] = R2; | 273 | [P0] = R2; |
271 | #endif | 274 | #endif |
272 | RTS; | 275 | RTS; |
273 | 276 | ENDPROC(_set_dram_srfs) | |
274 | 277 | ||
275 | ENTRY(_unset_dram_srfs) | 278 | ENTRY(_unset_dram_srfs) |
276 | /* set the dram out of self refresh mode */ | 279 | /* set the dram out of self refresh mode */ |
@@ -297,6 +300,7 @@ ENTRY(_unset_dram_srfs) | |||
297 | #endif | 300 | #endif |
298 | SSYNC; | 301 | SSYNC; |
299 | RTS; | 302 | RTS; |
303 | ENDPROC(_unset_dram_srfs) | ||
300 | 304 | ||
301 | ENTRY(_set_sic_iwr) | 305 | ENTRY(_set_sic_iwr) |
302 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 306 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
@@ -318,6 +322,7 @@ ENTRY(_set_sic_iwr) | |||
318 | 322 | ||
319 | SSYNC; | 323 | SSYNC; |
320 | RTS; | 324 | RTS; |
325 | ENDPROC(_set_sic_iwr) | ||
321 | 326 | ||
322 | ENTRY(_set_rtc_istat) | 327 | ENTRY(_set_rtc_istat) |
323 | #ifndef CONFIG_BF561 | 328 | #ifndef CONFIG_BF561 |
@@ -332,6 +337,7 @@ ENTRY(_set_rtc_istat) | |||
332 | nop; | 337 | nop; |
333 | #endif | 338 | #endif |
334 | RTS; | 339 | RTS; |
340 | ENDPROC(_set_rtc_istat) | ||
335 | 341 | ||
336 | ENTRY(_test_pll_locked) | 342 | ENTRY(_test_pll_locked) |
337 | P0.H = hi(PLL_STAT); | 343 | P0.H = hi(PLL_STAT); |
@@ -341,10 +347,10 @@ ENTRY(_test_pll_locked) | |||
341 | CC = BITTST(R0,5); | 347 | CC = BITTST(R0,5); |
342 | IF !CC JUMP 1b; | 348 | IF !CC JUMP 1b; |
343 | RTS; | 349 | RTS; |
350 | ENDPROC(_test_pll_locked) | ||
344 | 351 | ||
345 | .section .text | 352 | .section .text |
346 | 353 | ||
347 | |||
348 | ENTRY(_do_hibernate) | 354 | ENTRY(_do_hibernate) |
349 | [--SP] = ( R7:0, P5:0 ); | 355 | [--SP] = ( R7:0, P5:0 ); |
350 | [--SP] = RETS; | 356 | [--SP] = RETS; |
@@ -593,8 +599,8 @@ ENTRY(_do_hibernate) | |||
593 | R0.H = 0xDEAD; /* Hibernate Magic */ | 599 | R0.H = 0xDEAD; /* Hibernate Magic */ |
594 | R0.L = 0xBEEF; | 600 | R0.L = 0xBEEF; |
595 | [P0++] = R0; /* Store Hibernate Magic */ | 601 | [P0++] = R0; /* Store Hibernate Magic */ |
596 | R0.H = pm_resume_here; | 602 | R0.H = .Lpm_resume_here; |
597 | R0.L = pm_resume_here; | 603 | R0.L = .Lpm_resume_here; |
598 | [P0++] = R0; /* Save Return Address */ | 604 | [P0++] = R0; /* Save Return Address */ |
599 | [P0++] = SP; /* Save Stack Pointer */ | 605 | [P0++] = SP; /* Save Stack Pointer */ |
600 | P0.H = _hibernate_mode; | 606 | P0.H = _hibernate_mode; |
@@ -602,7 +608,7 @@ ENTRY(_do_hibernate) | |||
602 | R0 = R2; | 608 | R0 = R2; |
603 | call (P0); /* Goodbye */ | 609 | call (P0); /* Goodbye */ |
604 | 610 | ||
605 | pm_resume_here: | 611 | .Lpm_resume_here: |
606 | 612 | ||
607 | /* Restore Core Registers */ | 613 | /* Restore Core Registers */ |
608 | SEQSTAT = [sp++]; | 614 | SEQSTAT = [sp++]; |
@@ -846,3 +852,4 @@ pm_resume_here: | |||
846 | RETS = [SP++]; | 852 | RETS = [SP++]; |
847 | ( R7:0, P5:0 ) = [SP++]; | 853 | ( R7:0, P5:0 ) = [SP++]; |
848 | RTS; | 854 | RTS; |
855 | ENDPROC(_do_hibernate) | ||