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authorSonic Zhang <sonic.zhang@analog.com>2009-06-10 04:57:08 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-13 07:20:07 -0400
commit47e9dedb720364e0adff0e99960fa294c6161f71 (patch)
treefa5bcb532023a89fa11995e5ceca5ed5dfeabbba /arch/blackfin/mach-common
parent2466ac65560ee8b7506eea3987aba9519355fd02 (diff)
Blackfin: add blackfin_invalidate_entire_icache for SMP systems
The KGDB code uses this when switching processors to make sure the icache is in a valid state. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/cache-c.c14
-rw-r--r--arch/blackfin/mach-common/smp.c11
2 files changed, 24 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
index e6ab1f815123..b59ce3cb3807 100644
--- a/arch/blackfin/mach-common/cache-c.c
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -16,9 +16,21 @@
16void blackfin_invalidate_entire_dcache(void) 16void blackfin_invalidate_entire_dcache(void)
17{ 17{
18 u32 dmem = bfin_read_DMEM_CONTROL(); 18 u32 dmem = bfin_read_DMEM_CONTROL();
19 SSYNC();
20 bfin_write_DMEM_CONTROL(dmem & ~0xc); 19 bfin_write_DMEM_CONTROL(dmem & ~0xc);
21 SSYNC(); 20 SSYNC();
22 bfin_write_DMEM_CONTROL(dmem); 21 bfin_write_DMEM_CONTROL(dmem);
23 SSYNC(); 22 SSYNC();
24} 23}
24
25/* Invalidate the Entire Instruction cache by
26 * clearing IMC bit
27 */
28void blackfin_invalidate_entire_icache(void)
29{
30 u32 imem = bfin_read_IMEM_CONTROL();
31 bfin_write_IMEM_CONTROL(imem & ~0x4);
32 SSYNC();
33 bfin_write_IMEM_CONTROL(imem);
34 SSYNC();
35}
36
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 3b8ebaee77f2..c187da2448bf 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -468,6 +468,17 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
468} 468}
469EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); 469EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
470 470
471#ifdef __ARCH_SYNC_CORE_ICACHE
472void resync_core_icache(void)
473{
474 unsigned int cpu = get_cpu();
475 blackfin_invalidate_entire_icache();
476 ++per_cpu(cpu_data, cpu).icache_invld_count;
477 put_cpu();
478}
479EXPORT_SYMBOL(resync_core_icache);
480#endif
481
471#ifdef __ARCH_SYNC_CORE_DCACHE 482#ifdef __ARCH_SYNC_CORE_DCACHE
472unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); 483unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
473 484