Blackfin arch: SMP supporting patchset: Blackfin header files and machine common code

Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like

In this patch, we provide SMP extend to Blackfin header files
and machine common code

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

6 files changed, 605 insertions, 70 deletions

diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index e6ed57c56d4b..9388b4ab7349 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
 obj-$(CONFIG_PM)          += pm.o dpmc_modes.o
 obj-$(CONFIG_CPU_FREQ)    += cpufreq.o
 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
+obj-$(CONFIG_SMP)         += smp.o
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf289..118751287437 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -97,3 +97,39 @@ ENTRY(_blackfin_dflush_page)
         P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
         jump .Ldfr;
 ENDPROC(_blackfin_dflush_page)
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(_blackfin_invalidate_entire_dcache)
+        [--SP] = ( R7:5);
+
+        P0.L = LO(DMEM_CONTROL);
+        P0.H = HI(DMEM_CONTROL);
+        R7 = [P0];
+        R5 = R7;        /* Save DMEM_CNTR */
+
+        /* Clear the DMC[1:0] bits, All valid bits in the data
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,DMC0_P);
+        BITCLR(R7,DMC1_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+
+        /* Configures the data cache again */
+
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R5;
+        SSYNC;
+        STI R6;
+
+        ( R7:5) = [SP++];
+        RTS;
+ENDPROC(_blackfin_invalidate_entire_dcache)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index c6ae8442fc4e..5531f49c84e6 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -36,6 +36,7 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 #include <linux/unistd.h>
+#include <linux/threads.h>
 #include <asm/blackfin.h>
 #include <asm/errno.h>
 #include <asm/fixed_code.h>
@@ -75,11 +76,11 @@ ENTRY(_ex_workaround_261)
          * handle it.
          */
         P4 = R7;        /* Store EXCAUSE */
-        p5.l = _last_cplb_fault_retx;
-        p5.h = _last_cplb_fault_retx;
-        r7 = [p5];
+
+        GET_PDA(p5, r7);
+        r7 = [p5 + PDA_LFRETX];
         r6 = retx;
-        [p5] = r6;
+        [p5 + PDA_LFRETX] = r6;
         cc = r6 == r7;
         if !cc jump _bfin_return_from_exception;
         /* fall through */
@@ -324,7 +325,9 @@ ENTRY(_ex_trap_c)
         [p4] = p5;
         csync;
 
+        GET_PDA(p5, r6);
 #ifndef CONFIG_DEBUG_DOUBLEFAULT
+
         /*
          * Save these registers, as they are only valid in exception context
          *  (where we are now - as soon as we defer to IRQ5, they can change)
@@ -335,29 +338,25 @@ ENTRY(_ex_trap_c)
         p4.l = lo(DCPLB_FAULT_ADDR);
         p4.h = hi(DCPLB_FAULT_ADDR);
         r7 = [p4];
-        p5.h = _saved_dcplb_fault_addr;
-        p5.l = _saved_dcplb_fault_addr;
-        [p5] = r7;
+        [p5 + PDA_DCPLB] = r7;
 
-        r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
-        p5.h = _saved_icplb_fault_addr;
-        p5.l = _saved_icplb_fault_addr;
-        [p5] = r7;
+        p4.l = lo(ICPLB_FAULT_ADDR);
+        p4.h = hi(ICPLB_FAULT_ADDR);
+        r6 = [p4];
+        [p5 + PDA_ICPLB] = r6;
 
         r6 = retx;
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
-        [p4] = r6;
+        [p5 + PDA_RETX] = r6;
 #endif
         r6 = SYSCFG;
-        [p4 + 4] = r6;
+        [p5 + PDA_SYSCFG] = r6;
         BITCLR(r6, 0);
         SYSCFG = r6;
 
         /* Disable all interrupts, but make sure level 5 is enabled so
          * we can switch to that level.  Save the old mask.  */
         cli r6;
-        [p4 + 8] = r6;
+        [p5 + PDA_EXIMASK] = r6;
 
         p4.l = lo(SAFE_USER_INSTRUCTION);
         p4.h = hi(SAFE_USER_INSTRUCTION);
@@ -424,17 +423,16 @@ ENDPROC(_double_fault)
 ENTRY(_exception_to_level5)
         SAVE_ALL_SYS
 
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
-        r6 = [p4];
+        GET_PDA(p4, r7);        /* Fetch current PDA */
+        r6 = [p4 + PDA_RETX];
         [sp + PT_PC] = r6;
 
-        r6 = [p4 + 4];
+        r6 = [p4 + PDA_SYSCFG];
         [sp + PT_SYSCFG] = r6;
 
         /* Restore interrupt mask.  We haven't pushed RETI, so this
          * doesn't enable interrupts until we return from this handler.  */
-        r6 = [p4 + 8];
+        r6 = [p4 + PDA_EXIMASK];
         sti r6;
 
         /* Restore the hardware error vector.  */
@@ -478,8 +476,8 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
          * scratch register (for want of a better option).
          */
         EX_SCRATCH_REG = sp;
-        sp.l = _exception_stack_top;
-        sp.h = _exception_stack_top;
+        GET_PDA_SAFE(sp);
+        sp = [sp + PDA_EXSTACK]
         /* Try to deal with syscalls quickly.  */
         [--sp] = ASTAT;
         [--sp] = (R7:6,P5:4);
@@ -501,27 +499,22 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
          * but they are not very interesting, so don't save them
          */
 
+        GET_PDA(p5, r7);
         p4.l = lo(DCPLB_FAULT_ADDR);
         p4.h = hi(DCPLB_FAULT_ADDR);
         r7 = [p4];
-        p5.h = _saved_dcplb_fault_addr;
-        p5.l = _saved_dcplb_fault_addr;
-        [p5] = r7;
+        [p5 + PDA_DCPLB] = r7;
 
-        r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
-        p5.h = _saved_icplb_fault_addr;
-        p5.l = _saved_icplb_fault_addr;
-        [p5] = r7;
+        p4.l = lo(ICPLB_FAULT_ADDR);
+        p4.h = hi(ICPLB_FAULT_ADDR);
+        r7 = [p4];
+        [p5 + PDA_ICPLB] = r7;
 
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
         r6 = retx;
-        [p4] = r6;
+        [p5 + PDA_RETX] = r6;
 
         r7 = SEQSTAT;           /* reason code is in bit 5:0 */
-        p4.l = _saved_seqstat;
-        p4.h = _saved_seqstat;
-        [p4] = r7;
+        [p5 + PDA_SEQSTAT] = r7;
 #else
         r7 = SEQSTAT;           /* reason code is in bit 5:0 */
 #endif
@@ -546,11 +539,11 @@ ENTRY(_kernel_execve)
         p0 = sp;
         r3 = SIZEOF_PTREGS / 4;
         r4 = 0(x);
-0:
+.Lclear_regs:
         [p0++] = r4;
         r3 += -1;
         cc = r3 == 0;
-        if !cc jump 0b (bp);
+        if !cc jump .Lclear_regs (bp);
 
         p0 = sp;
         sp += -16;
@@ -558,7 +551,7 @@ ENTRY(_kernel_execve)
         call _do_execve;
         SP += 16;
         cc = r0 == 0;
-        if ! cc jump 1f;
+        if ! cc jump .Lexecve_failed;
         /* Success.  Copy our temporary pt_regs to the top of the kernel
          * stack and do a normal exception return.
          */
@@ -574,12 +567,12 @@ ENTRY(_kernel_execve)
         p0 = fp;
         r4 = [p0--];
         r3 = SIZEOF_PTREGS / 4;
-0:
+.Lcopy_regs:
         r4 = [p0--];
         [p1--] = r4;
         r3 += -1;
         cc = r3 == 0;
-        if ! cc jump 0b (bp);
+        if ! cc jump .Lcopy_regs (bp);
 
         r0 = (KERNEL_STACK_SIZE - SIZEOF_PTREGS) (z);
         p1 = r0;
@@ -591,7 +584,7 @@ ENTRY(_kernel_execve)
 
         RESTORE_CONTEXT;
         rti;
-1:
+.Lexecve_failed:
         unlink;
         rts;
 ENDPROC(_kernel_execve)
@@ -925,9 +918,14 @@ _schedule_and_signal_from_int:
         p1 = rets;
         [sp + PT_RESERVED] = p1;
 
+#ifdef CONFIG_SMP
+        GET_PDA(p0, r0);        /* Fetch current PDA (can't migrate to other CPU here) */
+        r0 = [p0 + PDA_IRQFLAGS];
+#else
         p0.l = _irq_flags;
         p0.h = _irq_flags;
         r0 = [p0];
+#endif
         sti r0;
 
         r0 = sp;
@@ -1539,12 +1537,6 @@ ENTRY(_sys_call_table)
         .endr
 END(_sys_call_table)
 
-#if ANOMALY_05000261
-/* Used by the assembly entry point to work around an anomaly.  */
-_last_cplb_fault_retx:
-        .long 0;
-#endif
-
 #ifdef CONFIG_EXCEPTION_L1_SCRATCH
 /* .section .l1.bss.scratch */
 .set _exception_stack_top, L1_SCRATCH_START + L1_SCRATCH_LENGTH
@@ -1554,8 +1546,8 @@ _last_cplb_fault_retx:
 #else
 .bss
 #endif
-_exception_stack:
-        .rept 1024
+ENTRY(_exception_stack)
+        .rept 1024 * NR_CPUS
         .long 0
         .endr
 _exception_stack_top:
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index c1dcaebbd3a9..a621ae444810 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -13,6 +13,7 @@
 #include <asm/blackfin.h>
 #include <asm/thread_info.h>
 #include <asm/trace.h>
+#include <asm/asm-offsets.h>
 
 __INIT
 
@@ -111,33 +112,26 @@ ENTRY(__start)
          * This happens here, since L1 gets clobbered
          * below
          */
-        p0.l = _saved_retx;
-        p0.h = _saved_retx;
+        GET_PDA(p0, r0);
+        r7 = [p0 + PDA_RETX];
         p1.l = _init_saved_retx;
         p1.h = _init_saved_retx;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_dcplb_fault_addr;
-        p0.h = _saved_dcplb_fault_addr;
+        r7 = [p0 + PDA_DCPLB];
         p1.l = _init_saved_dcplb_fault_addr;
         p1.h = _init_saved_dcplb_fault_addr;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_icplb_fault_addr;
-        p0.h = _saved_icplb_fault_addr;
+        r7 = [p0 + PDA_ICPLB];
         p1.l = _init_saved_icplb_fault_addr;
         p1.h = _init_saved_icplb_fault_addr;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_seqstat;
-        p0.h = _saved_seqstat;
+        r7 = [p0 + PDA_SEQSTAT];
         p1.l = _init_saved_seqstat;
         p1.h = _init_saved_seqstat;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 #endif
 
         /* Initialize stack pointer */
@@ -255,6 +249,9 @@ ENTRY(_real_start)
         sp = sp + p1;
         usp = sp;
         fp = sp;
+        sp += -12;
+        call _init_pda
+        sp += 12;
         jump.l _start_kernel;
 ENDPROC(_real_start)
 
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index d45d0c59fac7..eb8dfcfc3544 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -55,6 +55,7 @@
  * -
  */
 
+#ifndef CONFIG_SMP
 /* Initialize this to an actual value to force it into the .data
  * section so that we know it is properly initialized at entry into
  * the kernel but before bss is initialized to zero (which is where
@@ -63,6 +64,7 @@
  */
 unsigned long irq_flags = 0x1f;
 EXPORT_SYMBOL(irq_flags);
+#endif
 
 /* The number of spurious interrupts */
 atomic_t num_spurious;
@@ -163,6 +165,10 @@ static void bfin_internal_mask_irq(unsigned int irq)
         mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
                              ~(1 << mask_bit));
+#ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
+                             ~(1 << mask_bit));
+#endif
 #endif
 }
 
@@ -177,6 +183,10 @@ static void bfin_internal_unmask_irq(unsigned int irq)
         mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
                              (1 << mask_bit));
+#ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
+                             (1 << mask_bit));
+#endif
 #endif
 }
 
@@ -896,7 +906,7 @@ static struct irq_chip bfin_gpio_irqchip = {
 #endif
 };
 
-void __init init_exception_vectors(void)
+void __cpuinit init_exception_vectors(void)
 {
         /* cannot program in software:
          * evt0 - emulation (jtag)
@@ -935,6 +945,10 @@ int __init init_arch_irq(void)
 # ifdef CONFIG_BF54x
         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 # endif
+# ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
+        bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
+# endif
 #else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
@@ -995,6 +1009,17 @@ int __init init_arch_irq(void)
 
                         break;
 #endif
+#ifdef CONFIG_TICK_SOURCE_SYSTMR0
+                case IRQ_TIMER0:
+                        set_irq_handler(irq, handle_percpu_irq);
+                        break;
+#endif
+#ifdef CONFIG_SMP
+                case IRQ_SUPPLE_0:
+                case IRQ_SUPPLE_1:
+                        set_irq_handler(irq, handle_percpu_irq);
+                        break;
+#endif
                 default:
                         set_irq_handler(irq, handle_simple_irq);
                         break;
@@ -1029,7 +1054,7 @@ int __init init_arch_irq(void)
         search_IAR();
 
         /* Enable interrupts IVG7-15 */
-        irq_flags = irq_flags | IMASK_IVG15 |
+        irq_flags |= IMASK_IVG15 |
             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
@@ -1070,8 +1095,16 @@ void do_irq(int vec, struct pt_regs *fp)
         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
                 unsigned long sic_status[3];
 
-                sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
-                sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+                if (smp_processor_id()) {
+#ifdef CONFIG_SMP
+                        /* This will be optimized out in UP mode. */
+                        sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
+                        sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
+#endif
+                } else {
+                        sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+                        sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+                }
 #ifdef CONFIG_BF54x
                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
 #endif
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
new file mode 100644
index 000000000000..7aeecedd3147
--- /dev/null
+++ b/arch/blackfin/mach-common/smp.c
@@ -0,0 +1,476 @@
+/*
+ * File:         arch/blackfin/kernel/smp.c
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ * IPI management based on arch/arm/kernel/smp.c.
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/cache.h>
+#include <linux/profile.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
+#include <linux/seq_file.h>
+#include <linux/irq.h>
+#include <asm/atomic.h>
+#include <asm/cacheflush.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/cpu.h>
+#include <linux/err.h>
+
+struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
+
+void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
+        *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
+        *init_saved_dcplb_fault_addr_coreb;
+
+cpumask_t cpu_possible_map;
+EXPORT_SYMBOL(cpu_possible_map);
+
+cpumask_t cpu_online_map;
+EXPORT_SYMBOL(cpu_online_map);
+
+#define BFIN_IPI_RESCHEDULE   0
+#define BFIN_IPI_CALL_FUNC    1
+#define BFIN_IPI_CPU_STOP     2
+
+struct blackfin_flush_data {
+        unsigned long start;
+        unsigned long end;
+};
+
+void *secondary_stack;
+
+
+struct smp_call_struct {
+        void (*func)(void *info);
+        void *info;
+        int wait;
+        cpumask_t pending;
+        cpumask_t waitmask;
+};
+
+static struct blackfin_flush_data smp_flush_data;
+
+static DEFINE_SPINLOCK(stop_lock);
+
+struct ipi_message {
+        struct list_head list;
+        unsigned long type;
+        struct smp_call_struct call_struct;
+};
+
+struct ipi_message_queue {
+        struct list_head head;
+        spinlock_t lock;
+        unsigned long count;
+};
+
+static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
+
+static void ipi_cpu_stop(unsigned int cpu)
+{
+        spin_lock(&stop_lock);
+        printk(KERN_CRIT "CPU%u: stopping\n", cpu);
+        dump_stack();
+        spin_unlock(&stop_lock);
+
+        cpu_clear(cpu, cpu_online_map);
+
+        local_irq_disable();
+
+        while (1)
+                SSYNC();
+}
+
+static void ipi_flush_icache(void *info)
+{
+        struct blackfin_flush_data *fdata = info;
+
+        /* Invalidate the memory holding the bounds of the flushed region. */
+        blackfin_dcache_invalidate_range((unsigned long)fdata,
+                                         (unsigned long)fdata + sizeof(*fdata));
+
+        blackfin_icache_flush_range(fdata->start, fdata->end);
+}
+
+static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
+{
+        int wait;
+        void (*func)(void *info);
+        void *info;
+        func = msg->call_struct.func;
+        info = msg->call_struct.info;
+        wait = msg->call_struct.wait;
+        cpu_clear(cpu, msg->call_struct.pending);
+        func(info);
+        if (wait)
+                cpu_clear(cpu, msg->call_struct.waitmask);
+        else
+                kfree(msg);
+}
+
+static irqreturn_t ipi_handler(int irq, void *dev_instance)
+{
+        struct ipi_message *msg, *mg;
+        struct ipi_message_queue *msg_queue;
+        unsigned int cpu = smp_processor_id();
+
+        platform_clear_ipi(cpu);
+
+        msg_queue = &__get_cpu_var(ipi_msg_queue);
+        msg_queue->count++;
+
+        spin_lock(&msg_queue->lock);
+        list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
+                list_del(&msg->list);
+                switch (msg->type) {
+                case BFIN_IPI_RESCHEDULE:
+                        /* That's the easiest one; leave it to
+                         * return_from_int. */
+                        kfree(msg);
+                        break;
+                case BFIN_IPI_CALL_FUNC:
+                        ipi_call_function(cpu, msg);
+                        break;
+                case BFIN_IPI_CPU_STOP:
+                        ipi_cpu_stop(cpu);
+                        kfree(msg);
+                        break;
+                default:
+                        printk(KERN_CRIT "CPU%u: Unknown IPI message \
+                        0x%lx\n", cpu, msg->type);
+                        kfree(msg);
+                        break;
+                }
+        }
+        spin_unlock(&msg_queue->lock);
+        return IRQ_HANDLED;
+}
+
+static void ipi_queue_init(void)
+{
+        unsigned int cpu;
+        struct ipi_message_queue *msg_queue;
+        for_each_possible_cpu(cpu) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                INIT_LIST_HEAD(&msg_queue->head);
+                spin_lock_init(&msg_queue->lock);
+                msg_queue->count = 0;
+        }
+}
+
+int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+        unsigned int cpu;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return 0;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        INIT_LIST_HEAD(&msg->list);
+        msg->call_struct.func = func;
+        msg->call_struct.info = info;
+        msg->call_struct.wait = wait;
+        msg->call_struct.pending = callmap;
+        msg->call_struct.waitmask = callmap;
+        msg->type = BFIN_IPI_CALL_FUNC;
+
+        for_each_cpu_mask(cpu, callmap) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                spin_lock_irqsave(&msg_queue->lock, flags);
+                list_add(&msg->list, &msg_queue->head);
+                spin_unlock_irqrestore(&msg_queue->lock, flags);
+                platform_send_ipi_cpu(cpu);
+        }
+        if (wait) {
+                while (!cpus_empty(msg->call_struct.waitmask))
+                        blackfin_dcache_invalidate_range(
+                                (unsigned long)(&msg->call_struct.waitmask),
+                                (unsigned long)(&msg->call_struct.waitmask));
+                kfree(msg);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(smp_call_function);
+
+int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
+                                int wait)
+{
+        unsigned int cpu = cpuid;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        if (cpu_is_offline(cpu))
+                return 0;
+        cpus_clear(callmap);
+        cpu_set(cpu, callmap);
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        INIT_LIST_HEAD(&msg->list);
+        msg->call_struct.func = func;
+        msg->call_struct.info = info;
+        msg->call_struct.wait = wait;
+        msg->call_struct.pending = callmap;
+        msg->call_struct.waitmask = callmap;
+        msg->type = BFIN_IPI_CALL_FUNC;
+
+        msg_queue = &per_cpu(ipi_msg_queue, cpu);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+        list_add(&msg->list, &msg_queue->head);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
+        platform_send_ipi_cpu(cpu);
+
+        if (wait) {
+                while (!cpus_empty(msg->call_struct.waitmask))
+                        blackfin_dcache_invalidate_range(
+                                (unsigned long)(&msg->call_struct.waitmask),
+                                (unsigned long)(&msg->call_struct.waitmask));
+                kfree(msg);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(smp_call_function_single);
+
+void smp_send_reschedule(int cpu)
+{
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        if (cpu_is_offline(cpu))
+                return;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        memset(msg, 0, sizeof(msg));
+        INIT_LIST_HEAD(&msg->list);
+        msg->type = BFIN_IPI_RESCHEDULE;
+
+        msg_queue = &per_cpu(ipi_msg_queue, cpu);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+        list_add(&msg->list, &msg_queue->head);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
+        platform_send_ipi_cpu(cpu);
+
+        return;
+}
+
+void smp_send_stop(void)
+{
+        unsigned int cpu;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        memset(msg, 0, sizeof(msg));
+        INIT_LIST_HEAD(&msg->list);
+        msg->type = BFIN_IPI_CPU_STOP;
+
+        for_each_cpu_mask(cpu, callmap) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                spin_lock_irqsave(&msg_queue->lock, flags);
+                list_add(&msg->list, &msg_queue->head);
+                spin_unlock_irqrestore(&msg_queue->lock, flags);
+                platform_send_ipi_cpu(cpu);
+        }
+        return;
+}
+
+int __cpuinit __cpu_up(unsigned int cpu)
+{
+        struct task_struct *idle;
+        int ret;
+
+        idle = fork_idle(cpu);
+        if (IS_ERR(idle)) {
+                printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
+                return PTR_ERR(idle);
+        }
+
+        secondary_stack = task_stack_page(idle) + THREAD_SIZE;
+        smp_wmb();
+
+        ret = platform_boot_secondary(cpu, idle);
+
+        if (ret) {
+                cpu_clear(cpu, cpu_present_map);
+                printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
+                free_task(idle);
+        } else
+                cpu_set(cpu, cpu_online_map);
+
+        secondary_stack = NULL;
+
+        return ret;
+}
+
+static void __cpuinit setup_secondary(unsigned int cpu)
+{
+#ifndef CONFIG_TICK_SOURCE_SYSTMR0
+        struct irq_desc *timer_desc;
+#endif
+        unsigned long ilat;
+
+        bfin_write_IMASK(0);
+        CSYNC();
+        ilat = bfin_read_ILAT();
+        CSYNC();
+        bfin_write_ILAT(ilat);
+        CSYNC();
+
+        /* Reserve the PDA space for the secondary CPU. */
+        reserve_pda();
+
+        /* Enable interrupt levels IVG7-15. IARs have been already
+         * programmed by the boot CPU.  */
+        irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+
+#ifdef CONFIG_TICK_SOURCE_SYSTMR0
+        /* Power down the core timer, just to play safe. */
+        bfin_write_TCNTL(0);
+
+        /* system timer0 has been setup by CoreA. */
+#else
+        timer_desc = irq_desc + IRQ_CORETMR;
+        setup_core_timer();
+        timer_desc->chip->enable(IRQ_CORETMR);
+#endif
+}
+
+void __cpuinit secondary_start_kernel(void)
+{
+        unsigned int cpu = smp_processor_id();
+        struct mm_struct *mm = &init_mm;
+
+        if (_bfin_swrst & SWRST_DBL_FAULT_B) {
+                printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
+                        (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
+#endif
+                printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
+                        init_retx_coreb);
+        }
+
+        /*
+         * We want the D-cache to be enabled early, in case the atomic
+         * support code emulates cache coherence (see
+         * __ARCH_SYNC_CORE_DCACHE).
+         */
+        init_exception_vectors();
+
+        bfin_setup_caches(cpu);
+
+        local_irq_disable();
+
+        /* Attach the new idle task to the global mm. */
+        atomic_inc(&mm->mm_users);
+        atomic_inc(&mm->mm_count);
+        current->active_mm = mm;
+        BUG_ON(current->mm);    /* Can't be, but better be safe than sorry. */
+
+        preempt_disable();
+
+        setup_secondary(cpu);
+
+        local_irq_enable();
+
+        platform_secondary_init(cpu);
+
+        cpu_idle();
+}
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        platform_prepare_cpus(max_cpus);
+        ipi_queue_init();
+        platform_request_ipi(&ipi_handler);
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+        unsigned long bogosum = 0;
+        unsigned int cpu;
+
+        for_each_online_cpu(cpu)
+                bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
+
+        printk(KERN_INFO "SMP: Total of %d processors activated "
+               "(%lu.%02lu BogoMIPS).\n",
+               num_online_cpus(),
+               bogosum / (500000/HZ),
+               (bogosum / (5000/HZ)) % 100);
+}
+
+void smp_icache_flush_range_others(unsigned long start, unsigned long end)
+{
+        smp_flush_data.start = start;
+        smp_flush_data.end = end;
+
+        if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
+                printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
+}
+EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
+
+#ifdef __ARCH_SYNC_CORE_DCACHE
+unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
+
+void resync_core_dcache(void)
+{
+        unsigned int cpu = get_cpu();
+        blackfin_invalidate_entire_dcache();
+        ++per_cpu(cpu_data, cpu).dcache_invld_count;
+        put_cpu();
+}
+EXPORT_SYMBOL(resync_core_dcache);
+#endif