Blackfin arch: fix bug - gpio_bank() macros messed up bank number caculating with positioning a gpio

The whole story:

Before BF51x merged, all the MAX_BLACKFIN_GPIOS are integral multiple of GPIO_BANKSIZE (= 16).
But BF51x provides MAX_BLACKFIN_GPIOS = 40 which includes 3 banks and the 3rd bank has only 8
GPIO pins.

Therefore, gpio_bank() macros is correct when you try to find a GPIO in which bank (GPIO_35 is
in bank 2). But on BF51x gpio_bank(MAX_BLACKFIN_GPIOS) only gives out 2 banks instead of 3
banks for some static array initialization.

This patch add a new macros gpio_bank_n() and GPIO_BANK_NUM to do bank number caculating and
remain the gpio_bank() macros for positioning a gpio in which bank.

Signed-off-by: Bryan Wu <cooloney@kernel.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index c32fa695f8cc..5b374ff1c96e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -377,8 +377,8 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 
 #if !defined(CONFIG_BF54x)
 
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
-static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static unsigned short gpio_enabled[GPIO_BANK_NUM];
+static unsigned short gpio_edge_triggered[GPIO_BANK_NUM];
 
 extern void bfin_gpio_irq_prepare(unsigned gpio);
 
@@ -620,7 +620,7 @@ static unsigned char irq2pint_lut[NR_PINTS];
 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 
 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static unsigned short gpio_enabled[GPIO_BANK_NUM];
 
 
 struct pin_int_t {