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authorRobin Getz <robin.getz@analog.com>2007-08-03 06:07:17 -0400
committerBryan Wu <bryan.wu@analog.com>2007-08-03 06:07:17 -0400
commitf16295e7e7f2a2a15876f570f10d6dc8f1f36ab8 (patch)
tree71481c3d4ec249dddb6f16fe765a474a0d8b2fa9 /arch/blackfin/mach-common
parentb99ab54d4f11141b2ef3e50c3543b7243d3f49fb (diff)
Blackfin arch: Fix CCLK and SCLK checks
Fix CCLK and SCLK checks, combine all arch checks into one file for maintance. Checkins that remove more lines than they add are always good. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/Makefile2
-rw-r--r--arch/blackfin/mach-common/arch_checks.c55
-rw-r--r--arch/blackfin/mach-common/dpmc.S2
3 files changed, 57 insertions, 2 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 0279ede70392..4d7733dfd5de 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,7 +4,7 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ 6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
7 interrupt.o lock.o irqpanic.o 7 interrupt.o lock.o irqpanic.o arch_checks.o
8 8
9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o 10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
new file mode 100644
index 000000000000..f9160d83b91f
--- /dev/null
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -0,0 +1,55 @@
1/*
2 * File: arch/blackfin/mach-common/arch_checks.c
3 * Based on:
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Do some checking to make sure things are OK
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/mach/anomaly.h>
31#include <asm/mach-common/clocks.h>
32
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34
35# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
36# error "VCO selected is more than maximum value. Please change the VCO multipler"
37# endif
38
39# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
40# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
41# endif
42
43# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
44# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
45# endif
46
47# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
48# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
49# endif
50
51# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
52# error "Please select sclk less than cclk"
53# endif
54
55#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 04194dca0151..39fbc2861107 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -300,7 +300,7 @@ ENTRY(_sleep_deeper)
300 P0.H = hi(PLL_CTL); 300 P0.H = hi(PLL_CTL);
301 P0.L = lo(PLL_CTL); 301 P0.L = lo(PLL_CTL);
302 R5 = W[P0](z); 302 R5 = W[P0](z);
303 R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9; 303 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
304 W[P0] = R0.l; 304 W[P0] = R0.l;
305 305
306 SSYNC; 306 SSYNC;