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authorJie Zhang <jie.zhang@analog.com>2009-06-16 05:48:33 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-22 21:15:59 -0400
commit41ba653f24a39a0e6a4afe9b2763a95a57e042c2 (patch)
tree43eb086046d4eef764878e04512ddd215ca8845b /arch/blackfin/mach-common/pm.c
parent7c039a90f02c3fdcab8d3ca170c05ad37014189e (diff)
Blackfin: decouple unrelated cache settings to get exact behavior
The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/pm.c')
-rw-r--r--arch/blackfin/mach-common/pm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index bce5a84be49f..9e7e27b7fc8d 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
132 return 0; 132 return 0;
133} 133}
134 134
135#ifdef CONFIG_BFIN_WB 135#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
136static void flushinv_all_dcache(void) 136static void flushinv_all_dcache(void)
137{ 137{
138 u32 way, bank, subbank, set; 138 u32 way, bank, subbank, set;
@@ -175,7 +175,7 @@ static inline void dcache_disable(void)
175#ifdef CONFIG_BFIN_DCACHE 175#ifdef CONFIG_BFIN_DCACHE
176 unsigned long ctrl; 176 unsigned long ctrl;
177 177
178#ifdef CONFIG_BFIN_WB 178#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
179 flushinv_all_dcache(); 179 flushinv_all_dcache();
180#endif 180#endif
181 SSYNC(); 181 SSYNC();