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authorMike Frysinger <michael.frysinger@analog.com>2007-07-24 22:11:42 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-24 22:11:42 -0400
commite208f83a7aa4ebf6c0a68e814903e8aa33f9439a (patch)
treea45d34fa199c8e5d75878d8a2f15e944eadce852 /arch/blackfin/mach-common/lock.S
parent36a1548f99e54520f049a703e1b91bae95e72481 (diff)
Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common/lock.S')
-rw-r--r--arch/blackfin/mach-common/lock.S20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 386ac8dda076..190edb3cdc84 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -43,12 +43,12 @@ ENTRY(_cache_grab_lock)
43 43
44 [--SP]=( R7:0,P5:0 ); 44 [--SP]=( R7:0,P5:0 );
45 45
46 P1.H = (IMEM_CONTROL >> 16); 46 P1.H = HI(IMEM_CONTROL);
47 P1.L = (IMEM_CONTROL & 0xFFFF); 47 P1.L = LO(IMEM_CONTROL);
48 P5.H = (ICPLB_ADDR0 >> 16); 48 P5.H = HI(ICPLB_ADDR0);
49 P5.L = (ICPLB_ADDR0 & 0xFFFF); 49 P5.L = LO(ICPLB_ADDR0);
50 P4.H = (ICPLB_DATA0 >> 16); 50 P4.H = HI(ICPLB_DATA0);
51 P4.L = (ICPLB_DATA0 & 0xFFFF); 51 P4.L = LO(ICPLB_DATA0);
52 R7 = R0; 52 R7 = R0;
53 53
54 /* If the code of interest already resides in the cache 54 /* If the code of interest already resides in the cache
@@ -167,8 +167,8 @@ ENTRY(_cache_lock)
167 167
168 [--SP]=( R7:0,P5:0 ); 168 [--SP]=( R7:0,P5:0 );
169 169
170 P1.H = (IMEM_CONTROL >> 16); 170 P1.H = HI(IMEM_CONTROL);
171 P1.L = (IMEM_CONTROL & 0xFFFF); 171 P1.L = LO(IMEM_CONTROL);
172 172
173 /* Disable the Interrupts*/ 173 /* Disable the Interrupts*/
174 CLI R3; 174 CLI R3;
@@ -195,8 +195,8 @@ ENDPROC(_cache_lock)
195 */ 195 */
196 196
197ENTRY(_read_iloc) 197ENTRY(_read_iloc)
198 P1.H = (IMEM_CONTROL >> 16); 198 P1.H = HI(IMEM_CONTROL);
199 P1.L = (IMEM_CONTROL & 0xFFFF); 199 P1.L = LO(IMEM_CONTROL);
200 R1 = 0xF; 200 R1 = 0xF;
201 R0 = [P1]; 201 R0 = [P1];
202 R0 = R0 >> 3; 202 R0 = R0 >> 3;